From ac2835b1c04b3c702362c7eae57bd5d8dbece172 Mon Sep 17 00:00:00 2001 From: Ben Marshall Date: Tue, 18 Aug 2020 11:14:10 +0100 Subject: [PATCH] skw: Working on new soc architecture. - See #23. Working verilator build and running out of ROM. - Need to implement simulator appropriate UART. - See #17. FSBL now uses scarv-cpu core complex linker script. On branch scarv/skywater/dev Changes to be committed: modified: extern/scarv-cpu modified: flow/gtkwave/scarv-soc.gtkw modified: flow/selfcheck/Makefile.in modified: flow/verilator/Makefile.in new file: flow/verilator/manifest-soc-rtl.txt new file: flow/verilator/manifest-soc-tb.txt deleted: flow/verilator/scarv-soc-rtl.manifest new file: flow/verilator/scarv-soc-tb.cmd deleted: flow/verilator/scarv-soc-testbench.manifest new file: rtl/gpio/gpio_top.sv new file: rtl/soc/scarv_soc.sv deleted: rtl/soc/scarv_soc.v new file: rtl/soc/scarv_soc_periph_top.sv new file: rtl/uart/uart_top.sv --- extern/scarv-cpu | 2 +- flow/gtkwave/scarv-soc.gtkw | 584 +++----------------- flow/selfcheck/Makefile.in | 9 +- flow/verilator/Makefile.in | 57 +- flow/verilator/manifest-soc-rtl.txt | 5 + flow/verilator/manifest-soc-tb.txt | 4 + flow/verilator/scarv-soc-rtl.manifest | 28 - flow/verilator/scarv-soc-tb.cmd | 5 + flow/verilator/scarv-soc-testbench.manifest | 11 - rtl/gpio/gpio_top.sv | 35 ++ rtl/soc/scarv_soc.sv | 156 ++++++ rtl/soc/scarv_soc.v | 513 ----------------- rtl/soc/scarv_soc_periph_top.sv | 129 +++++ rtl/uart/uart_top.sv | 29 + 14 files changed, 470 insertions(+), 1097 deletions(-) create mode 100644 flow/verilator/manifest-soc-rtl.txt create mode 100644 flow/verilator/manifest-soc-tb.txt delete mode 100644 flow/verilator/scarv-soc-rtl.manifest create mode 100644 flow/verilator/scarv-soc-tb.cmd delete mode 100644 flow/verilator/scarv-soc-testbench.manifest create mode 100644 rtl/gpio/gpio_top.sv create mode 100644 rtl/soc/scarv_soc.sv delete mode 100644 rtl/soc/scarv_soc.v create mode 100644 rtl/soc/scarv_soc_periph_top.sv create mode 100644 rtl/uart/uart_top.sv diff --git a/extern/scarv-cpu b/extern/scarv-cpu index b5a577a..6a9be81 160000 --- a/extern/scarv-cpu +++ b/extern/scarv-cpu @@ -1 +1 @@ -Subproject commit b5a577a5b37d3c1d387b5b25fc7f98073ebfd010 +Subproject commit 6a9be8197e2589ea464902e7273a5edd3c4c2922 diff --git a/flow/gtkwave/scarv-soc.gtkw b/flow/gtkwave/scarv-soc.gtkw index 43fa881..5124675 100644 --- a/flow/gtkwave/scarv-soc.gtkw +++ b/flow/gtkwave/scarv-soc.gtkw @@ -1,561 +1,119 @@ [*] [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI -[*] Tue Apr 14 10:15:10 2020 +[*] Tue Aug 18 10:14:02 2020 [*] -[dumpfile] "/home/work/scarv/scarv-soc/work/selfcheck/test_01_simple/test_01_simple.vcd" -[dumpfile_mtime] "Tue Apr 14 10:14:01 2020" -[dumpfile_size] 2541924 -[savefile] "/home/work/scarv/scarv-soc/flow/gtkwave/scarv-soc.gtkw" +[dumpfile] "/home/work/scarv/skywater/scarv-soc/work/verilator/waves.vcd" +[dumpfile_mtime] "Tue Aug 18 10:11:47 2020" +[dumpfile_size] 15150217 +[savefile] "/home/work/scarv/skywater/scarv-soc/flow/gtkwave/scarv-soc.gtkw" [timestart] 1 [size] 1920 1025 [pos] -1 -1 -*-9.462320 1676 26746 -1 786 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-15.465881 100000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] TOP. [treeopen] TOP.scarv_soc. -[treeopen] TOP.scarv_soc.i_ic_top. -[treeopen] TOP.scarv_soc.i_scarv_cpu. -[treeopen] TOP.scarv_soc.i_scarv_cpu.i_pipeline. -[treeopen] TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch. -[treeopen] TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s1_decode. -[sst_width] 325 -[signals_width] 542 +[treeopen] TOP.scarv_soc.i_scarv_ccx_top. +[sst_width] 308 +[signals_width] 303 [sst_expanded] 1 -[sst_vpaned_height] 264 -@28 -TOP.g_clk -TOP.g_resetn +[sst_vpaned_height] 301 @800200 --SCARV CPU -@c00200 --CPU Instruction Memory -@28 -TOP.scarv_soc.cpu_imem_req -TOP.scarv_soc.cpu_imem_gnt -@22 -TOP.scarv_soc.cpu_imem_addr[31:0] -TOP.scarv_soc.cpu_imem_strb[3:0] -@28 -TOP.scarv_soc.cpu_imem_wen -@22 -TOP.scarv_soc.cpu_imem_wdata[31:0] +-SCARV_SOC +@28 +TOP.scarv_soc.f_clk +TOP.scarv_soc.g_resetn +TOP.scarv_soc.g_clk_gpio +TOP.scarv_soc.g_clk_req_gpio +TOP.scarv_soc.g_clk_req_uart +TOP.scarv_soc.g_clk_uart @200 - -@28 -TOP.scarv_soc.cpu_imem_recv -TOP.scarv_soc.cpu_imem_ack -TOP.scarv_soc.cpu_imem_error -@22 -TOP.scarv_soc.cpu_imem_rdata[31:0] -@1401200 --CPU Instruction Memory -@c00200 --CPU Fetch Stage -@28 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.buf_ready -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.buf_valid -@c00024 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.buf_depth[2:0] -@28 -(0)TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.buf_depth[2:0] -(1)TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.buf_depth[2:0] -(2)TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.buf_depth[2:0] -@1401200 --group_end -@24 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.i_core_fetch_buffer.n_bdepth[2:0] -@22 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.i_core_fetch_buffer.buffer[63:0] -@28 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.drop_response -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.f_ready -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.f_2byte -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.f_4byte -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.i_core_fetch_buffer.eat_2 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.i_core_fetch_buffer.eat_4 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.incomplete_instr -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.n_fetch_misaligned -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.allow_new_mem_req -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.new_mem_req -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.n_imem_req -@24 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.n_reqs_outstanding[2:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.reqs_outstanding[2:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.reqs_outstanding_add[2:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s0_fetch.reqs_outstanding_sub[2:0] -@1401200 --CPU Fetch Stage -@c00200 --CPU Decode Stage -@28 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.s1_bubble_no_instr -TOP.scarv_soc.i_scarv_cpu.i_pipeline.s1_bubble_from_s2 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.s1_bubble_from_s3 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.s1_bubble_from_s4 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.hzd_rs1_s2 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.hzd_rs2_s2 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.hzd_rs3_s2 -@2024 -^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/flow/gtkwave/filter-gprs.txt -TOP.scarv_soc.i_scarv_cpu.i_pipeline.s1_rs2_addr[4:0] -^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/flow/gtkwave/filter-gprs.txt -TOP.scarv_soc.i_scarv_cpu.i_pipeline.fwd_s2_rd[4:0] -^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/flow/gtkwave/filter-gprs.txt -TOP.scarv_soc.i_scarv_cpu.i_pipeline.fwd_s3_rd[4:0] -^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/flow/gtkwave/filter-gprs.txt -TOP.scarv_soc.i_scarv_cpu.i_pipeline.fwd_s4_rd[4:0] -@28 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.s1_bubble -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s1_decode.s1_busy -@22 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s1_decode.s1_data[31:0] -@28 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s1_decode.s1_valid @22 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s1_decode.n_s2_instr[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s1_decode.program_counter[31:0] -@2022 -^2 /home/work/scarv/scarv-soc/work/fsbl/fsbl.gtkwl -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_pipeline_s1_decode.s1_data[31:0] -^2 /home/work/scarv/scarv-soc/work/fsbl/fsbl.gtkwl -TOP.scarv_soc.i_scarv_cpu.i_pipeline.s2_instr[31:0] -^2 /home/work/scarv/scarv-soc/work/fsbl/fsbl.gtkwl -TOP.scarv_soc.i_scarv_cpu.i_pipeline.s3_instr[31:0] -^2 /home/work/scarv/scarv-soc/work/fsbl/fsbl.gtkwl -TOP.scarv_soc.i_scarv_cpu.i_pipeline.s4_instr[31:0] -@1401200 --CPU Decode Stage -@800200 --CPU Data Memory -@28 -TOP.scarv_soc.cpu_dmem_req -TOP.scarv_soc.cpu_dmem_gnt -@22 -TOP.scarv_soc.cpu_dmem_wdata[31:0] -TOP.scarv_soc.cpu_dmem_addr[31:0] -TOP.scarv_soc.cpu_dmem_strb[3:0] +TOP.scarv_soc.gpio_in[15:0] +TOP.scarv_soc.gpio_io[15:0] +TOP.scarv_soc.gpio_out[15:0] @28 -TOP.scarv_soc.cpu_dmem_wen +TOP.scarv_soc.uart_rx +TOP.scarv_soc.uart_tx @200 - -@28 -TOP.scarv_soc.cpu_dmem_recv -TOP.scarv_soc.cpu_dmem_ack -TOP.scarv_soc.cpu_dmem_error -@22 -TOP.scarv_soc.cpu_dmem_rdata[31:0] -@1000200 --CPU Data Memory -@c00200 --CPU Trace +@29 +TOP.scarv_soc.cpu_int_ext @22 -TOP.scarv_soc.cpu_trs_instr[31:0] +TOP.scarv_soc.cpu_int_ext_cause[31:0] +TOP.scarv_soc.cpu_trs_pc[31:0] @2022 -^3 /home/work/scarv/scarv-soc/work/selfcheck/test_05_instr_bus_error/test_05_instr_bus_error.gtkwl +^1 /home/work/scarv/skywater/scarv-soc/work/fsbl/fsbl.gtkwl TOP.scarv_soc.cpu_trs_instr[31:0] @22 ->1 -TOP.scarv_soc.cpu_trs_pc[31:0] +TOP.scarv_soc.cpu_trs_instr[31:0] @28 ->0 TOP.scarv_soc.cpu_trs_valid -TOP.scarv_soc.i_scarv_cpu.i_pipeline.trap_cpu -@24 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.trap_cause[5:0] -@28 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.trap_int -TOP.scarv_soc.i_scarv_cpu.i_pipeline.cf_req -TOP.scarv_soc.i_scarv_cpu.i_pipeline.cf_ack -@22 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.cf_target[31:0] -@1401200 --CPU Trace -@c00200 --GPRs -@22 -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(0)[31:0] -+{1 - ra} TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(1)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(2)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(3)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(4)[31:0] -+{5 - t0} TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(5)[31:0] -+{6 - t1} TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(6)[31:0] -+{7 - t2} TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(7)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(8)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(9)[31:0] -+{10 - a0} TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(10)[31:0] -+{11 - a1} TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(11)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(12)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(13)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(14)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(15)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(16)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(17)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(18)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(19)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(20)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(21)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(22)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(23)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(24)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(25)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(26)[31:0] -TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(27)[31:0] -+{28 - t3} TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(28)[31:0] -+{29 - t4} TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(29)[31:0] -+{30 - t5} TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(30)[31:0] -+{31 - t6} TOP.scarv_soc.i_scarv_cpu.i_pipeline.i_gprs.gprs(31)[31:0] -@1401200 --GPRs -@1000200 --SCARV CPU -@800200 --Interconnect -@c00200 --Routing -@28 -TOP.scarv_soc.i_ic_top.ic_dmem_route_axi -TOP.scarv_soc.i_ic_top.ic_dmem_route_ram -TOP.scarv_soc.i_ic_top.ic_dmem_route_rom -TOP.scarv_soc.i_ic_top.ic_dmem_error -TOP.scarv_soc.i_ic_top.ic_imem_route_axi -TOP.scarv_soc.i_ic_top.ic_imem_route_ram -TOP.scarv_soc.i_ic_top.ic_imem_route_rom -TOP.scarv_soc.i_ic_top.ic_imem_error -@1401200 --Routing -@c00200 --Router IMEM ROM -@1401200 --Router IMEM ROM -@c00200 --IMEM RSP Tracker -@28 -TOP.scarv_soc.i_ic_top.imem_rsp_mask_err -TOP.scarv_soc.i_ic_top.imem_rsp_mask_ram -TOP.scarv_soc.i_ic_top.imem_rsp_mask_rom -@200 -- -@24 -TOP.scarv_soc.i_ic_top.i_ic_rsp_tracker_imem.head[1:0] -TOP.scarv_soc.i_ic_top.i_ic_rsp_tracker_imem.tail[1:0] -TOP.scarv_soc.i_ic_top.i_ic_rsp_tracker_imem.n_head[1:0] -TOP.scarv_soc.i_ic_top.i_ic_rsp_tracker_imem.n_tail[1:0] -@28 -TOP.scarv_soc.i_ic_top.i_ic_rsp_tracker_imem.new_req -TOP.scarv_soc.i_ic_top.i_ic_rsp_tracker_imem.new_rsp -TOP.scarv_soc.i_ic_top.i_ic_rsp_tracker_imem.ready -TOP.scarv_soc.i_ic_top.i_ic_rsp_tracker_imem.req_buffer(0)[2:0] -TOP.scarv_soc.i_ic_top.i_ic_rsp_tracker_imem.req_buffer(1)[2:0] -TOP.scarv_soc.i_ic_top.i_ic_rsp_tracker_imem.req_buffer(2)[2:0] @200 - @28 -TOP.scarv_soc.i_ic_top.i_ic_rsp_tracker_imem.requests[2:0] -TOP.scarv_soc.i_ic_top.i_ic_rsp_tracker_imem.response_gnt[2:0] -TOP.scarv_soc.i_ic_top.i_ic_rsp_tracker_imem.responses[2:0] -@1401200 --IMEM RSP Tracker -@c00200 --ROM -@28 -TOP.scarv_soc.i_ic_top.rom_imem_ack -@22 -TOP.scarv_soc.i_ic_top.rom_imem_addr[31:0] -@28 -TOP.scarv_soc.i_ic_top.rom_imem_error -TOP.scarv_soc.i_ic_top.rom_imem_gnt -@22 -TOP.scarv_soc.i_ic_top.rom_imem_rdata[31:0] -@28 -TOP.scarv_soc.i_ic_top.rom_imem_recv -TOP.scarv_soc.i_ic_top.rom_imem_req -@22 -TOP.scarv_soc.i_ic_top.rom_imem_strb[3:0] -TOP.scarv_soc.i_ic_top.rom_imem_wdata[31:0] -@28 -TOP.scarv_soc.i_ic_top.rom_imem_wen -@1401200 --ROM -@c00200 --DMEM Error Stub -@28 -TOP.scarv_soc.i_ic_top.i_error_stub_dmem.enable -TOP.scarv_soc.i_ic_top.i_error_stub_dmem.n_fsm[1:0] -TOP.scarv_soc.i_ic_top.i_error_stub_dmem.fsm[1:0] -TOP.scarv_soc.i_ic_top.i_error_stub_dmem.fsm_buf -TOP.scarv_soc.i_ic_top.i_error_stub_dmem.fsm_rsp -TOP.scarv_soc.i_ic_top.i_error_stub_dmem.fsm_wait -TOP.scarv_soc.i_ic_top.i_error_stub_dmem.mem_stalled -TOP.scarv_soc.i_ic_top.i_error_stub_dmem.mem_error -TOP.scarv_soc.i_ic_top.i_error_stub_dmem.mem_req -TOP.scarv_soc.i_ic_top.i_error_stub_dmem.mem_gnt -@22 -TOP.scarv_soc.i_ic_top.i_error_stub_dmem.mem_addr[31:0] -@28 -TOP.scarv_soc.i_ic_top.i_error_stub_dmem.mem_recv -TOP.scarv_soc.i_ic_top.i_error_stub_dmem.mem_ack -@1401200 --DMEM Error Stub -@c00200 --RAM -@22 -TOP.scarv_soc.i_ic_top.ram_imem_addr[31:0] -@28 -TOP.scarv_soc.i_ic_top.ram_imem_error -TOP.scarv_soc.i_ic_top.ram_imem_gnt -@22 -TOP.scarv_soc.i_ic_top.ram_imem_rdata[31:0] -@28 -TOP.scarv_soc.i_ic_top.ram_imem_recv -TOP.scarv_soc.i_ic_top.ram_imem_req -TOP.scarv_soc.i_ic_top.ram_imem_ack +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.i_pipeline.cf_req +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.i_pipeline.cf_ack @22 -TOP.scarv_soc.i_ic_top.ram_imem_strb[3:0] -TOP.scarv_soc.i_ic_top.ram_imem_wdata[31:0] +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.i_pipeline.cf_target[31:0] +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.i_pipeline.trap_cause[5:0] @28 -TOP.scarv_soc.i_ic_top.ram_imem_wen -@1401200 --RAM -@1000200 --Interconnect -@c00200 --AXI Bridge -@800200 --CPU REQ -@1000200 --CPU REQ -@800200 --CPU RSP -@1000200 --CPU RSP -@c00200 --AR -@1401200 --AR -@c00200 --R -@1401200 --R -@800200 --AW -@1000200 --AW -@800200 --W -@1000200 --W -@800200 --B -@1000200 --B -@1401200 --AXI Bridge -@c00200 --ROM IMEM Bus Bridge -@28 -TOP.scarv_soc.i_rom_imem_bus_bridge.g_clk -TOP.scarv_soc.i_rom_imem_bus_bridge.g_resetn -@22 -TOP.scarv_soc.i_rom_imem_bus_bridge.bram_addr[31:0] -@28 -TOP.scarv_soc.i_rom_imem_bus_bridge.bram_cen -@22 -TOP.scarv_soc.i_rom_imem_bus_bridge.bram_rdata[31:0] -@28 -TOP.scarv_soc.i_rom_imem_bus_bridge.bram_stall -@22 -TOP.scarv_soc.i_rom_imem_bus_bridge.bram_wdata[31:0] -TOP.scarv_soc.i_rom_imem_bus_bridge.bram_wstrb[3:0] -@28 -TOP.scarv_soc.i_rom_imem_bus_bridge.enable -TOP.scarv_soc.i_rom_imem_bus_bridge.fsm[1:0] -TOP.scarv_soc.i_rom_imem_bus_bridge.n_fsm[1:0] -TOP.scarv_soc.i_rom_imem_bus_bridge.fsm_buf -TOP.scarv_soc.i_rom_imem_bus_bridge.fsm_wait -TOP.scarv_soc.i_rom_imem_bus_bridge.fsm_rsp -@200 -- -@28 -TOP.scarv_soc.i_rom_imem_bus_bridge.mem_req -TOP.scarv_soc.i_rom_imem_bus_bridge.mem_gnt -@22 -TOP.scarv_soc.i_rom_imem_bus_bridge.mem_addr[31:0] -TOP.scarv_soc.i_rom_imem_bus_bridge.mem_strb[3:0] -TOP.scarv_soc.i_rom_imem_bus_bridge.mem_wdata[31:0] -@28 -TOP.scarv_soc.i_rom_imem_bus_bridge.mem_wen -@200 -- -@22 -TOP.scarv_soc.i_rom_imem_bus_bridge.buffer_addr[31:0] -TOP.scarv_soc.i_rom_imem_bus_bridge.buffer_wdata[31:0] -TOP.scarv_soc.i_rom_imem_bus_bridge.buffer_rdata[31:0] -TOP.scarv_soc.i_rom_imem_bus_bridge.buffer_wstrb[3:0] -@200 -- -@28 -TOP.scarv_soc.i_rom_imem_bus_bridge.mem_recv -TOP.scarv_soc.i_rom_imem_bus_bridge.mem_ack -TOP.scarv_soc.i_rom_imem_bus_bridge.mem_error -@22 -TOP.scarv_soc.i_rom_imem_bus_bridge.mem_rdata[31:0] -@1401200 --ROM IMEM Bus Bridge -@c00200 --ROM Instance -@28 -TOP.scarv_soc.i_rom.clka -TOP.scarv_soc.i_rom.rsta -@22 -TOP.scarv_soc.i_rom.DEPTH[31:0] -TOP.scarv_soc.i_rom.LW[31:0] -@820 -TOP.scarv_soc.i_rom.MEMH_FILE[2040:0] +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.i_pipeline.trap_cpu +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.i_pipeline.trap_int @200 - -@28 -TOP.scarv_soc.i_rom.ena -@22 -TOP.scarv_soc.i_rom.addra[9:0] -TOP.scarv_soc.i_rom.dina[31:0] -TOP.scarv_soc.i_rom.douta[31:0] -TOP.scarv_soc.i_rom.idx_a[9:0] -TOP.scarv_soc.i_rom.read_data_a[31:0] -TOP.scarv_soc.i_rom.wea[3:0] -@200 -- -@28 -TOP.scarv_soc.i_rom.enb -@22 -TOP.scarv_soc.i_rom.addrb[9:0] -TOP.scarv_soc.i_rom.web[3:0] -TOP.scarv_soc.i_rom.dinb[31:0] -TOP.scarv_soc.i_rom.doutb[31:0] -TOP.scarv_soc.i_rom.idx_b[9:0] -TOP.scarv_soc.i_rom.read_data_b[31:0] -@28 -TOP.scarv_soc.i_rom.rsta -@1401200 --ROM Instance @800200 --RAM Instance -@820 -TOP.scarv_soc.i_ram.MEMH_FILE[2040:0] +-SCARV_CPU +-Memory - DATA @28 -TOP.scarv_soc.i_ram.clka -@200 -- -@28 -TOP.scarv_soc.i_ram.ena -@22 -TOP.scarv_soc.i_ram.dina[31:0] -TOP.scarv_soc.i_ram.douta[31:0] -TOP.scarv_soc.i_ram.read_data_a[31:0] -TOP.scarv_soc.i_ram.wea[3:0] -@200 -- -@28 -TOP.scarv_soc.i_ram.enb +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.dmem_req +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.dmem_gnt +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.dmem_wen @22 -TOP.scarv_soc.i_ram.dinb[31:0] -TOP.scarv_soc.i_ram.doutb[31:0] -TOP.scarv_soc.i_ram.read_data_b[31:0] -TOP.scarv_soc.i_ram.web[3:0] -@1000200 --RAM Instance -@c00200 --RAM IMEM Bus Bridge +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.dmem_addr[31:0] +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.dmem_strb[3:0] +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.dmem_wdata[31:0] @28 -TOP.scarv_soc.i_ram_imem_bus_bridge.g_clk -TOP.scarv_soc.i_ram_imem_bus_bridge.g_resetn +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.dmem_error @22 -TOP.scarv_soc.i_ram_imem_bus_bridge.bram_addr[31:0] -@28 -TOP.scarv_soc.i_ram_imem_bus_bridge.bram_cen -@22 -TOP.scarv_soc.i_ram_imem_bus_bridge.bram_rdata[31:0] -@28 -TOP.scarv_soc.i_ram_imem_bus_bridge.bram_stall -@22 -TOP.scarv_soc.i_ram_imem_bus_bridge.bram_wdata[31:0] -TOP.scarv_soc.i_ram_imem_bus_bridge.bram_wstrb[3:0] -@200 -- -@22 -TOP.scarv_soc.i_ram_imem_bus_bridge.buffer_addr[31:0] -TOP.scarv_soc.i_ram_imem_bus_bridge.buffer_rdata[31:0] -TOP.scarv_soc.i_ram_imem_bus_bridge.buffer_wdata[31:0] -TOP.scarv_soc.i_ram_imem_bus_bridge.buffer_wstrb[3:0] +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.dmem_rdata[31:0] @200 - @28 -TOP.scarv_soc.i_ram_imem_bus_bridge.enable -TOP.scarv_soc.i_ram_imem_bus_bridge.mem_ack -@22 -TOP.scarv_soc.i_ram_imem_bus_bridge.mem_addr[31:0] -@28 -TOP.scarv_soc.i_ram_imem_bus_bridge.mem_error -TOP.scarv_soc.i_ram_imem_bus_bridge.mem_gnt -@22 -TOP.scarv_soc.i_ram_imem_bus_bridge.mem_rdata[31:0] -@28 -TOP.scarv_soc.i_ram_imem_bus_bridge.mem_recv -TOP.scarv_soc.i_ram_imem_bus_bridge.mem_req +TOP.scarv_soc.i_scarv_ccx_top.i_interconnect.i_router_dmem.rsp_route_d0 +TOP.scarv_soc.i_scarv_ccx_top.i_interconnect.i_router_dmem.rsp_route_d1 +TOP.scarv_soc.i_scarv_ccx_top.i_interconnect.i_router_dmem.rsp_route_d2 +TOP.scarv_soc.i_scarv_ccx_top.i_interconnect.i_router_dmem.rsp_route_d3 +TOP.scarv_soc.i_scarv_ccx_top.i_interconnect.i_router_dmem.rsp_route_none +@1000200 +-Memory - DATA +@800200 +-Memory - INSTRS @22 -TOP.scarv_soc.i_ram_imem_bus_bridge.mem_strb[3:0] -TOP.scarv_soc.i_ram_imem_bus_bridge.mem_wdata[31:0] -@28 -TOP.scarv_soc.i_ram_imem_bus_bridge.mem_wen -@1401200 --RAM IMEM Bus Bridge -@c00200 --ROM DMEM Bus Bridge +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.imem_addr[31:0] @28 -TOP.scarv_soc.i_rom_dmem_bus_bridge.g_clk -TOP.scarv_soc.i_rom_dmem_bus_bridge.g_resetn -TOP.scarv_soc.i_rom_dmem_bus_bridge.enable -TOP.scarv_soc.i_rom_dmem_bus_bridge.n_fsm[1:0] -TOP.scarv_soc.i_rom_dmem_bus_bridge.fsm[1:0] -TOP.scarv_soc.i_rom_dmem_bus_bridge.fsm_buf -TOP.scarv_soc.i_rom_dmem_bus_bridge.fsm_rsp -TOP.scarv_soc.i_rom_dmem_bus_bridge.fsm_wait -TOP.scarv_soc.i_rom_dmem_bus_bridge.mem_req -TOP.scarv_soc.i_rom_dmem_bus_bridge.mem_gnt -TOP.scarv_soc.i_rom_dmem_bus_bridge.mem_recv -TOP.scarv_soc.i_rom_dmem_bus_bridge.mem_ack +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.imem_error +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.imem_gnt @22 -TOP.scarv_soc.i_rom_dmem_bus_bridge.mem_addr[31:0] +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.imem_rdata[31:0] @28 -TOP.scarv_soc.i_rom_dmem_bus_bridge.mem_error -TOP.scarv_soc.i_rom_dmem_bus_bridge.mem_stalled +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.imem_req @22 -TOP.scarv_soc.i_rom_dmem_bus_bridge.mem_strb[3:0] -TOP.scarv_soc.i_rom_dmem_bus_bridge.mem_wdata[31:0] -TOP.scarv_soc.i_rom_dmem_bus_bridge.mem_rdata[31:0] +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.imem_strb[3:0] +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.imem_wdata[31:0] @28 -TOP.scarv_soc.i_rom_dmem_bus_bridge.mem_wen -@200 -- -@22 -TOP.scarv_soc.i_rom_dmem_bus_bridge.buffer_addr[31:0] -TOP.scarv_soc.i_rom_dmem_bus_bridge.buffer_rdata[31:0] -TOP.scarv_soc.i_rom_dmem_bus_bridge.buffer_wdata[31:0] -TOP.scarv_soc.i_rom_dmem_bus_bridge.buffer_wstrb[3:0] +TOP.scarv_soc.i_scarv_ccx_top.i_scarv_cpu.imem_wen @200 - -@22 -TOP.scarv_soc.i_rom_dmem_bus_bridge.bram_addr[31:0] @28 -TOP.scarv_soc.i_rom_dmem_bus_bridge.bram_cen -@22 -TOP.scarv_soc.i_rom_dmem_bus_bridge.bram_rdata[31:0] -@28 -TOP.scarv_soc.i_rom_dmem_bus_bridge.bram_ready -TOP.scarv_soc.i_rom_dmem_bus_bridge.bram_stall -@22 -TOP.scarv_soc.i_rom_dmem_bus_bridge.bram_wdata[31:0] -TOP.scarv_soc.i_rom_dmem_bus_bridge.bram_wstrb[3:0] -@1401200 --ROM DMEM Bus Bridge +TOP.scarv_soc.i_scarv_ccx_top.i_interconnect.i_router_imem.rsp_route_d0 +TOP.scarv_soc.i_scarv_ccx_top.i_interconnect.i_router_imem.rsp_route_d1 +TOP.scarv_soc.i_scarv_ccx_top.i_interconnect.i_router_imem.rsp_route_d2 +TOP.scarv_soc.i_scarv_ccx_top.i_interconnect.i_router_imem.rsp_route_d3 +TOP.scarv_soc.i_scarv_ccx_top.i_interconnect.i_router_imem.rsp_route_none +@1000200 +-Memory - INSTRS +-SCARV_CPU +-SCARV_SOC [pattern_trace] 1 [pattern_trace] 0 diff --git a/flow/selfcheck/Makefile.in b/flow/selfcheck/Makefile.in index 779e914..6c3eb3e 100644 --- a/flow/selfcheck/Makefile.in +++ b/flow/selfcheck/Makefile.in @@ -171,9 +171,12 @@ SELFCHECK_RUN_TARGETS += selfcheck-run-$(call map_selfcheck_test_name,${1}) endef -$(foreach TEST,$(SELFCHECK_TESTS),\ - $(eval $(call add_target_selfcheck_test,$(TEST)))\ -) +# +# TODO: Re-instate the selfchecking tests +# +#$(foreach TEST,$(SELFCHECK_TESTS),\ +# $(eval $(call add_target_selfcheck_test,$(TEST)))\ +#) selfcheck-run-all: $(SELFCHECK_RUN_TARGETS) diff --git a/flow/verilator/Makefile.in b/flow/verilator/Makefile.in index 5ddad29..9d5c681 100644 --- a/flow/verilator/Makefile.in +++ b/flow/verilator/Makefile.in @@ -2,31 +2,30 @@ VERILATOR = $(VERILATOR_ROOT)/bin/verilator VL_DIR = $(SOC_WORK)/verilator -VL_OUT = $(SOC_WORK)/verilator/verilated VL_WAVES = $(VL_DIR)/waves.vcd VL_TIMEOUT = 10000 VL_ARGS = -VL_CSRC_DIR =$(SOC_HOME)/verif/scarv-soc - -VL_CSRC = $(VL_CSRC_DIR)/main.cpp \ - $(VL_CSRC_DIR)/dut_wrapper.cpp \ - $(VL_CSRC_DIR)/testbench.cpp - VL_FLAGS = --cc -CFLAGS "-O2" -O3 -CFLAGS -g\ - -I$(SCARV_CPU)/rtl/core \ --exe --trace \ - --top-module scarv_soc $(VL_BUILD_FLAGS) + $(VL_BUILD_FLAGS) -VL_RTL_MANIFEST = $(SOC_HOME)/flow/verilator/scarv-soc-rtl.manifest -VL_CPP_MANIFEST = $(SOC_HOME)/flow/verilator/scarv-soc-testbench.manifest -SCARV_CPU_MANIFEST=$(SCARV_CPU)/flow/verilator/core-rtl.manifest +VL_SOC_CMD = $(SOC_HOME)/flow/verilator/scarv-soc-tb.cmd -# Defined in $(SOC_HOME)/src/fsbl/Makefile.in -BRAM_ROM_MEMH = $(FSBL_HEX) +# +# 1. Build dir +# 2. Top module name +define map_vl_makefile +${1}/V${2}.mk +endef -.PHONY: $(VL_CSRC) +# +# 1. Build dir +# 2. Top module name +define map_vl_exe +${1}/${2} +endef # # Add a new verilator build @@ -38,26 +37,28 @@ BRAM_ROM_MEMH = $(FSBL_HEX) # define tgt_verilator_build -${1} : $(VL_CSRC) +$(call map_vl_makefile,${2},${1}) : @mkdir -p ${2} - $(VERILATOR) $(VL_FLAGS) --Mdir ${2} -o ${1} \ - -GBRAM_ROM_MEMH_FILE="\"$(strip ${3})\"" \ - -GBRAM_RAM_MEMH_FILE="\"$(strip ${4})\"" \ - -f $(VL_RTL_MANIFEST) \ - -f $(VL_CPP_MANIFEST) \ - -f $(SCARV_CPU_MANIFEST) + $(VERILATOR) $(VL_FLAGS) --Mdir ${2} -o $(call map_vl_exe,${2},${1}) \ + -GCCX_ROM_INIT_FILE="\"$(strip ${3})\"" \ + -GCCX_RAM_INIT_FILE="\"$(strip ${4})\"" \ + -DSCARV_SOC_VERILATOR \ + -f $(VL_SOC_CMD) + $(MAKE) -C ${2} -f Vscarv_soc.mk + +verilator-build-${1}: $(call map_vl_makefile,${2},${1}) $(MAKE) -C ${2} -f Vscarv_soc.mk endef -$(eval $(call tgt_verilator_build,$(VL_OUT),$(VL_DIR),rom.hex,ram.hex)) +$(eval $(call tgt_verilator_build,scarv-soc,$(VL_DIR),rom.hex,ram.hex)) -verilator-build: $(VL_OUT) - cp $(FSBL_HEX) $(dir $(VL_OUT))rom.hex - cp $(FSBL_HEX) $(dir $(VL_OUT))ram.hex +VL_SCARV_SOC=$(call map_vl_exe,$(VL_DIR),scarv-soc) -verilator-run-waves: $(VL_OUT) $(FSBL_HEX) - cd $(dir $(VL_OUT)) && $(VL_OUT) $(VL_ARGS) \ +verilator-run-waves: $(VL_SCARV_SOC) $(FSBL_HEX) + cp $(FSBL_HEX) $(dir $(VL_SCARV_SOC))/rom.hex + touch $(dir $(VL_SCARV_SOC))/ram.hex + cd $(dir $(VL_SCARV_SOC)) && $(VL_SCARV_SOC) $(VL_ARGS) \ +WAVES=$(VL_WAVES) \ +TIMEOUT=$(VL_TIMEOUT) diff --git a/flow/verilator/manifest-soc-rtl.txt b/flow/verilator/manifest-soc-rtl.txt new file mode 100644 index 0000000..b71b7b7 --- /dev/null +++ b/flow/verilator/manifest-soc-rtl.txt @@ -0,0 +1,5 @@ +$SCARV_SOC/rtl/gpio/gpio_top.sv +$SCARV_SOC/rtl/uart/uart_top.sv +$SCARV_SOC/rtl/soc/scarv_soc_periph_top.sv +$SCARV_SOC/rtl/soc/scarv_soc.sv + diff --git a/flow/verilator/manifest-soc-tb.txt b/flow/verilator/manifest-soc-tb.txt new file mode 100644 index 0000000..2522d56 --- /dev/null +++ b/flow/verilator/manifest-soc-tb.txt @@ -0,0 +1,4 @@ +$SOC_HOME/verif/verilator/dut_wrapper.cpp +$SOC_HOME/verif/verilator/testbench.cpp +$SOC_HOME/verif/verilator/main.cpp + diff --git a/flow/verilator/scarv-soc-rtl.manifest b/flow/verilator/scarv-soc-rtl.manifest deleted file mode 100644 index 4fd3df4..0000000 --- a/flow/verilator/scarv-soc-rtl.manifest +++ /dev/null @@ -1,28 +0,0 @@ - -// -// Reads all of the sources for the design to be verilated -// - -// -// Interconnect sources -$SOC_HOME/rtl/ic/ic_addr_decode.v -$SOC_HOME/rtl/ic/ic_cpu_bus_bram_bridge.v -$SOC_HOME/rtl/ic/ic_cpu_bus_axi_bridge.v -$SOC_HOME/rtl/ic/ic_rsp_tracker.v -$SOC_HOME/rtl/ic/ic_error_rsp_stub.v -$SOC_HOME/rtl/ic/ic_top.v - -// -// Random number generator sources -$SOC_HOME/rtl/rng/scarv_rng_lfsr.v -$SOC_HOME/rtl/rng/scarv_rng_top.v - -// -// Memories -$SOC_HOME/rtl/mem/scarv_soc_bram_dual_sim.v - - -// -// SCARV SoC top level sources. -$SOC_HOME/rtl/soc/scarv_soc.v - diff --git a/flow/verilator/scarv-soc-tb.cmd b/flow/verilator/scarv-soc-tb.cmd new file mode 100644 index 0000000..53e1e24 --- /dev/null +++ b/flow/verilator/scarv-soc-tb.cmd @@ -0,0 +1,5 @@ +-I$SCARV_CPU/rtl/core +--top-module scarv_soc +-f $SCARV_CPU/flow/verilator/manifest-ccx-rtl.txt +-f $SCARV_SOC/flow/verilator/manifest-soc-rtl.txt +-f $SCARV_SOC/flow/verilator/manifest-soc-tb.txt diff --git a/flow/verilator/scarv-soc-testbench.manifest b/flow/verilator/scarv-soc-testbench.manifest deleted file mode 100644 index 696905b..0000000 --- a/flow/verilator/scarv-soc-testbench.manifest +++ /dev/null @@ -1,11 +0,0 @@ - -$SOC_HOME/verif/scarv-soc/memory_bus/memory_bus.cpp -$SOC_HOME/verif/scarv-soc/memory_bus/memory_device.cpp -$SOC_HOME/verif/scarv-soc/memory_bus/memory_device_ram.cpp -$SOC_HOME/verif/scarv-soc/memory_bus/memory_device_uart.cpp -$SOC_HOME/verif/scarv-soc/memory_bus/memory_device_gpio.cpp -$SOC_HOME/verif/scarv-soc/axi4lite/a4l_slave_agent.cpp -$SOC_HOME/verif/scarv-soc/dut_wrapper.cpp -$SOC_HOME/verif/scarv-soc/testbench.cpp -$SOC_HOME/verif/scarv-soc/main.cpp - diff --git a/rtl/gpio/gpio_top.sv b/rtl/gpio/gpio_top.sv new file mode 100644 index 0000000..6200395 --- /dev/null +++ b/rtl/gpio/gpio_top.sv @@ -0,0 +1,35 @@ + +// +// module: gpio_top +// +// Top level of the GPIO peripheral +// +module gpio_top ( + +input wire g_clk , // Gated clock +output wire g_clk_req , // Clock request +input wire g_resetn , // Global Active low sync reset. + +output wire [GPION:0] gpio_io , // GPIO wire direction. 1=in, 0=out. +output wire [GPION:0] gpio_out , // GPIO outputs. +input wire [GPION:0] gpio_in , // GPIO inputs. + +scarv_ccx_memif.RSP memif // Memory request interface. + +); + +//! Number of GPIO pins. +parameter PERIPH_GPIO_NUM = 16; +localparam GPION = PERIPH_GPIO_NUM - 1; + +// +// Stub out for now +assign gpio_io = {PERIPH_GPIO_NUM{1'b0}}; +assign gpio_out = {PERIPH_GPIO_NUM{1'b0}}; + +assign memif.gnt = 1'b1; +assign memif.error = 1'b0; + +endmodule + + diff --git a/rtl/soc/scarv_soc.sv b/rtl/soc/scarv_soc.sv new file mode 100644 index 0000000..42b83a8 --- /dev/null +++ b/rtl/soc/scarv_soc.sv @@ -0,0 +1,156 @@ + +// +// module: scarv_soc +// +// Top level of the SCARV SoC core module. +// +module scarv_soc ( + +input wire f_clk , // Free running clock. +input wire g_resetn , // Global Active low sync reset. + +input wire uart_rx , // UART Recieve +output wire uart_tx , // UART Transmit + +output wire [GPION:0] gpio_io , // GPIO wire direction. 1=in, 0=out. +output wire [GPION:0] gpio_out , // GPIO outputs. +input wire [GPION:0] gpio_in // GPIO inputs. + +`ifdef SCARV_SOC_VERILATOR , +output wire trs_valid , // CPU trace word valid +output wire [31:0] trs_pc , // CPU trace program counter +output wire [31:0] trs_instr // CPU traced instruction. +`endif + +); + +// +// SCARV CPU Core Complex Parameters +// ------------------------------------------------------------ + +parameter CCX_MEM_ROM_BASE = 32'h0000_0000; //! Base address of ROM +parameter CCX_MEM_ROM_SIZE = 32'h0000_0400; //! Size in bytes of ROM. +parameter CCX_MEM_RAM_BASE = 32'h0001_0000; //! Base address of RAM +parameter CCX_MEM_RAM_SIZE = 32'h0001_0000; //! Size in bytes of RAM. +parameter CCX_MEM_MMIO_BASE = 32'h0002_0000; //! Base address of MMIO. +parameter CCX_MEM_MMIO_SIZE = 32'h0000_0100; //! Size in bytes of MMIO +parameter CCX_MEM_EXT_BASE = 32'h1000_0000; //! Base address of EXT Mem. +parameter CCX_MEM_EXT_SIZE = 32'h1000_0000; //! Size in bytes of EXT Mem. + +//! Base addr of UART. +parameter PERIPH_MEM_UART_BASE = CCX_MEM_EXT_BASE | 32'h0000_0000; + +//! Base addr of GPIO. +parameter PERIPH_MEM_GPIO_BASE = CCX_MEM_EXT_BASE | 32'h0000_1000; + +//! Reset value for the mtimecmp memory mapped register. +parameter CCX_CPU_MTIMECMP_RESET = 64'hFFFF_FFFF_FFFF_FFFF; + +//! Reset value for the program counter. +parameter CCX_CPU_PC_RESET = 32'b0; + +/* verilator lint_off WIDTH */ +//! Memory initialisation file for the ROM. +parameter [255*8-1:0] CCX_ROM_INIT_FILE = "rom.hex"; +parameter [255*8-1:0] CCX_RAM_INIT_FILE = "ram.hex"; +/* verilator lint_on WIDTH */ + +// +// Testbench code for Verilator +// ------------------------------------------------------------ + +`ifdef SCARV_SOC_VERILATOR + assign trs_valid = cpu_trs_valid; + assign trs_instr = cpu_trs_instr; + assign trs_pc = cpu_trs_pc ; +`endif + +// +// Peripheral Sub-system Parameters +// ------------------------------------------------------------ + +//! Number of GPIO pins. +parameter PERIPH_GPIO_NUM = 16; +localparam GPION = PERIPH_GPIO_NUM - 1; + + +// +// Inter sub-system wiring. +// ------------------------------------------------------------ + +wire cpu_int_ext ; // CPU External interrupt. +wire [31:0] cpu_int_ext_cause ; // CPU External interrupt cause. + +wire [31:0] cpu_trs_pc ; // CPU Trace program counter. +wire [31:0] cpu_trs_instr ; // CPU Trace instruction. +wire cpu_trs_valid ; // CPU Trace output valid. + +scarv_ccx_memif #() ccx_memif() ; // Core complex memory interface + +// +// Clock request and gating. +// ------------------------------------------------------------ + +wire g_clk_uart ; // UART Clock +wire g_clk_gpio ; // GPIO Clock + +wire g_clk_req_uart ; // UART Clock request +wire g_clk_req_gpio ; // GPIO Clock request + +// +// Core Complex Subsystem instance +// ------------------------------------------------------------ + +// +// instance: scarv_ccx_top +// +// Top level module of the core complex. +// +scarv_ccx_top #( +.ROM_BASE (CCX_MEM_ROM_BASE ), +.ROM_SIZE (CCX_MEM_ROM_SIZE ), +.RAM_BASE (CCX_MEM_RAM_BASE ), +.RAM_SIZE (CCX_MEM_RAM_SIZE ), +.MMIO_BASE (CCX_MEM_MMIO_BASE ), +.MMIO_SIZE (CCX_MEM_MMIO_SIZE ), +.EXT_BASE (CCX_MEM_EXT_BASE ), +.EXT_SIZE (CCX_MEM_EXT_SIZE ), +.MTIMECMP_RESET (CCX_CPU_MTIMECMP_RESET ), +.PC_RESET (CCX_CPU_PC_RESET ), +.ROM_INIT_FILE (CCX_ROM_INIT_FILE ), +.RAM_INIT_FILE (CCX_RAM_INIT_FILE ) +) i_scarv_ccx_top ( +.f_clk (f_clk ), // Free-running clock. +.g_resetn (g_resetn ), // Synchronous active low reset. +.int_ext (cpu_int_ext ), // External interrupt. +.int_ext_cause (cpu_int_ext_cause ), // External interrupt cause. +.cpu_trs_pc (cpu_trs_pc ), // Trace program counter. +.cpu_trs_instr (cpu_trs_instr ), // Trace instruction. +.cpu_trs_valid (cpu_trs_valid ), // Trace output valid. +.if_ext (ccx_memif ) // External memory requests. +); + + +// +// Core Complex Subsystem instance +// ------------------------------------------------------------ +scarv_soc_periph_top #( +.BASE_UART (PERIPH_MEM_UART_BASE ), +.BASE_GPIO (PERIPH_MEM_GPIO_BASE ), +.PERIPH_GPIO_NUM (PERIPH_GPIO_NUM ) +) i_scarv_soc_periph_top ( +.f_clk (f_clk ), // Free running clock. +.g_clk_uart (g_clk_uart ), // UART Clock +.g_clk_gpio (g_clk_gpio ), // GPIO Clock +.g_clk_req_uart (g_clk_req_uart ), // UART Clock request +.g_clk_req_gpio (g_clk_req_gpio ), // GPIO Clock request +.g_resetn (g_resetn ), // Global Active low sync reset. +.uart_rx (uart_rx ), // UART Recieve +.uart_tx (uart_tx ), // UART Transmit +.gpio_io (gpio_io ), // GPIO wire direction. +.gpio_out (gpio_out ), // GPIO outputs. +.gpio_in (gpio_in ), // GPIO inputs. +.memif (ccx_memif ) // Memory requests. +); + +endmodule diff --git a/rtl/soc/scarv_soc.v b/rtl/soc/scarv_soc.v deleted file mode 100644 index 0105cd8..0000000 --- a/rtl/soc/scarv_soc.v +++ /dev/null @@ -1,513 +0,0 @@ - -// -// module: scarv_soc -// -// Top level of the SCARV SoC core module. -// -module scarv_soc ( -input wire g_clk , -input wire g_resetn , - -input wire cpu_int_nmi , // Non-maskable interrupt. -input wire cpu_int_external , // External interrupt trigger line. -input wire [ 3:0] cpu_int_ext_cause, // External interrupt cause -input wire cpu_int_software , // Software interrupt trigger line. - -output wire m0_awvalid , // -input wire m0_awready , // -output wire [31:0] m0_awaddr , // -output wire [ 2:0] m0_awprot , // - -output wire m0_wvalid , // -input wire m0_wready , // -output wire [31:0] m0_wdata , // -output wire [ 3:0] m0_wstrb , // - -input wire m0_bvalid , // -output wire m0_bready , // -input wire [ 1:0] m0_bresp , // - -output wire m0_arvalid , // -input wire m0_arready , // -output wire [31:0] m0_araddr , // -output wire [ 2:0] m0_arprot , // - -input wire m0_rvalid , // -output wire m0_rready , // -input wire [ 1:0] m0_rresp , // -input wire [31:0] m0_rdata // -); - -// -// SCARV CPU Parameters -// ------------------------------------------------------------ - -// Value taken by the PC on a reset. -parameter SCARV_CPU_PC_RESET_VALUE = 32'h1000_0000; - -// -// BRAM Parameters -// ------------------------------------------------------------ - -/* verilator lint_off WIDTH */ -parameter [255*8:0] BRAM_ROM_MEMH_FILE = ""; -parameter [255*8:0] BRAM_RAM_MEMH_FILE = ""; -/* verilator lint_on WIDTH */ - -// Size of the ROM memory in bytes. -parameter BRAM_ROM_SIZE = 1024; - -// Size of the RAM memory in bytes. -parameter BRAM_RAM_SIZE = 'hFFFF; - -// Width of ram bus signals. -localparam RAM_W = $clog2(BRAM_RAM_SIZE); -localparam RAM_R = RAM_W-1; - -// RAM mask and range parameters for ic_addr_decode -localparam MAP_RAM_MASK = (32'hFFFF_FFFF >> RAM_W) << RAM_W; -localparam MAP_RAM_RANGE = ~MAP_RAM_MASK; - -// -// Interconnect parameters -// ------------------------------------------------------------ - -// Turn the AXI bridge on (1) or off (0). -parameter IC_ENABLE_AXI_BRIDGE = 1; - -// -// RNG Parameters -// ------------------------------------------------------------ - -/* -Which instance of the RNG should we use? -Valid values are one of the following strings: -- "lfsr" - A simple 32-bit linear feedback shift register. -*/ -parameter RNG_TYPE = "lfsr"; - -// -// SCARV CPU Interface Wires -// ------------------------------------------------------------ - -// CPU trace signals are make verilator public so that in the verilated -// model, the testbench can probe down and interface with them. -wire [31:0] cpu_trs_pc /*verilator public*/; // Trace program counter. -wire [31:0] cpu_trs_instr /*verilator public*/; // Trace instruction. -wire cpu_trs_valid /*verilator public*/; // Trace output valid. - -wire [31:0] cpu_leak_prng ; // Current PRNG value. -wire cpu_leak_fence_unc0 ; // uncore 0 fence -wire cpu_leak_fence_unc1 ; // uncore 1 fence -wire cpu_leak_fence_unc2 ; // uncore 2 fence - -wire cpu_rng_req_valid ; // Signal a new request to the RNG -wire [ 2:0] cpu_rng_req_op ; // Operation to perform on the RNG -wire [31:0] cpu_rng_req_data ; // Suplementary seed/init data -wire cpu_rng_req_ready ; // RNG accepts request -wire cpu_rng_rsp_valid ; // RNG response data valid -wire [ 2:0] cpu_rng_rsp_status ; // RNG status -wire [31:0] cpu_rng_rsp_data ; // RNG response / sample data. -wire cpu_rng_rsp_ready ; // CPU accepts response. - -wire cpu_imem_req ; // Start memory request -wire cpu_imem_wen ; // Write enable -wire [3:0] cpu_imem_strb ; // Write strobe -wire [31:0] cpu_imem_wdata ; // Write data -wire [31:0] cpu_imem_addr ; // Read/Write address -wire cpu_imem_gnt ; // request accepted -wire cpu_imem_recv ; // Instruction memory recieve response. -wire cpu_imem_ack ; // Instruction memory ack response. -wire cpu_imem_error ; // Error -wire [31:0] cpu_imem_rdata ; // Read data - -wire cpu_dmem_req ; // Start memory request -wire cpu_dmem_wen ; // Write enable -wire [ 3:0] cpu_dmem_strb ; // Write strobe -wire [31:0] cpu_dmem_wdata ; // Write data -wire [31:0] cpu_dmem_addr ; // Read/Write address -wire cpu_dmem_gnt ; // request accepted -wire cpu_dmem_recv ; // Data memory recieve response. -wire cpu_dmem_ack ; // Data memory ack response. -wire cpu_dmem_error ; // Error -wire [31:0] cpu_dmem_rdata ; // Read data - -wire cpu_int_mtime ; // Machine timer interrupt triggered. - -// -// Memory peripheral routing wires. -// ------------------------------------------------------------ - -wire rom_imem_req ; // Start memory request -wire rom_imem_wen ; // Write enable -wire [ 3:0] rom_imem_strb ; // Write strobe -wire [31:0] rom_imem_wdata ; // Write data -wire [31:0] rom_imem_addr ; // Read/Write address -wire rom_imem_gnt ; // request accepted -wire rom_imem_recv ; // Instruction memory recieve response. -wire rom_imem_ack ; // Instruction memory ack response. -wire rom_imem_error ; // Error -wire [31:0] rom_imem_rdata ; // Read data - -wire ram_imem_req ; // Start memory request -wire ram_imem_wen ; // Write enable -wire [ 3:0] ram_imem_strb ; // Write strobe -wire [31:0] ram_imem_wdata ; // Write data -wire [31:0] ram_imem_addr ; // Read/Write address -wire ram_imem_gnt ; // request accepted -wire ram_imem_recv ; // Instruction memory recieve response. -wire ram_imem_ack ; // Instruction memory ack response. -wire ram_imem_error ; // Error -wire [31:0] ram_imem_rdata ; // Read data - -wire rom_dmem_req ; // Start memory request -wire rom_dmem_wen ; // Write enable -wire [ 3:0] rom_dmem_strb ; // Write strobe -wire [31:0] rom_dmem_wdata ; // Write data -wire [31:0] rom_dmem_addr ; // Read/Write address -wire rom_dmem_gnt ; // request accepted -wire rom_dmem_recv ; // Instruction memory recieve response. -wire rom_dmem_ack ; // Instruction memory ack response. -wire rom_dmem_error ; // Error -wire [31:0] rom_dmem_rdata ; // Read data - -wire ram_dmem_req ; // Start memory request -wire ram_dmem_wen ; // Write enable -wire [ 3:0] ram_dmem_strb ; // Write strobe -wire [31:0] ram_dmem_wdata ; // Write data -wire [31:0] ram_dmem_addr ; // Read/Write address -wire ram_dmem_gnt ; // request accepted -wire ram_dmem_recv ; // Instruction memory recieve response. -wire ram_dmem_ack ; // Instruction memory ack response. -wire ram_dmem_error ; // Error -wire [31:0] ram_dmem_rdata ; // Read data - - -// -// SCARV CPU core instance. -// ------------------------------------------------------------ - -frv_core #( -.FRV_PC_RESET_VALUE (SCARV_CPU_PC_RESET_VALUE ), -.TRACE_INSTR_WORD (1'b1 ), -.BRAM_REGFILE (1'b1 ) -) i_scarv_cpu( -.g_clk (g_clk ), // global clock -.g_resetn (g_resetn ), // synchronous reset -.trs_pc (cpu_trs_pc ), // Trace program counter. -.trs_instr (cpu_trs_instr ), // Trace instruction. -.trs_valid (cpu_trs_valid ), // Trace output valid. -.leak_prng (cpu_leak_prng ), // Current PRNG value. -.leak_fence_unc0(cpu_leak_fence_unc0), // uncore 0 fence -.leak_fence_unc1(cpu_leak_fence_unc1), // uncore 1 fence -.leak_fence_unc2(cpu_leak_fence_unc2), // uncore 2 fence -.rng_req_valid (cpu_rng_req_valid ), // Signal a new request to the RNG -.rng_req_op (cpu_rng_req_op ), // Operation to perform on the RNG -.rng_req_data (cpu_rng_req_data ), // Suplementary seed/init data -.rng_req_ready (cpu_rng_req_ready ), // RNG accepts request -.rng_rsp_valid (cpu_rng_rsp_valid ), // RNG response data valid -.rng_rsp_status (cpu_rng_rsp_status ), // RNG status -.rng_rsp_data (cpu_rng_rsp_data ), // RNG response / sample data. -.rng_rsp_ready (cpu_rng_rsp_ready ), // CPU accepts response. -.int_nmi (cpu_int_nmi ), // Non-maskable interrupt -.int_external (cpu_int_external ), // External interrupt trigger line. -.int_extern_cause(cpu_int_ext_cause ), // External interrupt cause -.int_software (cpu_int_software ), // Software interrupt trigger line. -.int_mtime (cpu_int_mtime ), // Machine timer interrupt triggered. -.imem_req (cpu_imem_req ), // Start memory request -.imem_wen (cpu_imem_wen ), // Write enable -.imem_strb (cpu_imem_strb ), // Write strobe -.imem_wdata (cpu_imem_wdata ), // Write data -.imem_addr (cpu_imem_addr ), // Read/Write address -.imem_gnt (cpu_imem_gnt ), // request accepted -.imem_recv (cpu_imem_recv ), // Instruction memory recieve response. -.imem_ack (cpu_imem_ack ), // Instruction memory ack response. -.imem_error (cpu_imem_error ), // Error -.imem_rdata (cpu_imem_rdata ), // Read data -.dmem_req (cpu_dmem_req ), // Start memory request -.dmem_wen (cpu_dmem_wen ), // Write enable -.dmem_strb (cpu_dmem_strb ), // Write strobe -.dmem_wdata (cpu_dmem_wdata ), // Write data -.dmem_addr (cpu_dmem_addr ), // Read/Write address -.dmem_gnt (cpu_dmem_gnt ), // request accepted -.dmem_recv (cpu_dmem_recv ), // Data memory recieve response. -.dmem_ack (cpu_dmem_ack ), // Data memory ack response. -.dmem_error (cpu_dmem_error ), // Error -.dmem_rdata (cpu_dmem_rdata ) // Read data -); - - -// -// Memory Interconnect Instance -// ------------------------------------------------------------ - -ic_top #( -.ENABLE_AXI_BRIDGE(IC_ENABLE_AXI_BRIDGE), -.MAP_RAM_MASK (MAP_RAM_MASK ), -.MAP_RAM_RANGE (MAP_RAM_RANGE ) -) i_ic_top ( -.g_clk (g_clk ), -.g_resetn (g_resetn ), -.cpu_imem_req (cpu_imem_req ), // Start memory request -.cpu_imem_wen (cpu_imem_wen ), // Write enable -.cpu_imem_strb (cpu_imem_strb ), // Write strobe -.cpu_imem_wdata (cpu_imem_wdata ), // Write data -.cpu_imem_addr (cpu_imem_addr ), // Read/Write address -.cpu_imem_gnt (cpu_imem_gnt ), // request accepted -.cpu_imem_recv (cpu_imem_recv ), // Instruction memory recieve response. -.cpu_imem_ack (cpu_imem_ack ), // Instruction memory ack response. -.cpu_imem_error (cpu_imem_error ), // Error -.cpu_imem_rdata (cpu_imem_rdata ), // Read data -.cpu_dmem_req (cpu_dmem_req ), // Start memory request -.cpu_dmem_wen (cpu_dmem_wen ), // Write enable -.cpu_dmem_strb (cpu_dmem_strb ), // Write strobe -.cpu_dmem_wdata (cpu_dmem_wdata ), // Write data -.cpu_dmem_addr (cpu_dmem_addr ), // Read/Write address -.cpu_dmem_gnt (cpu_dmem_gnt ), // request accepted -.cpu_dmem_recv (cpu_dmem_recv ), // Data memory recieve response. -.cpu_dmem_ack (cpu_dmem_ack ), // Data memory ack response. -.cpu_dmem_error (cpu_dmem_error ), // Error -.cpu_dmem_rdata (cpu_dmem_rdata ), // Read data -.rom_imem_req (rom_imem_req ), // Start memory request -.rom_imem_wen (rom_imem_wen ), // Write enable -.rom_imem_strb (rom_imem_strb ), // Write strobe -.rom_imem_wdata (rom_imem_wdata ), // Write data -.rom_imem_addr (rom_imem_addr ), // Read/Write address -.rom_imem_gnt (rom_imem_gnt ), // request accepted -.rom_imem_recv (rom_imem_recv ), // Instruction memory recieve response. -.rom_imem_ack (rom_imem_ack ), // Instruction memory ack response. -.rom_imem_error (rom_imem_error ), // Error -.rom_imem_rdata (rom_imem_rdata ), // Read data -.ram_imem_req (ram_imem_req ), // Start memory request -.ram_imem_wen (ram_imem_wen ), // Write enable -.ram_imem_strb (ram_imem_strb ), // Write strobe -.ram_imem_wdata (ram_imem_wdata ), // Write data -.ram_imem_addr (ram_imem_addr ), // Read/Write address -.ram_imem_gnt (ram_imem_gnt ), // request accepted -.ram_imem_recv (ram_imem_recv ), // Instruction memory recieve response. -.ram_imem_ack (ram_imem_ack ), // Instruction memory ack response. -.ram_imem_error (ram_imem_error ), // Error -.ram_imem_rdata (ram_imem_rdata ), // Read data -.rom_dmem_req (rom_dmem_req ), // Start memory request -.rom_dmem_wen (rom_dmem_wen ), // Write enable -.rom_dmem_strb (rom_dmem_strb ), // Write strobe -.rom_dmem_wdata (rom_dmem_wdata ), // Write data -.rom_dmem_addr (rom_dmem_addr ), // Read/Write address -.rom_dmem_gnt (rom_dmem_gnt ), // request accepted -.rom_dmem_recv (rom_dmem_recv ), // Instruction memory recieve response. -.rom_dmem_ack (rom_dmem_ack ), // Instruction memory ack response. -.rom_dmem_error (rom_dmem_error ), // Error -.rom_dmem_rdata (rom_dmem_rdata ), // Read data -.ram_dmem_req (ram_dmem_req ), // Start memory request -.ram_dmem_wen (ram_dmem_wen ), // Write enable -.ram_dmem_strb (ram_dmem_strb ), // Write strobe -.ram_dmem_wdata (ram_dmem_wdata ), // Write data -.ram_dmem_addr (ram_dmem_addr ), // Read/Write address -.ram_dmem_gnt (ram_dmem_gnt ), // request accepted -.ram_dmem_recv (ram_dmem_recv ), // Instruction memory recieve response. -.ram_dmem_ack (ram_dmem_ack ), // Instruction memory ack response. -.ram_dmem_error (ram_dmem_error ), // Error -.ram_dmem_rdata (ram_dmem_rdata ), // Read data -.m0_awvalid (m0_awvalid ), // -.m0_awready (m0_awready ), // -.m0_awaddr (m0_awaddr ), // -.m0_awprot (m0_awprot ), // -.m0_wvalid (m0_wvalid ), // -.m0_wready (m0_wready ), // -.m0_wdata (m0_wdata ), // -.m0_wstrb (m0_wstrb ), // -.m0_bvalid (m0_bvalid ), // -.m0_bready (m0_bready ), // -.m0_bresp (m0_bresp ), // -.m0_arvalid (m0_arvalid ), // -.m0_arready (m0_arready ), // -.m0_araddr (m0_araddr ), // -.m0_arprot (m0_arprot ), // -.m0_rvalid (m0_rvalid ), // -.m0_rready (m0_rready ), // -.m0_rresp (m0_rresp ), // -.m0_rdata (m0_rdata ) // -); - -// -// RNG instances -// ------------------------------------------------------------ - -scarv_rng_top #( -.RNG_TYPE(RNG_TYPE) -) i_scarv_rng_top ( -.g_clk (g_clk ), // global clock -.g_resetn (g_resetn ), // synchronous reset -.rng_req_valid (cpu_rng_req_valid ), // Signal a new request to the RNG -.rng_req_op (cpu_rng_req_op ), // Operation to perform on the RNG -.rng_req_data (cpu_rng_req_data ), // Suplementary seed/init data -.rng_req_ready (cpu_rng_req_ready ), // RNG accepts request -.rng_rsp_valid (cpu_rng_rsp_valid ), // RNG response data valid -.rng_rsp_status (cpu_rng_rsp_status ), // RNG status -.rng_rsp_data (cpu_rng_rsp_data ), // RNG response / sample data. -.rng_rsp_ready (cpu_rng_rsp_ready ) // CPU accepts response. -); - -// -// ROM / RAM instances -// ------------------------------------------------------------ - -wire bram_reset = !g_resetn; - -// -// ROM - -wire rom_a_bram_cen ; -wire [31:0] rom_a_bram_addr ; -wire [31:0] rom_a_bram_wdata ; -wire [ 3:0] rom_a_bram_wstrb ; -wire [31:0] rom_a_bram_rdata ; - -wire rom_b_bram_cen ; -wire [31:0] rom_b_bram_addr ; -wire [31:0] rom_b_bram_wdata ; -wire [ 3:0] rom_b_bram_wstrb ; -wire [31:0] rom_b_bram_rdata ; - -ic_cpu_bus_bram_bridge i_rom_imem_bus_bridge( -.g_clk (g_clk ), -.g_resetn (g_resetn ), -.bram_cen (rom_a_bram_cen ), -.bram_addr (rom_a_bram_addr ), -.bram_wdata (rom_a_bram_wdata ), -.bram_wstrb (rom_a_bram_wstrb ), -.bram_stall (1'b0 ), -.bram_rdata (rom_a_bram_rdata ), -.enable (rom_imem_req ), // Enable requests / does addr map? -.mem_req (rom_imem_req ), // Start memory request -.mem_gnt (rom_imem_gnt ), // request accepted -.mem_wen (rom_imem_wen ), // Write enable -.mem_strb (rom_imem_strb ), // Write strobe -.mem_wdata (rom_imem_wdata ), // Write data -.mem_addr (rom_imem_addr ), // Read/Write address -.mem_recv (rom_imem_recv ), // Instruction memory recieve response. -.mem_ack (rom_imem_ack ), // Instruction memory ack response. -.mem_error (rom_imem_error ), // Error -.mem_rdata (rom_imem_rdata ) // Read data -); - -ic_cpu_bus_bram_bridge i_rom_dmem_bus_bridge( -.g_clk (g_clk ), -.g_resetn (g_resetn ), -.bram_cen (rom_b_bram_cen ), -.bram_addr (rom_b_bram_addr ), -.bram_wdata (rom_b_bram_wdata ), -.bram_wstrb (rom_b_bram_wstrb ), -.bram_stall (1'b0 ), -.bram_rdata (rom_b_bram_rdata ), -.enable (rom_dmem_req ), // Enable requests / does addr map? -.mem_req (rom_dmem_req ), // Start memory request -.mem_gnt (rom_dmem_gnt ), // request accepted -.mem_wen (rom_dmem_wen ), // Write enable -.mem_strb (rom_dmem_strb ), // Write strobe -.mem_wdata (rom_dmem_wdata ), // Write data -.mem_addr (rom_dmem_addr ), // Read/Write address -.mem_recv (rom_dmem_recv ), // Instruction memory recieve response. -.mem_ack (rom_dmem_ack ), // Instruction memory ack response. -.mem_error (rom_dmem_error ), // Error -.mem_rdata (rom_dmem_rdata ) // Read data -); - -scarv_soc_bram_dual #( -.MEMH_FILE(BRAM_ROM_MEMH_FILE), -.DEPTH (BRAM_ROM_SIZE ), -.WRITE_EN (0 ) -) i_rom ( -.clka (g_clk ), -.rsta (bram_reset ), -.ena (rom_a_bram_cen ), -.wea (rom_a_bram_wstrb ), -.addra(rom_a_bram_addr[ 9:0]), -.dina (rom_a_bram_wdata ), -.douta(rom_a_bram_rdata ), -.enb (rom_b_bram_cen ), -.web (rom_b_bram_wstrb ), -.addrb(rom_b_bram_addr[ 9:0]), -.dinb (rom_b_bram_wdata ), -.doutb(rom_b_bram_rdata ) -); - -// -// RAM - -wire ram_a_bram_cen ; -wire [31:0] ram_a_bram_addr ; -wire [31:0] ram_a_bram_wdata ; -wire [ 3:0] ram_a_bram_wstrb ; -wire [31:0] ram_a_bram_rdata ; - -wire ram_b_bram_cen ; -wire [31:0] ram_b_bram_addr ; -wire [31:0] ram_b_bram_wdata ; -wire [ 3:0] ram_b_bram_wstrb ; -wire [31:0] ram_b_bram_rdata ; - -ic_cpu_bus_bram_bridge i_ram_imem_bus_bridge( -.g_clk (g_clk ), -.g_resetn (g_resetn ), -.bram_cen (ram_a_bram_cen ), -.bram_addr (ram_a_bram_addr ), -.bram_wdata (ram_a_bram_wdata ), -.bram_wstrb (ram_a_bram_wstrb ), -.bram_stall (1'b0 ), -.bram_rdata (ram_a_bram_rdata ), -.enable (ram_imem_req ), // Enable requests / does addr map? -.mem_req (ram_imem_req ), // Start memory request -.mem_gnt (ram_imem_gnt ), // request accepted -.mem_wen (ram_imem_wen ), // Write enable -.mem_strb (ram_imem_strb ), // Write strobe -.mem_wdata (ram_imem_wdata ), // Write data -.mem_addr (ram_imem_addr ), // Read/Write address -.mem_recv (ram_imem_recv ), // Instruction memory recieve response. -.mem_ack (ram_imem_ack ), // Instruction memory ack response. -.mem_error (ram_imem_error ), // Error -.mem_rdata (ram_imem_rdata ) // Read data -); - -ic_cpu_bus_bram_bridge i_ram_dmem_bus_bridge( -.g_clk (g_clk ), -.g_resetn (g_resetn ), -.bram_cen (ram_b_bram_cen ), -.bram_addr (ram_b_bram_addr ), -.bram_wdata (ram_b_bram_wdata ), -.bram_wstrb (ram_b_bram_wstrb ), -.bram_stall (1'b0 ), -.bram_rdata (ram_b_bram_rdata ), -.enable (ram_dmem_req ), // Enable requests / does addr map? -.mem_req (ram_dmem_req ), // Start memory request -.mem_gnt (ram_dmem_gnt ), // request accepted -.mem_wen (ram_dmem_wen ), // Write enable -.mem_strb (ram_dmem_strb ), // Write strobe -.mem_wdata (ram_dmem_wdata ), // Write data -.mem_addr (ram_dmem_addr ), // Read/Write address -.mem_recv (ram_dmem_recv ), // Instruction memory recieve response. -.mem_ack (ram_dmem_ack ), // Instruction memory ack response. -.mem_error (ram_dmem_error ), // Error -.mem_rdata (ram_dmem_rdata ) // Read data -); - -scarv_soc_bram_dual #( -.MEMH_FILE(BRAM_RAM_MEMH_FILE), -.DEPTH (BRAM_RAM_SIZE ), -.WRITE_EN (1 ) -) i_ram ( -.clka (g_clk ), -.rsta (bram_reset ), -.ena (ram_a_bram_cen ), -.wea (ram_a_bram_wstrb ), -.addra(ram_a_bram_addr[RAM_R:0]), -.dina (ram_a_bram_wdata ), -.douta(ram_a_bram_rdata ), -.enb (ram_b_bram_cen ), -.web (ram_b_bram_wstrb ), -.addrb(ram_b_bram_addr[RAM_R:0]), -.dinb (ram_b_bram_wdata ), -.doutb(ram_b_bram_rdata ) -); - -endmodule diff --git a/rtl/soc/scarv_soc_periph_top.sv b/rtl/soc/scarv_soc_periph_top.sv new file mode 100644 index 0000000..8c7b81d --- /dev/null +++ b/rtl/soc/scarv_soc_periph_top.sv @@ -0,0 +1,129 @@ + +// +// module: scarv_soc_periph_top +// +// Top level module containing all of the peripheral devices. +// +// - The peripheral subsystem has a 64KB address sub-space +// +// - Each peripheral has a 4KB address space for registers etc, meaning +// space for 16 devices. +// +// - The top module is responsible for selecting which device to route a +// request to, and response from. +// +// - The default address map is: +// +// Peripheral | Base Address | Top Address +// ------------|-------------------|----------------- +// UART | 0x????_0000 | 0x????_0FFF +// GPIO | 0x????_1000 | 0x????_1FFF +// +module scarv_soc_periph_top ( + +input wire f_clk , // Free running clock. +input wire g_clk_uart , // UART Clock +input wire g_clk_gpio , // GPIO Clock +output wire g_clk_req_uart , // UART Clock request +output wire g_clk_req_gpio , // GPIO Clock request +input wire g_resetn , // Global Active low sync reset. + +input wire uart_rx , // UART Recieve +output wire uart_tx , // UART Transmit + +output wire [GPION:0] gpio_io , // GPIO wire direction. 1=in, 0=out. +output wire [GPION:0] gpio_out , // GPIO outputs. +input wire [GPION:0] gpio_in , // GPIO inputs. + +scarv_ccx_memif.RSP memif // Memory requests. + +); + +// +// Address Map Parameters +// ------------------------------------------------------------ + +parameter BASE_UART = 32'h1000_0000; +parameter BASE_GPIO = 32'h1000_1000; + +localparam PERIPH_SIZE = 32'h0FFF; + +// +// Peripheral Parameters +// ------------------------------------------------------------ + +//! Number of GPIO pins. +parameter PERIPH_GPIO_NUM = 16; +localparam GPION = PERIPH_GPIO_NUM - 1; + +// +// Peripheral device selection +// ------------------------------------------------------------ + +scarv_ccx_memif #(.AW(32)) memif_uart (); // UART memory interface. +scarv_ccx_memif #(.AW(32)) memif_gpio (); // GPIO memory interface. +scarv_ccx_memif #(.AW(32)) memif_null0(); // spare memory interface. +scarv_ccx_memif #(.AW(32)) memif_null1(); // spare memory interface. + +// +// Requestor to device router. Re-used from the scarv-cpu core complex. +scarv_ccx_ic_router #( +.AW ( 32), +.DW ( 32), +.NDEVICES ( 2), +.D0_BASE ( BASE_UART), +.D0_SIZE ( PERIPH_SIZE), +.D1_BASE ( BASE_GPIO), +.D1_SIZE ( PERIPH_SIZE), +.D2_BASE (32'hFFFFFFFF), +.D2_SIZE ( PERIPH_SIZE), +.D3_BASE (32'hFFFFFFFF), +.D3_SIZE ( PERIPH_SIZE) +)i_periph_router ( +.g_clk (f_clk ), +.g_resetn (g_resetn ), +.if_core (memif ), // CPU requestor +.if_d0 (memif_uart ), +.if_d1 (memif_gpio ), +.if_d2 (memif_null0 ), +.if_d3 (memif_null1 ) +); + +// +// Peripheral device instantiation +// ------------------------------------------------------------ + +// +// instance: uart_top +// +// Top level of the UART peripheral +// +uart_top i_uart ( +.g_clk (g_clk_uart ), // Gated clock +.g_clk_req (g_clk_req_uart ), // Clock request +.g_resetn (g_resetn ), // Global Active low sync reset. +.uart_rx (uart_rx ), // UART Recieve +.uart_tx (uart_tx ), // UART Transmit +.memif (memif_uart ) // Memory request interface. +); + + +// +// instance: gpio_top +// +// Top level of the GPIO peripheral +// +gpio_top #( +.PERIPH_GPIO_NUM (PERIPH_GPIO_NUM ) +) i_gpio( +.g_clk (g_clk_gpio ), // Gated clock +.g_clk_req (g_clk_req_gpio ), // Clock request +.g_resetn (g_resetn ), // Global Active low sync reset. +.gpio_io (gpio_io ), // GPIO wire direction. 1=in, 0=out. +.gpio_out (gpio_out ), // GPIO outputs. +.gpio_in (gpio_in ), // GPIO inputs. +.memif (memif_gpio ) // Memory request interface. +); + +endmodule + diff --git a/rtl/uart/uart_top.sv b/rtl/uart/uart_top.sv new file mode 100644 index 0000000..996cc51 --- /dev/null +++ b/rtl/uart/uart_top.sv @@ -0,0 +1,29 @@ + +// +// module: uart_top +// +// Top level of the UART peripheral +// +module uart_top ( + +input wire g_clk , // Gated clock +output wire g_clk_req , // Clock request +input wire g_resetn , // Global Active low sync reset. + +input wire uart_rx , // UART Recieve +output wire uart_tx , // UART Transmit + +scarv_ccx_memif.RSP memif // Memory request interface. + +); + +// +// Stub out for now +assign uart_tx = 1'b1; +assign memif.gnt = 1'b1; +assign memif.error = 1'b0; + + +endmodule + +