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vgaPong.par
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vgaPong.par
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Release 14.6 par P.68d (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
SAM-PC:: Wed Aug 28 12:42:22 2013
par -filter C:/Users/Sam/Documents/FPGA/vgaPong_v2/iseconfig/filter.filter -w
-intstyle ise -ol high -t 1 vgaPong_map.ncd vgaPong.ncd vgaPong.pcf
Constraints file: vgaPong.pcf.
Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Xilinx\14.6\ISE_DS\ISE\.
"vgaPong" is an NCD, version 3.2, device xc3s500e, package vq100, speed -5
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
Device speed data version: "PRODUCTION 1.27 2013-06-08".
Design Summary Report:
Number of External IOBs 24 out of 66 36%
Number of External Input IOBs 6
Number of External Input IBUFs 6
Number of LOCed External Input IBUFs 6 out of 6 100%
Number of External Output IOBs 18
Number of External Output IOBs 18
Number of LOCed External Output IOBs 18 out of 18 100%
Number of External Bidir IOBs 0
Number of BUFGMUXs 2 out of 24 8%
Number of DCMs 1 out of 4 25%
Number of Slices 644 out of 4656 13%
Number of SLICEMs 0 out of 2328 0%
Overall effort level (-ol): High
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 2 secs
Finished initial Timing Analysis. REAL time: 2 secs
Starting Placer
Total REAL time at the beginning of Placer: 2 secs
Total CPU time at the beginning of Placer: 2 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:4fa22a9f) REAL time: 2 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:4fa22a9f) REAL time: 2 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:4fa22a9f) REAL time: 2 secs
Phase 4.2 Initial Clock and IO Placement
Phase 4.2 Initial Clock and IO Placement (Checksum:20fab3b7) REAL time: 2 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:20fab3b7) REAL time: 2 secs
Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:20fab3b7) REAL time: 2 secs
Phase 7.8 Global Placement
....................
..
Phase 7.8 Global Placement (Checksum:fca126be) REAL time: 5 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:fca126be) REAL time: 5 secs
Phase 9.18 Placement Optimization
Phase 9.18 Placement Optimization (Checksum:3bdeadee) REAL time: 5 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:3bdeadee) REAL time: 5 secs
Total REAL time to Placer completion: 5 secs
Total CPU time to Placer completion: 5 secs
Writing design to file vgaPong.ncd
Starting Router
Phase 1 : 3568 unrouted; REAL time: 10 secs
Phase 2 : 3366 unrouted; REAL time: 10 secs
Phase 3 : 493 unrouted; REAL time: 10 secs
Phase 4 : 493 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 11 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 11 secs
Updating file: vgaPong.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 11 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 12 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 12 secs
WARNING:Route:455 - CLK Net:Mcompar_wall_draw_cmp_lt0000_cy<7> may have excessive skew because
3 CLK pins and 2 NON_CLK pins failed to route using a CLK template.
Total REAL time to Router completion: 12 secs
Total CPU time to Router completion: 11 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| vga_pixel_clock | BUFGMUX_X2Y11| No | 148 | 0.050 | 0.152 |
+---------------------+--------------+------+------+------------+-------------+
|Mcompar_wall_draw_cm | | | | | |
| p_lt0000_cy<7> | Local| | 5 | 0.242 | 2.020 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 1
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
NET "Inst_pixel_clock/CLKIN_IBUFG" PERIOD | MINLOWPULSE | 21.250ns| 10.000ns| 0| 0
= 31.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
PERIOD analysis for net "Inst_pixel_clock | SETUP | 27.270ns| 12.730ns| 0| 0
/CLKFX_BUF" derived from NET "Inst_pixel | HOLD | 1.397ns| | 0| 0
_clock/CLKIN_IBUFG" PERIOD = 31.25 ns HIG | | | | |
H 50% | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for Inst_pixel_clock/CLKIN_IBUFG
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|Inst_pixel_clock/CLKIN_IBUFG | 31.250ns| 10.000ns| 9.945ns| 0| 0| 0| 469446|
| Inst_pixel_clock/CLKFX_BUF | 40.000ns| 12.730ns| N/A| 0| 0| 469446| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 12 secs
Total CPU time to PAR completion: 12 secs
Peak Memory Usage: 342 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 1
Number of info messages: 0
Writing design to file vgaPong.ncd
PAR done!