From 4652b8846c4ff817602e95a24bd41045fbcb24d7 Mon Sep 17 00:00:00 2001 From: LuiSzee Date: Tue, 26 Oct 2021 06:36:55 +0800 Subject: [PATCH] Update Centec platform support for Bullseye and 5.10 kernel (#7) 1. Fix build for armhf and arm64 2. upgrade centec tsingma bsp support to 5.10 kernel 3. modify centec platform driver for linux 5.10 Co-authored-by: Shi Lei --- files/apt/sources.list.arm64 | 20 +- files/apt/sources.list.armhf | 20 +- .../build_templates/sonic_debian_extension.j2 | 2 +- .../arm64/debian_mirror_arm64.list | 16 +- .../armhf/debian_mirror_armhf.list | 16 +- platform/centec-arm64/modules | 2 +- .../24x2c/modules/Makefile | 2 + .../modules/centec_e530_24x2c_platform.c | 7 +- .../24x2q/modules/Makefile | 2 + .../modules/centec_e530_24x2q_platform.c | 7 +- .../48s4x/modules/Makefile | 2 + .../modules/centec_e530_48s4x_platform.c | 7 +- .../48t4x-p/modules/Makefile | 2 + .../modules/centec_e530_48t4x_p_platform.c | 3 +- .../debian/control | 8 +- .../debian/platform-modules-e530-24x2c.init | 6 +- .../platform-modules-e530-24x2c.install | 1 - .../debian/platform-modules-e530-24x2q.init | 6 +- .../platform-modules-e530-24x2q.install | 1 - .../debian/platform-modules-e530-48s4x.init | 6 +- .../platform-modules-e530-48s4x.install | 1 - .../debian/platform-modules-e530-48t4x-p.init | 6 +- .../platform-modules-e530-48t4x-p.install | 1 - .../sonic-platform-modules-e530/debian/rules | 6 +- .../pca954x/Makefile | 1 + .../pca954x/ctc-i2c-mux-pca954x.c | 581 ++ .../pca954x/ctc-pca954x.h | 48 + platform/centec-arm64/sonic_fit.its | 4 +- .../centec-arm64/tsingma-bsp/debian/control | 2 +- .../centec-arm64/tsingma-bsp/debian/rules | 2 +- .../tsingma-bsp/debian/tsingma-bsp.install | 28 +- .../tsingma-bsp/src/ctc-dts/arm-gic.h | 1 + .../tsingma-bsp/src/ctc-dts/ctc5236.dtsi | 66 +- .../tsingma-bsp/src/ctc-dts/e530-ctc5236.dts | 3 +- .../tsingma-bsp/src/ctc-dts/irq.h | 1 + .../tsingma-bsp/src/ctc-phy/Makefile | 1 + .../tsingma-bsp/src/ctc-phy/mars.c | 316 + .../tsingma-bsp/src/ctc5236-mc/ctc5236-mc.c | 254 +- .../src/ctc5236_switch/ctc5236_switch.c | 129 +- .../tsingma-bsp/src/ctc_wdt/ctc_wdt.c | 7 + .../tsingma-bsp/src/ctcmac/Makefile | 2 +- .../tsingma-bsp/src/ctcmac/ctc5236_mdio.c | 29 +- .../tsingma-bsp/src/ctcmac/ctcmac.c | 2156 ++++-- .../tsingma-bsp/src/ctcmac/ctcmac.h | 94 +- .../tsingma-bsp/src/ctcmac/ctcmac_reg.h | 5756 +++++++++-------- .../tsingma-bsp/src/ctcmac/ctcmac_test.c | 2116 ------ .../tsingma-bsp/src/ehci-ctc/ehci-ctc.c | 266 +- .../tsingma-bsp/src/ehci-ctc/ehci.h | 588 +- .../tsingma-bsp/src/gpio-ctc/gpio-ctc.c | 98 +- .../tsingma-bsp/src/gpio-ctc/gpiolib.h | 244 +- .../tsingma-bsp/src/i2c-ctc/i2c-ctc.c | 147 +- .../tsingma-bsp/src/i2c-ctc/i2c-ctc.h | 49 +- .../tsingma-bsp/src/include/ctc5236_switch.h | 18 +- .../tsingma-bsp/src/include/sysctl.h | 520 +- .../tsingma-bsp/src/pinctrl-ctc/core.h | 18 +- .../tsingma-bsp/src/pinctrl-ctc/pinconf.h | 7 +- .../tsingma-bsp/src/pinctrl-ctc/pinctrl-ctc.c | 46 +- .../tsingma-bsp/src/pwm-ctc/pwm-ctc.c | 51 +- .../tsingma-bsp/src/rtc-sd2405/rtc-sd2405.c | 23 +- .../src/sdhci-ctc5236/sdhci-ctc5236.c | 191 +- .../src/sdhci-ctc5236/sdhci-pltfm.h | 34 +- .../tsingma-bsp/src/sdhci-ctc5236/sdhci.h | 258 +- .../src/spi-ctc-qspi/spi-ctc-qspi.c | 71 +- platform/centec/centec-dal/dal_kernel.c | 21 +- .../48x2q4z/modules/Makefile | 4 +- .../48x2q4z/modules/centec_at24c64.c | 602 -- .../modules/centec_e582_48x2q4z_platform.c | 24 +- .../48x2q4z/scripts/48x2q4z_platform.sh | 9 +- .../48x6q/modules/Makefile | 4 +- .../48x6q/modules/centec_at24c64.c | 602 -- .../modules/centec_e582_48x6q_platform.c | 24 +- .../48x6q/scripts/48x6q_platform.sh | 9 +- .../debian/control | 4 +- .../sonic-platform-modules-e582/debian/rules | 5 + .../pca954x/Makefile | 1 + .../pca954x/ctc-i2c-mux-pca954x.c | 581 ++ .../pca954x/ctc-pca954x.h | 48 + .../debian/control | 2 +- scripts/build_debian_base_system.sh | 8 +- sonic-slave-bullseye/Dockerfile.j2 | 7 + 80 files changed, 8258 insertions(+), 8073 deletions(-) create mode 100644 platform/centec-arm64/sonic-platform-modules-e530/pca954x/Makefile create mode 100644 platform/centec-arm64/sonic-platform-modules-e530/pca954x/ctc-i2c-mux-pca954x.c create mode 100644 platform/centec-arm64/sonic-platform-modules-e530/pca954x/ctc-pca954x.h mode change 100644 => 100755 platform/centec-arm64/tsingma-bsp/debian/rules mode change 100644 => 100755 platform/centec-arm64/tsingma-bsp/src/ctc-dts/arm-gic.h mode change 100644 => 100755 platform/centec-arm64/tsingma-bsp/src/ctc-dts/ctc5236.dtsi create mode 100644 platform/centec-arm64/tsingma-bsp/src/ctc-phy/Makefile create mode 100644 platform/centec-arm64/tsingma-bsp/src/ctc-phy/mars.c mode change 100644 => 100755 platform/centec-arm64/tsingma-bsp/src/ctc5236-mc/ctc5236-mc.c mode change 100644 => 100755 platform/centec-arm64/tsingma-bsp/src/ctc5236_switch/ctc5236_switch.c mode change 100644 => 100755 platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac.c delete mode 100644 platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac_test.c mode change 100644 => 100755 platform/centec-arm64/tsingma-bsp/src/ehci-ctc/ehci-ctc.c mode change 100644 => 100755 platform/centec-arm64/tsingma-bsp/src/gpio-ctc/gpio-ctc.c mode change 100644 => 100755 platform/centec-arm64/tsingma-bsp/src/i2c-ctc/i2c-ctc.c mode change 100644 => 100755 platform/centec-arm64/tsingma-bsp/src/pinctrl-ctc/pinctrl-ctc.c mode change 100644 => 100755 platform/centec-arm64/tsingma-bsp/src/pwm-ctc/pwm-ctc.c mode change 100644 => 100755 platform/centec-arm64/tsingma-bsp/src/sdhci-ctc5236/sdhci-ctc5236.c delete mode 100644 platform/centec/sonic-platform-modules-e582/48x2q4z/modules/centec_at24c64.c delete mode 100644 platform/centec/sonic-platform-modules-e582/48x6q/modules/centec_at24c64.c create mode 100644 platform/centec/sonic-platform-modules-e582/pca954x/Makefile create mode 100644 platform/centec/sonic-platform-modules-e582/pca954x/ctc-i2c-mux-pca954x.c create mode 100644 platform/centec/sonic-platform-modules-e582/pca954x/ctc-pca954x.h diff --git a/files/apt/sources.list.arm64 b/files/apt/sources.list.arm64 index 58b84978d023..abd625070414 100644 --- a/files/apt/sources.list.arm64 +++ b/files/apt/sources.list.arm64 @@ -1,13 +1,13 @@ ## Debian mirror for ARM ## Not the repo mirror site can change in future, and needs to be updated to be in sync -deb [arch=arm64] http://deb.debian.org/debian buster main contrib non-free -deb-src [arch=arm64] http://deb.debian.org/debian buster main contrib non-free -deb [arch=arm64] http://deb.debian.org/debian buster-updates main contrib non-free -deb-src [arch=arm64] http://deb.debian.org/debian buster-updates main contrib non-free -deb [arch=arm64] http://ftp.debian.org/debian buster-backports main -deb [arch=arm64] http://packages.trafficmanager.net/debian/debian buster main contrib non-free -deb-src [arch=arm64] http://packages.trafficmanager.net/debian/debian buster main contrib non-free -deb [arch=arm64] http://packages.trafficmanager.net/debian/debian buster-updates main contrib non-free -deb-src [arch=arm64] http://packages.trafficmanager.net/debian/debian buster-updates main contrib non-free -deb [arch=arm64] http://packages.trafficmanager.net/debian/debian buster-backports main +deb [arch=arm64] http://deb.debian.org/debian bullseye main contrib non-free +deb-src [arch=arm64] http://deb.debian.org/debian bullseye main contrib non-free +deb [arch=arm64] http://deb.debian.org/debian bullseye-updates main contrib non-free +deb-src [arch=arm64] http://deb.debian.org/debian bullseye-updates main contrib non-free +deb [arch=arm64] http://ftp.debian.org/debian bullseye-backports main +# deb [arch=arm64] http://packages.trafficmanager.net/debian/debian bullseye main contrib non-free +# deb-src [arch=arm64] http://packages.trafficmanager.net/debian/debian bullseye main contrib non-free +# deb [arch=arm64] http://packages.trafficmanager.net/debian/debian bullseye-updates main contrib non-free +# deb-src [arch=arm64] http://packages.trafficmanager.net/debian/debian bullseye-updates main contrib non-free +# deb [arch=arm64] http://packages.trafficmanager.net/debian/debian bullseye-backports main diff --git a/files/apt/sources.list.armhf b/files/apt/sources.list.armhf index eb6fe3be6889..ded8e27e6b2b 100644 --- a/files/apt/sources.list.armhf +++ b/files/apt/sources.list.armhf @@ -1,13 +1,13 @@ ## Debian mirror for ARM ## Not the repo mirror site can change in future, and needs to be updated to be in sync -deb [arch=armhf] http://deb.debian.org/debian buster main contrib non-free -deb-src [arch=armhf] http://deb.debian.org/debian buster main contrib non-free -deb [arch=armhf] http://deb.debian.org/debian buster-updates main contrib non-free -deb-src [arch=armhf] http://deb.debian.org/debian buster-updates main contrib non-free -deb [arch=armhf] http://ftp.debian.org/debian buster-backports main -deb [arch=armhf] http://packages.trafficmanager.net/debian/debian buster main contrib non-free -deb-src [arch=armhf] http://packages.trafficmanager.net/debian/debian buster main contrib non-free -deb [arch=armhf] http://packages.trafficmanager.net/debian/debian buster-updates main contrib non-free -deb-src [arch=armhf] http://packages.trafficmanager.net/debian/debian buster-updates main contrib non-free -deb [arch=armhf] http://packages.trafficmanager.net/debian/debian buster-backports main +deb [arch=armhf] http://deb.debian.org/debian bullseye main contrib non-free +deb-src [arch=armhf] http://deb.debian.org/debian bullseye main contrib non-free +deb [arch=armhf] http://deb.debian.org/debian bullseye-updates main contrib non-free +deb-src [arch=armhf] http://deb.debian.org/debian bullseye-updates main contrib non-free +deb [arch=armhf] http://ftp.debian.org/debian bullseye-backports main +# deb [arch=armhf] http://packages.trafficmanager.net/debian/debian bullseye main contrib non-free +# deb-src [arch=armhf] http://packages.trafficmanager.net/debian/debian bullseye main contrib non-free +# deb [arch=armhf] http://packages.trafficmanager.net/debian/debian bullseye-updates main contrib non-free +# deb-src [arch=armhf] http://packages.trafficmanager.net/debian/debian bullseye-updates main contrib non-free +# deb [arch=armhf] http://packages.trafficmanager.net/debian/debian bullseye-backports main diff --git a/files/build_templates/sonic_debian_extension.j2 b/files/build_templates/sonic_debian_extension.j2 index 363ca7ec550b..3d4e0b55e5d3 100644 --- a/files/build_templates/sonic_debian_extension.j2 +++ b/files/build_templates/sonic_debian_extension.j2 @@ -635,7 +635,7 @@ clean_proc() { sudo umount /proc || true } trap_push clean_proc -sudo mount proc /proc -t proc +sudo mount proc /proc -t proc || true sudo mkdir $FILESYSTEM_ROOT/target sudo mount --bind target $FILESYSTEM_ROOT/target sudo LANG=C DOCKER_HOST="$DOCKER_HOST" chroot $FILESYSTEM_ROOT docker info diff --git a/files/image_config/apt/sources.list.d/arm64/debian_mirror_arm64.list b/files/image_config/apt/sources.list.d/arm64/debian_mirror_arm64.list index 9e7dec92d39e..a34ce92658cc 100644 --- a/files/image_config/apt/sources.list.d/arm64/debian_mirror_arm64.list +++ b/files/image_config/apt/sources.list.d/arm64/debian_mirror_arm64.list @@ -1,9 +1,9 @@ -deb [arch=arm64] http://deb.debian.org/debian buster main contrib non-free -deb-src [arch=arm64] http://deb.debian.org/debian buster main contrib non-free -deb [arch=arm64] http://deb.debian.org/debian buster-updates main contrib non-free -deb-src [arch=arm64] http://deb.debian.org/debian buster-updates main contrib non-free -deb [arch=arm64] http://security.debian.org buster/updates main contrib non-free -deb-src [arch=arm64] http://security.debian.org buster/updates main contrib non-free -deb [arch=arm64] https://download.docker.com/linux/debian buster stable -deb [arch=arm64] http://ftp.debian.org/debian buster-backports main +deb [arch=arm64] http://deb.debian.org/debian bullseye main contrib non-free +deb-src [arch=arm64] http://deb.debian.org/debian bullseye main contrib non-free +deb [arch=arm64] http://deb.debian.org/debian bullseye-updates main contrib non-free +deb-src [arch=arm64] http://deb.debian.org/debian bullseye-updates main contrib non-free +deb [arch=arm64] http://security.debian.org bullseye-security main contrib non-free +deb-src [arch=arm64] http://security.debian.org bullseye-security main contrib non-free +deb [arch=arm64] https://download.docker.com/linux/debian bullseye stable +deb [arch=arm64] http://ftp.debian.org/debian bullseye-backports main diff --git a/files/image_config/apt/sources.list.d/armhf/debian_mirror_armhf.list b/files/image_config/apt/sources.list.d/armhf/debian_mirror_armhf.list index a7b831ef301c..7c4865525feb 100644 --- a/files/image_config/apt/sources.list.d/armhf/debian_mirror_armhf.list +++ b/files/image_config/apt/sources.list.d/armhf/debian_mirror_armhf.list @@ -1,9 +1,9 @@ -deb [arch=armhf] http://deb.debian.org/debian buster main contrib non-free -deb-src [arch=armhf] http://deb.debian.org/debian buster main contrib non-free -deb [arch=armhf] http://deb.debian.org/debian buster-updates main contrib non-free -deb-src [arch=armhf] http://deb.debian.org/debian buster-updates main contrib non-free -deb [arch=armhf] http://security.debian.org buster/updates main contrib non-free -deb-src [arch=armhf] http://security.debian.org buster/updates main contrib non-free -deb [arch=armhf] https://download.docker.com/linux/debian buster stable -deb [arch=armhf] http://ftp.debian.org/debian buster-backports main +deb [arch=armhf] http://deb.debian.org/debian bullseye main contrib non-free +deb-src [arch=armhf] http://deb.debian.org/debian bullseye main contrib non-free +deb [arch=armhf] http://deb.debian.org/debian bullseye-updates main contrib non-free +deb-src [arch=armhf] http://deb.debian.org/debian bullseye-updates main contrib non-free +deb [arch=armhf] http://security.debian.org bullseye-security main contrib non-free +deb-src [arch=armhf] http://security.debian.org bullseye-security main contrib non-free +deb [arch=armhf] https://download.docker.com/linux/debian bullseye stable +deb [arch=armhf] http://ftp.debian.org/debian bullseye-backports main diff --git a/platform/centec-arm64/modules b/platform/centec-arm64/modules index 30cdc339d8de..e980c08f5802 100644 --- a/platform/centec-arm64/modules +++ b/platform/centec-arm64/modules @@ -10,7 +10,6 @@ rtc-sd2405 ctc5236_switch ctc5236_mdio ctcmac -ctcmac_test ctc5236-mc ctc_wdt ehci-ctc @@ -20,3 +19,4 @@ pwm-ctc ext4 overlay squashfs +mars diff --git a/platform/centec-arm64/sonic-platform-modules-e530/24x2c/modules/Makefile b/platform/centec-arm64/sonic-platform-modules-e530/24x2c/modules/Makefile index c1beeaa15c68..e7b2176d96ef 100644 --- a/platform/centec-arm64/sonic-platform-modules-e530/24x2c/modules/Makefile +++ b/platform/centec-arm64/sonic-platform-modules-e530/24x2c/modules/Makefile @@ -1 +1,3 @@ +KBUILD_EXTRA_SYMBOLS = /sonic/platform/centec-arm64/sonic-platform-modules-e530/pca954x/Module.symvers + obj-m := centec_e530_24x2c_platform.o diff --git a/platform/centec-arm64/sonic-platform-modules-e530/24x2c/modules/centec_e530_24x2c_platform.c b/platform/centec-arm64/sonic-platform-modules-e530/24x2c/modules/centec_e530_24x2c_platform.c index 8c2437a2d071..f22794c15fc7 100644 --- a/platform/centec-arm64/sonic-platform-modules-e530/24x2c/modules/centec_e530_24x2c_platform.c +++ b/platform/centec-arm64/sonic-platform-modules-e530/24x2c/modules/centec_e530_24x2c_platform.c @@ -1,7 +1,6 @@ #include #include #include -#include #include #include #include @@ -129,7 +128,7 @@ static int e530_24x2c_init_i2c_gpio(void) return -1; } - i2c_client_gpio0 = i2c_new_device(i2c_adp_gpio0, &i2c_dev_gpio0); + i2c_client_gpio0 = i2c_new_client_device(i2c_adp_gpio0, &i2c_dev_gpio0); if(IS_INVALID_PTR(i2c_client_gpio0)) { i2c_client_gpio0 = NULL; @@ -145,7 +144,7 @@ static int e530_24x2c_init_i2c_gpio(void) return -1; } - i2c_client_gpio1 = i2c_new_device(i2c_adp_gpio1, &i2c_dev_gpio1); + i2c_client_gpio1 = i2c_new_client_device(i2c_adp_gpio1, &i2c_dev_gpio1); if(IS_INVALID_PTR(i2c_client_gpio1)) { i2c_client_gpio1 = NULL; @@ -161,7 +160,7 @@ static int e530_24x2c_init_i2c_gpio(void) return -1; } - i2c_client_gpio2 = i2c_new_device(i2c_adp_gpio2, &i2c_dev_gpio2); + i2c_client_gpio2 = i2c_new_client_device(i2c_adp_gpio2, &i2c_dev_gpio2); if(IS_INVALID_PTR(i2c_client_gpio2)) { i2c_client_gpio2 = NULL; diff --git a/platform/centec-arm64/sonic-platform-modules-e530/24x2q/modules/Makefile b/platform/centec-arm64/sonic-platform-modules-e530/24x2q/modules/Makefile index 8736ed3a8d9b..612bed73c602 100644 --- a/platform/centec-arm64/sonic-platform-modules-e530/24x2q/modules/Makefile +++ b/platform/centec-arm64/sonic-platform-modules-e530/24x2q/modules/Makefile @@ -1 +1,3 @@ +KBUILD_EXTRA_SYMBOLS = /sonic/platform/centec-arm64/sonic-platform-modules-e530/pca954x/Module.symvers + obj-m := centec_e530_24x2q_platform.o diff --git a/platform/centec-arm64/sonic-platform-modules-e530/24x2q/modules/centec_e530_24x2q_platform.c b/platform/centec-arm64/sonic-platform-modules-e530/24x2q/modules/centec_e530_24x2q_platform.c index 68830775e003..97c89027e970 100644 --- a/platform/centec-arm64/sonic-platform-modules-e530/24x2q/modules/centec_e530_24x2q_platform.c +++ b/platform/centec-arm64/sonic-platform-modules-e530/24x2q/modules/centec_e530_24x2q_platform.c @@ -1,7 +1,6 @@ #include #include #include -#include #include #include #include @@ -129,7 +128,7 @@ static int e530_24x2q_init_i2c_gpio(void) return -1; } - i2c_client_gpio0 = i2c_new_device(i2c_adp_gpio0, &i2c_dev_gpio0); + i2c_client_gpio0 = i2c_new_client_device(i2c_adp_gpio0, &i2c_dev_gpio0); if(IS_INVALID_PTR(i2c_client_gpio0)) { i2c_client_gpio0 = NULL; @@ -145,7 +144,7 @@ static int e530_24x2q_init_i2c_gpio(void) return -1; } - i2c_client_gpio1 = i2c_new_device(i2c_adp_gpio1, &i2c_dev_gpio1); + i2c_client_gpio1 = i2c_new_client_device(i2c_adp_gpio1, &i2c_dev_gpio1); if(IS_INVALID_PTR(i2c_client_gpio1)) { i2c_client_gpio1 = NULL; @@ -161,7 +160,7 @@ static int e530_24x2q_init_i2c_gpio(void) return -1; } - i2c_client_gpio2 = i2c_new_device(i2c_adp_gpio2, &i2c_dev_gpio2); + i2c_client_gpio2 = i2c_new_client_device(i2c_adp_gpio2, &i2c_dev_gpio2); if(IS_INVALID_PTR(i2c_client_gpio2)) { i2c_client_gpio2 = NULL; diff --git a/platform/centec-arm64/sonic-platform-modules-e530/48s4x/modules/Makefile b/platform/centec-arm64/sonic-platform-modules-e530/48s4x/modules/Makefile index b3a639cc40b8..25a513cb5a29 100644 --- a/platform/centec-arm64/sonic-platform-modules-e530/48s4x/modules/Makefile +++ b/platform/centec-arm64/sonic-platform-modules-e530/48s4x/modules/Makefile @@ -1 +1,3 @@ +KBUILD_EXTRA_SYMBOLS = /sonic/platform/centec-arm64/sonic-platform-modules-e530/pca954x/Module.symvers + obj-m := centec_e530_48s4x_platform.o diff --git a/platform/centec-arm64/sonic-platform-modules-e530/48s4x/modules/centec_e530_48s4x_platform.c b/platform/centec-arm64/sonic-platform-modules-e530/48s4x/modules/centec_e530_48s4x_platform.c index 179db78738e5..4bae7ddc52dd 100644 --- a/platform/centec-arm64/sonic-platform-modules-e530/48s4x/modules/centec_e530_48s4x_platform.c +++ b/platform/centec-arm64/sonic-platform-modules-e530/48s4x/modules/centec_e530_48s4x_platform.c @@ -1,7 +1,6 @@ #include #include #include -#include #include #include #include @@ -197,7 +196,7 @@ static int e530_48s4x_init_i2c_gpio(void) return -1; } - i2c_client_gpio0 = i2c_new_device(i2c_adp_gpio0, &i2c_dev_gpio0); + i2c_client_gpio0 = i2c_new_client_device(i2c_adp_gpio0, &i2c_dev_gpio0); if(IS_INVALID_PTR(i2c_client_gpio0)) { i2c_client_gpio0 = NULL; @@ -213,7 +212,7 @@ static int e530_48s4x_init_i2c_gpio(void) return -1; } - i2c_client_gpio1 = i2c_new_device(i2c_adp_gpio1, &i2c_dev_gpio1); + i2c_client_gpio1 = i2c_new_client_device(i2c_adp_gpio1, &i2c_dev_gpio1); if(IS_INVALID_PTR(i2c_client_gpio1)) { i2c_client_gpio1 = NULL; @@ -274,7 +273,7 @@ static int e530_48s4x_init_i2c_epld(void) return -1; } - i2c_client_epld = i2c_new_device(i2c_adp_master, &i2c_dev_epld); + i2c_client_epld = i2c_new_client_device(i2c_adp_master, &i2c_dev_epld); if(IS_INVALID_PTR(i2c_client_epld)) { i2c_client_epld = NULL; diff --git a/platform/centec-arm64/sonic-platform-modules-e530/48t4x-p/modules/Makefile b/platform/centec-arm64/sonic-platform-modules-e530/48t4x-p/modules/Makefile index 47327a1a0037..a0f8b48d38b4 100644 --- a/platform/centec-arm64/sonic-platform-modules-e530/48t4x-p/modules/Makefile +++ b/platform/centec-arm64/sonic-platform-modules-e530/48t4x-p/modules/Makefile @@ -1 +1,3 @@ +KBUILD_EXTRA_SYMBOLS = /sonic/platform/centec-arm64/sonic-platform-modules-e530/pca954x/Module.symvers + obj-m := centec_e530_48t4x_p_platform.o diff --git a/platform/centec-arm64/sonic-platform-modules-e530/48t4x-p/modules/centec_e530_48t4x_p_platform.c b/platform/centec-arm64/sonic-platform-modules-e530/48t4x-p/modules/centec_e530_48t4x_p_platform.c index 7f5584279ee9..b91e578de76b 100644 --- a/platform/centec-arm64/sonic-platform-modules-e530/48t4x-p/modules/centec_e530_48t4x_p_platform.c +++ b/platform/centec-arm64/sonic-platform-modules-e530/48t4x-p/modules/centec_e530_48t4x_p_platform.c @@ -1,7 +1,6 @@ #include #include #include -#include #include #include #include @@ -195,7 +194,7 @@ static int e530_48t4x_p_init_i2c_gpio(void) return -1; } - i2c_client_gpio0 = i2c_new_device(i2c_adp_gpio0, &i2c_dev_gpio0); + i2c_client_gpio0 = i2c_new_client_device(i2c_adp_gpio0, &i2c_dev_gpio0); if(IS_INVALID_PTR(i2c_client_gpio0)) { i2c_client_gpio0 = NULL; diff --git a/platform/centec-arm64/sonic-platform-modules-e530/debian/control b/platform/centec-arm64/sonic-platform-modules-e530/debian/control index 31abd51cdc2d..2e8becc2c718 100644 --- a/platform/centec-arm64/sonic-platform-modules-e530/debian/control +++ b/platform/centec-arm64/sonic-platform-modules-e530/debian/control @@ -7,20 +7,20 @@ Standards-Version: 3.9.3 Package: platform-modules-e530-48t4x-p Architecture: arm64 -Depends: linux-image-4.19.0-12-2-arm64-unsigned +Depends: linux-image-5.10.0-8-2-arm64-unsigned Description: kernel modules for platform devices such as fan, led, sfp Package: platform-modules-e530-24x2c Architecture: arm64 -Depends: linux-image-4.19.0-12-2-arm64-unsigned +Depends: linux-image-5.10.0-8-2-arm64-unsigned Description: kernel modules for platform devices such as fan, led, sfp Package: platform-modules-e530-48s4x Architecture: arm64 -Depends: linux-image-4.19.0-12-2-arm64-unsigned +Depends: linux-image-5.10.0-8-2-arm64-unsigned Description: kernel modules for platform devices such as fan, led, sfp Package: platform-modules-e530-24x2q Architecture: arm64 -Depends: linux-image-4.19.0-12-2-arm64-unsigned +Depends: linux-image-5.10.0-8-2-arm64-unsigned Description: kernel modules for platform devices such as fan, led, sfp diff --git a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2c.init b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2c.init index e508d52053e7..dc61f8e00fbd 100755 --- a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2c.init +++ b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2c.init @@ -17,10 +17,6 @@ function install_python_api_package() device="/usr/share/sonic/device" platform=$(/usr/local/bin/sonic-cfggen -H -v DEVICE_METADATA.localhost.platform) - rv=$(pip2 show sonic-platform > /dev/null 2>/dev/null) - if [ $? -ne 0 ]; then - rv=$(pip2 install $device/$platform/sonic_platform-1.0-py2-none-any.whl) - fi rv=$(pip3 show sonic-platform > /dev/null 2>/dev/null) if [ $? -ne 0 ]; then rv=$(pip3 install $device/$platform/sonic_platform-1.0-py3-none-any.whl) @@ -34,6 +30,7 @@ function load_kernel_modules() ifconfig eth0 hw ether $hwaddr fi depmod -a + modprobe ctc-i2c-mux-pca954x modprobe centec_e530_24x2c_platform modprobe fan-ctc5236 modprobe dal @@ -48,6 +45,7 @@ function remove_kernel_modules() modprobe -r dal modprobe -r fan-ctc5236 modprobe -r centec_e530_24x2c_platform + modprobe -r ctc-i2c-mux-pca954x } case "$1" in diff --git a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2c.install b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2c.install index 567afa923ace..7c246f32f939 100644 --- a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2c.install +++ b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2c.install @@ -1,2 +1 @@ -24x2c/modules/sonic_platform-1.0-py2-none-any.whl usr/share/sonic/device/arm64-centec_e530_24x2c-r0 24x2c/modules/sonic_platform-1.0-py3-none-any.whl usr/share/sonic/device/arm64-centec_e530_24x2c-r0 diff --git a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2q.init b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2q.init index 60b3b69a1d38..b2eed3c72e09 100644 --- a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2q.init +++ b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2q.init @@ -17,10 +17,6 @@ function install_python_api_package() device="/usr/share/sonic/device" platform=$(/usr/local/bin/sonic-cfggen -H -v DEVICE_METADATA.localhost.platform) - rv=$(pip2 show sonic-platform > /dev/null 2>/dev/null) - if [ $? -ne 0 ]; then - rv=$(pip2 install $device/$platform/sonic_platform-1.0-py2-none-any.whl) - fi rv=$(pip3 show sonic-platform > /dev/null 2>/dev/null) if [ $? -ne 0 ]; then rv=$(pip3 install $device/$platform/sonic_platform-1.0-py3-none-any.whl) @@ -34,6 +30,7 @@ function load_kernel_modules() ifconfig eth0 hw ether $hwaddr fi depmod -a + modprobe ctc-i2c-mux-pca954x modprobe centec_e530_24x2q_platform modprobe fan-ctc5236 modprobe dal @@ -48,6 +45,7 @@ function remove_kernel_modules() modprobe -r dal modprobe -r fan-ctc5236 modprobe -r centec_e530_24x2q_platform + modprobe -r ctc-i2c-mux-pca954x } case "$1" in diff --git a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2q.install b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2q.install index d572108887af..e57100ec5d91 100644 --- a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2q.install +++ b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-24x2q.install @@ -1,2 +1 @@ -24x2q/modules/sonic_platform-1.0-py2-none-any.whl usr/share/sonic/device/arm64-centec_e530_24x2q-r0 24x2q/modules/sonic_platform-1.0-py3-none-any.whl usr/share/sonic/device/arm64-centec_e530_24x2q-r0 diff --git a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48s4x.init b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48s4x.init index 1fa1970f64d5..25cdbee7fdaa 100644 --- a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48s4x.init +++ b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48s4x.init @@ -17,10 +17,6 @@ function install_python_api_package() device="/usr/share/sonic/device" platform=$(/usr/local/bin/sonic-cfggen -H -v DEVICE_METADATA.localhost.platform) - rv=$(pip2 show sonic-platform > /dev/null 2>/dev/null) - if [ $? -ne 0 ]; then - rv=$(pip2 install $device/$platform/sonic_platform-1.0-py2-none-any.whl) - fi rv=$(pip3 show sonic-platform > /dev/null 2>/dev/null) if [ $? -ne 0 ]; then rv=$(pip3 install $device/$platform/sonic_platform-1.0-py3-none-any.whl) @@ -34,6 +30,7 @@ function load_kernel_modules() ifconfig eth0 hw ether $hwaddr fi depmod -a + modprobe ctc-i2c-mux-pca954x modprobe centec_e530_48s4x_platform modprobe fan-ctc5236 modprobe dal @@ -48,6 +45,7 @@ function remove_kernel_modules() modprobe -r dal modprobe -r fan-ctc5236 modprobe -r centec_e530_48s4x_platform + modprobe -r ctc-i2c-mux-pca954x } case "$1" in diff --git a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48s4x.install b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48s4x.install index d319f3f65548..97296c90af70 100644 --- a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48s4x.install +++ b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48s4x.install @@ -1,2 +1 @@ -48s4x/modules/sonic_platform-1.0-py2-none-any.whl usr/share/sonic/device/arm64-centec_e530_48s4x-r0 48s4x/modules/sonic_platform-1.0-py3-none-any.whl usr/share/sonic/device/arm64-centec_e530_48s4x-r0 diff --git a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48t4x-p.init b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48t4x-p.init index cefacf6668b2..8e2a2bfbddcb 100755 --- a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48t4x-p.init +++ b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48t4x-p.init @@ -17,10 +17,6 @@ function install_python_api_package() device="/usr/share/sonic/device" platform=$(/usr/local/bin/sonic-cfggen -H -v DEVICE_METADATA.localhost.platform) - rv=$(pip2 show sonic-platform > /dev/null 2>/dev/null) - if [ $? -ne 0 ]; then - rv=$(pip2 install $device/$platform/sonic_platform-1.0-py2-none-any.whl) - fi rv=$(pip3 show sonic-platform > /dev/null 2>/dev/null) if [ $? -ne 0 ]; then rv=$(pip3 install $device/$platform/sonic_platform-1.0-py3-none-any.whl) @@ -34,6 +30,7 @@ function load_kernel_modules() ifconfig eth0 hw ether $hwaddr fi depmod -a + modprobe ctc-i2c-mux-pca954x modprobe centec_e530_48t4x_p_platform modprobe fan-ctc5236 modprobe dal @@ -48,6 +45,7 @@ function remove_kernel_modules() modprobe -r dal modprobe -r fan-ctc5236 modprobe -r centec_e530_48t4x_p_platform + modprobe -r ctc-i2c-mux-pca954x } case "$1" in diff --git a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48t4x-p.install b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48t4x-p.install index 634e57f367ee..22fc8eca995e 100644 --- a/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48t4x-p.install +++ b/platform/centec-arm64/sonic-platform-modules-e530/debian/platform-modules-e530-48t4x-p.install @@ -1,2 +1 @@ -48t4x-p/modules/sonic_platform-1.0-py2-none-any.whl usr/share/sonic/device/arm64-centec_e530_48t4x_p-r0 48t4x-p/modules/sonic_platform-1.0-py3-none-any.whl usr/share/sonic/device/arm64-centec_e530_48t4x_p-r0 diff --git a/platform/centec-arm64/sonic-platform-modules-e530/debian/rules b/platform/centec-arm64/sonic-platform-modules-e530/debian/rules index 0fb2c85a8b1b..5351f7f364b4 100755 --- a/platform/centec-arm64/sonic-platform-modules-e530/debian/rules +++ b/platform/centec-arm64/sonic-platform-modules-e530/debian/rules @@ -24,6 +24,7 @@ CLASSES_DIR := classes CONF_DIR := conf KDAL_DIR := ../../centec/centec-dal/ FAN_DIR := fan +PCA954X_DIR := pca954x %: dh $@ @@ -41,10 +42,12 @@ build: (for mod in $(FAN_DIR); do \ make modules -C $(KERNEL_SRC)/build M=$(MOD_SRC_DIR)/$${mod}/; \ done) + (for mod in $(PCA954X_DIR); do \ + make modules -C $(KERNEL_SRC)/build M=$(MOD_SRC_DIR)/$${mod}/; \ + done) (for mod in $(MODULE_DIRS); do \ make modules -C $(KERNEL_SRC)/build M=$(MOD_SRC_DIR)/$${mod}/modules; \ cd $${mod}; \ - python2.7 setup.py bdist_wheel -d $(MOD_SRC_DIR)/$${mod}/modules; \ python3 setup.py bdist_wheel -d $(MOD_SRC_DIR)/$${mod}/modules; \ cd -; \ done) @@ -73,6 +76,7 @@ binary-indep: cp $(MOD_SRC_DIR)/$${mod}/$(MODULE_DIR)/*.ko debian/$(PACKAGE_PRE_NAME)-$${mod}/$(KERNEL_SRC)/$(INSTALL_MOD_DIR); \ cp $(MOD_SRC_DIR)/$(KDAL_DIR)/*.ko debian/$(PACKAGE_PRE_NAME)-$${mod}/$(KERNEL_SRC)/$(INSTALL_MOD_DIR); \ cp $(MOD_SRC_DIR)/$(FAN_DIR)/*.ko debian/$(PACKAGE_PRE_NAME)-$${mod}/$(KERNEL_SRC)/$(INSTALL_MOD_DIR); \ + cp $(MOD_SRC_DIR)/$(PCA954X_DIR)/*.ko debian/$(PACKAGE_PRE_NAME)-$${mod}/$(KERNEL_SRC)/$(INSTALL_MOD_DIR); \ cp $(MOD_SRC_DIR)/$${mod}/$(SERVICE_DIR)/*.service debian/$(PACKAGE_PRE_NAME)-$${mod}/lib/systemd/system/; \ done) # Resuming debhelper scripts diff --git a/platform/centec-arm64/sonic-platform-modules-e530/pca954x/Makefile b/platform/centec-arm64/sonic-platform-modules-e530/pca954x/Makefile new file mode 100644 index 000000000000..0cd3701f1b7f --- /dev/null +++ b/platform/centec-arm64/sonic-platform-modules-e530/pca954x/Makefile @@ -0,0 +1 @@ +obj-m := ctc-i2c-mux-pca954x.o diff --git a/platform/centec-arm64/sonic-platform-modules-e530/pca954x/ctc-i2c-mux-pca954x.c b/platform/centec-arm64/sonic-platform-modules-e530/pca954x/ctc-i2c-mux-pca954x.c new file mode 100644 index 000000000000..3c14bae6654b --- /dev/null +++ b/platform/centec-arm64/sonic-platform-modules-e530/pca954x/ctc-i2c-mux-pca954x.c @@ -0,0 +1,581 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * I2C multiplexer + * + * Copyright (c) 2008-2009 Rodolfo Giometti + * Copyright (c) 2008-2009 Eurotech S.p.A. + * + * This module supports the PCA954x and PCA984x series of I2C multiplexer/switch + * chips made by NXP Semiconductors. + * This includes the: + * PCA9540, PCA9542, PCA9543, PCA9544, PCA9545, PCA9546, PCA9547, + * PCA9548, PCA9846, PCA9847, PCA9848 and PCA9849. + * + * These chips are all controlled via the I2C bus itself, and all have a + * single 8-bit register. The upstream "parent" bus fans out to two, + * four, or eight downstream busses or channels; which of these + * are selected is determined by the chip type and register contents. A + * mux can select only one sub-bus at a time; a switch can select any + * combination simultaneously. + * + * Based on: + * pca954x.c from Kumar Gala + * Copyright (C) 2006 + * + * Based on: + * pca954x.c from Ken Harrenstien + * Copyright (C) 2004 Google, Inc. (Ken Harrenstien) + * + * Based on: + * i2c-virtual_cb.c from Brian Kuschak + * and + * pca9540.c from Jean Delvare . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ctc-pca954x.h" + +#define PCA954X_MAX_NCHANS 8 + +#define PCA954X_IRQ_OFFSET 4 + +enum pca_type { + pca_9540, + pca_9542, + pca_9543, + pca_9544, + pca_9545, + pca_9546, + pca_9547, + pca_9548, + pca_9846, + pca_9847, + pca_9848, + pca_9849, +}; + +struct chip_desc { + u8 nchans; + u8 enable; /* used for muxes only */ + u8 has_irq; + enum muxtype { + pca954x_ismux = 0, + pca954x_isswi + } muxtype; + struct i2c_device_identity id; +}; + +struct pca954x { + const struct chip_desc *chip; + + u8 last_chan; /* last register value */ + /* MUX_IDLE_AS_IS, MUX_IDLE_DISCONNECT or >= 0 for channel */ + s32 idle_state; + + struct i2c_client *client; + + struct irq_domain *irq; + unsigned int irq_mask; + raw_spinlock_t lock; +}; + +/* Provide specs for the PCA954x types we know about */ +static const struct chip_desc chips[] = { + [pca_9540] = { + .nchans = 2, + .enable = 0x4, + .muxtype = pca954x_ismux, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9542] = { + .nchans = 2, + .enable = 0x4, + .has_irq = 1, + .muxtype = pca954x_ismux, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9543] = { + .nchans = 2, + .has_irq = 1, + .muxtype = pca954x_isswi, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9544] = { + .nchans = 4, + .enable = 0x4, + .has_irq = 1, + .muxtype = pca954x_ismux, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9545] = { + .nchans = 4, + .has_irq = 1, + .muxtype = pca954x_isswi, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9546] = { + .nchans = 4, + .muxtype = pca954x_isswi, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9547] = { + .nchans = 8, + .enable = 0x8, + .muxtype = pca954x_ismux, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9548] = { + .nchans = 8, + .muxtype = pca954x_isswi, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9846] = { + .nchans = 4, + .muxtype = pca954x_isswi, + .id = { + .manufacturer_id = I2C_DEVICE_ID_NXP_SEMICONDUCTORS, + .part_id = 0x10b, + }, + }, + [pca_9847] = { + .nchans = 8, + .enable = 0x8, + .muxtype = pca954x_ismux, + .id = { + .manufacturer_id = I2C_DEVICE_ID_NXP_SEMICONDUCTORS, + .part_id = 0x108, + }, + }, + [pca_9848] = { + .nchans = 8, + .muxtype = pca954x_isswi, + .id = { + .manufacturer_id = I2C_DEVICE_ID_NXP_SEMICONDUCTORS, + .part_id = 0x10a, + }, + }, + [pca_9849] = { + .nchans = 4, + .enable = 0x4, + .muxtype = pca954x_ismux, + .id = { + .manufacturer_id = I2C_DEVICE_ID_NXP_SEMICONDUCTORS, + .part_id = 0x109, + }, + }, +}; + +static const struct i2c_device_id pca954x_id[] = { + { "ctc_pca9540", pca_9540 }, + { "ctc_pca9542", pca_9542 }, + { "ctc_pca9543", pca_9543 }, + { "ctc_pca9544", pca_9544 }, + { "ctc_pca9545", pca_9545 }, + { "ctc_pca9546", pca_9546 }, + { "ctc_pca9547", pca_9547 }, + { "ctc_pca9548", pca_9548 }, + { "ctc_pca9846", pca_9846 }, + { "ctc_pca9847", pca_9847 }, + { "ctc_pca9848", pca_9848 }, + { "ctc_pca9849", pca_9849 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, pca954x_id); + +static const struct of_device_id pca954x_of_match[] = { + { .compatible = "nxp,ctc_pca9540", .data = &chips[pca_9540] }, + { .compatible = "nxp,ctc_pca9542", .data = &chips[pca_9542] }, + { .compatible = "nxp,ctc_pca9543", .data = &chips[pca_9543] }, + { .compatible = "nxp,ctc_pca9544", .data = &chips[pca_9544] }, + { .compatible = "nxp,ctc_pca9545", .data = &chips[pca_9545] }, + { .compatible = "nxp,ctc_pca9546", .data = &chips[pca_9546] }, + { .compatible = "nxp,ctc_pca9547", .data = &chips[pca_9547] }, + { .compatible = "nxp,ctc_pca9548", .data = &chips[pca_9548] }, + { .compatible = "nxp,ctc_pca9846", .data = &chips[pca_9846] }, + { .compatible = "nxp,ctc_pca9847", .data = &chips[pca_9847] }, + { .compatible = "nxp,ctc_pca9848", .data = &chips[pca_9848] }, + { .compatible = "nxp,ctc_pca9849", .data = &chips[pca_9849] }, + {} +}; +MODULE_DEVICE_TABLE(of, pca954x_of_match); + +/* Write to mux register. Don't use i2c_transfer()/i2c_smbus_xfer() + for this as they will try to lock adapter a second time */ +static int pca954x_reg_write(struct i2c_adapter *adap, + struct i2c_client *client, u8 val) +{ + union i2c_smbus_data dummy; + + return __i2c_smbus_xfer(adap, client->addr, client->flags, + I2C_SMBUS_WRITE, val, + I2C_SMBUS_BYTE, &dummy); +} + +static u8 pca954x_regval(struct pca954x *data, u8 chan) +{ + /* We make switches look like muxes, not sure how to be smarter. */ + if (data->chip->muxtype == pca954x_ismux) + return chan | data->chip->enable; + else + return 1 << chan; +} + +static int pca954x_select_chan(struct i2c_mux_core *muxc, u32 chan) +{ + struct pca954x *data = i2c_mux_priv(muxc); + struct i2c_client *client = data->client; + u8 regval; + int ret = 0; + + regval = pca954x_regval(data, chan); + /* Only select the channel if its different from the last channel */ + if (data->last_chan != regval) { + ret = pca954x_reg_write(muxc->parent, client, regval); + data->last_chan = ret < 0 ? 0 : regval; + } + + return ret; +} + +static int pca954x_deselect_mux(struct i2c_mux_core *muxc, u32 chan) +{ + struct pca954x *data = i2c_mux_priv(muxc); + struct i2c_client *client = data->client; + s32 idle_state; + + idle_state = READ_ONCE(data->idle_state); + if (idle_state >= 0) + /* Set the mux back to a predetermined channel */ + return pca954x_select_chan(muxc, idle_state); + + if (idle_state == MUX_IDLE_DISCONNECT) { + /* Deselect active channel */ + data->last_chan = 0; + return pca954x_reg_write(muxc->parent, client, + data->last_chan); + } + + /* otherwise leave as-is */ + + return 0; +} + +static ssize_t idle_state_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct i2c_mux_core *muxc = i2c_get_clientdata(client); + struct pca954x *data = i2c_mux_priv(muxc); + + return sprintf(buf, "%d\n", READ_ONCE(data->idle_state)); +} + +static ssize_t idle_state_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev); + struct i2c_mux_core *muxc = i2c_get_clientdata(client); + struct pca954x *data = i2c_mux_priv(muxc); + int val; + int ret; + + ret = kstrtoint(buf, 0, &val); + if (ret < 0) + return ret; + + if (val != MUX_IDLE_AS_IS && val != MUX_IDLE_DISCONNECT && + (val < 0 || val >= data->chip->nchans)) + return -EINVAL; + + i2c_lock_bus(muxc->parent, I2C_LOCK_SEGMENT); + + WRITE_ONCE(data->idle_state, val); + /* + * Set the mux into a state consistent with the new + * idle_state. + */ + if (data->last_chan || val != MUX_IDLE_DISCONNECT) + ret = pca954x_deselect_mux(muxc, 0); + + i2c_unlock_bus(muxc->parent, I2C_LOCK_SEGMENT); + + return ret < 0 ? ret : count; +} + +static DEVICE_ATTR_RW(idle_state); + +static irqreturn_t pca954x_irq_handler(int irq, void *dev_id) +{ + struct pca954x *data = dev_id; + unsigned long pending; + int ret, i; + + ret = i2c_smbus_read_byte(data->client); + if (ret < 0) + return IRQ_NONE; + + pending = (ret >> PCA954X_IRQ_OFFSET) & (BIT(data->chip->nchans) - 1); + for_each_set_bit(i, &pending, data->chip->nchans) + handle_nested_irq(irq_linear_revmap(data->irq, i)); + + return IRQ_RETVAL(pending); +} + +static int pca954x_irq_set_type(struct irq_data *idata, unsigned int type) +{ + if ((type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_LOW) + return -EINVAL; + return 0; +} + +static struct irq_chip pca954x_irq_chip = { + .name = "i2c-mux-pca954x", + .irq_set_type = pca954x_irq_set_type, +}; + +static int pca954x_irq_setup(struct i2c_mux_core *muxc) +{ + struct pca954x *data = i2c_mux_priv(muxc); + struct i2c_client *client = data->client; + int c, irq; + + if (!data->chip->has_irq || client->irq <= 0) + return 0; + + raw_spin_lock_init(&data->lock); + + data->irq = irq_domain_add_linear(client->dev.of_node, + data->chip->nchans, + &irq_domain_simple_ops, data); + if (!data->irq) + return -ENODEV; + + for (c = 0; c < data->chip->nchans; c++) { + irq = irq_create_mapping(data->irq, c); + if (!irq) { + dev_err(&client->dev, "failed irq create map\n"); + return -EINVAL; + } + irq_set_chip_data(irq, data); + irq_set_chip_and_handler(irq, &pca954x_irq_chip, + handle_simple_irq); + } + + return 0; +} + +static void pca954x_cleanup(struct i2c_mux_core *muxc) +{ + struct pca954x *data = i2c_mux_priv(muxc); + int c, irq; + + if (data->irq) { + for (c = 0; c < data->chip->nchans; c++) { + irq = irq_find_mapping(data->irq, c); + irq_dispose_mapping(irq); + } + irq_domain_remove(data->irq); + } + i2c_mux_del_adapters(muxc); +} + +static int pca954x_init(struct i2c_client *client, struct pca954x *data) +{ + int ret; + + if (data->idle_state >= 0) + data->last_chan = pca954x_regval(data, data->idle_state); + else + data->last_chan = 0; /* Disconnect multiplexer */ + + ret = i2c_smbus_write_byte(client, data->last_chan); + if (ret < 0) + data->last_chan = 0; + + return ret; +} + +/* + * I2C init/probing/exit functions + */ +static int pca954x_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct i2c_adapter *adap = client->adapter; + struct pca954x_platform_data *pdata = dev_get_platdata(&client->dev); + struct device *dev = &client->dev; + struct gpio_desc *gpio; + int num, force, class; + struct i2c_mux_core *muxc; + struct pca954x *data; + int ret; + + if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_BYTE)) + return -ENODEV; + + muxc = i2c_mux_alloc(adap, dev, PCA954X_MAX_NCHANS, sizeof(*data), 0, + pca954x_select_chan, pca954x_deselect_mux); + if (!muxc) + return -ENOMEM; + data = i2c_mux_priv(muxc); + + i2c_set_clientdata(client, muxc); + data->client = client; + + /* Reset the mux if a reset GPIO is specified. */ + gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(gpio)) + return PTR_ERR(gpio); + if (gpio) { + udelay(1); + gpiod_set_value_cansleep(gpio, 0); + /* Give the chip some time to recover. */ + udelay(1); + } + + data->chip = device_get_match_data(dev); + if (!data->chip) + data->chip = &chips[id->driver_data]; + + if (data->chip->id.manufacturer_id != I2C_DEVICE_ID_NONE) { + struct i2c_device_identity id; + + ret = i2c_get_device_id(client, &id); + if (ret && ret != -EOPNOTSUPP) + return ret; + + if (!ret && + (id.manufacturer_id != data->chip->id.manufacturer_id || + id.part_id != data->chip->id.part_id)) { + dev_warn(dev, "unexpected device id %03x-%03x-%x\n", + id.manufacturer_id, id.part_id, + id.die_revision); + return -ENODEV; + } + } + + data->idle_state = MUX_IDLE_AS_IS; + if (device_property_read_u32(dev, "idle-state", &data->idle_state)) { + if (device_property_read_bool(dev, "i2c-mux-idle-disconnect")) + data->idle_state = MUX_IDLE_DISCONNECT; + } + + /* + * Write the mux register at addr to verify + * that the mux is in fact present. This also + * initializes the mux to a channel + * or disconnected state. + */ + ret = pca954x_init(client, data); + if (ret < 0) { + dev_warn(dev, "probe failed\n"); + return -ENODEV; + } + + ret = pca954x_irq_setup(muxc); + if (ret) + goto fail_cleanup; + + /* Now create an adapter for each channel */ + for (num = 0; num < data->chip->nchans; num++) { + force = 0; /* dynamic adap number */ + class = 0; /* no class by default */ + if (pdata) { + if (num < pdata->num_modes) { + /* force static number */ + force = pdata->modes[num].adap_id; + class = pdata->modes[num].class; + } else + /* discard unconfigured channels */ + break; + } + + ret = i2c_mux_add_adapter(muxc, force, num, class); + if (ret) + goto fail_cleanup; + } + + if (data->irq) { + ret = devm_request_threaded_irq(dev, data->client->irq, + NULL, pca954x_irq_handler, + IRQF_ONESHOT | IRQF_SHARED, + "pca954x", data); + if (ret) + goto fail_cleanup; + } + + /* + * The attr probably isn't going to be needed in most cases, + * so don't fail completely on error. + */ + device_create_file(dev, &dev_attr_idle_state); + + dev_info(dev, "registered %d multiplexed busses for I2C %s %s\n", + num, data->chip->muxtype == pca954x_ismux + ? "mux" : "switch", client->name); + + return 0; + +fail_cleanup: + pca954x_cleanup(muxc); + return ret; +} + +static int pca954x_remove(struct i2c_client *client) +{ + struct i2c_mux_core *muxc = i2c_get_clientdata(client); + + device_remove_file(&client->dev, &dev_attr_idle_state); + + pca954x_cleanup(muxc); + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int pca954x_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct i2c_mux_core *muxc = i2c_get_clientdata(client); + struct pca954x *data = i2c_mux_priv(muxc); + int ret; + + ret = pca954x_init(client, data); + if (ret < 0) + dev_err(&client->dev, "failed to verify mux presence\n"); + + return ret; +} +#endif + +static SIMPLE_DEV_PM_OPS(pca954x_pm, NULL, pca954x_resume); + +static struct i2c_driver pca954x_driver = { + .driver = { + .name = "ctc_pca954x", + .pm = &pca954x_pm, + .of_match_table = pca954x_of_match, + }, + .probe = pca954x_probe, + .remove = pca954x_remove, + .id_table = pca954x_id, +}; + +module_i2c_driver(pca954x_driver); + +MODULE_AUTHOR("Rodolfo Giometti "); +MODULE_DESCRIPTION("PCA954x I2C mux/switch driver"); +MODULE_LICENSE("GPL v2"); diff --git a/platform/centec-arm64/sonic-platform-modules-e530/pca954x/ctc-pca954x.h b/platform/centec-arm64/sonic-platform-modules-e530/pca954x/ctc-pca954x.h new file mode 100644 index 000000000000..eab9cdd990c9 --- /dev/null +++ b/platform/centec-arm64/sonic-platform-modules-e530/pca954x/ctc-pca954x.h @@ -0,0 +1,48 @@ +/* + * + * pca954x.h - I2C multiplexer/switch support + * + * Copyright (c) 2008-2009 Rodolfo Giometti + * Copyright (c) 2008-2009 Eurotech S.p.A. + * Michael Lawnick + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + +#ifndef _LINUX_I2C_PCA954X_H +#define _LINUX_I2C_PCA954X_H + +/* Platform data for the PCA954x I2C multiplexers */ + +/* Per channel initialisation data: + * @adap_id: bus number for the adapter. 0 = don't care + * @deselect_on_exit: set this entry to 1, if your H/W needs deselection + * of this channel after transaction. + * + */ +struct pca954x_platform_mode { + int adap_id; + unsigned int deselect_on_exit:1; + unsigned int class; +}; + +/* Per mux/switch data, used with i2c_register_board_info */ +struct pca954x_platform_data { + struct pca954x_platform_mode *modes; + int num_modes; +}; + +#endif /* _LINUX_I2C_PCA954X_H */ diff --git a/platform/centec-arm64/sonic_fit.its b/platform/centec-arm64/sonic_fit.its index 7ee89e6c812f..71b013ab3221 100644 --- a/platform/centec-arm64/sonic_fit.its +++ b/platform/centec-arm64/sonic_fit.its @@ -12,7 +12,7 @@ images { kernel_ctc { description = "ARM64 Kernel"; - data = /incbin/("./vmlinuz-4.19.0-12-2-arm64"); + data = /incbin/("./vmlinuz-5.10.0-8-2-arm64"); type = "kernel"; arch = "arm64"; os = "linux"; @@ -25,7 +25,7 @@ }; initramfs { description = "initramfs"; - data = /incbin/("./initrd.img-4.19.0-12-2-arm64"); + data = /incbin/("./initrd.img-5.10.0-8-2-arm64"); type = "ramdisk"; arch = "arm64"; os = "linux"; diff --git a/platform/centec-arm64/tsingma-bsp/debian/control b/platform/centec-arm64/tsingma-bsp/debian/control index fc6d0b8def4f..9be7aa41d47e 100644 --- a/platform/centec-arm64/tsingma-bsp/debian/control +++ b/platform/centec-arm64/tsingma-bsp/debian/control @@ -7,5 +7,5 @@ Standards-Version: 3.9.3 Package: tsingma-bsp Architecture: arm64 -Depends: linux-image-4.19.0-12-2-arm64-unsigned +Depends: linux-image-5.10.0-8-2-arm64-unsigned Description: kernel modules for tsingma bsp diff --git a/platform/centec-arm64/tsingma-bsp/debian/rules b/platform/centec-arm64/tsingma-bsp/debian/rules old mode 100644 new mode 100755 index 17788b62411a..39744906e3cf --- a/platform/centec-arm64/tsingma-bsp/debian/rules +++ b/platform/centec-arm64/tsingma-bsp/debian/rules @@ -15,7 +15,7 @@ PACKAGE_PRE_NAME := tsingma-bsp KVERSION ?= $(shell uname -r) KERNEL_SRC := /lib/modules/$(KVERSION) MOD_SRC_DIR:= $(shell pwd) -MODULE_DIRS:= ctc5236-mc ctc5236_switch ctcmac ctc_wdt ehci-ctc gpio-ctc i2c-ctc pinctrl-ctc pwm-ctc rtc-sd2405 sdhci-ctc5236 spi-ctc-qspi +MODULE_DIRS:= ctc5236-mc ctc5236_switch ctcmac ctc_wdt ehci-ctc gpio-ctc i2c-ctc pinctrl-ctc pwm-ctc rtc-sd2405 sdhci-ctc5236 spi-ctc-qspi ctc-phy DTS_DIR := ctc-dts MODULE_DIR := src UTILS_DIR := utils diff --git a/platform/centec-arm64/tsingma-bsp/debian/tsingma-bsp.install b/platform/centec-arm64/tsingma-bsp/debian/tsingma-bsp.install index e2fb35af1b6c..ea3262bff452 100644 --- a/platform/centec-arm64/tsingma-bsp/debian/tsingma-bsp.install +++ b/platform/centec-arm64/tsingma-bsp/debian/tsingma-bsp.install @@ -1,17 +1,17 @@ -src/ctc5236-mc/ctc5236-mc.ko /lib/modules/4.19.0-12-2-arm64/kernel/extra -src/pwm-ctc/pwm-ctc.ko /lib/modules/4.19.0-12-2-arm64/kernel/extra -src/ctc5236_switch/ctc5236_switch.ko /lib/modules/4.19.0-12-2-arm64/kernel/extra -src/pinctrl-ctc/pinctrl-ctc.ko /lib/modules/4.19.0-12-2-arm64/kernel/extra -src/ctc_wdt/ctc_wdt.ko /lib/modules/4.19.0-12-2-arm64/kernel/extra -src/ctcmac/ctcmac.ko /lib/modules/4.19.0-12-2-arm64/kernel/extra -src/ctcmac/ctcmac_test.ko /lib/modules/4.19.0-12-2-arm64/kernel/extra -src/ctcmac/ctc5236_mdio.ko /lib/modules/4.19.0-12-2-arm64/kernel/extra -src/i2c-ctc/i2c-ctc.ko /lib/modules/4.19.0-12-2-arm64/kernel/extra -src/gpio-ctc/gpio-ctc.ko /lib/modules/4.19.0-12-2-arm64/kernel/extra -src/ehci-ctc/ehci-ctc.ko /lib/modules/4.19.0-12-2-arm64/kernel/extra -src/rtc-sd2405/rtc-sd2405.ko /lib/modules/4.19.0-12-2-arm64/kernel/extra -src/sdhci-ctc5236/sdhci-ctc5236.ko /lib/modules/4.19.0-12-2-arm64/kernel/extra -src/spi-ctc-qspi/spi-ctc-qspi.ko /lib/modules/4.19.0-12-2-arm64/kernel/extra +src/ctc5236-mc/ctc5236-mc.ko /lib/modules/5.10.0-8-2-arm64/kernel/extra +src/pwm-ctc/pwm-ctc.ko /lib/modules/5.10.0-8-2-arm64/kernel/extra +src/ctc5236_switch/ctc5236_switch.ko /lib/modules/5.10.0-8-2-arm64/kernel/extra +src/pinctrl-ctc/pinctrl-ctc.ko /lib/modules/5.10.0-8-2-arm64/kernel/extra +src/ctc_wdt/ctc_wdt.ko /lib/modules/5.10.0-8-2-arm64/kernel/extra +src/ctcmac/ctcmac.ko /lib/modules/5.10.0-8-2-arm64/kernel/extra +src/ctcmac/ctc5236_mdio.ko /lib/modules/5.10.0-8-2-arm64/kernel/extra +src/ctc-phy/mars.ko /lib/modules/5.10.0-8-2-arm64/kernel/extra +src/i2c-ctc/i2c-ctc.ko /lib/modules/5.10.0-8-2-arm64/kernel/extra +src/gpio-ctc/gpio-ctc.ko /lib/modules/5.10.0-8-2-arm64/kernel/extra +src/ehci-ctc/ehci-ctc.ko /lib/modules/5.10.0-8-2-arm64/kernel/extra +src/rtc-sd2405/rtc-sd2405.ko /lib/modules/5.10.0-8-2-arm64/kernel/extra +src/sdhci-ctc5236/sdhci-ctc5236.ko /lib/modules/5.10.0-8-2-arm64/kernel/extra +src/spi-ctc-qspi/spi-ctc-qspi.ko /lib/modules/5.10.0-8-2-arm64/kernel/extra src/ctc-dts/e530-ctc5236.dtb /boot/ src/config/fw_env.config /etc/ src/config/tsingma-bsp.service /lib/systemd/system diff --git a/platform/centec-arm64/tsingma-bsp/src/ctc-dts/arm-gic.h b/platform/centec-arm64/tsingma-bsp/src/ctc-dts/arm-gic.h old mode 100644 new mode 100755 index 8c75d237d4b7..ef79498bdde5 --- a/platform/centec-arm64/tsingma-bsp/src/ctc-dts/arm-gic.h +++ b/platform/centec-arm64/tsingma-bsp/src/ctc-dts/arm-gic.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * This header provides constants for the ARM GIC. */ diff --git a/platform/centec-arm64/tsingma-bsp/src/ctc-dts/ctc5236.dtsi b/platform/centec-arm64/tsingma-bsp/src/ctc-dts/ctc5236.dtsi old mode 100644 new mode 100755 index d92000612c29..41932f88b46c --- a/platform/centec-arm64/tsingma-bsp/src/ctc-dts/ctc5236.dtsi +++ b/platform/centec-arm64/tsingma-bsp/src/ctc-dts/ctc5236.dtsi @@ -88,7 +88,11 @@ memory-controller@30600000 { compatible = "ctc,ctc5236-ddr-ctrl"; reg = <0x0 0x30600000 0x0 0x100000>; - interrupts = ; + interrupts = , + , + , + ; + ctc,sysctrl = <&sysctrl>; }; sysctrl: sysctrl@33200000 { @@ -136,12 +140,15 @@ #size-cells = <2>; interrupt-parent = <&gic>; status = "disabled"; + local-mac-address = [00 00 00 00 00 00]; index = <0x00>; reg = <0x0 0x33410000 0x0 0x10000>, <0x0 0x33400000 0x0 0x10000>; interrupts = , , - ; + , + , + ; ctc,sysctrl = <&sysctrl>; }; @@ -152,12 +159,15 @@ #size-cells = <2>; interrupt-parent = <&gic>; status = "disabled"; + local-mac-address = [00 00 00 00 00 00]; index = <0x01>; reg = <0x0 0x33420000 0x0 0x10000>, <0x0 0x33400000 0x0 0x10000>; interrupts = , , - ; + , + , + ; ctc,sysctrl = <&sysctrl>; }; @@ -165,6 +175,7 @@ compatible = "ctc-ehci"; reg = <0x0 0x30500000 0x0 0x1000>; interrupts = ; + ctc,sysctrl = <&sysctrl>; status = "disabled"; }; @@ -172,7 +183,7 @@ compatible = "generic-ohci"; reg = <0x0 0x30580000 0x0 0x1000>; interrupts = ; - status = "disabled"; + status = "okay"; }; spi: spi@33100000 { @@ -188,7 +199,7 @@ status ="disabled"; }; - qspi: qspi@10000000 { + qspi: spi@10000000 { compatible = "ctc, igdaxi001a-qspi"; #address-cells = <1>; #size-cells = <0>; @@ -228,6 +239,8 @@ reg = <0x0 0x33700000 0x0 0x1000>; interrupts = ; clocks = <&i2c_clk>; + ctc,sysctrl = <&sysctrl>; + i2c-num = <0>; status ="disabled"; }; @@ -238,6 +251,8 @@ reg = <0x0 0x33701000 0x0 0x1000>; interrupts = ; clocks = <&i2c_clk>; + ctc,sysctrl = <&sysctrl>; + i2c-num = <1>; status ="disabled"; }; @@ -257,7 +272,8 @@ interrupt-names = "msi","aer","pme"; msi-parent = <&pcie>; bus-range = <0 0xff>; - ranges = <0x43000000 0 0x00000000 0 0x40000000 0 0x40000000>; + ranges = <0x42000000 0 0x00000000 0 0x40000000 0 0x20000000 + 0x02000000 0 0x20000000 0 0x60000000 0 0x20000000>; num-lanes = <1>; ctc,sysctrl = <&sysctrl>; status ="disabled"; @@ -338,6 +354,7 @@ reg = <0x0 0x33610000 0x0 0x10000>; #address-cells = <1>; #size-cells = <0>; + ctc,sysctrl = <&sysctrl>; porta: gpio-port@0 { compatible = "ctc,apb-gpio-porta"; @@ -368,7 +385,42 @@ ctc,pinctrl-bank0 = <16>; ctc,pinctrl-bank1 = <8>; ctc,sysctrl = <&sysctrl>; - status = "okay"; + + spi0 { + spi_pin: spi_pin { + ctc,pins = <0 0 PIN_FUNC_SPI>, + <0 2 PIN_FUNC_SPI>, + <0 3 PIN_FUNC_SPI>, + <0 4 PIN_FUNC_SPI>, + <0 5 PIN_FUNC_SPI>, + <0 6 PIN_FUNC_SPI>, + <0 7 PIN_FUNC_SPI>; + }; + }; + + uart2 { + uart2_pin: uart2_pin { + ctc,pins = <0 10 PIN_FUNC_UART>, + <0 11 PIN_FUNC_UART>, + <0 12 PIN_FUNC_UART>, + <0 13 PIN_FUNC_UART>, + <0 14 PIN_FUNC_UART>, + <0 15 PIN_FUNC_UART>; + }; + }; + + fc { + fc_pin: fc_pin { + ctc,pins = <1 0 PIN_FUNC_FC>, + <1 1 PIN_FUNC_FC>, + <1 2 PIN_FUNC_FC>, + <1 3 PIN_FUNC_FC>, + <1 4 PIN_FUNC_FC>, + <1 5 PIN_FUNC_FC>, + <1 6 PIN_FUNC_FC>, + <1 7 PIN_FUNC_FC>; + }; + }; }; }; diff --git a/platform/centec-arm64/tsingma-bsp/src/ctc-dts/e530-ctc5236.dts b/platform/centec-arm64/tsingma-bsp/src/ctc-dts/e530-ctc5236.dts index d8544666e2ce..422cf22fbae7 100644 --- a/platform/centec-arm64/tsingma-bsp/src/ctc-dts/e530-ctc5236.dts +++ b/platform/centec-arm64/tsingma-bsp/src/ctc-dts/e530-ctc5236.dts @@ -157,6 +157,7 @@ non-removable; no-sd; no-sdio; + cap-mmc-hw-reset; voltage-ranges = <3300 3300>; status = "okay"; }; @@ -187,7 +188,7 @@ &pinctrl { - spi { + spi0 { spi_pin: spi_pin { status = "disabled"; ctc,pins = <0 0 PIN_FUNC_SPI>, diff --git a/platform/centec-arm64/tsingma-bsp/src/ctc-dts/irq.h b/platform/centec-arm64/tsingma-bsp/src/ctc-dts/irq.h index 33a1003c55aa..9e3d183e1381 100644 --- a/platform/centec-arm64/tsingma-bsp/src/ctc-dts/irq.h +++ b/platform/centec-arm64/tsingma-bsp/src/ctc-dts/irq.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * This header provides constants for most IRQ bindings. * diff --git a/platform/centec-arm64/tsingma-bsp/src/ctc-phy/Makefile b/platform/centec-arm64/tsingma-bsp/src/ctc-phy/Makefile new file mode 100644 index 000000000000..eb040d626d51 --- /dev/null +++ b/platform/centec-arm64/tsingma-bsp/src/ctc-phy/Makefile @@ -0,0 +1 @@ +obj-m = mars.o diff --git a/platform/centec-arm64/tsingma-bsp/src/ctc-phy/mars.c b/platform/centec-arm64/tsingma-bsp/src/ctc-phy/mars.c new file mode 100644 index 000000000000..675ba528fe68 --- /dev/null +++ b/platform/centec-arm64/tsingma-bsp/src/ctc-phy/mars.c @@ -0,0 +1,316 @@ +/* + * drivers/net/phy/mars.c + * + * Driver for Centec PHYs + * + * Author: liuht + * + * Copyright 2002-2018, Centec Networks (Suzhou) Co., Ltd. + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + + /* Mask used for ID comparisons */ +#define CTC_PHY_ID_MASK 0xffffffff + +/* Known PHY IDs */ +#define CTC_PHY_ID_MARS1S_V1 0x00782013 +#define CTC_PHY_ID_MARS1S 0x01E04013 +#define CTC_PHY_ID_MARS1P_V1 0x00782011 +#define CTC_PHY_ID_MARS1P 0x01E04011 +#define CTC_PHY_IMASK 0x12 +#define CTC_PHY_IEVENT 0x13 + +#define CTC_PHY_IMASK_INIT 0x6c00 +#define CTC_PHY_IMASK_CLEAR 0x0000 + +#define CTC_PHY_REG_SPACE 0 +#define CTC_SDS_REG_SPACE 1 + +static int mars_ext_read(struct phy_device *phydev, u32 regnum) +{ + int ret; + + ret = phy_write(phydev, 0x1e, regnum); + if (ret < 0) + return ret; + + return phy_read(phydev, 0x1f); +} + +static int mars_ext_write(struct phy_device *phydev, u32 regnum, u16 val) +{ + int ret; + + ret = phy_write(phydev, 0x1e, regnum); + if (ret < 0) + return ret; + + return phy_write(phydev, 0x1f, val); +} + +static int mars_select_reg_space(struct phy_device *phydev, int space) +{ + int ret; + + if (space == CTC_PHY_REG_SPACE) { + ret = mars_ext_write(phydev, 0xa000, 0x0); + } else { + ret = mars_ext_write(phydev, 0xa000, 0x2); + } + + return ret; +} + +static int mars_config_advert(struct phy_device *phydev) +{ + int err, bmsr, changed = 0; + u32 adv; + + /* Only allow advertising what this PHY supports */ + linkmode_and(phydev->advertising, phydev->advertising, + phydev->supported); + + adv = linkmode_adv_to_mii_adv_t(phydev->advertising); + + /* Setup standard advertisement */ + err = phy_modify_changed(phydev, MII_ADVERTISE, + ADVERTISE_ALL | ADVERTISE_100BASE4 | + ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, + adv); + if (err < 0) + return err; + if (err > 0) + changed = 1; + + bmsr = phy_read(phydev, MII_BMSR); + if (bmsr < 0) + return bmsr; + + /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all + * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a + * logical 1. + */ + if (!(bmsr & BMSR_ESTATEN)) + return changed; + + adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); + + err = phy_modify_changed(phydev, MII_CTRL1000, + ADVERTISE_1000FULL | ADVERTISE_1000HALF, adv); + if (err < 0) + return err; + if (err > 0) + changed = 1; + + return changed; +} + +int mars1s_config_aneg(struct phy_device *phydev) +{ + int err, changed = 0; + + if (AUTONEG_ENABLE != phydev->autoneg) + return genphy_setup_forced(phydev); + + err = mars_config_advert(phydev); + if (err < 0) /* error */ + return err; + + changed |= err; + + if (changed == 0) { + /* Advertisement hasn't changed, but maybe aneg was never on to + * begin with? Or maybe phy was isolated? + */ + int ctl = phy_read(phydev, MII_BMCR); + + if (ctl < 0) + return ctl; + + if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE)) + changed = 1; /* do restart aneg */ + } + + /* Only restart aneg if we are advertising something different + * than we were before. + */ + if (changed > 0) + return genphy_restart_aneg(phydev); + + return 0; +} + +static int mars_ack_interrupt(struct phy_device *phydev) +{ + int err; + +#if 1 + /* Clear the interrupts by reading the reg */ + err = phy_read(phydev, CTC_PHY_IEVENT); +#else + err = mars_ext_read(phydev, 0xa011); +#endif + if (err < 0) + return err; + + return 0; +} + +static int mars_config_intr(struct phy_device *phydev) +{ + int err; + +#if 1 + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) + err = phy_write(phydev, CTC_PHY_IMASK, CTC_PHY_IMASK_INIT); + else + err = phy_write(phydev, CTC_PHY_IMASK, CTC_PHY_IMASK_CLEAR); +#else + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) + err = mars_ext_write(phydev, 0xa010, 0xffff); + else + err = mars_ext_write(phydev, 0xa010, 0x0000); +#endif + return err; +} + +#if 0 +static int mars_set_link_timer_6_3ms(struct phy_device *phydev) +{ + int ret = 0; + + ret = mars_select_reg_space(phydev, CTC_SDS_REG_SPACE); + if (!ret) + mars_ext_write(phydev, 0xa5, 0xc); + mars_select_reg_space(phydev, CTC_PHY_REG_SPACE); + + return 0; +} +#endif + +static int mars_set_link_timer_2_6ms(struct phy_device *phydev) +{ + int ret = 0; + + ret = mars_select_reg_space(phydev, CTC_SDS_REG_SPACE); + if (!ret) + mars_ext_write(phydev, 0xa5, 0x5); + mars_select_reg_space(phydev, CTC_PHY_REG_SPACE); + + return 0; +} + +int mars_config_init(struct phy_device *phydev) +{ + return mars_set_link_timer_2_6ms(phydev); +} + +int mars1p_config_init(struct phy_device *phydev) +{ + /*RGMII clock 2.5M when link down, bit12:1->0 */ + mars_ext_write(phydev, 0xc, 0x8051); + /*Disable sleep mode, bit15:1->0 */ + mars_ext_write(phydev, 0x27, 0x2029); + /* disable PHY to respond to MDIO access with PHYAD0 */ + /* MMD7 8001h: bit6: 0, change value: 0x7f --> 0x3f */ + phy_write(phydev, 0xd, 0x7); + phy_write(phydev, 0xe, 0x8001); + phy_write(phydev, 0xd, 0x4007); + phy_write(phydev, 0xe, 0x3f); + + return mars_set_link_timer_2_6ms(phydev); +} + +static struct phy_driver ctc_drivers[] = { + { + .phy_id = CTC_PHY_ID_MARS1S, + .phy_id_mask = CTC_PHY_ID_MASK, + .name = "CTC MARS1S", + .config_init = mars_config_init, + .features = PHY_GBIT_FEATURES, + .config_aneg = mars1s_config_aneg, + .ack_interrupt = &mars_ack_interrupt, + .config_intr = &mars_config_intr, + .read_status = genphy_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, + { + .phy_id = CTC_PHY_ID_MARS1S_V1, + .phy_id_mask = CTC_PHY_ID_MASK, + .name = "CTC MARS1S_V1", + .config_init = mars_config_init, + .features = PHY_GBIT_FEATURES, + .config_aneg = mars1s_config_aneg, + .ack_interrupt = &mars_ack_interrupt, + .config_intr = &mars_config_intr, + .read_status = genphy_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, + { + .phy_id = CTC_PHY_ID_MARS1P, + .phy_id_mask = CTC_PHY_ID_MASK, + .name = "CTC MARS1P", + .config_init = mars1p_config_init, + .features = PHY_GBIT_FEATURES, + .config_aneg = mars1s_config_aneg, + .ack_interrupt = &mars_ack_interrupt, + .config_intr = &mars_config_intr, + .read_status = genphy_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, + { + .phy_id = CTC_PHY_ID_MARS1P_V1, + .phy_id_mask = CTC_PHY_ID_MASK, + .name = "CTC MARS1P_V1", + .config_init = mars1p_config_init, + .features = PHY_GBIT_FEATURES, + .config_aneg = mars1s_config_aneg, + .ack_interrupt = &mars_ack_interrupt, + .config_intr = &mars_config_intr, + .read_status = genphy_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, +}; + +module_phy_driver(ctc_drivers); + +static struct mdio_device_id __maybe_unused mars_tbl[] = { + {CTC_PHY_ID_MARS1S, CTC_PHY_ID_MASK}, + {CTC_PHY_ID_MARS1S_V1, CTC_PHY_ID_MASK}, + {CTC_PHY_ID_MARS1P, CTC_PHY_ID_MASK}, + {CTC_PHY_ID_MARS1P_V1, CTC_PHY_ID_MASK}, + {} +}; + +MODULE_DEVICE_TABLE(mdio, mars_tbl); diff --git a/platform/centec-arm64/tsingma-bsp/src/ctc5236-mc/ctc5236-mc.c b/platform/centec-arm64/tsingma-bsp/src/ctc5236-mc/ctc5236-mc.c old mode 100644 new mode 100755 index 55c86b3a5626..0ecde7bff4fb --- a/platform/centec-arm64/tsingma-bsp/src/ctc5236-mc/ctc5236-mc.c +++ b/platform/centec-arm64/tsingma-bsp/src/ctc5236-mc/ctc5236-mc.c @@ -1,4 +1,5 @@ -/* Centec TsingMa Memory Controller Driver +/* + * Centec TsingMa Memory Contoller Driver * * Author: lius * @@ -22,22 +23,29 @@ #include #include #include +#include "../include/sysctl.h" +#include +#include struct ctc5236_mc { struct device *dev; void __iomem *base; int irq; - + int irq1; /* one bit ecc error irq num, only use in TM1.1 */ + int irq2; /* more than one bit ecc error irq num, only use in TM1.1 */ + int irq_cache_ecc; /* cache error interrupt */ + struct regmap *regmap_base; + unsigned int soc_ver; }; /* DDR interrupt enable register */ -#define DDR_ERR_INT_EN 0xF0 +#define DDR_ERR_INT_EN 0xF0 /* DDR interrupt status register */ -#define DDR_ERR_INT_STATUS 0xF4 +#define DDR_ERR_INT_STATUS 0xF4 /* over top-bound info register*/ -#define DDR_ERR_INT_OVER_TOPBOUND_L 0xF8 +#define DDR_ERR_INT_OVER_TOPBOUND_L 0xF8 #define DDR_ERR_INT_OVER_TOPBOUND_H 0xFC #define DDR_PORT0_ERR_INT_STATUS 0x1 @@ -45,15 +53,16 @@ struct ctc5236_mc { #define DDR_PORT2_ERR_INT_STATUS 0x3 #define DDR_PORT3_ERR_INT_STATUS 0x4 #define DDR_ERR_ECC_INT_STATUS 0x10000 +#define DDR_ERR_CRC_INT_STATUS 0x200000 #define DDR_ERR_WR_PORT_REC_UNDERFLOW 0x20000 #define DDR_ERR_WR_PORT_REC_OVERFLOW 0x40000 #define DDR_ERR_RD_PORT_REC_UNDERFLOW 0x80000 #define DDR_ERR_RD_PORT_REC_OVERFLOW 0x100000 -#define DDR_PORT0_STATUS 0xB0 -#define DDR_PORT1_STATUS 0xB4 -#define DDR_PORT2_STATUS 0xB8 -#define DDR_PORT3_STATUS 0xBC +#define DDR_PORT0_STATUS 0xB0 +#define DDR_PORT1_STATUS 0xB4 +#define DDR_PORT2_STATUS 0xB8 +#define DDR_PORT3_STATUS 0xBC #define DDR_ERR_OVER_TOPBOUND 0x20000 #define DDR_ERR_WCMDQ_OVER 0x40000 @@ -76,10 +85,10 @@ struct ctc5236_mc { #define DDR_PORT2_BASE 0xB8 #define DDR_PORT3_BASE 0xBc -#define DDR_PORT0 0 -#define DDR_PORT1 1 -#define DDR_PORT2 2 -#define DDR_PORT3 3 +#define DDR_PORT0 0 +#define DDR_PORT1 1 +#define DDR_PORT2 2 +#define DDR_PORT3 3 static int port_err_status(int status, int port, void *dev_id) { @@ -98,53 +107,80 @@ static int port_err_status(int status, int port, void *dev_id) temp = (addr_l | (((unsigned long)((addr_h >> 12) & 0x3)) << 32) ); - pr_emerg("ERROR:port%d is out of top-bound range!\n" - "The error address is 0x%p\n", - id, (void *)temp); + printk(KERN_EMERG + "ERROR:port%d is out of top-bound range!\n The error address is 0x%p\n", + id, (void *)temp); } - if (status & DDR_ERR_WCMDQ_OVER) - pr_err("ERROR:port%d write command queue is overflow!\n", id); - - if (status & DDR_ERR_WCMDQ_UNDER) - pr_err("ERROR:port%d write command queue is underflow!\n", id); + if (status & DDR_ERR_WCMDQ_OVER) { + printk(KERN_ERR + "ERROR:port%d write command queue is overflow!\n", id); + } - if (status & DDR_ERR_WDATAQ_OVER) - pr_err("ERROR:port%d write data queue is overflow!\n", id); + if (status & DDR_ERR_WCMDQ_UNDER) { + printk(KERN_ERR + "ERROR:port%d write command queue is underflow!\n", id); + } - if (status & DDR_ERR_WDATAQ_UNDER) - pr_err("ERROR:port%d write data queue is underflow!\n", id); + if (status & DDR_ERR_WDATAQ_OVER) { + printk(KERN_ERR "ERROR:port%d write data queue is overflow!\n", + id); + } - if (status & DDR_ERR_WESPQ_OVER) - pr_err("ERROR:port%d write response queue is overflow!\n", id); + if (status & DDR_ERR_WDATAQ_UNDER) { + printk(KERN_ERR "ERROR:port%d write data queue is underflow!\n", + id); + } - if (status & DDR_ERR_WESPQ_UNDER) - pr_err("ERROR:port%d write response queue is underflow!\n", id); + if (status & DDR_ERR_WESPQ_OVER) { + printk(KERN_ERR + "ERROR:port%d write response queue is overflow!\n", id); + } - if (status & DDR_ERR_WINFOQ_OVER) - pr_err("ERROR:port%d write info queue is overflow!\n", id); + if (status & DDR_ERR_WESPQ_UNDER) { + printk(KERN_ERR + "ERROR:port%d write response queue is underflow!\n", id); + } - if (status & DDR_ERR_WINFOQ_UNDER) - pr_err("ERROR:port%d write info queue is underflow!\n", id); + if (status & DDR_ERR_WINFOQ_OVER) { + printk(KERN_ERR "ERROR:port%d write info queue is overflow!\n", + id); + } - if (status & DDR_ERR_RCMDQ_OVER) - pr_err("ERROR:port%d read command queue is overflow!\n", id); + if (status & DDR_ERR_WINFOQ_UNDER) { + printk(KERN_ERR "ERROR:port%d write info queue is underflow!\n", + id); + } - if (status & DDR_ERR_RCMDQ_UNDER) - pr_err("ERROR:port%d read command queue is underflow!\n", id); + if (status & DDR_ERR_RCMDQ_OVER) { + printk(KERN_ERR + "ERROR:port%d read command queue is overflow!\n", id); + } - if (status & DDR_ERR_RDATAQ_OVER) - pr_err("ERROR:port%d read data queue is overflow!\n", id); + if (status & DDR_ERR_RCMDQ_UNDER) { + printk(KERN_ERR + "ERROR:port%d read command queue is underflow!\n", id); + } - if (status & DDR_ERR_RDATAQ_UNDER) - pr_err("ERROR:port%d read data queue is underflow!\n", id); + if (status & DDR_ERR_RDATAQ_OVER) { + printk(KERN_ERR "ERROR:port%d read data queue is overflow!\n", + id); + } - if (status & DDR_ERR_RESPQ_OVER) - pr_err("ERROR:port%d read response queue is overflow!\n", id); + if (status & DDR_ERR_RDATAQ_UNDER) { + printk(KERN_ERR "ERROR:port%d read data queue is underflow!\n", + id); + } - if (status & DDR_ERR_RESPQ_UNDER) - pr_err("ERROR:port%d read response queue is underflow!\n", id); + if (status & DDR_ERR_RESPQ_OVER) { + printk(KERN_ERR + "ERROR:port%d read response queue is overflow!\n", id); + } + if (status & DDR_ERR_RESPQ_UNDER) { + printk(KERN_ERR + "ERROR:port%d read response queue is underflow!\n", id); + } return 1; } @@ -177,20 +213,29 @@ static irqreturn_t ctc_mc_err_handler(int irq, void *dev_id) port_err_status(ret, DDR_PORT3, mci); } - if (status & DDR_ERR_ECC_INT_STATUS) - pr_err("ERROR:The ecc more than 1-bit error !\n"); + if (status & DDR_ERR_ECC_INT_STATUS) { + printk(KERN_ERR "ERROR:The ecc more than 1-bit error !\n"); + } - if (status & DDR_ERR_WR_PORT_REC_UNDERFLOW) - pr_err("ERROR:MPARB wr_port_rec FIFO is underflow!\n"); + if (status & DDR_ERR_WR_PORT_REC_UNDERFLOW) { + printk(KERN_ERR "ERROR:MPARB wr_port_rec FIFO is underflow!\n"); + } - if (status & DDR_ERR_WR_PORT_REC_OVERFLOW) - pr_err("ERROR:MPARB wr_port_rec FIFO is overflow!\n"); + if (status & DDR_ERR_WR_PORT_REC_OVERFLOW) { + printk(KERN_ERR "ERROR:MPARB wr_port_rec FIFO is overflow!\n"); + } - if (status & DDR_ERR_RD_PORT_REC_UNDERFLOW) - pr_err("ERROR:MPARB rd_port_rec FIFO is underflow!\n"); + if (status & DDR_ERR_RD_PORT_REC_UNDERFLOW) { + printk(KERN_ERR "ERROR:MPARB rd_port_rec FIFO is underflow!\n"); + } - if (status & DDR_ERR_RD_PORT_REC_OVERFLOW) - pr_err("ERROR:MPARB rd_port_rec FIFO is underflow!\n"); + if (status & DDR_ERR_RD_PORT_REC_OVERFLOW) { + printk(KERN_ERR "ERROR:MPARB rd_port_rec FIFO is overflow!\n"); + } + + if (status & DDR_ERR_CRC_INT_STATUS) { + printk(KERN_ERR "ERROR:The crc error from DRAM!\n"); + } /* disable DDR interrupt */ writel(0x0, mci->base + DDR_ERR_INT_EN); @@ -198,6 +243,43 @@ static irqreturn_t ctc_mc_err_handler(int irq, void *dev_id) return IRQ_HANDLED; } +static irqreturn_t ctc_mc_onebit_ecc_err_handler(int irq, void *dev_id) +{ + struct ctc5236_mc *mci = dev_id; + unsigned int val; + + printk(KERN_ERR "ERROR:One-Bit ECC Error!\n"); + regmap_read(mci->regmap_base, + offsetof(struct SysCtl_regs, SysDdrEccCtl), &val); + printk(KERN_ERR "One-Bit ECC Error Count is %d\n", ((val >> 8) & 0xf)); + printk(KERN_ERR "more than One-Bit ECC Error Count is %d\n", + ((val >> 12) & 0xf)); + + return IRQ_HANDLED; +} + +static irqreturn_t ctc_mc_twobit_ecc_err_handler(int irq, void *dev_id) +{ + struct ctc5236_mc *mci = dev_id; + unsigned int val; + + printk(KERN_ERR "ERROR:more than One-Bit ECC Error!\n"); + regmap_read(mci->regmap_base, + offsetof(struct SysCtl_regs, SysDdrEccCtl), &val); + printk(KERN_ERR "One-Bit ECC Error Count is %d\n", ((val >> 8) & 0xf)); + printk(KERN_ERR "more than One-Bit ECC Error Count is %d\n", + ((val >> 12) & 0xf)); + + return IRQ_HANDLED; +} + +static irqreturn_t ctc_cache_err_handler(int irq, void *dev_id) +{ + + printk(KERN_ERR "ERROR:Cache ECC Error!\n"); + return IRQ_HANDLED; +} + static const struct of_device_id ctc5236_ddr_ctrl_of_match[] = { { .compatible = "ctc,ctc5236-ddr-ctrl", @@ -212,6 +294,7 @@ static int ctc5236_mc_probe(struct platform_device *pdev) const struct of_device_id *id; struct ctc5236_mc *mci; int ret; + unsigned int val; id = of_match_device(ctc5236_ddr_ctrl_of_match, &pdev->dev); if (!id) @@ -225,12 +308,67 @@ static int ctc5236_mc_probe(struct platform_device *pdev) if (IS_ERR(mci->base)) return PTR_ERR(mci->base); + mci->regmap_base = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "ctc,sysctrl"); + if (IS_ERR(mci->regmap_base)) + return PTR_ERR(mci->regmap_base); + + regmap_read(mci->regmap_base, + offsetof(struct SysCtl_regs, SysCtlSysRev), &val); + mci->soc_ver = val; + mci->irq = platform_get_irq(pdev, 0); ret = devm_request_irq(&pdev->dev, mci->irq, ctc_mc_err_handler, 0, - dev_name(&pdev->dev), mci); + "DDR Ecc", mci); + if (ret < 0) { + dev_err(&pdev->dev, "Unable to request ddr error irq %d\n", + mci->irq); + goto err; + } + + val = readl(mci->base); + /* register ecc interrupt when use TM1.1 soc and enable ecc function */ + if ((0x0 != (val & BIT(10))) && (0x1 == mci->soc_ver)) { + /* clean ecc status */ + regmap_write(mci->regmap_base, + offsetof(struct SysCtl_regs, SysDdrEccCtl), 0x1); + regmap_write(mci->regmap_base, + offsetof(struct SysCtl_regs, SysDdrEccCtl), 0x0); + + mci->irq1 = platform_get_irq(pdev, 1); + ret = + devm_request_irq(&pdev->dev, mci->irq1, + ctc_mc_twobit_ecc_err_handler, 0, + "DDR two-bit Ecc(TM1.1)", mci); + if (ret < 0) { + dev_err(&pdev->dev, + "Unable to request ddr two-bit ecc error irq %d\n", + mci->irq1); + goto err; + } + + mci->irq2 = platform_get_irq(pdev, 2); + ret = + devm_request_irq(&pdev->dev, mci->irq2, + ctc_mc_onebit_ecc_err_handler, 0, + "DDR one-bit Ecc(TM1.1)", mci); + if (ret < 0) { + dev_err(&pdev->dev, + "Unable to request one-bit ecc error irq %d\n", + mci->irq2); + goto err; + } + } + + mci->irq_cache_ecc = platform_get_irq(pdev, 3); + ret = + devm_request_irq(&pdev->dev, mci->irq_cache_ecc, + ctc_cache_err_handler, 0, "Cache Ecc", mci); if (ret < 0) { - dev_err(&pdev->dev, "Unable to request irq %d\n", mci->irq); + dev_err(&pdev->dev, + "Unable to request cache ecc error irq %d\n", + mci->irq_cache_ecc); goto err; } @@ -276,4 +414,4 @@ module_exit(ctc5236_mc_exit); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Centec Network"); -MODULE_DESCRIPTION("Centec TsingMa memory controller driver"); +MODULE_DESCRIPTION("Centec TsingMa memory contoller driver"); diff --git a/platform/centec-arm64/tsingma-bsp/src/ctc5236_switch/ctc5236_switch.c b/platform/centec-arm64/tsingma-bsp/src/ctc5236_switch/ctc5236_switch.c old mode 100644 new mode 100755 index 1cc86667d9b9..2635a86e6ff3 --- a/platform/centec-arm64/tsingma-bsp/src/ctc5236_switch/ctc5236_switch.c +++ b/platform/centec-arm64/tsingma-bsp/src/ctc5236_switch/ctc5236_switch.c @@ -1,4 +1,5 @@ -/* (C) Copyright 2004-2017 Centec Networks (suzhou) Co., LTD. +/* + * (C) Copyright 2004-2017 Centec Networks (suzhou) Co., LTD. * Wangyb * * SPDX-License-Identifier: GPL-2.0+ @@ -9,15 +10,15 @@ #include #include #include -#include <../include/ctc5236_switch.h> +#include "../include/ctc5236_switch.h" -struct ctc_access_t *access; +ctc_access_t *access; -#define SWITCH_DTS_OFFSET 0x1000 +#define SWITCH_DTS_OFFSET 0x1000 -int ctc5236_switch_read(u32 offset, u32 len, u32 *p_value) +int ctc5236_switch_read(u32 offset, u32 len, u32 * p_value) { - union ctc_switch_cmd_status_u_t cmd_status_u; + ctc_switch_cmd_status_u_t cmd_status_u; u32 timeout = 0x6400; u32 cmd_len = 0; u8 index = 0; @@ -28,8 +29,8 @@ int ctc5236_switch_read(u32 offset, u32 len, u32 *p_value) } /* switch only have 16 databuf, len must not exceed 16 */ - if (len > 16 || len == 0) { - pr_err("switch read: length error! len = %d\n", len); + if ((16 < len) || (0 == len)) { + pr_err("switch read: length error! len = %d \n", len); return -1; } /* cmdDataLen must be power of 2 */ @@ -39,22 +40,23 @@ int ctc5236_switch_read(u32 offset, u32 len, u32 *p_value) cmd_len = len; do { cmd_len++; - } while ((cmd_len <= 16) && (cmd_len & (cmd_len - 1))); + } + while ((cmd_len <= 16) && (cmd_len & (cmd_len - 1))); } /* 1. write CmdStatusReg */ - memset(&cmd_status_u, 0, sizeof(union ctc_switch_cmd_status_u_t)); + memset(&cmd_status_u, 0, sizeof(ctc_switch_cmd_status_u_t)); cmd_status_u.cmd_status.cmdReadType = 1; - /* normal operate only support 1 entry */ - cmd_status_u.cmd_status.cmdEntryWords = (len == 16) ? 0 : len; + cmd_status_u.cmd_status.cmdEntryWords = (len == 16) ? 0 : len; /* normal operate only support 1 entry */ cmd_status_u.cmd_status.cmdDataLen = len; writel(cmd_status_u.val, &access->cmd_status); /* 2. write AddrReg */ writel(offset, &access->addr); /* 3. polling status and check */ cmd_status_u.val = readl(&access->cmd_status); - while (!(cmd_status_u.cmd_status.reqProcDone) && (--timeout)) + while (!(cmd_status_u.cmd_status.reqProcDone) && (--timeout)) { cmd_status_u.val = readl(&access->cmd_status); + } /* 4. check cmd done */ if (!(cmd_status_u.cmd_status.reqProcDone)) { pr_err("switch read error! cmd_status = %x\n", @@ -69,15 +71,16 @@ int ctc5236_switch_read(u32 offset, u32 len, u32 *p_value) } /* 6. read data from buffer */ - for (index = 0; index < len; index++) + for (index = 0; index < len; index++) { p_value[index] = readl(&access->data[index]); + } return 0; } -int ctc5236_switch_write(u32 offset, u32 len, u32 *p_value) +int ctc5236_switch_write(u32 offset, u32 len, u32 * p_value) { - union ctc_switch_cmd_status_u_t cmd_status_u; + ctc_switch_cmd_status_u_t cmd_status_u; u32 timeout = 0x6400; /* need to be confirmed */ u32 cmd_len = 0; u8 index = 0; @@ -88,8 +91,8 @@ int ctc5236_switch_write(u32 offset, u32 len, u32 *p_value) } /* switch only have 16 databuf, len must not exceed 16 */ - if (len > 16 || len == 0) { - pr_err("switch write length error! len = %d\n", len); + if ((16 < len) || (0 == len)) { + pr_err("switch write length error! len = %d \n", len); return -1; } @@ -100,28 +103,28 @@ int ctc5236_switch_write(u32 offset, u32 len, u32 *p_value) cmd_len = len; do { cmd_len++; - } while ((cmd_len <= 16) && (cmd_len & (cmd_len - 1))); + } + while ((cmd_len <= 16) && (cmd_len & (cmd_len - 1))); } /* 1. write CmdStatusReg */ - memset(&cmd_status_u, 0, sizeof(struct ctc_switch_cmd_status_t)); + memset(&cmd_status_u, 0, sizeof(ctc_switch_cmd_status_t)); cmd_status_u.cmd_status.cmdReadType = 0; cmd_status_u.cmd_status.cmdEntryWords = (len == 16) ? 0 : len; - /* Notice: for 1 entry op, cmdDatalen eq cmdEntryWords, - * but for mutil entry, len = cmd_len - */ - cmd_status_u.cmd_status.cmdDataLen = len; + cmd_status_u.cmd_status.cmdDataLen = len; /* Notice: for 1 entry op, cmdDatalen eq cmdEntryWords, but for mutil entry, len = cmd_len */ writel(cmd_status_u.val, &access->cmd_status); /* 2. write AddrReg */ writel(offset, &access->addr); /* 3. write data into databuffer */ - for (index = 0; index < len; index++) + for (index = 0; index < len; index++) { writel(p_value[index], &access->data[index]); + } /* 4. polling status and check */ cmd_status_u.val = readl(&access->cmd_status); - while (!(cmd_status_u.cmd_status.reqProcDone) && (--timeout)) + while (!(cmd_status_u.cmd_status.reqProcDone) && (--timeout)) { cmd_status_u.val = readl(&access->cmd_status); + } /* 5. check cmd done */ if (!(cmd_status_u.cmd_status.reqProcDone)) { @@ -141,29 +144,29 @@ int ctc5236_switch_write(u32 offset, u32 len, u32 *p_value) } static int -_sys_tsingma_peri_get_temp_with_code(u8 lchip, u32 temp_code, u32 *p_temp_val) +_sys_tsingma_peri_get_temp_with_code(u8 lchip, u32 temp_code, u32 * p_temp_val) { u16 temp_mapping_tbl[SYS_TSINGMA_TEMP_TABLE_NUM + 1] = { - 804, 801, 798, 795, 792, 790, 787, 784, 781, 778, - 775, 772, 769, 766, 763, 761, 758, 755, 752, 749, - 746, 743, 740, 737, 734, 731, 728, 725, 722, 719, - 717, 714, 711, 708, 705, 702, 699, 696, 693, 690, - 687, 684, 681, 678, 675, 672, 669, 666, 663, 660, - 658, 655, 652, 649, 646, 643, 640, 637, 634, 631, - 628, 625, 622, 619, 616, 613, 610, 607, 604, 601, - 599, 596, 593, 590, 587, 584, 581, 578, 575, 572, - 569, 566, 563, 560, 557, 554, 551, 548, 545, 542, - 540, 537, 534, 531, 528, 525, 522, 519, 516, 513, - 510, 507, 504, 501, 498, 495, 492, 489, 486, 483, - 481, 478, 475, 472, 469, 466, 463, 460, 457, 454, - 451, 448, 445, 442, 439, 436, 433, 430, 427, 424, - 421, 418, 415, 412, 409, 406, 403, 400, 397, 394, - 391, 388, 385, 382, 379, 376, 373, 370, 367, 364, - 361, 358, 355, 352, 349, 346, 343, 340, 337, 334, + 804, 801, 798, 795, 792, 790, 787, 784, 781, 778, 775, 772, 769, 766, 763, 761, 758, 755, 752, 749, + /*-40~-21*/ + 746, 743, 740, 737, 734, 731, 728, 725, 722, 719, 717, 714, 711, 708, 705, 702, 699, 696, 693, 690, + /*-20~-1*/ + 687, 684, 681, 678, 675, 672, 669, 666, 663, 660, 658, 655, 652, 649, 646, 643, 640, 637, 634, 631, /*0~19 */ + 628, 625, 622, 619, 616, 613, 610, 607, 604, 601, 599, 596, 593, 590, 587, 584, 581, 578, 575, 572, /*20~39 */ + 569, 566, 563, 560, 557, 554, 551, 548, 545, 542, 540, 537, 534, 531, 528, 525, 522, 519, 516, 513, /*40~59 */ + 510, 507, 504, 501, 498, 495, 492, 489, 486, 483, 481, 478, 475, 472, 469, 466, 463, 460, 457, 454, /*60~79 */ + 451, 448, 445, 442, 439, 436, 433, 430, 427, 424, 421, 418, 415, 412, 409, 406, 403, 400, 397, 394, /*80~99 */ + 391, 388, 385, 382, 379, 376, 373, 370, 367, 364, 361, 358, 355, 352, 349, 346, 343, 340, 337, 334, /*100~119 */ 331, 328, 325, 322, 319, 316, 0 - }; + }; /*120~125 */ u8 index = 0; + /*if ((temp_code > temp_mapping_tbl[0]) || (temp_code < temp_mapping_tbl[SYS_TSINGMA_TEMP_TABLE_NUM-1])) + { + SYS_PERI_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "temp code error %d\n", temp_code); + return CTC_E_HW_INVALID_INDEX; + } */ + for (index = 0; index < SYS_TSINGMA_TEMP_TABLE_NUM; index++) { if ((temp_code <= temp_mapping_tbl[index]) && (temp_code > temp_mapping_tbl[index + 1])) { @@ -171,10 +174,11 @@ _sys_tsingma_peri_get_temp_with_code(u8 lchip, u32 temp_code, u32 *p_temp_val) } } - if (index < 39) + if (index < 40) { *p_temp_val = 40 - index + (1 << 31); - else + } else { *p_temp_val = index - 40; + } return 0; } @@ -189,27 +193,6 @@ int get_switch_temperature(void) offset = 0xf * 4; ctc5236_switch_write(OMCMEM_BASE + offset, 1, &value); - /*config RTHMC_RST=1 */ - /*mask_write tbl-reg OmcMem 0x10 offset 0x0 0x00000010 0x00000010 */ - offset = 0x10 * 4; - ctc5236_switch_read(OMCMEM_BASE + offset, 1, &value); - value |= BIT(4); - ctc5236_switch_write(OMCMEM_BASE + offset, 1, &value); - - /*wait RTHMC_RST=1 */ - /*read tbl-reg OmcMem 0x10 offset 0x0 */ - timeout = SYS_TSINGMA_SENSOR_TIMEOUT; - offset = 0x10 * 4; - while (timeout) { - timeout--; - ctc5236_switch_read(OMCMEM_BASE + offset, 1, &value); - if ((BIT(4) & value) == 0) - break; - msleep(1); - } - if (timeout == 0) - return 0xffff; - /*config ENBIAS=1£¬ENVR=1£¬ENAD=1 */ /*mask_write tbl-reg OmcMem 0x11 offset 0x0 0x02000007 0x03000007 */ offset = 0x11 * 4; @@ -237,6 +220,8 @@ int get_switch_temperature(void) value |= BIT(0); ctc5236_switch_write(OMCMEM_BASE + offset, 1, &value); + msleep(1); + /*mask_write tbl-reg OmcMem 0x10 offset 0x0 0x00000001 0x00000001 */ offset = 0x10 * 4; ctc5236_switch_read(OMCMEM_BASE + offset, 1, &value); @@ -262,8 +247,9 @@ int get_switch_temperature(void) msleep(1); } - if (timeout == 0) + if (0 == timeout) { return 0xffff; + } /*mask_write tbl-reg OmcMem 0x11 offset 0x0 0x00000006 0x00000006 */ offset = 0x11 * 4; @@ -284,6 +270,7 @@ int get_switch_temperature(void) return -temperature; } + EXPORT_SYMBOL_GPL(get_switch_temperature); static int ctc_switch_probe(struct platform_device *pdev) @@ -291,14 +278,16 @@ static int ctc_switch_probe(struct platform_device *pdev) struct resource *iomem; void __iomem *ioaddr; resource_size_t start; + uint val; iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); start = iomem->start - 0x1000; ioaddr = devm_ioremap(&pdev->dev, start, resource_size(iomem)); - if (IS_ERR(ioaddr)) + if (IS_ERR(ioaddr)) { return -1; - access = (struct ctc_access_t *) ioaddr; + } + access = (ctc_access_t *) ioaddr; return 0; } diff --git a/platform/centec-arm64/tsingma-bsp/src/ctc_wdt/ctc_wdt.c b/platform/centec-arm64/tsingma-bsp/src/ctc_wdt/ctc_wdt.c index 2beecbb99e70..8cac376c0bbe 100644 --- a/platform/centec-arm64/tsingma-bsp/src/ctc_wdt/ctc_wdt.c +++ b/platform/centec-arm64/tsingma-bsp/src/ctc_wdt/ctc_wdt.c @@ -1,3 +1,4 @@ +/* /* drivers/char/watchdog/ctc-wdt.c * * Watchdog driver for CTC TSINGMA, based on ARM SP805 watchdog module @@ -290,6 +291,12 @@ static int ctc_wdt_probe(struct amba_device *adev, const struct amba_id *id) if (IS_ERR(wdt->regmap_base)) return PTR_ERR(wdt->regmap_base); + /* reset wdt module */ + regmap_write(wdt->regmap_base, + offsetof(struct SysCtl_regs, SysWdtResetCtl), 0x3); + regmap_write(wdt->regmap_base, + offsetof(struct SysCtl_regs, SysWdtResetCtl), 0x0); + /* * TsingMa SoC wdt reference clock is obtained by clockSub frequency * division,which is 500Mhz.So we need to set the frequency division diff --git a/platform/centec-arm64/tsingma-bsp/src/ctcmac/Makefile b/platform/centec-arm64/tsingma-bsp/src/ctcmac/Makefile index f29ac076955d..bcba00068ea2 100644 --- a/platform/centec-arm64/tsingma-bsp/src/ctcmac/Makefile +++ b/platform/centec-arm64/tsingma-bsp/src/ctcmac/Makefile @@ -1,3 +1,3 @@ KBUILD_EXTRA_SYMBOLS = /sonic/platform/centec-arm64/tsingma-bsp/src/ctc5236_switch/Module.symvers -obj-m = ctcmac.o ctcmac_test.o ctc5236_mdio.o +obj-m = ctcmac.o ctc5236_mdio.o diff --git a/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctc5236_mdio.c b/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctc5236_mdio.c index c176e0cfbc86..95ae43d76fbc 100644 --- a/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctc5236_mdio.c +++ b/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctc5236_mdio.c @@ -1,4 +1,5 @@ -/* Centec cpu_mac Ethernet Driver -- cpu_mac controller implementation +/* + * Centec CpuMac Ethernet Driver -- CpuMac controller implementation * Provides Bus interface for MIIM regs * * Author: liuht @@ -10,6 +11,7 @@ * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. + * */ #include @@ -44,7 +46,7 @@ struct ctc_mdio_priv { void __iomem *map; - struct mdio_soc_regs *mdio_reg; + struct MdioSoc_regs *mdio_reg; }; static int ctc_mdio_write(struct mii_bus *bus, int mii_id, int reg, u16 value) @@ -57,14 +59,15 @@ static int ctc_mdio_write(struct mii_bus *bus, int mii_id, int reg, u16 value) cmd = CTCMAC_MDIO_CMD_REGAD(reg) | CTCMAC_MDIO_CMD_PHYAD(mii_id) | CTCMAC_MDIO_CMD_OPCODE(1) | CTCMAC_MDIO_CMD_DATA(value); - writel(cmd, &priv->mdio_reg->mdio_soc_cmd_0[0]); - writel(1, &priv->mdio_reg->mdio_soc_cmd_0[1]); + writel(cmd, &priv->mdio_reg->MdioSocCmd0[0]); + writel(1, &priv->mdio_reg->MdioSocCmd0[1]); - ret = readl_poll_timeout(&priv->mdio_reg->mdio_soc_status_0, + ret = readl_poll_timeout(&priv->mdio_reg->MdioSocStatus0, tmp, tmp & CTCMAC_MDIO_STAT(1), 1000, 10000); - if (ret < 0) + if (ret < 0) { return -1; + } return 0; } @@ -80,18 +83,18 @@ static int ctc_mdio_read(struct mii_bus *bus, int mii_id, int reg) cmd = CTCMAC_MDIO_CMD_REGAD(reg) | CTCMAC_MDIO_CMD_PHYAD(mii_id) | CTCMAC_MDIO_CMD_OPCODE(2); - writel(cmd, &priv->mdio_reg->mdio_soc_cmd_0[0]); - writel(1, &priv->mdio_reg->mdio_soc_cmd_0[1]); + writel(cmd, &priv->mdio_reg->MdioSocCmd0[0]); + writel(1, &priv->mdio_reg->MdioSocCmd0[1]); - ret = readl_poll_timeout(&priv->mdio_reg->mdio_soc_status_0, + ret = readl_poll_timeout(&priv->mdio_reg->MdioSocStatus0, status, status & CTCMAC_MDIO_STAT(1), 1000, 10000); if (ret < 0) { - pr_err("ctc_mdio_read1\n"); + printk(KERN_ERR "ctc_mdio_read1\n"); return -1; } - value = (readl(&priv->mdio_reg->mdio_soc_status_0) & 0xffff); + value = (readl(&priv->mdio_reg->MdioSocStatus0) & 0xffff); return value; } @@ -100,7 +103,7 @@ static int ctc_mdio_reset(struct mii_bus *bus) { struct ctc_mdio_priv *priv = (struct ctc_mdio_priv *)bus->priv; - writel(0x91f, &priv->mdio_reg->mdio_soc_cfg_0); + writel(0x91f, &priv->mdio_reg->MdioSocCfg0); return 0; } @@ -146,7 +149,7 @@ static int ctc_mdio_probe(struct platform_device *pdev) pr_err("of iomap fail %d!\n", err); goto error; } - priv->mdio_reg = (struct mdio_soc_regs *)priv->map; + priv->mdio_reg = (struct MdioSoc_regs *)priv->map; new_bus->parent = &pdev->dev; platform_set_drvdata(pdev, new_bus); diff --git a/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac.c b/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac.c old mode 100644 new mode 100755 index 6e267ed8fb42..ea28b561ecaf --- a/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac.c +++ b/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac.c @@ -1,4 +1,5 @@ -/* Centec cpu_mac Ethernet Driver -- cpu_mac controller implementation +/* + * Centec CpuMac Ethernet Driver -- CpuMac controller implementation * Provides Bus interface for MIIM regs * * Author: liuht @@ -34,6 +35,7 @@ #include #include #include +#include #include #include "../pinctrl-ctc/pinctrl-ctc.h" @@ -41,8 +43,9 @@ #include #include #include -#include "../include/ctc5236_switch.h" #include +#include "../include/ctc5236_switch.h" + #include "ctcmac.h" #include "ctcmac_reg.h" @@ -51,9 +54,11 @@ static int ctcmac_free_skb_resources(struct ctcmac_private *priv); static void cpumac_start(struct ctcmac_private *priv); static void cpumac_halt(struct ctcmac_private *priv); static void ctcmac_hw_init(struct ctcmac_private *priv); +static int ctcmac_set_ffe(struct ctcmac_private *priv, u16 coefficient[]); +static int ctcmac_get_ffe(struct ctcmac_private *priv, u16 coefficient[]); static spinlock_t global_reglock __aligned(SMP_CACHE_BYTES); -static int g_reglock_init_done; -static int g_mac_unit_init_done; +static int g_reglock_init_done = 0; +static int g_mac_unit_init_done = 0; static struct regmap *regmap_base; static struct ctcmac_pkt_stats g_pkt_stats[2]; @@ -134,20 +139,19 @@ static const char ctc_stat_gstrings[][ETH_GSTRING_LEN] = { "mtu2", }; -static void clrsetbits(unsigned __iomem *addr, u32 clr, u32 set) +static void clrsetbits(unsigned __iomem * addr, u32 clr, u32 set) { writel((readl(addr) & ~(clr)) | (set), addr); } -static inline u32 ctcmac_regr(unsigned __iomem *addr) +static inline u32 ctcmac_regr(unsigned __iomem * addr) { u32 val; - val = readl(addr); return val; } -static inline void ctcmac_regw(unsigned __iomem *addr, u32 val) +static inline void ctcmac_regw(unsigned __iomem * addr, u32 val) { writel(val, addr); } @@ -166,7 +170,7 @@ static int ctcmac_alloc_tx_queues(struct ctcmac_private *priv) int i; for (i = 0; i < priv->num_tx_queues; i++) { - priv->tx_queue[i] = kzalloc(sizeof(*priv->tx_queue[i]), + priv->tx_queue[i] = kzalloc(sizeof(struct ctcmac_priv_tx_q), GFP_KERNEL); if (!priv->tx_queue[i]) return -ENOMEM; @@ -174,7 +178,7 @@ static int ctcmac_alloc_tx_queues(struct ctcmac_private *priv) priv->tx_queue[i]->tx_skbuff = NULL; priv->tx_queue[i]->qindex = i; priv->tx_queue[i]->dev = priv->ndev; - spin_lock_init(&priv->tx_queue[i]->txlock); + spin_lock_init(&(priv->tx_queue[i]->txlock)); } return 0; } @@ -184,7 +188,7 @@ static int ctcmac_alloc_rx_queues(struct ctcmac_private *priv) int i; for (i = 0; i < priv->num_rx_queues; i++) { - priv->rx_queue[i] = kzalloc(sizeof(*priv->rx_queue[i]), + priv->rx_queue[i] = kzalloc(sizeof(struct ctcmac_priv_rx_q), GFP_KERNEL); if (!priv->rx_queue[i]) return -ENOMEM; @@ -205,16 +209,20 @@ static void ctcmac_free_tx_queues(struct ctcmac_private *priv) { int i; - for (i = 0; i < priv->num_tx_queues; i++) - kfree(priv->tx_queue[i]); + for (i = 0; i < priv->num_tx_queues; i++) { + if (priv->tx_queue[i]) + kfree(priv->tx_queue[i]); + } } static void ctcmac_free_rx_queues(struct ctcmac_private *priv) { int i; - for (i = 0; i < priv->num_rx_queues; i++) - kfree(priv->rx_queue[i]); + for (i = 0; i < priv->num_rx_queues; i++) { + if (priv->rx_queue[i]) + kfree(priv->rx_queue[i]); + } } static void ctcmac_free_dev(struct ctcmac_private *priv) @@ -237,7 +245,7 @@ static int ctcmac_fixed_phy_link_update(struct net_device *dev, if (priv->interface != PHY_INTERFACE_MODE_SGMII) return 0; - mon = readl(&priv->cpumac_reg->cpu_mac_sgmii_mon[0]); + mon = readl(&priv->cpumac_reg->CpuMacSgmiiMon[0]); if (priv->autoneg_mode == CTCMAC_AUTONEG_DISABLE) { if ((mon & 0x100) == 0x100) status->link = 1; @@ -257,8 +265,10 @@ static int ctcmac_fixed_phy_link_update(struct net_device *dev, static int ctcmac_of_init(struct platform_device *ofdev, struct net_device **pdev) { - int err = 0, index; - const char *ctype, *automode, *dfe; + u32 val; + int err = 0, index, int_coalesce; + const void *mac_addr; + const char *ctype, *automode, *dfe, *int_type, *tx_inv, *rx_inv; struct net_device *dev = NULL; struct ctcmac_private *priv = NULL; unsigned int num_tx_qs, num_rx_qs; @@ -269,7 +279,7 @@ static int ctcmac_of_init(struct platform_device *ofdev, *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); dev = *pdev; - if (!dev) + if (NULL == dev) return -ENOMEM; priv = netdev_priv(dev); @@ -278,6 +288,9 @@ static int ctcmac_of_init(struct platform_device *ofdev, priv->dev = &ofdev->dev; priv->dev->coherent_dma_mask = DMA_BIT_MASK(64); priv->num_tx_queues = num_tx_qs; + regmap_read(regmap_base, offsetof(struct SysCtl_regs, SysCtlSysRev), + &val); + priv->version = val; netif_set_real_num_rx_queues(dev, num_rx_qs); priv->num_rx_queues = num_rx_qs; @@ -293,16 +306,50 @@ static int ctcmac_of_init(struct platform_device *ofdev, priv->cpumac_mem = priv->iobase + CPUMAC_MEM_BASE; priv->cpumacu_reg = of_iomap(np, 1) + CPUMACUNIT_REG_BASE; - /* Get cpu_mac index */ + /* Get CpuMac index */ err = of_property_read_u32(np, "index", &index); - if (err == 0) + if ((err == 0)) priv->index = index; else priv->index = 0; + mac_addr = of_get_mac_address(np); + + if (!IS_ERR(mac_addr)) + memcpy(dev->dev_addr, mac_addr, ETH_ALEN); + + err = of_property_read_string(np, "int-type", &int_type); + if ((err == 0) && !strncmp(int_type, "desc", 4)) { + priv->int_type = CTCMAC_INT_DESC; + if (priv->version == 0) { + priv->rx_int_coalesce_cnt = DESC_INT_COALESCE_CNT_MIN; + priv->tx_int_coalesce_cnt = DESC_INT_COALESCE_CNT_MIN; + } else { + err = + of_property_read_u32(np, "rx-int-coalesce-count", + &int_coalesce); + if (err == 0) + priv->rx_int_coalesce_cnt = int_coalesce; + else + priv->rx_int_coalesce_cnt = + DESC_RX_INT_COALESCE_CNT_DEFAULT; + + err = + of_property_read_u32(np, "tx-int-coalesce-count", + &int_coalesce); + if (err == 0) + priv->tx_int_coalesce_cnt = int_coalesce; + else + priv->tx_int_coalesce_cnt = + DESC_TX_INT_COALESCE_CNT_DEFAULT; + } + } else { + priv->int_type = CTCMAC_INT_PACKET; + } + /* Get interface type, CTC5236 only support PHY_INTERFACE_MODE_SGMII */ err = of_property_read_string(np, "phy-connection-type", &ctype); - if (err == 0 && !strncmp(ctype, "mii", 3)) { + if ((err == 0) && !strncmp(ctype, "mii", 3)) { priv->interface = PHY_INTERFACE_MODE_MII; priv->supported = SUPPORTED_10baseT_Full; } else { @@ -311,22 +358,38 @@ static int ctcmac_of_init(struct platform_device *ofdev, } err = of_property_read_string(np, "auto-nego-mode", &automode); - if (err == 0 && !strncmp(automode, "disable", 7)) + if ((err == 0) && !strncmp(automode, "disable", 7)) { priv->autoneg_mode = CTCMAC_AUTONEG_DISABLE; - else if (err == 0 && !strncmp(automode, "sgmii-mac", 9)) + } else if ((err == 0) && !strncmp(automode, "sgmii-mac", 9)) { priv->autoneg_mode = CTCMAC_AUTONEG_MAC_M; - else if (err == 0 && !strncmp(automode, "sgmii-phy", 9)) + } else if ((err == 0) && !strncmp(automode, "sgmii-phy", 9)) { priv->autoneg_mode = CTCMAC_AUTONEG_PHY_M; - else if (err == 0 && !strncmp(automode, "1000base-x", 10)) + } else if ((err == 0) && !strncmp(automode, "1000base-x", 10)) { priv->autoneg_mode = CTCMAC_AUTONEG_1000BASEX_M; - else + } else { priv->autoneg_mode = CTCMAC_AUTONEG_MAC_M; + } err = of_property_read_string(np, "dfe", &dfe); - if (err == 0 && !strncmp(dfe, "enable", 6)) + if ((err == 0) && !strncmp(dfe, "enable", 6)) { priv->dfe_enable = 1; - else + } else { priv->dfe_enable = 0; + } + + err = of_property_read_string(np, "tx-pol-inv", &tx_inv); + if ((err == 0) && !strncmp(tx_inv, "enable", 6)) { + priv->tx_pol_inv = CTCMAC_TX_POL_INV_ENABLE; + } else { + priv->tx_pol_inv = CTCMAC_TX_POL_INV_DISABLE; + } + + err = of_property_read_string(np, "rx-pol-inv", &rx_inv); + if ((err == 0) && !strncmp(rx_inv, "enable", 6)) { + priv->rx_pol_inv = CTCMAC_RX_POL_INV_ENABLE; + } else { + priv->rx_pol_inv = CTCMAC_RX_POL_INV_DISABLE; + } priv->phy_node = of_parse_phandle(np, "phy-handle", 0); /* In the case of a fixed PHY, the DT node associated @@ -342,6 +405,12 @@ static int ctcmac_of_init(struct platform_device *ofdev, /* mapping from hw irq to sw irq */ priv->irqinfo[CTCMAC_NORMAL].irq = irq_of_parse_and_map(np, 0); priv->irqinfo[CTCMAC_FUNC].irq = irq_of_parse_and_map(np, 1); + if (priv->version > 0) { + priv->irqinfo[CTCMAC_FUNC_RX0].irq = + irq_of_parse_and_map(np, 3); + priv->irqinfo[CTCMAC_FUNC_RX1].irq = + irq_of_parse_and_map(np, 4); + } return 0; @@ -365,10 +434,8 @@ int startup_ctcmac(struct net_device *ndev) if (err) return err; - /* barrier */ smp_mb__before_atomic(); clear_bit(CTCMAC_DOWN, &priv->state); - /* barrier */ smp_mb__after_atomic(); cpumac_start(priv); @@ -381,6 +448,8 @@ int startup_ctcmac(struct net_device *ndev) napi_enable(&priv->napi_rx); napi_enable(&priv->napi_tx); + if (priv->version > 0) + napi_enable(&priv->napi_rx1); netif_tx_wake_all_queues(ndev); @@ -396,13 +465,13 @@ void stop_ctcmac(struct net_device *ndev) netif_tx_stop_all_queues(ndev); - /* barrier */ smp_mb__before_atomic(); set_bit(CTCMAC_DOWN, &priv->state); - /* barrier */ smp_mb__after_atomic(); napi_disable(&priv->napi_rx); napi_disable(&priv->napi_tx); + if (priv->version > 0) + napi_disable(&priv->napi_rx1); phy_stop(ndev->phydev); ctcmac_free_skb_resources(priv); } @@ -410,7 +479,6 @@ void stop_ctcmac(struct net_device *ndev) static void ctcmac_reset(struct net_device *ndev) { struct ctcmac_private *priv = netdev_priv(ndev); - while (test_and_set_bit_lock(CTCMAC_RESETTING, &priv->state)) cpu_relax(); @@ -431,37 +499,33 @@ static void ctcmac_reset_task(struct work_struct *work) ctcmac_reset(priv->ndev); } -/* get the rxdesc number that was used by cpu_mac but has not been - * handled by CPU - */ +/* get the rxdesc number that was used by CpuMac but has not been handled by CPU */ static int ctcmac_rxbd_recycle(struct ctcmac_private *priv, int qidx) { u32 count; if (qidx) { - count = readl(&priv->cpumac_reg->cpu_mac_desc_mon[2]); + count = readl(&priv->cpumac_reg->CpuMacDescMon[2]); return count & 0xffff; } - count = readl(&priv->cpumac_reg->cpu_mac_desc_mon[1]); + count = readl(&priv->cpumac_reg->CpuMacDescMon[1]); return (count >> 16) & 0xffff; } static int ctcmac_rxbd_usable(struct ctcmac_private *priv, int qidx) { - return (readl(&priv->cpumac_reg->cpu_mac_desc_mon[0]) >> (qidx * 16)) & + return (readl(&priv->cpumac_reg->CpuMacDescMon[0]) >> (qidx * 16)) & 0xffff; } -/* get the txdesc number that was used by cpu_mac - * but has not been handled by CPU - */ +/* get the txdesc number that was used by CpuMac but has not been handled by CPU */ static int ctcmac_txbd_used_untreated(struct ctcmac_private *priv) { u32 count; - count = readl(&priv->cpumac_reg->cpu_mac_desc_mon[2]); + count = readl(&priv->cpumac_reg->CpuMacDescMon[2]); return (count >> 16) & 0xffff; } @@ -476,7 +540,7 @@ static bool ctcmac_add_rx_frag(struct ctcmac_rx_buff *rxb, u32 lstatus, int data_size; /* Remove the CRC from the packet length */ - if (lstatus & CPU_MAC_DESC_INTF_W1_DESC_EOP) + if (lstatus & BIT(CPU_MAC_DESC_INTF_W1_DESC_EOP_BIT)) data_size = size - 4; else data_size = size; @@ -528,7 +592,7 @@ static void ctcmac_reuse_rx_page(struct ctcmac_priv_rx_q *rxq, CTCMAC_RXB_TRUESIZE, DMA_FROM_DEVICE); } -/* Handle the rx buffer that has been used by cpu_mac */ +/* Handle the rx buffer that has been used by CpuMac */ static struct sk_buff *ctcmac_get_next_rxbuff(struct ctcmac_priv_rx_q *rx_queue, u32 lstatus, struct sk_buff *skb) { @@ -539,10 +603,10 @@ static struct sk_buff *ctcmac_get_next_rxbuff(struct ctcmac_priv_rx_q *rx_queue, if (likely(!skb)) { void *buff_addr = page_address(page) + rxb->page_offset; - skb = build_skb(buff_addr, CTCMAC_SKBFRAG_SIZE); - if (unlikely(!skb)) + if (unlikely(!skb)) { return NULL; + } first = true; } @@ -583,19 +647,19 @@ int ctc_mac_hss_write(struct ctcmac_private *priv, u8 addr, u8 data, else accid = 0; val = addr | (data << 8) | (accid << 24) | (1 << 31); - writel(val, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(val, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); while (timeout--) { - mon = - readl(&priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_result); - if (mon & CPU_MAC_UNIT_HSS_REG_ACC_RESULT_W0_HSS_ACC_ACK_MASK) + mon = readl(&priv->cpumacu_reg->CpuMacUnitHssRegAccResult); + if (mon & CPU_MAC_UNIT_HSS_REG_ACC_RESULT_W0_HSS_ACC_ACK_MASK) { break; + } mdelay(1); } if (!(mon & CPU_MAC_UNIT_HSS_REG_ACC_RESULT_W0_HSS_ACC_ACK_MASK)) { dev_err(&priv->ndev->dev, - "wait for write ack cpu_mac_unit_hss_reg_acc_result:0x%x addr 0x%x data 0x%x serdes %d fail!\n", - readl(&priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_result), + "wait for write ack CpuMacUnitHssRegAccResult:0x%x addr 0x%x data 0x%x serdes %d fail!\n", + readl(&priv->cpumacu_reg->CpuMacUnitHssRegAccResult), addr, data, serdes_id); return -1; } @@ -603,13 +667,13 @@ int ctc_mac_hss_write(struct ctcmac_private *priv, u8 addr, u8 data, return 0; } -int ctc_mac_hss_read(struct ctcmac_private *priv, u8 addr, u8 *data, +int ctc_mac_hss_read(struct ctcmac_private *priv, u8 addr, u8 * data, u8 serdes_id) { u8 accid; u32 val = 0; u32 mon = 0; - int timeout = 2000; + int timeout = 2000;; if (serdes_id == 0) accid = 3; @@ -619,24 +683,24 @@ int ctc_mac_hss_read(struct ctcmac_private *priv, u8 addr, u8 *data, accid = 0; val = addr | (1 << 16) | (accid << 24) | (1 << 31); - writel(val, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(val, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); while (timeout--) { - mon = - readl(&priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_result); - if (mon & CPU_MAC_UNIT_HSS_REG_ACC_RESULT_W0_HSS_ACC_ACK_MASK) + mon = readl(&priv->cpumacu_reg->CpuMacUnitHssRegAccResult); + if (mon & CPU_MAC_UNIT_HSS_REG_ACC_RESULT_W0_HSS_ACC_ACK_MASK) { break; + } mdelay(1); } if (!(mon & CPU_MAC_UNIT_HSS_REG_ACC_RESULT_W0_HSS_ACC_ACK_MASK)) { dev_err(&priv->ndev->dev, - "wait for read ack cpu_mac_unit_hss_reg_acc_result:0x%x fail!\n", - readl(&priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_result)); + "wait for read ack CpuMacUnitHssRegAccResult:0x%x fail!\n", + readl(&priv->cpumacu_reg->CpuMacUnitHssRegAccResult)); *data = 0x0; return -1; } - val = readl(&priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_result); + val = readl(&priv->cpumacu_reg->CpuMacUnitHssRegAccResult); *data = val & 0xff; return 0; @@ -648,29 +712,25 @@ static int ctcmac_maximize_margin_of_cmu_tempearture_ramp(struct ctcmac_private u8 val, ctune, delta, ctune_cal; int tmpr = 0; + get_switch_temperature(); tmpr = get_switch_temperature(); - if (tmpr == 0xffff) { - pr_err("get temperature fail!\n"); + if (0xffff == tmpr) { + printk(KERN_ERR "get temperature fail!\n"); return -1; } - ctc_mac_hss_read(priv, 0x1c, &val, 2); - val &= 0xf8; - val |= 0x4; - ctc_mac_hss_write(priv, 0x1c, val, 2); - /*r_pll_dlol_en 0x30[0] write 1 enable pll lol status output */ ctc_mac_hss_read(priv, 0x30, &val, 2); val |= BIT(0); ctc_mac_hss_write(priv, 0x30, val, 2); - if (tmpr <= -20) + if (tmpr <= -20) { delta = 2; - else if (tmpr <= 60) + } else if (tmpr <= 60) { delta = 1; - else + } else { delta = 0; - + } /*read_vco_ctune 0xe0[3:0] read ctune raw value */ ctc_mac_hss_read(priv, 0xe0, &val, 2); ctune = val & 0xf; @@ -690,7 +750,7 @@ static int ctcmac_maximize_margin_of_cmu_tempearture_ramp(struct ctcmac_private mdelay(10); /*pll_lol_udl 0xe0[4] read 0 */ val = ctc_mac_hss_read(priv, 0xe0, &val, 2); - if ((0 != (val & BIT(4))) && delta == 2) { + if ((0 != (val & BIT(4))) && (delta == 2)) { /*cfg_vco_byp_ctune 0x07[3:0] write (ctune - 1) */ ctune_cal = ctune - 1; ctc_mac_hss_read(priv, 0x7, &val, 2); @@ -703,141 +763,158 @@ static int ctcmac_maximize_margin_of_cmu_tempearture_ramp(struct ctcmac_private /*pll_lol_udl 0xe0[4] read 0 */ val = ctc_mac_hss_read(priv, 0xe0, &val, 2); if (0 != (val & BIT(4))) { - pr_err("maximize margin of cmu tempearture ramp fail!\n"); + printk(KERN_ERR + "maximize margin of cmu tempearture ramp fail!\n"); return -1; } return 0; } +/* tx/rx polarity invert */ +static int ctc_mac_pol_inv(struct ctcmac_private *priv) +{ + u8 data = 0; + + if (priv->tx_pol_inv) { + /* tx polarity will be inverted */ + ctc_mac_hss_read(priv, 0x83, &data, priv->index); + ctc_mac_hss_write(priv, 0x83, (data | 0x2), priv->index); + } + + if (priv->rx_pol_inv) { + /* rx polarity will be inverted */ + ctc_mac_hss_read(priv, 0x83, &data, priv->index); + ctc_mac_hss_write(priv, 0x83, (data | 0x8), priv->index); + } + return 0; +} + /* serdes init flow */ static int ctc_mac_serdes_init(struct ctcmac_private *priv) { + u8 val; int ret = 0; u32 status; int delay_ms = 10; if (priv->dfe_enable) { /* reset serdes */ - writel(0x4610b003, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[5]); - writel(0x4610b003, - &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[11]); - writel(0x83806000, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[0]); - writel(0x28061800, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[2]); - writel(0x0066c03a, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[6]); - writel(0x28061810, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[8]); - writel(0x0066c03a, - &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[12]); + writel(0x4610b003, &priv->cpumacu_reg->CpuMacUnitHssCfg[5]); + writel(0x4610b003, &priv->cpumacu_reg->CpuMacUnitHssCfg[11]); + writel(0x83806000, &priv->cpumacu_reg->CpuMacUnitHssCfg[0]); + writel(0x28061800, &priv->cpumacu_reg->CpuMacUnitHssCfg[2]); + writel(0x0066c03a, &priv->cpumacu_reg->CpuMacUnitHssCfg[6]); + writel(0x28061810, &priv->cpumacu_reg->CpuMacUnitHssCfg[8]); + writel(0x0066c03a, &priv->cpumacu_reg->CpuMacUnitHssCfg[12]); } else { /* reset serdes */ - writel(0x4610a805, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[5]); - writel(0x4610a805, - &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[11]); - writel(0x83806000, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[0]); - writel(0x28061800, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[2]); - writel(0x0026c02a, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[6]); - writel(0x28061810, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[8]); - writel(0x0026c02a, - &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[12]); + writel(0x4610a805, &priv->cpumacu_reg->CpuMacUnitHssCfg[5]); + writel(0x4610a805, &priv->cpumacu_reg->CpuMacUnitHssCfg[11]); + writel(0x83806000, &priv->cpumacu_reg->CpuMacUnitHssCfg[0]); + writel(0x28061800, &priv->cpumacu_reg->CpuMacUnitHssCfg[2]); + writel(0x0026c02a, &priv->cpumacu_reg->CpuMacUnitHssCfg[6]); + writel(0x28061810, &priv->cpumacu_reg->CpuMacUnitHssCfg[8]); + writel(0x0026c02a, &priv->cpumacu_reg->CpuMacUnitHssCfg[12]); } /* offset0 bit1 BlkRstN */ - writel(0x83806002, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[0]); + writel(0x83806002, &priv->cpumacu_reg->CpuMacUnitHssCfg[0]); mdelay(delay_ms); - writel(0x80002309, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x80002309, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x80000842, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x80000842, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x8000ea45, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x8000ea45, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); /* serdes 0 init */ - writel(0x83000a05, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x83000a05, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x83002008, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x83002008, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x8300640f, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x8300640f, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x83000214, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x83000214, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x83008015, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x83008015, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x83000116, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x83000116, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x83001817, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x83001817, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x83003018, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x83003018, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x83000e24, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x83000e24, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x83008226, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x83008226, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x83001f27, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x83001f27, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x83002028, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x83002028, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x83002829, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x83002829, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x8300302a, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x8300302a, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x83002038, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x83002038, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x8300223a, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x8300223a, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x8300523b, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x8300523b, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x83002040, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x83002040, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x8300f141, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x8300f141, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x8300014a, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x8300014a, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x8300e693, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x8300e693, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); /* serdes 1 init */ - writel(0x84000a05, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x84000a05, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x84002008, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x84002008, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x8400640f, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x8400640f, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x84000214, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x84000214, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x84008015, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x84008015, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x84000116, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x84000116, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x84001817, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x84001817, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x84003018, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x84003018, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x84000e24, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x84000e24, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x84008226, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x84008226, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x84001f27, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x84001f27, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x84002028, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x84002028, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x84002829, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x84002829, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x8400302a, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x8400302a, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x84002038, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x84002038, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x8400223a, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x8400223a, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x8400523b, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x8400523b, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x84002040, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x84002040, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x8400f141, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x8400f141, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x8400014a, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x8400014a, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); - writel(0x8400e693, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); + writel(0x8400e693, &priv->cpumacu_reg->CpuMacUnitHssRegAccCtl); mdelay(delay_ms); ctc_mac_hss_write(priv, 0x0c, 0x21, 0); @@ -862,29 +939,34 @@ static int ctc_mac_serdes_init(struct ctcmac_private *priv) ctc_mac_hss_write(priv, 0x14, 0x01, 1); ctc_mac_hss_write(priv, 0x26, 0x81, 1); + ctc_mac_hss_read(priv, 0x1c, &val, 2); + val &= 0xf8; + val |= 0x4; + ctc_mac_hss_write(priv, 0x1c, val, 2); + /* serdes post release */ - writel(0x83806003, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[0]); - writel(0x83826003, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[0]); + writel(0x83806003, &priv->cpumacu_reg->CpuMacUnitHssCfg[0]); + writel(0x83826003, &priv->cpumacu_reg->CpuMacUnitHssCfg[0]); - writel(0x28061801, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[2]); - writel(0x28061c01, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[2]); - writel(0x28071c01, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[2]); + writel(0x28061801, &priv->cpumacu_reg->CpuMacUnitHssCfg[2]); + writel(0x28061c01, &priv->cpumacu_reg->CpuMacUnitHssCfg[2]); + writel(0x28071c01, &priv->cpumacu_reg->CpuMacUnitHssCfg[2]); - writel(0x28061811, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[8]); - writel(0x28061c11, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[8]); - writel(0x28071c11, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[8]); + writel(0x28061811, &priv->cpumacu_reg->CpuMacUnitHssCfg[8]); + writel(0x28061c11, &priv->cpumacu_reg->CpuMacUnitHssCfg[8]); + writel(0x28071c11, &priv->cpumacu_reg->CpuMacUnitHssCfg[8]); ret = - readl_poll_timeout(&priv->cpumacu_reg->cpu_mac_unit_hss_mon[1], - status, + readl_poll_timeout(&priv->cpumacu_reg->CpuMacUnitHssMon[1], status, status & - CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_DFE_RST_DONE, + BIT + (CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_DFE_RST_DONE_BIT), 1000, 2000000); if (ret) { netdev_dbg(priv->ndev, - "%s:wait for hss reset done fail with cpu_mac_unit_hss_mon[1]:0x%x\n", + "%s:wait for hss reset done fail with CpuMacUnitHssMon[1]:0x%x\n", priv->ndev->name, - readl(&priv->cpumacu_reg->cpu_mac_unit_hss_mon[1])); + readl(&priv->cpumacu_reg->CpuMacUnitHssMon[1])); } mdelay(delay_ms); @@ -893,6 +975,122 @@ static int ctc_mac_serdes_init(struct ctcmac_private *priv) return 0; } +static void ctcmac_mac_filter_init(struct ctcmac_private *priv) +{ + unsigned char *dev_addr; + u32 val, addr_h = 0, addr_l = 0; + + if (priv->version == 0) + return; + + /* mac filter table 0~3 are assigned to cpumac0 + mac filter table 4~7 are assigned to cpumac1 + mac filter table 0/4:white list to receive pacekt with local mac address + mac filter table 1/5:white list to receive pacekt with broadcast mac address + mac filter table 2/6:white list to receive pacekt with multicast mac address + mac filter table 3/7:white list to receive pacekt with multicast mac address + */ + + /* 1. mac filter table 0~3 are assigned to cpumac0 + mac filter table 4~7 are assigned to cpumac1 */ + if (priv->index == 0) { + val = readl(&priv->cpumacu_reg->CpuMacUnitFilterCfg1[0]); + val |= (0xf << 16); + val &= ~(0xf0 << 16); + writel(val, &priv->cpumacu_reg->CpuMacUnitFilterCfg1[0]); + + val = readl(&priv->cpumacu_reg->CpuMacUnitFilterCfg1[1]); + val |= + BIT + (CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_CHECK_NORMAL_PKT_ENABLE0_BIT); + val |= + BIT(CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_DROP_NORMAL_PKT0_BIT); + writel(val, &priv->cpumacu_reg->CpuMacUnitFilterCfg1[1]); + } else { + val = readl(&priv->cpumacu_reg->CpuMacUnitFilterCfg1[0]); + val |= (0xf0 << 24); + val &= ~(0xf << 24); + writel(val, &priv->cpumacu_reg->CpuMacUnitFilterCfg1[0]); + + val = readl(&priv->cpumacu_reg->CpuMacUnitFilterCfg1[1]); + val |= + BIT + (CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_CHECK_NORMAL_PKT_ENABLE1_BIT); + val |= + BIT(CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_DROP_NORMAL_PKT1_BIT); + writel(val, &priv->cpumacu_reg->CpuMacUnitFilterCfg1[1]); + } + + /* 2. enable mac filter function */ + val = readl(&priv->cpumacu_reg->CpuMacUnitFilterCfg[0]); + val |= BIT(CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_FILTER_EN_BIT); + val &= ~BIT(CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_CAM_IS_BLACK_LIST_BIT); + val &= ~BIT(CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA0_BIT); + val &= ~BIT(CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA1_BIT); + val &= ~BIT(CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA2_BIT); + val &= ~BIT(CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA3_BIT); + val &= ~BIT(CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA4_BIT); + val &= ~BIT(CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA5_BIT); + val &= ~BIT(CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA6_BIT); + val &= ~BIT(CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA7_BIT); + writel(val, &priv->cpumacu_reg->CpuMacUnitFilterCfg[0]); + + /* 3. mac filter table 0/4:white list to receive pacekt with local mac address */ + dev_addr = priv->ndev->dev_addr; + addr_h = dev_addr[0] << 8 | dev_addr[1]; + addr_l = + dev_addr[2] << 24 | dev_addr[3] << 16 | dev_addr[4] << 8 | + dev_addr[5]; + if (priv->index == 0) { + writel(addr_l, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[0]); + writel(addr_h, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[1]); + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[16]); + writel(0x0000ffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[17]); + } else { + writel(addr_l, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[8]); + writel(addr_h, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[9]); + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[24]); + writel(0x0000ffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[25]); + } + + /* 4. mac filter table 1/5:white list to receive pacekt with broadcast mac address */ + if (priv->index == 0) { + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[2]); + writel(0x0000ffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[3]); + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[18]); + writel(0x0000ffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[19]); + } else { + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[10]); + writel(0x0000ffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[11]); + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[26]); + writel(0x0000ffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[27]); + } + + /* mac filter table 2/6/3/7 reserved */ + if (priv->index == 0) { + writel(0x00000000, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[4]); + writel(0x00000000, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[5]); + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[20]); + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[21]); + + writel(0x00000000, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[6]); + writel(0x00000000, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[7]); + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[22]); + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[23]); + } else { + writel(0x00000000, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[12]); + writel(0x00000000, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[13]); + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[28]); + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[29]); + + writel(0x00000000, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[14]); + writel(0x00000000, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[15]); + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[30]); + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[31]); + } + +} + /* Hardware init flow */ static void ctcmac_hw_init(struct ctcmac_private *priv) { @@ -900,92 +1098,101 @@ static void ctcmac_hw_init(struct ctcmac_private *priv) u32 val; int use_extram = 0; + /* tx/rx polarity invert */ + ctc_mac_pol_inv(priv); + /* two cpumac access the same cpumac unit register */ spin_lock_irq(&global_reglock); if (priv->index == 0) { - /* release cpu_mac_0 */ - clrsetbits(&priv->cpumacu_reg->cpu_mac_unit_reset_ctl, - CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_BASE, - CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC0); - clrsetbits(&priv->cpumacu_reg->cpu_mac_unit_reset_ctl, - CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC0, 0); + /* release CpuMac0 */ + clrsetbits(&priv->cpumacu_reg->CpuMacUnitResetCtl, + BIT(CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_BASE_BIT), + BIT + (CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC0_BIT)); + clrsetbits(&priv->cpumacu_reg->CpuMacUnitResetCtl, + BIT + (CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC0_BIT), + 0); } else { - /* release cpu_mac_0 */ - clrsetbits(&priv->cpumacu_reg->cpu_mac_unit_reset_ctl, - CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_BASE, - CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC1); - clrsetbits(&priv->cpumacu_reg->cpu_mac_unit_reset_ctl, - CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC1, 0); + /* release CpuMac0 */ + clrsetbits(&priv->cpumacu_reg->CpuMacUnitResetCtl, + BIT(CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_BASE_BIT), + BIT + (CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC1_BIT)); + clrsetbits(&priv->cpumacu_reg->CpuMacUnitResetCtl, + BIT + (CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC1_BIT), + 0); } - clrsetbits(&priv->cpumacu_reg->cpu_mac_unit_ts_cfg, - 0, CPU_MAC_UNIT_TS_CFG_W0_CFG_FORCE_S_AND_NS_EN); + clrsetbits(&priv->cpumacu_reg->CpuMacUnitTsCfg, + 0, BIT(CPU_MAC_UNIT_TS_CFG_W0_CFG_FORCE_S_AND_NS_EN_BIT)); spin_unlock_irq(&global_reglock); mdelay(10); - /* init cpu_mac */ - clrsetbits(&priv->cpumac_reg->cpu_mac_init, 0, - CPU_MAC_INIT_DONE_W0_INIT_DONE); + /* init CpuMac */ + clrsetbits(&priv->cpumac_reg->CpuMacInit, 0, + BIT(CPU_MAC_INIT_DONE_W0_INIT_DONE_BIT)); udelay(1); if (priv->interface == PHY_INTERFACE_MODE_SGMII) { /* switch to sgmii and enable auto nego */ - val = readl(&priv->cpumac_reg->cpu_mac_sgmii_auto_neg_cfg); + val = readl(&priv->cpumac_reg->CpuMacSgmiiAutoNegCfg); val &= ~(CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_ENABLE_MASK | CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_MODE_MASK); val |= (CSA_SGMII_MD_MASK | CSA_EN); - writel(val, &priv->cpumac_reg->cpu_mac_sgmii_auto_neg_cfg); + writel(val, &priv->cpumac_reg->CpuMacSgmiiAutoNegCfg); } if (priv->autoneg_mode == CTCMAC_AUTONEG_DISABLE) { - clrsetbits(&priv->cpumac_reg->cpu_mac_sgmii_auto_neg_cfg, - CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_ENABLE, 0); + clrsetbits(&priv->cpumac_reg->CpuMacSgmiiAutoNegCfg, + BIT(CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_ENABLE_BIT), + 0); } else { - val = readl(&priv->cpumac_reg->cpu_mac_sgmii_auto_neg_cfg); + val = readl(&priv->cpumac_reg->CpuMacSgmiiAutoNegCfg); val &= ~CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_MODE_MASK; val |= - (priv->autoneg_mode << 2 | - CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_ENABLE); - writel(val, &priv->cpumac_reg->cpu_mac_sgmii_auto_neg_cfg); + (priv-> + autoneg_mode << 2 | + BIT(CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_ENABLE_BIT)); + writel(val, &priv->cpumac_reg->CpuMacSgmiiAutoNegCfg); } /* disable rx link filter */ - clrsetbits(&priv->cpumac_reg->cpu_mac_sgmii_cfg[0], - CPU_MAC_SGMII_CFG_W0_CFG_MII_RX_LINK_FILTER_EN, 0); + clrsetbits(&priv->cpumac_reg->CpuMacSgmiiCfg[0], + BIT(CPU_MAC_SGMII_CFG_W0_CFG_MII_RX_LINK_FILTER_EN_BIT), 0); /* ignore tx event */ - clrsetbits(&priv->cpumac_reg->cpu_mac_sgmii_cfg[0], - 0, CPU_MAC_SGMII_CFG_W0_CFG_TX_EVEN_IGNORE); + clrsetbits(&priv->cpumac_reg->CpuMacSgmiiCfg[0], + 0, BIT(CPU_MAC_SGMII_CFG_W0_CFG_TX_EVEN_IGNORE_BIT)); - clrsetbits(&priv->cpumac_reg->cpu_mac_axi_cfg, - 0, CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_D_WORD_SWAP_EN); - clrsetbits(&priv->cpumac_reg->cpu_mac_axi_cfg, - 0, CPU_MAC_AXI_CFG_W0_CFG_AXI_WR_D_WORD_SWAP_EN); + clrsetbits(&priv->cpumac_reg->CpuMacAxiCfg, + 0, BIT(CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_D_WORD_SWAP_EN_BIT)); + clrsetbits(&priv->cpumac_reg->CpuMacAxiCfg, + 0, BIT(CPU_MAC_AXI_CFG_W0_CFG_AXI_WR_D_WORD_SWAP_EN_BIT)); /* drop over size packet */ - clrsetbits(&priv->cpumac_reg->cpu_mac_gmac_cfg[0], - 0, CPU_MAC_GMAC_CFG_W0_CFG_RX_OVERRUN_DROP_EN - | CPU_MAC_GMAC_CFG_W0_CFG_RX_OVERSIZE_DROP_EN); + clrsetbits(&priv->cpumac_reg->CpuMacGmacCfg[0], + 0, BIT(CPU_MAC_GMAC_CFG_W0_CFG_RX_OVERRUN_DROP_EN_BIT) + | BIT(CPU_MAC_GMAC_CFG_W0_CFG_RX_OVERSIZE_DROP_EN_BIT)); /* not strip 4B crc when send packet */ - clrsetbits(&priv->cpumac_reg->cpu_mac_gmac_cfg[2], - CPU_MAC_GMAC_CFG_W2_CFG_TX_STRIP_CRC_EN, 0); + clrsetbits(&priv->cpumac_reg->CpuMacGmacCfg[2], + BIT(CPU_MAC_GMAC_CFG_W2_CFG_TX_STRIP_CRC_EN_BIT), 0); /* enable cut-through mode */ - clrsetbits(&priv->cpumac_reg->cpu_mac_gmac_cfg[2], - 0, CPU_MAC_GMAC_CFG_W2_CFG_TX_CUT_THROUGH_EN); + clrsetbits(&priv->cpumac_reg->CpuMacGmacCfg[2], + 0, BIT(CPU_MAC_GMAC_CFG_W2_CFG_TX_CUT_THROUGH_EN_BIT)); for (i = 0; i < priv->num_tx_queues; i++) { - if (priv->tx_queue[i]->tx_ring_size > - CTCMAC_INTERNAL_RING_SIZE) { + if (priv->tx_queue[i]->tx_ring_size > CTCMAC_INTERNAL_RING_SIZE) { use_extram = 1; break; } } for (i = 0; i < priv->num_rx_queues; i++) { - if (priv->rx_queue[i]->rx_ring_size > - CTCMAC_INTERNAL_RING_SIZE) { + if (priv->rx_queue[i]->rx_ring_size > CTCMAC_INTERNAL_RING_SIZE) { use_extram = 1; break; } @@ -993,9 +1200,7 @@ static void ctcmac_hw_init(struct ctcmac_private *priv) if (use_extram) { spin_lock_irq(&global_reglock); - /* enable external SRAM to store rx/tx desc, - * support max 1023*3 desc - */ + /* enable external SRAM to store rx/tx desc, support max 1023*3 desc */ regmap_read(regmap_base, offsetof(struct SysCtl_regs, SysMemCtl), &val); val |= SYS_MEM_CTL_W0_CFG_RAM_MUX_EN; @@ -1004,22 +1209,20 @@ static void ctcmac_hw_init(struct ctcmac_private *priv) spin_unlock_irq(&global_reglock); if (priv->index == 0) { - ctcmac_regw(&priv->cpumac_reg->cpu_mac_ext_ram_cfg[1], + ctcmac_regw(&priv->cpumac_reg->CpuMacExtRamCfg[1], CTCMAC0_EXSRAM_BASE); } else { - ctcmac_regw(&priv->cpumac_reg->cpu_mac_ext_ram_cfg[1], + ctcmac_regw(&priv->cpumac_reg->CpuMacExtRamCfg[1], CTCMAC1_EXSRAM_BASE); } - ctcmac_regw(&priv->cpumac_reg->cpu_mac_ext_ram_cfg[0], + ctcmac_regw(&priv->cpumac_reg->CpuMacExtRamCfg[0], CTCMAC_TX_RING_SIZE); - clrsetbits(&priv->cpumac_reg->cpu_mac_ext_ram_cfg[0], 0, - CPU_MAC_EXT_RAM_CFG_W0_CFG_EXT_RAM_EN); + clrsetbits(&priv->cpumac_reg->CpuMacExtRamCfg[0], 0, + BIT(CPU_MAC_EXT_RAM_CFG_W0_CFG_EXT_RAM_EN_BIT)); } else { - /* disable external SRAM to store rx/tx desc, - * support max 64*3 desc - */ - clrsetbits(&priv->cpumac_reg->cpu_mac_ext_ram_cfg[0], - CPU_MAC_EXT_RAM_CFG_W0_CFG_EXT_RAM_EN, 0); + /* disable external SRAM to store rx/tx desc, support max 64*3 desc */ + clrsetbits(&priv->cpumac_reg->CpuMacExtRamCfg[0], + BIT(CPU_MAC_EXT_RAM_CFG_W0_CFG_EXT_RAM_EN_BIT), 0); spin_lock_irq(&global_reglock); regmap_read(regmap_base, @@ -1031,24 +1234,55 @@ static void ctcmac_hw_init(struct ctcmac_private *priv) } if (priv->int_type == CTCMAC_INT_DESC) { - val = CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_ACK_EN - | (CTCMAC_DESC_INT_NUM << 16) - | (CTCMAC_DESC_INT_NUM << 8) - | (CTCMAC_DESC_INT_NUM << 0); - ctcmac_regw(&priv->cpumac_reg->cpu_mac_desc_cfg[0], val); + val = BIT(CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_ACK_EN_BIT) + | (priv->rx_int_coalesce_cnt << 16) + | (priv->rx_int_coalesce_cnt << 8) + | (priv->tx_int_coalesce_cnt << 0); + ctcmac_regw(&priv->cpumac_reg->CpuMacDescCfg[0], val); + if (priv->version > 0) { + val = ctcmac_regr(&priv->cpumac_reg->CpuMacDescCfg1[0]); + val |= + (1 << + CPU_MAC_DESC_CFG1_W0_CFG_RX_DESC_DONE_INTR_TIMER_EN) + | (1 << + CPU_MAC_DESC_CFG1_W0_CFG_TX_DESC_DONE_INTR_TIMER_EN); + ctcmac_regw(&priv->cpumac_reg->CpuMacDescCfg1[0], val); + ctcmac_regw(&priv->cpumac_reg->CpuMacDescCfg1[1], + CTCMAC_TIMER_THRD); + ctcmac_regw(&priv->cpumac_reg->CpuMacDescCfg1[2], + CTCMAC_TIMER_THRD); + } } else { - val = CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_DONE_INTR_EOP_EN - | CPU_MAC_DESC_CFG_W0_CFG_RX_DESC_DONE_INTR_EOP_EN - | CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_ACK_EN; - ctcmac_regw(&priv->cpumac_reg->cpu_mac_desc_cfg[0], val); + val = BIT(CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_DONE_INTR_EOP_EN_BIT) + | BIT(CPU_MAC_DESC_CFG_W0_CFG_RX_DESC_DONE_INTR_EOP_EN_BIT) + | BIT(CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_ACK_EN_BIT); + ctcmac_regw(&priv->cpumac_reg->CpuMacDescCfg[0], val); + } + + ctcmac_mac_filter_init(priv); + + /* clear and mask all interrupt */ + ctcmac_regw(&priv->cpumac_reg->CpuMacInterruptFunc[1], 0xffffffff); + ctcmac_regw(&priv->cpumac_reg->CpuMacInterruptNormal[1], 0xffffffff); + ctcmac_regw(&priv->cpumac_reg->CpuMacInterruptFunc[2], 0xffffffff); + ctcmac_regw(&priv->cpumac_reg->CpuMacInterruptNormal[2], 0xffffffff); + + if (priv->version > 0) { + ctcmac_regw(&priv->cpumac_reg->CpuMacInterruptFunc0[1], + 0xffffffff); + ctcmac_regw(&priv->cpumac_reg->CpuMacInterruptFunc1[1], + 0xffffffff); + ctcmac_regw(&priv->cpumac_reg->CpuMacInterruptFunc0[2], + 0xffffffff); + ctcmac_regw(&priv->cpumac_reg->CpuMacInterruptFunc1[2], + 0xffffffff); } +#if 0 + if (!(priv->ndev->flags & IFF_PROMISC)) { + ctcmac_init_mac_filter(priv); + } +#endif - /* clear all interrupt */ - ctcmac_regw(&priv->cpumac_reg->cpu_mac_interrupt_func[1], 0xffffffff); - ctcmac_regw(&priv->cpumac_reg->cpu_mac_interrupt_normal[1], 0xffffffff); - /* mask all interrupt */ - ctcmac_regw(&priv->cpumac_reg->cpu_mac_interrupt_func[2], 0xffffffff); - ctcmac_regw(&priv->cpumac_reg->cpu_mac_interrupt_normal[2], 0xffffffff); } static int ctcmac_wait_for_linkup(struct ctcmac_private *priv) @@ -1059,31 +1293,35 @@ static int ctcmac_wait_for_linkup(struct ctcmac_private *priv) if (priv->autoneg_mode == CTCMAC_AUTONEG_DISABLE) { /* wait for linkup */ while (timeout--) { - mon = readl(&priv->cpumac_reg->cpu_mac_sgmii_mon[0]); - if ((mon & 0x100) == 0x100) + mon = readl(&priv->cpumac_reg->CpuMacSgmiiMon[0]); + if ((mon & 0x100) == 0x100) { break; + } mdelay(1); } if ((mon & 0x100) != 0x100) { - pr_err("Error! when phy link up, link status %d is not right.\n", - mon); + printk + ("Error! when phy link up, link status %d is not right.\n", + mon); return -1; } } else { /* wait for sgmii auto nego complete */ while (timeout--) { - mon = readl(&priv->cpumac_reg->cpu_mac_sgmii_mon[0]); - if ((mon & CSM_ANST_MASK) == 6) + mon = readl(&priv->cpumac_reg->CpuMacSgmiiMon[0]); + if ((mon & CSM_ANST_MASK) == 6) { break; + } mdelay(1); } if ((mon & CSM_ANST_MASK) != 6) { - pr_err("Error! when phy link up, auto-neg status %d is not right.\n", - mon); + printk + ("Error! when phy link up, auto-neg status %d is not right.\n", + mon); return -1; } } @@ -1091,6 +1329,79 @@ static int ctcmac_wait_for_linkup(struct ctcmac_private *priv) return 0; } +static void ctcmac_cfg_flow_ctrl(struct ctcmac_private *priv, u8 tx_pause_en, + u8 rx_pause_en) +{ + u32 val; + + val = 1 << CPU_MAC_PAUSE_CFG_W0_CFG_RX_PAUSE_TIMER_DEC_VALUE_BIT; + writel(val, &priv->cpumac_reg->CpuMacPauseCfg[0]); + val = (0xffff << CPU_MAC_PAUSE_CFG_W1_CFG_TX_PAUSE_TIMER_ADJ_VALUE_BIT) + | (1 << CPU_MAC_PAUSE_CFG_W1_CFG_TX_PAUSE_TIMER_DEC_VALUE_BIT); + writel(val, &priv->cpumac_reg->CpuMacPauseCfg[1]); + + if (tx_pause_en || rx_pause_en) + val = 0xff; + else + val = 0x800000ff; + writel(val, &priv->cpumacu_reg->CpuMacUnitRefPulseCfg[0]); + + if (tx_pause_en) + clrsetbits(&priv->cpumac_reg->CpuMacPauseCfg[1], 0, + BIT(CPU_MAC_PAUSE_CFG_W1_CFG_TX_PAUSE_EN_BIT)); + if (rx_pause_en) { + clrsetbits(&priv->cpumac_reg->CpuMacPauseCfg[0], 0, + BIT(CPU_MAC_PAUSE_CFG_W0_CFG_RX_NORM_PAUSE_EN_BIT)); + clrsetbits(&priv->cpumac_reg->CpuMacGmacCfg[2], 0, + BIT(CPU_MAC_GMAC_CFG_W2_CFG_TX_PAUSE_STALL_EN_BIT)); + } +} + +/* IEEE 802.3-2000 +* Table 28B-3 +* Pause Resolution +* +* Local Remote Local Resolution Remote Resolution +* PAUSE ASM_DIR PAUSE ASM_DIR TX RX TX RX +* +* 0 0 x x 0 0 0 0 +* 0 1 0 x 0 0 0 0 +* 0 1 1 0 0 0 0 0 +* 0 1 1 1 1 0 0 1 +* 1 0 0 x 0 0 0 0 +* 1 x 1 x 1 1 1 1 +* 1 1 0 0 0 0 0 0 +* 1 1 0 1 0 1 1 0 +* +*/ +static void ctcmac_adjust_flow_ctrl(struct ctcmac_private *priv) +{ + struct net_device *ndev = priv->ndev; + struct phy_device *phydev = ndev->phydev; + + if (!phydev->duplex) + return; + + if (!priv->pause_aneg_en) { + ctcmac_cfg_flow_ctrl(priv, priv->tx_pause_en, + priv->rx_pause_en); + } else { + u16 lcl_adv, rmt_adv; + u8 flowctrl; + /* get link partner capabilities */ + rmt_adv = 0; + if (phydev->pause) + rmt_adv = LPA_PAUSE_CAP; + if (phydev->asym_pause) + rmt_adv |= LPA_PAUSE_ASYM; + + lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising); + flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); + ctcmac_cfg_flow_ctrl(priv, flowctrl & FLOW_CTRL_TX, + flowctrl & FLOW_CTRL_RX); + } +} + /* update cpumac speed when phy linkup speed changed */ static noinline void ctcmac_update_link_state(struct ctcmac_private *priv, struct phy_device *phydev) @@ -1101,12 +1412,13 @@ static noinline void ctcmac_update_link_state(struct ctcmac_private *priv, if (priv->interface != PHY_INTERFACE_MODE_SGMII) return; - if (netif_msg_link(priv)) + if (netif_msg_link(priv)) { netdev_dbg(priv->ndev, "link up speed is %d\n", speed); + } if (phydev->link) { - cfg_rep = readl(&priv->cpumac_reg->cpu_mac_sgmii_cfg[0]); - cfg_smp = readl(&priv->cpumac_reg->cpu_mac_sgmii_cfg[1]); + cfg_rep = readl(&priv->cpumac_reg->CpuMacSgmiiCfg[0]); + cfg_smp = readl(&priv->cpumac_reg->CpuMacSgmiiCfg[1]); cfg_rep &= ~CSC_REP_MASK; cfg_smp &= ~CSC_SMP_MASK; if (speed == 1000) { @@ -1121,9 +1433,10 @@ static noinline void ctcmac_update_link_state(struct ctcmac_private *priv, } else { return; } - writel(cfg_rep, &priv->cpumac_reg->cpu_mac_sgmii_cfg[0]); - writel(cfg_smp, &priv->cpumac_reg->cpu_mac_sgmii_cfg[1]); + writel(cfg_rep, &priv->cpumac_reg->CpuMacSgmiiCfg[0]); + writel(cfg_smp, &priv->cpumac_reg->CpuMacSgmiiCfg[1]); + ctcmac_adjust_flow_ctrl(priv); ctcmac_wait_for_linkup(priv); if (!priv->oldlink) @@ -1134,6 +1447,8 @@ static noinline void ctcmac_update_link_state(struct ctcmac_private *priv, priv->oldspeed = 0; priv->oldduplex = -1; } + + return; } static void adjust_link(struct net_device *dev) @@ -1153,10 +1468,28 @@ static void adjust_link(struct net_device *dev) static int ctcmac_init_phy(struct net_device *dev) { int err; + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { + 0,}; struct ctcmac_private *priv = netdev_priv(dev); phy_interface_t interface; struct phy_device *phydev; - + const int phy_10_features_array[2] = { + ETHTOOL_LINK_MODE_10baseT_Half_BIT, + ETHTOOL_LINK_MODE_10baseT_Full_BIT, + }; + + linkmode_set_bit_array(phy_10_features_array, + ARRAY_SIZE(phy_10_features_array), mask); + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask); + linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask); + if (priv->supported & SUPPORTED_100baseT_Full) { + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); + } + if (priv->supported & SUPPORTED_1000baseT_Full) { + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mask); + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mask); + } priv->oldlink = 0; priv->oldspeed = 0; priv->oldduplex = -1; @@ -1177,8 +1510,11 @@ static int ctcmac_init_phy(struct net_device *dev) } /* Remove any features not supported by the controller */ - phydev->supported &= priv->supported; - phydev->advertising = phydev->supported; + linkmode_and(phydev->supported, phydev->supported, mask); + linkmode_copy(phydev->advertising, phydev->supported); + + /* Add support for flow control */ + phy_support_asym_pause(phydev); return 0; } @@ -1191,13 +1527,45 @@ static irqreturn_t ctcmac_receive(int irq, struct ctcmac_private *priv) /* disable interrupt */ spin_lock_irqsave(&priv->reglock, flags); writel(CTCMAC_NOR_RX0_D | CTCMAC_NOR_RX1_D, - &priv->cpumac_reg->cpu_mac_interrupt_func[2]); + &priv->cpumac_reg->CpuMacInterruptFunc[2]); spin_unlock_irqrestore(&priv->reglock, flags); __napi_schedule(&priv->napi_rx); } else { /* clear interrupt */ writel(CTCMAC_NOR_RX0_D | CTCMAC_NOR_RX1_D, - &priv->cpumac_reg->cpu_mac_interrupt_func[1]); + &priv->cpumac_reg->CpuMacInterruptFunc[1]); + } + + return IRQ_HANDLED; +} + +static irqreturn_t ctcmac_receive0(int irq, struct ctcmac_private *priv) +{ + if (likely(napi_schedule_prep(&priv->napi_rx))) { + /* disable interrupt */ + writel(CTCMAC_FUNC0_RX_D, + &priv->cpumac_reg->CpuMacInterruptFunc0[2]); + __napi_schedule(&priv->napi_rx); + } else { + /* clear interrupt */ + writel(CTCMAC_FUNC0_RX_D, + &priv->cpumac_reg->CpuMacInterruptFunc0[1]); + } + + return IRQ_HANDLED; +} + +static irqreturn_t ctcmac_receive1(int irq, struct ctcmac_private *priv) +{ + if (likely(napi_schedule_prep(&priv->napi_rx1))) { + /* disable interrupt */ + writel(CTCMAC_FUNC1_RX_D, + &priv->cpumac_reg->CpuMacInterruptFunc1[2]); + __napi_schedule(&priv->napi_rx1); + } else { + /* clear interrupt */ + writel(CTCMAC_FUNC1_RX_D, + &priv->cpumac_reg->CpuMacInterruptFunc1[1]); } return IRQ_HANDLED; @@ -1211,14 +1579,14 @@ static irqreturn_t ctcmac_transmit(int irq, struct ctcmac_private *priv) /* disable interrupt */ spin_lock_irqsave(&priv->reglock, flags); writel(CTCMAC_NOR_TX_D, - &priv->cpumac_reg->cpu_mac_interrupt_func[2]); + &priv->cpumac_reg->CpuMacInterruptFunc[2]); spin_unlock_irqrestore(&priv->reglock, flags); __napi_schedule(&priv->napi_tx); } else { /* clear interrupt */ writel(CTCMAC_NOR_TX_D, - &priv->cpumac_reg->cpu_mac_interrupt_func[1]); + &priv->cpumac_reg->CpuMacInterruptFunc[1]); } return IRQ_HANDLED; @@ -1229,8 +1597,8 @@ static irqreturn_t ctcmac_func(int irq, void *data) u32 event, stat, mask; struct ctcmac_private *priv = (struct ctcmac_private *)data; - stat = ctcmac_regr(&priv->cpumac_reg->cpu_mac_interrupt_func[0]); - mask = ctcmac_regr(&priv->cpumac_reg->cpu_mac_interrupt_func[2]); + stat = ctcmac_regr(&priv->cpumac_reg->CpuMacInterruptFunc[0]); + mask = ctcmac_regr(&priv->cpumac_reg->CpuMacInterruptFunc[2]); event = stat & ~mask; if (netif_msg_intr(priv)) { @@ -1238,11 +1606,40 @@ static irqreturn_t ctcmac_func(int irq, void *data) "function interrupt stat 0x%x mask 0x%x\n", stat, mask); } - if ((event & CTCMAC_NOR_RX0_D) || (event & CTCMAC_NOR_RX1_D)) + if ((event & CTCMAC_NOR_RX0_D) || (event & CTCMAC_NOR_RX1_D)) { ctcmac_receive(irq, priv); + } - if (event & CTCMAC_NOR_TX_D) + if (event & CTCMAC_NOR_TX_D) { ctcmac_transmit(irq, priv); + } + + return IRQ_HANDLED; +} + +static irqreturn_t ctcmac_tx_isr(int irq, void *data) +{ + struct ctcmac_private *priv = (struct ctcmac_private *)data; + + ctcmac_transmit(irq, priv); + + return IRQ_HANDLED; +} + +static irqreturn_t ctcmac_rx0_isr(int irq, void *data) +{ + struct ctcmac_private *priv = (struct ctcmac_private *)data; + + ctcmac_receive0(irq, priv); + + return IRQ_HANDLED; +} + +static irqreturn_t ctcmac_rx1_isr(int irq, void *data) +{ + struct ctcmac_private *priv = (struct ctcmac_private *)data; + + ctcmac_receive1(irq, priv); return IRQ_HANDLED; } @@ -1253,8 +1650,8 @@ static irqreturn_t ctcmac_normal(int irq, void *data) //TODO by liuht u32 stat, mask; struct ctcmac_private *priv = (struct ctcmac_private *)data; - stat = ctcmac_regr(&priv->cpumac_reg->cpu_mac_interrupt_func[0]); - mask = ctcmac_regr(&priv->cpumac_reg->cpu_mac_interrupt_func[2]); + stat = ctcmac_regr(&priv->cpumac_reg->CpuMacInterruptFunc[0]); + mask = ctcmac_regr(&priv->cpumac_reg->CpuMacInterruptFunc[2]); if (netif_msg_intr(priv)) { netdev_dbg(priv->ndev, "normal interrupt stat 0x%x mask 0x%x\n", @@ -1270,15 +1667,50 @@ static int ctcmac_request_irq(struct ctcmac_private *priv) err = request_irq(priv->irqinfo[CTCMAC_NORMAL].irq, ctcmac_normal, 0, priv->irqinfo[CTCMAC_NORMAL].name, priv); - if (err < 0) + if (err < 0) { free_irq(priv->irqinfo[CTCMAC_NORMAL].irq, priv); - enable_irq_wake(priv->irqinfo[CTCMAC_NORMAL].irq); + } - err = request_irq(priv->irqinfo[CTCMAC_FUNC].irq, ctcmac_func, 0, - priv->irqinfo[CTCMAC_FUNC].name, priv); - if (err < 0) - free_irq(priv->irqinfo[CTCMAC_FUNC].irq, priv); - enable_irq_wake(priv->irqinfo[CTCMAC_FUNC].irq); + enable_irq_wake(priv->irqinfo[CTCMAC_NORMAL].irq); + if (priv->version == 0) { + err = + request_irq(priv->irqinfo[CTCMAC_FUNC].irq, ctcmac_func, 0, + priv->irqinfo[CTCMAC_FUNC].name, priv); + if (err < 0) { + free_irq(priv->irqinfo[CTCMAC_FUNC].irq, priv); + } + enable_irq_wake(priv->irqinfo[CTCMAC_FUNC].irq); + } else { + err = + request_irq(priv->irqinfo[CTCMAC_FUNC].irq, ctcmac_tx_isr, + 0, priv->irqinfo[CTCMAC_FUNC].name, priv); + if (err < 0) { + free_irq(priv->irqinfo[CTCMAC_FUNC].irq, priv); + } + irq_set_affinity_hint(priv->irqinfo[CTCMAC_FUNC].irq, + get_cpu_mask(0)); + enable_irq_wake(priv->irqinfo[CTCMAC_FUNC].irq); + err = + request_irq(priv->irqinfo[CTCMAC_FUNC_RX0].irq, + ctcmac_rx0_isr, 0, + priv->irqinfo[CTCMAC_FUNC_RX0].name, priv); + if (err < 0) { + free_irq(priv->irqinfo[CTCMAC_FUNC_RX0].irq, priv); + } + irq_set_affinity_hint(priv->irqinfo[CTCMAC_FUNC_RX0].irq, + get_cpu_mask(0)); + enable_irq_wake(priv->irqinfo[CTCMAC_FUNC_RX0].irq); + err = + request_irq(priv->irqinfo[CTCMAC_FUNC_RX1].irq, + ctcmac_rx1_isr, 0, + priv->irqinfo[CTCMAC_FUNC_RX1].name, priv); + if (err < 0) { + free_irq(priv->irqinfo[CTCMAC_FUNC_RX1].irq, priv); + } + irq_set_affinity_hint(priv->irqinfo[CTCMAC_FUNC_RX1].irq, + get_cpu_mask(1)); + enable_irq_wake(priv->irqinfo[CTCMAC_FUNC_RX1].irq); + } return err; } @@ -1286,7 +1718,16 @@ static int ctcmac_request_irq(struct ctcmac_private *priv) static void ctcmac_free_irq(struct ctcmac_private *priv) { free_irq(priv->irqinfo[CTCMAC_NORMAL].irq, priv); - free_irq(priv->irqinfo[CTCMAC_FUNC].irq, priv); + if (priv->version == 0) { + free_irq(priv->irqinfo[CTCMAC_FUNC].irq, priv); + } else { + irq_set_affinity_hint(priv->irqinfo[CTCMAC_FUNC].irq, NULL); + irq_set_affinity_hint(priv->irqinfo[CTCMAC_FUNC_RX0].irq, NULL); + irq_set_affinity_hint(priv->irqinfo[CTCMAC_FUNC_RX1].irq, NULL); + free_irq(priv->irqinfo[CTCMAC_FUNC].irq, priv); + free_irq(priv->irqinfo[CTCMAC_FUNC_RX0].irq, priv); + free_irq(priv->irqinfo[CTCMAC_FUNC_RX1].irq, priv); + } } static bool ctcmac_new_page(struct ctcmac_priv_rx_q *rxq, @@ -1319,7 +1760,7 @@ static void ctcmac_fill_rxbd(struct ctcmac_private *priv, u32 desc_cfg_low, desc_cfg_high; dma_addr_t bufaddr = rxb->dma + rxb->page_offset; - /* DDR base address is 0 for cpu_mac, but is 0x80000000 for CPU */ + /* DDR base address is 0 for CpuMac, but is 0x80000000 for CPU */ desc_cfg_low = (bufaddr - CTC_DDR_BASE) & CPU_MAC_DESC_INTF_W0_DESC_ADDR_31_0_MASK; /* CPU_MAC_DESC_INTF_W1_DESC_SIZE:bit(8) */ @@ -1330,19 +1771,17 @@ static void ctcmac_fill_rxbd(struct ctcmac_private *priv, spin_lock_irq(&priv->reglock); if (qidx) { - ctcmac_regw(&priv->cpumac_mem->cpu_mac_desc_intf_1[0], + ctcmac_regw(&priv->cpumac_mem->CpuMacDescIntf1[0], desc_cfg_low); - /* barrier */ smp_mb__before_atomic(); - ctcmac_regw(&priv->cpumac_mem->cpu_mac_desc_intf_1[1], + ctcmac_regw(&priv->cpumac_mem->CpuMacDescIntf1[1], desc_cfg_high); } else { - ctcmac_regw(&priv->cpumac_mem->cpu_mac_desc_intf_0[0], + ctcmac_regw(&priv->cpumac_mem->CpuMacDescIntf0[0], desc_cfg_low); - /* barrier */ smp_mb__before_atomic(); - ctcmac_regw(&priv->cpumac_mem->cpu_mac_desc_intf_0[1], + ctcmac_regw(&priv->cpumac_mem->CpuMacDescIntf0[1], desc_cfg_high); } @@ -1362,10 +1801,9 @@ static void ctcmac_fill_txbd(struct ctcmac_private *priv, (txdesc->size << 8) | (txdesc->sop << 22) | (txdesc->eop << 23); spin_lock_irq(&priv->reglock); - ctcmac_regw(&priv->cpumac_mem->cpu_mac_desc_intf_2[0], desc_cfg_low); - /* barrier */ + ctcmac_regw(&priv->cpumac_mem->CpuMacDescIntf2[0], desc_cfg_low); smp_mb__before_atomic(); - ctcmac_regw(&priv->cpumac_mem->cpu_mac_desc_intf_2[1], desc_cfg_high); + ctcmac_regw(&priv->cpumac_mem->CpuMacDescIntf2[1], desc_cfg_high); spin_unlock_irq(&priv->reglock); } @@ -1376,28 +1814,24 @@ static void ctcmac_get_txbd(struct ctcmac_private *priv) u32 lstatus; spin_lock_irq(&priv->reglock); - lstatus = ctcmac_regr(&priv->cpumac_mem->cpu_mac_desc_intf_2[0]); - /* barrier */ + lstatus = ctcmac_regr(&priv->cpumac_mem->CpuMacDescIntf2[0]); smp_mb__before_atomic(); - lstatus = ctcmac_regr(&priv->cpumac_mem->cpu_mac_desc_intf_2[1]); + lstatus = ctcmac_regr(&priv->cpumac_mem->CpuMacDescIntf2[1]); spin_unlock_irq(&priv->reglock); } /* reclaim rx desc */ -static void ctcmac_get_rxbd(struct ctcmac_private *priv, u32 *lstatus, +static void ctcmac_get_rxbd(struct ctcmac_private *priv, u32 * lstatus, int qidx) { spin_lock_irq(&priv->reglock); if (qidx) { - ctcmac_regr(&priv->cpumac_mem->cpu_mac_desc_intf_1[0]); - *lstatus = - ctcmac_regr(&priv->cpumac_mem->cpu_mac_desc_intf_1[1]); + ctcmac_regr(&priv->cpumac_mem->CpuMacDescIntf1[0]); + *lstatus = ctcmac_regr(&priv->cpumac_mem->CpuMacDescIntf1[1]); } else { - ctcmac_regr(&priv->cpumac_mem->cpu_mac_desc_intf_0[0]); - *lstatus = - ctcmac_regr(&priv->cpumac_mem->cpu_mac_desc_intf_0[1]); + ctcmac_regr(&priv->cpumac_mem->CpuMacDescIntf0[0]); + *lstatus = ctcmac_regr(&priv->cpumac_mem->CpuMacDescIntf0[1]); } - /* barrier */ smp_mb__before_atomic(); spin_unlock_irq(&priv->reglock); @@ -1420,10 +1854,12 @@ static void ctcmac_alloc_rx_buffs(struct ctcmac_priv_rx_q *rx_queue, while (alloc_cnt--) { /* if rx buffer is unmapped, alloc new pages */ if (unlikely(!rxb->page)) { - if (unlikely(!ctcmac_new_page(rx_queue, rxb))) + if (unlikely(!ctcmac_new_page(rx_queue, rxb))) { break; - if (unlikely(++j == rx_queue->rx_ring_size)) + } + if (unlikely(++j == rx_queue->rx_ring_size)) { j = 0; + } } /* fill rx desc */ @@ -1453,14 +1889,17 @@ static void ctcmac_alloc_one_rx_buffs(struct ctcmac_priv_rx_q *rx_queue) rxb = &rx_queue->rx_buff[i]; if (unlikely(!rxb->page)) { - if (unlikely(!ctcmac_new_page(rx_queue, rxb))) + if (unlikely(!ctcmac_new_page(rx_queue, rxb))) { return; - if (unlikely(++j == rx_queue->rx_ring_size)) + } + if (unlikely(++j == rx_queue->rx_ring_size)) { j = 0; + } } - if (unlikely(++i == rx_queue->rx_ring_size)) + if (unlikely(++i == rx_queue->rx_ring_size)) { i = 0; + } rx_queue->next_to_use = i; rx_queue->next_to_alloc = j; @@ -1495,9 +1934,8 @@ static noinline int ctcmac_clean_rx_ring(struct ctcmac_priv_rx_q *rx_queue, } } else { alloc_new = rx_queue->token / CTCMAC_TOKEN_PER_PKT; - if (cleaned_cnt >= CTCMAC_RX_BUFF_ALLOC && alloc_new) { - alloc_new = min_t(int, cleaned_cnt, - (int)alloc_new); + if ((cleaned_cnt >= CTCMAC_RX_BUFF_ALLOC) && alloc_new) { + alloc_new = min(cleaned_cnt, (int)alloc_new); ctcmac_alloc_rx_buffs(rx_queue, alloc_new); rx_queue->token -= CTCMAC_TOKEN_PER_PKT * alloc_new; @@ -1532,13 +1970,13 @@ static noinline int ctcmac_clean_rx_ring(struct ctcmac_priv_rx_q *rx_queue, } /* fetch next buffer if not the last in frame */ - if (!(lstatus & CPU_MAC_DESC_INTF_W1_DESC_EOP)) { + if (!(lstatus & BIT(CPU_MAC_DESC_INTF_W1_DESC_EOP_BIT))) { if (rx_queue->pps_limit) rx_queue->token += CTCMAC_TOKEN_PER_PKT; continue; } - if (unlikely(lstatus & CPU_MAC_DESC_INTF_W1_DESC_ERR)) { + if (unlikely(lstatus & BIT(CPU_MAC_DESC_INTF_W1_DESC_ERR_BIT))) { /* discard faulty buffer */ dev_kfree_skb(skb); skb = NULL; @@ -1553,8 +1991,8 @@ static noinline int ctcmac_clean_rx_ring(struct ctcmac_priv_rx_q *rx_queue, skb_record_rx_queue(skb, rx_queue->qindex); ctcmac_process_frame(ndev, skb); - if (!(ndev->flags & IFF_PROMISC) && - skb->pkt_type == PACKET_OTHERHOST) { + if ((priv->version == 0) && !(ndev->flags & IFF_PROMISC) + && (skb->pkt_type == PACKET_OTHERHOST)) { /* discard */ dev_kfree_skb(skb); skb = NULL; @@ -1565,7 +2003,10 @@ static noinline int ctcmac_clean_rx_ring(struct ctcmac_priv_rx_q *rx_queue, total_pkts++; total_bytes += skb->len + ETH_HLEN; /* Send the packet up the stack */ - napi_gro_receive(&priv->napi_rx, skb); + if (qidx == 0) + napi_gro_receive(&priv->napi_rx, skb); + else + napi_gro_receive(&priv->napi_rx1, skb); skb = NULL; } @@ -1576,19 +2017,21 @@ static noinline int ctcmac_clean_rx_ring(struct ctcmac_priv_rx_q *rx_queue, rx_queue->stats.rx_packets += total_pkts; rx_queue->stats.rx_bytes += total_bytes; - if (!rx_queue->pps_limit && cleaned_cnt) + if (!rx_queue->pps_limit && cleaned_cnt) { ctcmac_alloc_rx_buffs(rx_queue, cleaned_cnt); + } - if (rx_queue->pps_limit && rx_queue->skb) + if (rx_queue->pps_limit && rx_queue->skb) { return budget; + } return howmany; } static void ctcmac_clean_tx_ring(struct ctcmac_priv_tx_q *tx_queue) { - u16 next_to_clean; - int tqi = tx_queue->qindex; + u16 skb_dirty, desc_dirty; + int tqi = tx_queue->qindex, nr_txbds, txbd_index; struct sk_buff *skb; struct netdev_queue *txq; struct ctcmac_tx_buff *tx_buff; @@ -1596,28 +2039,47 @@ static void ctcmac_clean_tx_ring(struct ctcmac_priv_tx_q *tx_queue) struct ctcmac_private *priv = netdev_priv(dev); txq = netdev_get_tx_queue(dev, tqi); - next_to_clean = tx_queue->next_to_clean; - while (ctcmac_txbd_used_untreated(priv)) { - ctcmac_get_txbd(priv); - skb = tx_queue->tx_skbuff[next_to_clean]; + skb_dirty = tx_queue->skb_dirty; + desc_dirty = tx_queue->desc_dirty; + while ((skb = tx_queue->tx_skbuff[skb_dirty].skb)) { + if (tx_queue->tx_skbuff[skb_dirty].frag_merge == 0) { + nr_txbds = skb_shinfo(skb)->nr_frags + 1; + } else { + nr_txbds = 1; + } + + if (ctcmac_txbd_used_untreated(priv) < nr_txbds) + break; + + for (txbd_index = 0; txbd_index < nr_txbds; txbd_index++) { + ctcmac_get_txbd(priv); + tx_buff = &tx_queue->tx_buff[desc_dirty]; + dma_unmap_single(priv->dev, tx_buff->dma, tx_buff->len, + DMA_TO_DEVICE); + if (tx_buff->alloc) + kfree(tx_buff->vaddr); + + desc_dirty = + (desc_dirty >= + tx_queue->tx_ring_size - 1) ? 0 : desc_dirty + 1; + } + skb = tx_queue->tx_skbuff[skb_dirty].skb; dev_kfree_skb_any(skb); - tx_queue->tx_skbuff[next_to_clean] = NULL; - tx_buff = &tx_queue->tx_buff[next_to_clean]; - dma_unmap_single(priv->dev, tx_buff->dma, - tx_buff->len, DMA_TO_DEVICE); - if (tx_buff->alloc) - kfree(tx_buff->vaddr); + tx_queue->tx_skbuff[skb_dirty].skb = NULL; + tx_queue->tx_skbuff[skb_dirty].frag_merge = 0; + skb_dirty = + (skb_dirty >= + tx_queue->tx_ring_size - 1) ? 0 : skb_dirty + 1; if (netif_msg_tx_queued(priv)) { - netdev_dbg(priv->ndev, "%s: clean skbuff id %d\n", - priv->ndev->name, tx_queue->next_to_clean); + netdev_dbg(priv->ndev, + "%s: skb_cur %d skb_dirty %d desc_cur %d desc_dirty %d\n", + priv->ndev->name, tx_queue->skb_cur, + tx_queue->skb_dirty, tx_queue->desc_cur, + tx_queue->desc_dirty); } - if ((next_to_clean + 1) >= tx_queue->tx_ring_size) - next_to_clean = 0; - else - next_to_clean++; spin_lock(&tx_queue->txlock); - tx_queue->num_txbdfree++; + tx_queue->num_txbdfree += nr_txbds; spin_unlock(&tx_queue->txlock); } @@ -1628,7 +2090,8 @@ static void ctcmac_clean_tx_ring(struct ctcmac_priv_tx_q *tx_queue) netif_wake_subqueue(priv->ndev, tqi); } - tx_queue->next_to_clean = next_to_clean; + tx_queue->skb_dirty = skb_dirty; + tx_queue->desc_dirty = desc_dirty; } static int ctcmac_poll_rx_sq(struct napi_struct *napi, int budget) @@ -1641,7 +2104,7 @@ static int ctcmac_poll_rx_sq(struct napi_struct *napi, int budget) /* clear interrupt */ writel(CTCMAC_NOR_RX0_D | CTCMAC_NOR_RX1_D, - &priv->cpumac_reg->cpu_mac_interrupt_func[1]); + &priv->cpumac_reg->CpuMacInterruptFunc[1]); rx_work_limit = budget; rxq0 = priv->rx_queue[0]; @@ -1656,39 +2119,83 @@ static int ctcmac_poll_rx_sq(struct napi_struct *napi, int budget) rxq1->rx_trigger = 0; if (work_done < budget) { napi_complete(napi); - if (!ctcmac_rxbd_usable(priv, 0) && - !ctcmac_rxbd_recycle(priv, 0)) + if (!ctcmac_rxbd_usable(priv, 0) + && !ctcmac_rxbd_recycle(priv, 0)) rxq0->rx_trigger = 1; - if (!ctcmac_rxbd_usable(priv, 1) && - !ctcmac_rxbd_recycle(priv, 1)) + if (!ctcmac_rxbd_usable(priv, 1) + && !ctcmac_rxbd_recycle(priv, 1)) rxq1->rx_trigger = 1; spin_lock_irq(&priv->reglock); /* enable interrupt */ writel(CTCMAC_NOR_RX0_D | CTCMAC_NOR_RX1_D, - &priv->cpumac_reg->cpu_mac_interrupt_func[3]); + &priv->cpumac_reg->CpuMacInterruptFunc[3]); spin_unlock_irq(&priv->reglock); } return work_done; } -static int ctcmac_poll_tx_sq(struct napi_struct *napi, int budget) +static int ctcmac_poll_rx0_sq(struct napi_struct *napi, int budget) +{ + int work_done = 0; + struct ctcmac_private *priv = + container_of(napi, struct ctcmac_private, napi_rx); + struct ctcmac_priv_rx_q *rx_queue = NULL; + + /* clear interrupt */ + writel(CTCMAC_FUNC0_RX_D, &priv->cpumac_reg->CpuMacInterruptFunc0[1]); + rx_queue = priv->rx_queue[0]; + work_done = ctcmac_clean_rx_ring(rx_queue, budget); + + if (work_done < budget) { + napi_complete(napi); + /* enable interrupt */ + writel(CTCMAC_FUNC0_RX_D, + &priv->cpumac_reg->CpuMacInterruptFunc0[3]); + } + + return work_done; +} + +static int ctcmac_poll_rx1_sq(struct napi_struct *napi, int budget) +{ + int work_done = 0; + struct ctcmac_private *priv = + container_of(napi, struct ctcmac_private, napi_rx1); + struct ctcmac_priv_rx_q *rx_queue = NULL; + + /* clear interrupt */ + writel(CTCMAC_FUNC1_RX_D, &priv->cpumac_reg->CpuMacInterruptFunc1[1]); + rx_queue = priv->rx_queue[1]; + work_done = ctcmac_clean_rx_ring(rx_queue, budget); + + if (work_done < budget) { + napi_complete(napi); + /* enable interrupt */ + writel(CTCMAC_FUNC1_RX_D, + &priv->cpumac_reg->CpuMacInterruptFunc1[3]); + } + + return work_done; +} + +static int ctcmac_poll_tx_sq(struct napi_struct *napi, int budget) //TODO by liuht { struct ctcmac_private *priv = container_of(napi, struct ctcmac_private, napi_tx); struct ctcmac_priv_tx_q *tx_queue = priv->tx_queue[0]; /* clear interrupt */ - writel(CTCMAC_NOR_TX_D, &priv->cpumac_reg->cpu_mac_interrupt_func[1]); + writel(CTCMAC_NOR_TX_D, &priv->cpumac_reg->CpuMacInterruptFunc[1]); ctcmac_clean_tx_ring(tx_queue); napi_complete(napi); /* enable interrupt */ spin_lock_irq(&priv->reglock); - writel(CTCMAC_NOR_TX_D, &priv->cpumac_reg->cpu_mac_interrupt_func[3]); + writel(CTCMAC_NOR_TX_D, &priv->cpumac_reg->CpuMacInterruptFunc[3]); spin_unlock_irq(&priv->reglock); return 0; @@ -1706,15 +2213,16 @@ static void ctcmac_free_rx_resources(struct ctcmac_private *priv) for (j = 0; j < rx_queue->rx_ring_size; j++) { struct ctcmac_rx_buff *rxb = &rx_queue->rx_buff[j]; - if (!rxb->page) continue; dma_unmap_single(rx_queue->dev, rxb->dma, PAGE_SIZE, DMA_TO_DEVICE); __free_page(rxb->page); } - kfree(rx_queue->rx_buff); - rx_queue->rx_buff = NULL; + if (rx_queue->rx_buff) { + kfree(rx_queue->rx_buff); + rx_queue->rx_buff = NULL; + } } } @@ -1762,8 +2270,10 @@ static void ctcmac_free_tx_resources(struct ctcmac_private *priv) tx_queue = priv->tx_queue[i]; txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); - kfree(tx_queue->tx_skbuff); - tx_queue->tx_skbuff = NULL; + if (tx_queue->tx_skbuff) { + kfree(tx_queue->tx_skbuff); + tx_queue->tx_skbuff = NULL; + } } } @@ -1776,12 +2286,15 @@ static int ctcmac_init_tx_resources(struct net_device *ndev) for (i = 0; i < priv->num_tx_queues; i++) { tx_queue = priv->tx_queue[i]; tx_queue->num_txbdfree = tx_queue->tx_ring_size; - tx_queue->next_to_clean = 0; - tx_queue->next_to_alloc = 0; + tx_queue->skb_cur = 0; + tx_queue->skb_dirty = 0; + tx_queue->desc_cur = 0; + tx_queue->desc_dirty = 0; tx_queue->dev = ndev; tx_queue->tx_skbuff = kmalloc_array(tx_queue->tx_ring_size, - sizeof(*tx_queue->tx_skbuff), GFP_KERNEL); + sizeof(*tx_queue->tx_skbuff), + GFP_KERNEL | __GFP_ZERO); if (!tx_queue->tx_skbuff) goto cleanup; @@ -1816,15 +2329,22 @@ static int ctcmac_free_skb_resources(struct ctcmac_private *priv) static void cpumac_start(struct ctcmac_private *priv) { /* 1. enable rx/tx interrupt */ - writel(CTCMAC_NOR_TX_D | CTCMAC_NOR_RX0_D | CTCMAC_NOR_RX1_D, - &priv->cpumac_reg->cpu_mac_interrupt_func[3]); + if (priv->version == 0) { + writel(CTCMAC_NOR_TX_D | CTCMAC_NOR_RX0_D | CTCMAC_NOR_RX1_D, + &priv->cpumac_reg->CpuMacInterruptFunc[3]); + } else { + writel(CTCMAC_NOR_TX_D, + &priv->cpumac_reg->CpuMacInterruptFunc[3]); + writel(CTCMAC_FUNC0_RX_D, + &priv->cpumac_reg->CpuMacInterruptFunc0[3]); + writel(CTCMAC_FUNC1_RX_D, + &priv->cpumac_reg->CpuMacInterruptFunc1[3]); + } /* 2. enable rx/tx */ - clrsetbits(&priv->cpumac_reg->cpu_mac_reset, - CPU_MAC_RESET_W0_SOFT_RST_TX, - 0); - clrsetbits(&priv->cpumac_reg->cpu_mac_reset, - CPU_MAC_RESET_W0_SOFT_RST_RX, - 0); + clrsetbits(&priv->cpumac_reg->CpuMacReset, + BIT(CPU_MAC_RESET_W0_SOFT_RST_TX_BIT), 0); + clrsetbits(&priv->cpumac_reg->CpuMacReset, + BIT(CPU_MAC_RESET_W0_SOFT_RST_RX_BIT), 0); netif_trans_update(priv->ndev); /* prevent tx timeout */ } @@ -1832,13 +2352,19 @@ static void cpumac_start(struct ctcmac_private *priv) static void cpumac_halt(struct ctcmac_private *priv) { /* 1. disable rx/tx interrupt */ - ctcmac_regw(&priv->cpumac_reg->cpu_mac_interrupt_func[2], 0xffffffff); - ctcmac_regw(&priv->cpumac_reg->cpu_mac_interrupt_normal[2], 0xffffffff); + ctcmac_regw(&priv->cpumac_reg->CpuMacInterruptFunc[2], 0xffffffff); + ctcmac_regw(&priv->cpumac_reg->CpuMacInterruptNormal[2], 0xffffffff); + if (priv->version > 0) { + ctcmac_regw(&priv->cpumac_reg->CpuMacInterruptFunc0[2], + 0xffffffff); + ctcmac_regw(&priv->cpumac_reg->CpuMacInterruptFunc1[2], + 0xffffffff); + } /* 2. disable rx/tx */ - clrsetbits(&priv->cpumac_reg->cpu_mac_reset, 0, - CPU_MAC_RESET_W0_SOFT_RST_TX); - clrsetbits(&priv->cpumac_reg->cpu_mac_reset, 0, - CPU_MAC_RESET_W0_SOFT_RST_RX); + clrsetbits(&priv->cpumac_reg->CpuMacReset, 0, + BIT(CPU_MAC_RESET_W0_SOFT_RST_TX_BIT)); + clrsetbits(&priv->cpumac_reg->CpuMacReset, 0, + BIT(CPU_MAC_RESET_W0_SOFT_RST_RX_BIT)); } static void ctcmac_token_timer(struct timer_list *t) @@ -1852,31 +2378,31 @@ static void ctcmac_token_timer(struct timer_list *t) rxq0->token = min(rxq0->token + rxq0->pps_limit, rxq0->token_max); rxq1->token = min(rxq1->token + rxq1->pps_limit, rxq1->token_max); - if (rxq0->rx_trigger == 1 && (rxq0->token / CTCMAC_TOKEN_PER_PKT)) { + if ((rxq0->rx_trigger == 1) && (rxq0->token / CTCMAC_TOKEN_PER_PKT)) { rxq0->rx_trigger = 0; rxq0->token -= CTCMAC_TOKEN_PER_PKT; ctcmac_alloc_one_rx_buffs(rxq0); } - if (rxq1->rx_trigger == 1 && (rxq1->token / CTCMAC_TOKEN_PER_PKT)) { + if ((rxq1->rx_trigger == 1) && (rxq1->token / CTCMAC_TOKEN_PER_PKT)) { rxq1->rx_trigger = 0; rxq1->token -= CTCMAC_TOKEN_PER_PKT; ctcmac_alloc_one_rx_buffs(rxq1); } } -static ssize_t rxq0_pps_show(struct device *dev, - struct device_attribute *attr, char *buf) +static ssize_t ctcmac_get_rxq0_pps(struct device *dev, + struct device_attribute *attr, char *buf) { struct ctcmac_private *priv = (struct ctcmac_private *)dev_get_drvdata(dev); - return sprintf(buf, "%d\n", priv->rx_queue[0]->pps_limit); + return sprintf(buf, "%d\n", priv->rx_queue[0]->pps_limit);; } -static ssize_t rxq0_pps_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) +static ssize_t ctcmac_set_rxq0_pps(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) { u32 rq0_pps; struct ctcmac_private *priv = @@ -1891,18 +2417,18 @@ static ssize_t rxq0_pps_store(struct device *dev, return count; } -static ssize_t rxq1_pps_show(struct device *dev, - struct device_attribute *attr, char *buf) +static ssize_t ctcmac_get_rxq1_pps(struct device *dev, + struct device_attribute *attr, char *buf) { struct ctcmac_private *priv = (struct ctcmac_private *)dev_get_drvdata(dev); - return sprintf(buf, "%d\n", priv->rx_queue[1]->pps_limit); + return sprintf(buf, "%d\n", priv->rx_queue[1]->pps_limit);; } -static ssize_t rxq1_pps_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) +static ssize_t ctcmac_set_rxq1_pps(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) { u32 rq1_pps; struct ctcmac_private *priv = @@ -1917,8 +2443,10 @@ static ssize_t rxq1_pps_store(struct device *dev, return count; } -static DEVICE_ATTR(rxq0_pps, S_IRUGO | S_IWUSR, rxq0_pps_show, rxq0_pps_store); -static DEVICE_ATTR(rxq1_pps, S_IRUGO | S_IWUSR, rxq1_pps_show, rxq1_pps_store); +static DEVICE_ATTR(rxq0_pps, S_IRUGO | S_IWUSR, ctcmac_get_rxq0_pps, + ctcmac_set_rxq0_pps); +static DEVICE_ATTR(rxq1_pps, S_IRUGO | S_IWUSR, ctcmac_get_rxq1_pps, + ctcmac_set_rxq1_pps); static void ctcmac_pps_init(struct ctcmac_private *priv) { @@ -1966,8 +2494,6 @@ static void ctcmac_pps_cfg(struct ctcmac_private *priv) add_timer(&priv->token_timer); /* when enable pps ratelimit, must use desc done interrupt */ priv->int_type = CTCMAC_INT_DESC; - } else { - priv->int_type = CTCMAC_INT_PACKET; } } @@ -1979,77 +2505,226 @@ static int ctcmac_enet_open(struct net_device *dev) ctcmac_pps_cfg(priv); err = ctcmac_init_phy(dev); - if (err) + if (err) { return err; + } err = ctcmac_request_irq(priv); - if (err) + if (err) { return err; + } err = startup_ctcmac(dev); - if (err) + if (err) { return err; + } return 0; } -static struct ctcmac_tx_buff *skb_to_txbuff(struct ctcmac_private *priv, - struct sk_buff *skb) +static void head_to_txbuff_direct(struct device *dev, struct sk_buff *skb, + struct ctcmac_tx_buff *tx_buff) +{ + tx_buff->alloc = 0; + tx_buff->vaddr = skb->data; + tx_buff->len = skb_headlen(skb); + tx_buff->dma = dma_map_single(dev, skb->data, skb_headlen(skb), + DMA_TO_DEVICE); + tx_buff->offset = 0; +} + +static void frag_to_txbuff_direct(struct device *dev, skb_frag_t * frag, + struct ctcmac_tx_buff *tx_buff) +{ + tx_buff->alloc = 0; + tx_buff->vaddr = skb_frag_address(frag); + tx_buff->len = skb_frag_size(frag); + tx_buff->dma = + dma_map_single(dev, tx_buff->vaddr, tx_buff->len, DMA_TO_DEVICE); + tx_buff->offset = 0; +} + +static void head_to_txbuff_alloc(struct device *dev, struct sk_buff *skb, + struct ctcmac_tx_buff *tx_buff) { - u64 addr, offset; - int frag_index, nr_frags, rq; + u64 offset; + int alloc_size; + + alloc_size = ALIGN(skb->len, BUF_ALIGNMENT); + tx_buff->alloc = 1; + tx_buff->len = skb->len; + tx_buff->vaddr = kmalloc(alloc_size, GFP_KERNEL); + offset = + (BUF_ALIGNMENT - (((u64) tx_buff->vaddr) & (BUF_ALIGNMENT - 1))); + if (offset == BUF_ALIGNMENT) { + offset = 0; + } + tx_buff->offset = offset; + memcpy(tx_buff->vaddr + offset, skb->data, skb_headlen(skb)); + tx_buff->dma = dma_map_single(dev, tx_buff->vaddr, tx_buff->len, + DMA_TO_DEVICE); +} + +static void frag_to_txbuff_alloc(struct device *dev, skb_frag_t * frag, + struct ctcmac_tx_buff *tx_buff) +{ + u64 offset; + int alloc_size; + + alloc_size = ALIGN(skb_frag_size(frag), BUF_ALIGNMENT); + tx_buff->alloc = 1; + tx_buff->len = skb_frag_size(frag); + tx_buff->vaddr = kmalloc(alloc_size, GFP_KERNEL); + offset = + (BUF_ALIGNMENT - (((u64) tx_buff->vaddr) & (BUF_ALIGNMENT - 1))); + if (offset == BUF_ALIGNMENT) { + offset = 0; + } + tx_buff->offset = offset; + memcpy(tx_buff->vaddr + offset, skb_frag_address(frag), + skb_frag_size(frag)); + tx_buff->dma = + dma_map_single(dev, tx_buff->vaddr, tx_buff->len, DMA_TO_DEVICE); +} + +static void skb_to_txbuff_alloc(struct device *dev, struct sk_buff *skb, + struct ctcmac_tx_buff *tx_buff) +{ + u64 offset; + int alloc_size, frag_index; + skb_frag_t *frag; + + alloc_size = ALIGN(skb->len, BUF_ALIGNMENT); + tx_buff->alloc = 1; + tx_buff->len = skb->len; + tx_buff->vaddr = kmalloc(alloc_size, GFP_KERNEL); + offset = + (BUF_ALIGNMENT - (((u64) tx_buff->vaddr) & (BUF_ALIGNMENT - 1))); + if (offset == BUF_ALIGNMENT) { + offset = 0; + } + tx_buff->offset = offset; + memcpy(tx_buff->vaddr + offset, skb->data, skb_headlen(skb)); + offset += skb_headlen(skb); + for (frag_index = 0; frag_index < skb_shinfo(skb)->nr_frags; + frag_index++) { + frag = &skb_shinfo(skb)->frags[frag_index]; + memcpy(tx_buff->vaddr + offset, skb_frag_address(frag), + skb_frag_size(frag)); + offset += skb_frag_size(frag); + } + tx_buff->dma = + dma_map_single(dev, tx_buff->vaddr, tx_buff->len, DMA_TO_DEVICE); +} + +static int skb_to_txbuff(struct ctcmac_private *priv, struct sk_buff *skb) +{ + u64 addr; + int frag_index, rq, to_use, nr_frags; skb_frag_t *frag; struct ctcmac_tx_buff *tx_buff; struct ctcmac_priv_tx_q *tx_queue = NULL; + bool addr_align256, not_span_4K, len_align8 = 1; - nr_frags = skb_shinfo(skb)->nr_frags; rq = skb->queue_mapping; tx_queue = priv->tx_queue[rq]; + to_use = tx_queue->desc_cur; + tx_buff = &tx_queue->tx_buff[to_use]; + nr_frags = skb_shinfo(skb)->nr_frags; - tx_buff = &tx_queue->tx_buff[tx_queue->next_to_alloc]; - addr = (u64)skb->data; - if (!nr_frags && - ((addr & PAGE_MASK) == ((addr + skb_headlen(skb)) & PAGE_MASK))) { - tx_buff->alloc = 0; - tx_buff->vaddr = skb->data; - tx_buff->len = skb_headlen(skb); - tx_buff->dma = - dma_map_single(priv->dev, skb->data, skb_headlen(skb), - DMA_TO_DEVICE); - tx_buff->offset = 0; - - } else { - int alloc_size; - - alloc_size = ALIGN(skb->len, BUF_ALIGNMENT); - tx_buff->alloc = 1; - tx_buff->len = skb->len; - tx_buff->vaddr = kmalloc(alloc_size, GFP_KERNEL); - offset = - (BUF_ALIGNMENT - - (((u64)tx_buff->vaddr) & (BUF_ALIGNMENT - 1))); - if (offset == BUF_ALIGNMENT) - offset = 0; - tx_buff->offset = offset; - memcpy(tx_buff->vaddr + offset, skb->data, skb_headlen(skb)); - offset += skb_headlen(skb); + if (priv->version) { + head_to_txbuff_direct(priv->dev, skb, tx_buff); + to_use = + (to_use >= tx_queue->tx_ring_size - 1) ? 0 : to_use + 1; + //printk(KERN_ERR "skb_to_txbuff0 %llx %d %d\n", (u64)skb->data, skb_headlen(skb), to_use); for (frag_index = 0; frag_index < nr_frags; frag_index++) { + tx_buff = &tx_queue->tx_buff[to_use]; frag = &skb_shinfo(skb)->frags[frag_index]; - memcpy(tx_buff->vaddr + offset, frag, - skb_frag_size(frag)); - offset += skb_frag_size(frag); + frag_to_txbuff_direct(priv->dev, frag, tx_buff); + to_use = + to_use >= + tx_queue->tx_ring_size - 1 ? 0 : to_use + 1; + //printk(KERN_ERR "skb_to_txbuff1 %llx %d %d %d\n", + // (u64)skb_frag_address(frag), skb_frag_size(frag), to_use, frag_index); + } + } else { + if (skb_shinfo(skb)->nr_frags) { + if (skb_headlen(skb) & 0x7) { + len_align8 = 0; + } + for (frag_index = 0; (len_align8 == 1) && + (frag_index < nr_frags - 1); frag_index++) { + frag = &skb_shinfo(skb)->frags[frag_index]; + if (skb_frag_size(frag) & 0x7) + len_align8 = 0; + } } - tx_buff->dma = - dma_map_single(priv->dev, tx_buff->vaddr, tx_buff->len, - DMA_TO_DEVICE); + if (len_align8 == 0) { + //printk(KERN_ERR "skb_to_txbuff2 %llx %d %d\n", (u64)skb->data, skb_headlen(skb), to_use); + for (frag_index = 0; frag_index < nr_frags; + frag_index++) { + frag = &skb_shinfo(skb)->frags[frag_index]; + //printk(KERN_ERR "skb_to_txbuff3 %llx %d %d %d\n", (u64)skb_frag_address(frag), skb_frag_size(frag), to_use, frag_index); + } + skb_to_txbuff_alloc(priv->dev, skb, tx_buff); + to_use = + (to_use >= + tx_queue->tx_ring_size - 1) ? 0 : to_use + 1; + } else { + addr = (u64) skb->data; + addr_align256 = + ((addr & (BUF_ALIGNMENT - 1)) == 0) ? 1 : 0; + not_span_4K = + ((addr & PAGE_MASK) == + ((addr + skb_headlen(skb)) & PAGE_MASK)) ? 1 : 0; + if (addr_align256 || not_span_4K) { + head_to_txbuff_direct(priv->dev, skb, tx_buff); + //printk(KERN_ERR "skb_to_txbuff4 %llx %d %d\n", (u64)skb->data, skb_headlen(skb), to_use); + } else { + head_to_txbuff_alloc(priv->dev, skb, tx_buff); + //printk(KERN_ERR "skb_to_txbuff5 %llx %d %d\n", (u64)skb->data, skb_headlen(skb), to_use); + } + to_use = + (to_use >= + tx_queue->tx_ring_size - 1) ? 0 : to_use + 1; + for (frag_index = 0; frag_index < nr_frags; + frag_index++) { + tx_buff = &tx_queue->tx_buff[to_use]; + frag = &skb_shinfo(skb)->frags[frag_index]; + addr = (u64) skb_frag_address(frag); + + addr_align256 = + ((addr & (BUF_ALIGNMENT - 1)) == 0) ? 1 : 0; + not_span_4K = + ((addr & PAGE_MASK) == + ((addr + + skb_frag_size(frag)) & PAGE_MASK)) ? 1 : + 0; + if (addr_align256 || not_span_4K) { + frag_to_txbuff_direct(priv->dev, frag, + tx_buff); + //printk(KERN_ERR "skb_to_txbuff6 %llx %d %d %d\n", (u64)skb_frag_address(frag), skb_frag_size(frag), to_use, frag_index); + } else { + frag_to_txbuff_alloc(priv->dev, frag, + tx_buff); + //printk(KERN_ERR "skb_to_txbuff7 %llx %d %d %d\n", (u64)skb_frag_address(frag), skb_frag_size(frag), to_use, frag_index); + } + to_use = + to_use >= + tx_queue->tx_ring_size - 1 ? 0 : to_use + 1; + } + } } - return tx_buff; + + return len_align8 ? 0 : 1; } static int ctcmac_start_xmit(struct sk_buff *skb, struct net_device *dev) { int rq = 0; + int to_use = 0, frag_merged; + unsigned int frag_index, nr_txbds; unsigned int bytes_sent; struct netdev_queue *txq; struct ctcmac_desc_cfg tx_desc; @@ -2061,8 +2736,9 @@ static int ctcmac_start_xmit(struct sk_buff *skb, struct net_device *dev) tx_queue = priv->tx_queue[rq]; txq = netdev_get_tx_queue(dev, rq); + nr_txbds = skb_shinfo(skb)->nr_frags + 1; /* check if there is space to queue this packet */ - if (tx_queue->num_txbdfree <= 0) { + if (tx_queue->num_txbdfree < nr_txbds) { if (netif_msg_tx_err(priv)) { netdev_dbg(priv->ndev, "%s: no space left before send pkt!\n", @@ -2079,28 +2755,59 @@ static int ctcmac_start_xmit(struct sk_buff *skb, struct net_device *dev) tx_queue->stats.tx_bytes += bytes_sent; tx_queue->stats.tx_packets++; - tx_buff = skb_to_txbuff(priv, skb); - tx_queue->tx_skbuff[tx_queue->next_to_alloc] = skb; - tx_desc.sop = 1; - tx_desc.eop = 1; - tx_desc.size = tx_buff->len; - tx_desc.addr_low = (tx_buff->dma + tx_buff->offset - CTC_DDR_BASE) - & CPU_MAC_DESC_INTF_W0_DESC_ADDR_31_0_MASK; - tx_desc.addr_high = - ((tx_buff->dma + tx_buff->offset - CTC_DDR_BASE) >> 32) - & CPU_MAC_DESC_INTF_W1_DESC_ADDR_39_32_MASK; - ctcmac_fill_txbd(priv, &tx_desc); + frag_merged = skb_to_txbuff(priv, skb); + tx_queue->tx_skbuff[tx_queue->skb_cur].skb = skb; + tx_queue->tx_skbuff[tx_queue->skb_cur].frag_merge = frag_merged; + tx_queue->skb_cur = + (tx_queue->skb_cur >= + tx_queue->tx_ring_size - 1) ? 0 : tx_queue->skb_cur + 1; + if (frag_merged) { + nr_txbds = 1; + } + to_use = tx_queue->desc_cur; + if (nr_txbds <= 1) { + tx_buff = &tx_queue->tx_buff[to_use]; + tx_desc.sop = 1; + tx_desc.eop = 1; + tx_desc.size = tx_buff->len; + tx_desc.addr_low = + (tx_buff->dma + tx_buff->offset - CTC_DDR_BASE) + & CPU_MAC_DESC_INTF_W0_DESC_ADDR_31_0_MASK; + tx_desc.addr_high = + ((tx_buff->dma + tx_buff->offset - CTC_DDR_BASE) >> 32) + & CPU_MAC_DESC_INTF_W1_DESC_ADDR_39_32_MASK; + ctcmac_fill_txbd(priv, &tx_desc); + to_use = + (to_use >= tx_queue->tx_ring_size - 1) ? 0 : to_use + 1; + } else { + for (frag_index = 0; frag_index < nr_txbds; frag_index++) { + tx_buff = &tx_queue->tx_buff[to_use]; + tx_desc.sop = (frag_index == 0) ? 1 : 0; + tx_desc.eop = (frag_index == nr_txbds - 1) ? 1 : 0; + tx_desc.size = tx_buff->len; + tx_desc.addr_low = + (tx_buff->dma + tx_buff->offset - CTC_DDR_BASE) + & CPU_MAC_DESC_INTF_W0_DESC_ADDR_31_0_MASK; + tx_desc.addr_high = + ((tx_buff->dma + tx_buff->offset - + CTC_DDR_BASE) >> 32) + & CPU_MAC_DESC_INTF_W1_DESC_ADDR_39_32_MASK; + ctcmac_fill_txbd(priv, &tx_desc); + to_use = + (to_use >= + tx_queue->tx_ring_size - 1) ? 0 : to_use + 1; + } + } + tx_queue->desc_cur = to_use; if (netif_msg_tx_queued(priv)) { - netdev_dbg(priv->ndev, "%s: alloc skbuff id %d\n", - priv->ndev->name, tx_queue->next_to_alloc); + netdev_dbg(priv->ndev, + "%s: skb_cur %d skb_dirty %d desc_cur %d desc_dirty %d\n", + priv->ndev->name, tx_queue->skb_cur, + tx_queue->skb_dirty, tx_queue->desc_cur, + tx_queue->desc_dirty); } - if (tx_queue->next_to_alloc >= tx_queue->tx_ring_size - 1) - tx_queue->next_to_alloc = 0; - else - tx_queue->next_to_alloc++; - /* We can work in parallel with 872(), except * when modifying num_txbdfree. Note that we didn't grab the lock * when we were reading the num_txbdfree and checking for available @@ -2108,7 +2815,7 @@ static int ctcmac_start_xmit(struct sk_buff *skb, struct net_device *dev) */ spin_lock_bh(&tx_queue->txlock); /* reduce TxBD free count */ - tx_queue->num_txbdfree--; + tx_queue->num_txbdfree -= nr_txbds; spin_unlock_bh(&tx_queue->txlock); /* If the next BD still needs to be cleaned up, then the bds @@ -2117,8 +2824,9 @@ static int ctcmac_start_xmit(struct sk_buff *skb, struct net_device *dev) if (!tx_queue->num_txbdfree) { netif_tx_stop_queue(txq); if (netif_msg_tx_err(priv)) { - netdev_dbg(dev, "%s: no space left before send pkt!\n", - priv->ndev->name); + printk(KERN_ERR + "%s: no space left before send pkt22!\n", + priv->ndev->name); } dev->stats.tx_fifo_errors++; } @@ -2131,8 +2839,9 @@ static int ctcmac_change_mtu(struct net_device *dev, int new_mtu) struct ctcmac_private *priv = netdev_priv(dev); int frame_size = new_mtu + ETH_HLEN; - if (frame_size < 64 || frame_size > CTCMAC_JUMBO_FRAME_SIZE) + if ((frame_size < 64) || (frame_size > CTCMAC_JUMBO_FRAME_SIZE)) { return -EINVAL; + } while (test_and_set_bit_lock(CTCMAC_RESETTING, &priv->state)) cpu_relax(); @@ -2175,9 +2884,136 @@ static int ctcmac_close(struct net_device *dev) static void ctcmac_set_multi(struct net_device *dev) { + int idx = 0; + u32 val, addr_h = 0, addr_l = 0; + struct netdev_hw_addr *ha; + struct ctcmac_private *priv = netdev_priv(dev); + + if (priv->version == 0) + return; + + /* receive all packets */ + if (dev->flags & IFF_PROMISC) { + /* not check normal packet */ + if (priv->index == 0) { + val = + readl(&priv->cpumacu_reg->CpuMacUnitFilterCfg1[1]); + val &= + ~BIT + (CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_CHECK_NORMAL_PKT_ENABLE0_BIT); + writel(val, + &priv->cpumacu_reg->CpuMacUnitFilterCfg1[1]); + } else { + val = + readl(&priv->cpumacu_reg->CpuMacUnitFilterCfg1[1]); + val &= + ~BIT + (CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_CHECK_NORMAL_PKT_ENABLE1_BIT); + writel(val, + &priv->cpumacu_reg->CpuMacUnitFilterCfg1[1]); + } + return; + } + + if (priv->index == 0) { + val = readl(&priv->cpumacu_reg->CpuMacUnitFilterCfg1[1]); + val |= + BIT + (CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_CHECK_NORMAL_PKT_ENABLE0_BIT); + val |= + BIT(CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_DROP_NORMAL_PKT0_BIT); + writel(val, &priv->cpumacu_reg->CpuMacUnitFilterCfg1[1]); + } else { + val = readl(&priv->cpumacu_reg->CpuMacUnitFilterCfg1[1]); + val |= + BIT + (CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_CHECK_NORMAL_PKT_ENABLE1_BIT); + val |= + BIT(CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_DROP_NORMAL_PKT1_BIT); + writel(val, &priv->cpumacu_reg->CpuMacUnitFilterCfg1[1]); + } + + /* receive packets with local mac address + receive packets with broadcast mac address + receive packets with multicast mac address + */ + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 2)) { + /* mac filter table 2/6:white list to receive all pacekt with multicast mac address */ + if (priv->index == 0) { + writel(0x00000000, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[4]); + writel(0x00000100, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[5]); + writel(0x00000000, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[20]); + writel(0x00000100, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[21]); + } else { + writel(0x00000000, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[12]); + writel(0x00000100, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[13]); + writel(0x00000000, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[28]); + writel(0x00000100, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[29]); + } + return; + } + + if (netdev_mc_empty(dev)) { + return; + } + /* receive packet with local mac address */ + /* receive packet with broadcast mac address */ + /* receive packet with multicast mac address in mc list */ + netdev_for_each_mc_addr(ha, dev) { + addr_h = ha->addr[0] << 8 | ha->addr[1]; + addr_l = + ha->addr[2] << 24 | ha->addr[3] << 16 | ha-> + addr[4] << 8 | ha->addr[5]; + if (priv->index == 0) { + writel(addr_l, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[4 + + idx * + 2]); + writel(addr_h, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[5 + + idx * + 2]); + writel(0xffffffff, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[20 + + idx * + 2]); + writel(0x0000ffff, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[21 + + idx * + 2]); + } else { + writel(addr_l, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[12 + + idx * + 2]); + writel(addr_h, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[13 + + idx * + 2]); + writel(0xffffffff, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[28 + + idx * + 2]); + writel(0x0000ffff, + &priv->cpumacu_reg->CpuMacUnitMacCamCfg[29 + + idx * + 2]); + } + idx++; + if (idx >= 2) + return; + } } -static void ctcmac_timeout(struct net_device *dev) +static void ctcmac_timeout(struct net_device *dev, unsigned int txqueue) { struct ctcmac_private *priv = netdev_priv(dev); @@ -2206,15 +3042,17 @@ static struct net_device_stats *ctcmac_get_stats(struct net_device *dev) struct ctcmac_private *priv = netdev_priv(dev); for (qidx = 0; qidx < priv->num_rx_queues; qidx++) { - if (!priv->rx_queue[qidx]) + if (!priv->rx_queue[qidx]) { return &dev->stats; + } rx_packets += priv->rx_queue[qidx]->stats.rx_packets; rx_bytes += priv->rx_queue[qidx]->stats.rx_bytes; rx_dropped += priv->rx_queue[qidx]->stats.rx_dropped; } - if (!priv->tx_queue[0]) + if (!priv->tx_queue[0]) { return &dev->stats; + } tx_packets = priv->tx_queue[0]->stats.tx_packets; tx_bytes = priv->tx_queue[0]->stats.tx_bytes; @@ -2228,9 +3066,52 @@ static struct net_device_stats *ctcmac_get_stats(struct net_device *dev) return &dev->stats; } +static void ctcmac_set_mac_for_addr(struct ctcmac_private *priv, + const u8 * addr) +{ + u32 addr_h = 0, addr_l = 0; + + addr_h = addr[0] << 8 | addr[1]; + addr_l = addr[2] << 24 | addr[3] << 16 | addr[4] << 8 | addr[5]; + if (priv->index == 0) { + writel(addr_l, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[0]); + writel(addr_h, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[1]); + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[16]); + writel(0x0000ffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[17]); + } else { + writel(addr_l, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[8]); + writel(addr_h, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[9]); + writel(0xffffffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[24]); + writel(0x0000ffff, &priv->cpumacu_reg->CpuMacUnitMacCamCfg[25]); + } +} + +static void ctcmac_set_src_mac_for_flow_ctrl(struct ctcmac_private *priv, + const u8 * addr) +{ + u32 val; + u32 addr_h = 0, addr_l = 0; + + addr_h = addr[0] << 8 | addr[1]; + addr_l = addr[2] << 24 | addr[3] << 16 | addr[4] << 8 | addr[5]; + + writel(addr_l, &priv->cpumac_reg->CpuMacPauseCfg[2]); + val = readl(&priv->cpumac_reg->CpuMacPauseCfg[3]); + val &= 0xffff0000; + addr_h &= 0xffff; + val |= addr_h; + writel(val, &priv->cpumac_reg->CpuMacPauseCfg[3]); +} + static int ctcmac_set_mac_addr(struct net_device *dev, void *p) { + struct ctcmac_private *priv = netdev_priv(dev); + eth_mac_addr(dev, p); + ctcmac_set_src_mac_for_flow_ctrl(priv, dev->dev_addr); + if (priv->version > 0) + ctcmac_set_mac_for_addr(priv, dev->dev_addr); + return 0; } @@ -2246,7 +3127,7 @@ static void ctcmac_gdrvinfo(struct net_device *dev, /* Return the length of the register structure */ static int ctcmac_reglen(struct net_device *dev) { - return sizeof(struct cpu_mac_regs); + return sizeof(struct CpuMac_regs); } /* Return a dump of the GFAR register space */ @@ -2255,17 +3136,16 @@ static void ctcmac_get_regs(struct net_device *dev, struct ethtool_regs *regs, { int i; struct ctcmac_private *priv = netdev_priv(dev); - u32 __iomem *theregs = (u32 __iomem *)priv->cpumac_reg; - u32 *buf = (u32 *)regbuf; + u32 __iomem *theregs = (u32 __iomem *) priv->cpumac_reg; + u32 *buf = (u32 *) regbuf; - for (i = 0; i < sizeof(struct cpu_mac_regs) / sizeof(u32); i++) + for (i = 0; i < sizeof(struct CpuMac_regs) / sizeof(u32); i++) buf[i] = ctcmac_regr(&theregs[i]); } /* Fills in rvals with the current ring parameters. Currently, * rx, rx_mini, and rx_jumbo rings are the same size, as mini and - * jumbo are ignored by the driver - */ + * jumbo are ignored by the driver */ static void ctcmac_gringparam(struct net_device *dev, struct ethtool_ringparam *rvals) { @@ -2330,15 +3210,64 @@ static int ctcmac_sringparam(struct net_device *dev, static void ctcmac_gpauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) { -} + struct ctcmac_private *priv = netdev_priv(dev); + epause->autoneg = ! !priv->pause_aneg_en; + epause->rx_pause = ! !priv->rx_pause_en; + epause->tx_pause = ! !priv->tx_pause_en; +} + +/* +* IEEE 802.3-2000 +* Table 28B-2 +* Pause Encoding +* +* PAUSE ASM_DIR TX RX +* ----- ----- -- -- +* 0 0 0 0 +* 0 1 1 0 +* 1 0 1 1 +* 1 1 0 1 +* +*/ static int ctcmac_spauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) { + struct ctcmac_private *priv = netdev_priv(dev); + struct phy_device *phydev = dev->phydev; + + if (!phydev) + return -ENODEV; + + if (!phy_validate_pause(phydev, epause)) + return -EINVAL; + + priv->rx_pause_en = priv->tx_pause_en = 0; + if (epause->rx_pause) { + priv->rx_pause_en = 1; + + if (epause->tx_pause) { + priv->tx_pause_en = 1; + } + } else if (epause->tx_pause) { + priv->tx_pause_en = 1; + + } + + if (epause->autoneg) + priv->pause_aneg_en = 1; + else + priv->pause_aneg_en = 0; + + if (!epause->autoneg) { + ctcmac_cfg_flow_ctrl(priv, priv->tx_pause_en, + priv->rx_pause_en); + } + return 0; } -static void ctcmac_gstrings(struct net_device *dev, u32 stringset, u8 *buf) +static void ctcmac_gstrings(struct net_device *dev, u32 stringset, u8 * buf) { memcpy(buf, ctc_stat_gstrings, CTCMAC_STATS_LEN * ETH_GSTRING_LEN); } @@ -2349,7 +3278,7 @@ static int ctcmac_sset_count(struct net_device *dev, int sset) } static void ctcmac_fill_stats(struct net_device *netdev, - struct ethtool_stats *dummy, u64 *buf) + struct ethtool_stats *dummy, u64 * buf) { u32 mtu; unsigned long flags; @@ -2359,150 +3288,105 @@ static void ctcmac_fill_stats(struct net_device *netdev, spin_lock_irqsave(&priv->reglock, flags); stats = &g_pkt_stats[priv->index]; stats->rx_good_ucast_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_0[0]); + readq(&priv->cpumac_mem->CpuMacStatsRam0[0]); stats->rx_good_ucast_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_0[2]); + readq(&priv->cpumac_mem->CpuMacStatsRam0[2]); stats->rx_good_mcast_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_1[0]); + readq(&priv->cpumac_mem->CpuMacStatsRam1[0]); stats->rx_good_mcast_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_1[2]); + readq(&priv->cpumac_mem->CpuMacStatsRam1[2]); stats->rx_good_bcast_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_2[0]); + readq(&priv->cpumac_mem->CpuMacStatsRam2[0]); stats->rx_good_bcast_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_2[2]); + readq(&priv->cpumac_mem->CpuMacStatsRam2[2]); stats->rx_good_pause_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_3[0]); + readq(&priv->cpumac_mem->CpuMacStatsRam3[0]); stats->rx_good_pause_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_3[2]); + readq(&priv->cpumac_mem->CpuMacStatsRam3[2]); stats->rx_good_pfc_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_4[0]); - stats->rx_good_pfc_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_4[2]); + readq(&priv->cpumac_mem->CpuMacStatsRam4[0]); + stats->rx_good_pfc_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam4[2]); stats->rx_good_control_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_5[0]); + readq(&priv->cpumac_mem->CpuMacStatsRam5[0]); stats->rx_good_control_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_5[2]); + readq(&priv->cpumac_mem->CpuMacStatsRam5[2]); stats->rx_fcs_error_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_6[0]); - stats->rx_fcs_error_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_6[2]); + readq(&priv->cpumac_mem->CpuMacStatsRam6[0]); + stats->rx_fcs_error_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam6[2]); stats->rx_mac_overrun_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_7[0]); + readq(&priv->cpumac_mem->CpuMacStatsRam7[0]); stats->rx_mac_overrun_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_7[2]); + readq(&priv->cpumac_mem->CpuMacStatsRam7[2]); stats->rx_good_63B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_8[0]); - stats->rx_good_63B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_8[2]); - stats->rx_bad_63B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_9[0]); - stats->rx_bad_63B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_9[2]); + readq(&priv->cpumac_mem->CpuMacStatsRam8[0]); + stats->rx_good_63B_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam8[2]); + stats->rx_bad_63B_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam9[0]); + stats->rx_bad_63B_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam9[2]); stats->rx_good_mtu2B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_10[0]); + readq(&priv->cpumac_mem->CpuMacStatsRam10[0]); stats->rx_good_mtu2B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_10[2]); + readq(&priv->cpumac_mem->CpuMacStatsRam10[2]); stats->rx_bad_mtu2B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_11[0]); + readq(&priv->cpumac_mem->CpuMacStatsRam11[0]); stats->rx_bad_mtu2B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_11[2]); + readq(&priv->cpumac_mem->CpuMacStatsRam11[2]); stats->rx_good_jumbo_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_12[0]); + readq(&priv->cpumac_mem->CpuMacStatsRam12[0]); stats->rx_good_jumbo_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_12[2]); + readq(&priv->cpumac_mem->CpuMacStatsRam12[2]); stats->rx_bad_jumbo_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_13[0]); + readq(&priv->cpumac_mem->CpuMacStatsRam13[0]); stats->rx_bad_jumbo_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_13[2]); - stats->rx_64B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_14[0]); - stats->rx_64B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_14[2]); - stats->rx_127B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_15[0]); - stats->rx_127B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_15[2]); - stats->rx_255B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_16[0]); - stats->rx_255B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_16[2]); - stats->rx_511B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_17[0]); - stats->rx_511B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_17[2]); - stats->rx_1023B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_18[0]); - stats->rx_1023B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_18[2]); - stats->rx_mtu1B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_19[0]); - stats->rx_mtu1B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_19[2]); - stats->tx_ucast_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_20[0]); - stats->tx_ucast_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_20[2]); - stats->tx_mcast_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_21[0]); - stats->tx_mcast_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_21[2]); - stats->tx_bcast_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_22[0]); - stats->tx_bcast_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_22[2]); - stats->tx_pause_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_23[0]); - stats->tx_pause_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_23[2]); + readq(&priv->cpumac_mem->CpuMacStatsRam13[2]); + stats->rx_64B_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam14[0]); + stats->rx_64B_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam14[2]); + stats->rx_127B_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam15[0]); + stats->rx_127B_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam15[2]); + stats->rx_255B_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam16[0]); + stats->rx_255B_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam16[2]); + stats->rx_511B_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam17[0]); + stats->rx_511B_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam17[2]); + stats->rx_1023B_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam18[0]); + stats->rx_1023B_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam18[2]); + stats->rx_mtu1B_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam19[0]); + stats->rx_mtu1B_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam19[2]); + stats->tx_ucast_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam20[0]); + stats->tx_ucast_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam20[2]); + stats->tx_mcast_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam21[0]); + stats->tx_mcast_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam21[2]); + stats->tx_bcast_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam22[0]); + stats->tx_bcast_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam22[2]); + stats->tx_pause_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam23[0]); + stats->tx_pause_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam23[2]); stats->tx_control_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_24[0]); - stats->tx_control_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_24[2]); + readq(&priv->cpumac_mem->CpuMacStatsRam24[0]); + stats->tx_control_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam24[2]); stats->tx_fcs_error_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_25[0]); + readq(&priv->cpumac_mem->CpuMacStatsRam25[0]); stats->tx_fcs_error_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_25[2]); + readq(&priv->cpumac_mem->CpuMacStatsRam25[2]); stats->tx_underrun_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_26[0]); - stats->tx_underrun_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_26[2]); - stats->tx_63B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_27[0]); - stats->tx_63B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_27[2]); - stats->tx_64B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_28[0]); - stats->tx_64B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_28[2]); - stats->tx_127B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_29[0]); - stats->tx_127B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_29[2]); - stats->tx_255B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_30[0]); - stats->tx_255B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_30[2]); - stats->tx_511B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_31[0]); - stats->tx_511B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_31[2]); - stats->tx_1023B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_32[0]); - stats->tx_1023B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_32[2]); - stats->tx_mtu1_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_33[0]); - stats->tx_mtu1_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_33[2]); - stats->tx_mtu2_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_34[0]); - stats->tx_mtu2_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_34[2]); - stats->tx_jumbo_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_35[0]); - stats->tx_jumbo_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_35[2]); - mtu = readl(&priv->cpumac_reg->cpu_mac_stats_cfg[1]); + readq(&priv->cpumac_mem->CpuMacStatsRam26[0]); + stats->tx_underrun_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam26[2]); + stats->tx_63B_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam27[0]); + stats->tx_63B_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam27[2]); + stats->tx_64B_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam28[0]); + stats->tx_64B_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam28[2]); + stats->tx_127B_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam29[0]); + stats->tx_127B_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam29[2]); + stats->tx_255B_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam30[0]); + stats->tx_255B_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam30[2]); + stats->tx_511B_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam31[0]); + stats->tx_511B_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam31[2]); + stats->tx_1023B_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam32[0]); + stats->tx_1023B_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam32[2]); + stats->tx_mtu1_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam33[0]); + stats->tx_mtu1_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam33[2]); + stats->tx_mtu2_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam34[0]); + stats->tx_mtu2_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam34[2]); + stats->tx_jumbo_bytes += readq(&priv->cpumac_mem->CpuMacStatsRam35[0]); + stats->tx_jumbo_pkt += readq(&priv->cpumac_mem->CpuMacStatsRam35[2]); + mtu = readl(&priv->cpumac_reg->CpuMacStatsCfg[1]); stats->mtu1 = mtu & 0x3fff; stats->mtu2 = (mtu >> 16) & 0x3fff; spin_unlock_irqrestore(&priv->reglock, flags); @@ -2527,6 +3411,22 @@ static void ctcmac_set_msglevel(struct net_device *dev, uint32_t data) static int ctcmac_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info) { +#if 0 + struct gfar_private *priv = netdev_priv(dev); + + if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) { + info->so_timestamping = SOF_TIMESTAMPING_RX_SOFTWARE | + SOF_TIMESTAMPING_SOFTWARE; + info->phc_index = -1; + return 0; + } + info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | + SOF_TIMESTAMPING_RX_HARDWARE | SOF_TIMESTAMPING_RAW_HARDWARE; + info->phc_index = gfar_phc_index; + info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); + info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | + (1 << HWTSTAMP_FILTER_ALL); +#endif return 0; } @@ -2575,8 +3475,9 @@ static int ctcmac_probe(struct platform_device *ofdev) return PTR_ERR(regmap_base); err = ctcmac_of_init(ofdev, &dev); - if (err) + if (err) { return err; + } priv = netdev_priv(dev); SET_NETDEV_DEV(dev, &ofdev->dev); @@ -2590,10 +3491,19 @@ static int ctcmac_probe(struct platform_device *ofdev) dev->netdev_ops = &ctcmac_netdev_ops; dev->ethtool_ops = &ctcmac_ethtool_ops; - netif_napi_add(dev, &priv->napi_rx, ctcmac_poll_rx_sq, - CTCMAC_NAIP_RX_WEIGHT); - netif_napi_add(dev, &priv->napi_tx, ctcmac_poll_tx_sq, - CTCMAC_NAIP_TX_WEIGHT); + if (priv->version == 0) { + netif_napi_add(dev, &priv->napi_rx, ctcmac_poll_rx_sq, + CTCMAC_NAIP_RX_WEIGHT); + netif_napi_add(dev, &priv->napi_tx, ctcmac_poll_tx_sq, + CTCMAC_NAIP_TX_WEIGHT); + } else { + netif_napi_add(dev, &priv->napi_rx, ctcmac_poll_rx0_sq, + CTCMAC_NAIP_RX_WEIGHT); + netif_napi_add(dev, &priv->napi_rx1, ctcmac_poll_rx1_sq, + CTCMAC_NAIP_RX_WEIGHT); + netif_napi_add(dev, &priv->napi_tx, ctcmac_poll_tx_sq, + CTCMAC_NAIP_TX_WEIGHT); + } /* Initializing some of the rx/tx queue level parameters */ for (i = 0; i < priv->num_tx_queues; i++) { @@ -2601,8 +3511,9 @@ static int ctcmac_probe(struct platform_device *ofdev) priv->tx_queue[i]->num_txbdfree = CTCMAC_TX_RING_SIZE; } - for (i = 0; i < priv->num_rx_queues; i++) + for (i = 0; i < priv->num_rx_queues; i++) { priv->rx_queue[i]->rx_ring_size = CTCMAC_RX_RING_SIZE; + } set_bit(CTCMAC_DOWN, &priv->state); @@ -2615,20 +3526,25 @@ static int ctcmac_probe(struct platform_device *ofdev) /* Carrier starts down, phylib will bring it up */ netif_carrier_off(dev); err = register_netdev(dev); - if (err) + if (err) { goto register_fail; + } if (!g_mac_unit_init_done) { - writel(0x07, &priv->cpumacu_reg->cpu_mac_unit_reset_ctl); - writel(0x00, &priv->cpumacu_reg->cpu_mac_unit_reset_ctl); + writel(0x07, &priv->cpumacu_reg->CpuMacUnitResetCtl); + writel(0x00, &priv->cpumacu_reg->CpuMacUnitResetCtl); - clrsetbits(&priv->cpumacu_reg->cpu_mac_unit_ts_cfg, - 0, CPU_MAC_UNIT_TS_CFG_W0_CFG_FORCE_S_AND_NS_EN); + clrsetbits(&priv->cpumacu_reg->CpuMacUnitTsCfg, + 0, + BIT + (CPU_MAC_UNIT_TS_CFG_W0_CFG_FORCE_S_AND_NS_EN_BIT)); if (priv->interface == PHY_INTERFACE_MODE_SGMII) { - clrsetbits(&priv->cpumacu_reg->cpu_mac_unit_ref_pulse_cfg[1], - CPU_MAC_UNIT_REF_PULSE_CFG_W1_REF_LINK_PULSE_RST, + clrsetbits(&priv->cpumacu_reg->CpuMacUnitRefPulseCfg[1], + BIT + (CPU_MAC_UNIT_REF_PULSE_CFG_W1_REF_LINK_PULSE_RST_BIT), 0); - + writel(0x1f3f, + &priv->cpumacu_reg->CpuMacUnitRefPulseCfg[1]); ctc_mac_serdes_init(priv); } g_mac_unit_init_done = 1; @@ -2641,7 +3557,12 @@ static int ctcmac_probe(struct platform_device *ofdev) sprintf(priv->irqinfo[CTCMAC_NORMAL].name, "%s%s", dev->name, "_normal"); sprintf(priv->irqinfo[CTCMAC_FUNC].name, "%s%s", dev->name, "_func"); - + if (priv->version > 0) { + sprintf(priv->irqinfo[CTCMAC_FUNC_RX0].name, "%s%s", + dev->name, "_func_rx0"); + sprintf(priv->irqinfo[CTCMAC_FUNC_RX1].name, "%s%s", + dev->name, "_func_rx1"); + } return 0; register_fail: @@ -2695,3 +3616,90 @@ static struct platform_driver ctcmac_driver = { module_platform_driver(ctcmac_driver); MODULE_LICENSE("GPL"); + +static int ctcmac_set_ffe(struct ctcmac_private *priv, u16 coefficient[]) +{ + u32 val; + + if (priv->index == 0) { + val = readl(&priv->cpumacu_reg->CpuMacUnitHssCfg[3]); + val |= BIT(CPU_MAC_UNIT_HSS_CFG_W3_CFG_HSS_L0_PCS_EN_ADV_BIT) + | BIT(CPU_MAC_UNIT_HSS_CFG_W3_CFG_HSS_L0_PCS_EN_DLY_BIT); + val &= ~CPU_MAC_UNIT_HSS_CFG_W3_CFG_HSS_L0_PCS_TAP_ADV_MASK; + val |= + (coefficient[0] << + CPU_MAC_UNIT_HSS_CFG_W3_CFG_HSS_L0_PCS_TAP_ADV_BIT); + val &= ~CPU_MAC_UNIT_HSS_CFG_W3_CFG_HSS_L0_PCS_TAP_DLY_MASK; + val |= + (coefficient[2] << + CPU_MAC_UNIT_HSS_CFG_W3_CFG_HSS_L0_PCS_TAP_DLY_BIT); + writel(val, &priv->cpumacu_reg->CpuMacUnitHssCfg[3]); + val = readl(&priv->cpumacu_reg->CpuMacUnitHssCfg[6]); + val &= + ~CPU_MAC_UNIT_HSS_CFG_W6_CFG_HSS_L0_PCS2_PMA_TX_MARGIN_MASK; + val |= + (coefficient[1] << + CPU_MAC_UNIT_HSS_CFG_W6_CFG_HSS_L0_PCS2_PMA_TX_MARGIN_BIT); + writel(val, &priv->cpumacu_reg->CpuMacUnitHssCfg[6]); + } else { + val = readl(&priv->cpumacu_reg->CpuMacUnitHssCfg[9]); + val |= BIT(CPU_MAC_UNIT_HSS_CFG_W9_CFG_HSS_L1_PCS_EN_ADV_BIT) + | BIT(CPU_MAC_UNIT_HSS_CFG_W9_CFG_HSS_L1_PCS_EN_DLY_BIT); + val &= ~CPU_MAC_UNIT_HSS_CFG_W9_CFG_HSS_L1_PCS_TAP_ADV_MASK; + val |= + (coefficient[0] << + CPU_MAC_UNIT_HSS_CFG_W9_CFG_HSS_L1_PCS_TAP_ADV_BIT); + val &= ~CPU_MAC_UNIT_HSS_CFG_W9_CFG_HSS_L1_PCS_TAP_DLY_MASK; + val |= + (coefficient[2] << + CPU_MAC_UNIT_HSS_CFG_W9_CFG_HSS_L1_PCS_TAP_DLY_BIT); + writel(val, &priv->cpumacu_reg->CpuMacUnitHssCfg[9]); + val = readl(&priv->cpumacu_reg->CpuMacUnitHssCfg[12]); + val &= + ~CPU_MAC_UNIT_HSS_CFG_W12_CFG_HSS_L1_PCS2_PMA_TX_MARGIN_MASK; + val |= + (coefficient[1] << + CPU_MAC_UNIT_HSS_CFG_W12_CFG_HSS_L1_PCS2_PMA_TX_MARGIN_BIT); + writel(val, &priv->cpumacu_reg->CpuMacUnitHssCfg[12]); + } + + return 0; +} + +static int ctcmac_get_ffe(struct ctcmac_private *priv, u16 coefficient[]) +{ + u32 val; + + if (priv->index == 0) { + val = readl(&priv->cpumacu_reg->CpuMacUnitHssCfg[3]); + coefficient[0] = + (val & CPU_MAC_UNIT_HSS_CFG_W3_CFG_HSS_L0_PCS_TAP_ADV_MASK) + >> CPU_MAC_UNIT_HSS_CFG_W3_CFG_HSS_L0_PCS_TAP_ADV_BIT; + coefficient[2] = + (val & CPU_MAC_UNIT_HSS_CFG_W3_CFG_HSS_L0_PCS_TAP_DLY_MASK) + >> CPU_MAC_UNIT_HSS_CFG_W3_CFG_HSS_L0_PCS_TAP_DLY_BIT; + val = readl(&priv->cpumacu_reg->CpuMacUnitHssCfg[6]); + coefficient[1] = + (val & + CPU_MAC_UNIT_HSS_CFG_W6_CFG_HSS_L0_PCS2_PMA_TX_MARGIN_MASK) + >> + CPU_MAC_UNIT_HSS_CFG_W6_CFG_HSS_L0_PCS2_PMA_TX_MARGIN_BIT; + + } else { + val = readl(&priv->cpumacu_reg->CpuMacUnitHssCfg[9]); + coefficient[0] = + (val & CPU_MAC_UNIT_HSS_CFG_W9_CFG_HSS_L1_PCS_TAP_ADV_MASK) + >> CPU_MAC_UNIT_HSS_CFG_W9_CFG_HSS_L1_PCS_TAP_ADV_BIT; + coefficient[2] = + (val & CPU_MAC_UNIT_HSS_CFG_W9_CFG_HSS_L1_PCS_TAP_DLY_MASK) + >> CPU_MAC_UNIT_HSS_CFG_W9_CFG_HSS_L1_PCS_TAP_DLY_BIT; + val = readl(&priv->cpumacu_reg->CpuMacUnitHssCfg[12]); + coefficient[1] = + (val & + CPU_MAC_UNIT_HSS_CFG_W12_CFG_HSS_L1_PCS2_PMA_TX_MARGIN_MASK) + >> + CPU_MAC_UNIT_HSS_CFG_W12_CFG_HSS_L1_PCS2_PMA_TX_MARGIN_BIT; + } + + return 0; +} diff --git a/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac.h b/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac.h index 4378c2c802e9..2987a49941fd 100644 --- a/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac.h +++ b/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac.h @@ -1,5 +1,5 @@ /* - * Centec cpu_mac Ethernet Driver -- cpu_mac controller implementation + * Centec CpuMac Ethernet Driver -- CpuMac controller implementation * Provides Bus interface for MIIM regs * * Author: liuht @@ -17,7 +17,7 @@ #ifndef __CTCMAC_H #define __CTCMAC_H -#define TX_TIMEOUT (5 * HZ) +#define TX_TIMEOUT (5*HZ) #define CTCMAC_DEFAULT_MTU 1500 #define CTCMAC_MIN_PKT_LEN 64 @@ -47,14 +47,18 @@ #define CTCMAC_TOKEN_PER_PKT 10 #define CTCMAC_TIMER_COMPENSATE 1 -#define CTCMAC_NOR_RX1_R BIT(7) -#define CTCMAC_NOR_RX0_R BIT(6) -#define CTCMAC_NOR_RX1_D BIT(5) -#define CTCMAC_NOR_RX0_D BIT(4) -#define CTCMAC_NOR_TX_D BIT(3) -#define CTCMAC_NOR_AN_D BIT(2) -#define CTCMAC_NOR_LINK_DOWN BIT(1) -#define CTCMAC_NOR_LINK_UP BIT(0) +#define CTCMAC_NOR_RX1_R (1<<7) +#define CTCMAC_NOR_RX0_R (1<<6) +#define CTCMAC_NOR_RX1_D (1<<5) +#define CTCMAC_NOR_RX0_D (1<<4) +#define CTCMAC_NOR_TX_D (1<<3) +#define CTCMAC_NOR_AN_D (1<<2) +#define CTCMAC_NOR_LINK_DOWN (1<<1) +#define CTCMAC_NOR_LINK_UP (1<<0) +#define CTCMAC_FUNC0_RX_D (1<<0) +#define CTCMAC_FUNC0_RX_R (1<<1) +#define CTCMAC_FUNC1_RX_D (1<<0) +#define CTCMAC_FUNC1_RX_R (1<<1) #define CTC_DDR_BASE 0x80000000 @@ -72,25 +76,33 @@ #define CSC_100M 0x02400000 #define CSC_10M 0x18c00000 -#define CTCMAC_DESC_INT_NUM 1 +#define DESC_INT_COALESCE_CNT_MIN 1 +#define DESC_TX_INT_COALESCE_CNT_DEFAULT 16 +#define DESC_RX_INT_COALESCE_CNT_DEFAULT 16 + +/* emu 100us */ +//#define CTCMAC_TIMER_THRD 0x4B0 +/* board 100us */ +#define CTCMAC_TIMER_THRD 0xc350 #define CTCMAC_SUPPORTED (SUPPORTED_10baseT_Full \ | SUPPORTED_100baseT_Full \ | SUPPORTED_1000baseT_Full \ | SUPPORTED_Autoneg) -#define CTCMAC_STATS_LEN (sizeof(struct ctcmac_pkt_stats) / sizeof(u64)) +#define CTCMAC_STATS_LEN (sizeof(struct ctcmac_pkt_stats)/sizeof(u64)) struct ctcmac_skb_cb { unsigned int bytes_sent; /* bytes-on-wire (i.e. no FCB) */ }; - #define CTCMAC_CB(skb) ((struct ctcmac_skb_cb *)((skb)->cb)) enum ctcmac_irqinfo_id { CTCMAC_NORMAL = 0, CTCMAC_FUNC, CTCMAC_UNIT, + CTCMAC_FUNC_RX0, + CTCMAC_FUNC_RX1, CTCMAC_NUM_IRQS }; @@ -105,6 +117,16 @@ enum ctcmac_int_type { CTCMAC_INT_MAX }; +enum ctcmac_tx_pol_inv { + CTCMAC_TX_POL_INV_DISABLE, + CTCMAC_TX_POL_INV_ENABLE, +}; + +enum ctcmac_rx_pol_inv { + CTCMAC_RX_POL_INV_DISABLE, + CTCMAC_RX_POL_INV_ENABLE, +}; + enum ctcmac_autoneg { CTCMAC_AUTONEG_1000BASEX_M, CTCMAC_AUTONEG_PHY_M, @@ -113,34 +135,46 @@ enum ctcmac_autoneg { CTCMAC_AUTONEG_MAX }; -/* Per TX queue stats */ +/* + * Per TX queue stats + */ struct txq_stats { unsigned long tx_packets; unsigned long tx_bytes; }; +struct tx_skb { + struct sk_buff *skb; + int frag_merge; +}; + struct ctcmac_tx_buff { void *vaddr; dma_addr_t dma; u32 len; u32 offset; - u8 alloc; + bool alloc; }; struct ctcmac_priv_tx_q { - spinlock_t txlock __aligned(SMP_CACHE_BYTES); + spinlock_t txlock __attribute__ ((aligned(SMP_CACHE_BYTES))); struct ctcmac_tx_buff tx_buff[CTCMAC_MAX_RING_SIZE + 1]; unsigned int num_txbdfree; u16 tx_ring_size; u16 qindex; - u16 next_to_alloc; - u16 next_to_clean; + u16 skb_cur; + u16 skb_dirty; + u16 desc_cur; + u16 desc_dirty; struct txq_stats stats; struct net_device *dev; - struct sk_buff **tx_skbuff; + struct tx_skb *tx_skbuff; + struct napi_struct napi_tx; }; -/*Per RX queue stats */ +/* + * Per RX queue stats + */ struct rxq_stats { unsigned long rx_packets; unsigned long rx_bytes; @@ -167,6 +201,7 @@ struct ctcmac_priv_rx_q { u32 pps_limit; u32 token, token_max; u32 rx_trigger; + struct napi_struct napi_rx; }; struct ctcmac_irqinfo { @@ -189,9 +224,9 @@ struct ctcmac_private { struct device *dev; struct net_device *ndev; void __iomem *iobase; - struct cpu_mac_regs __iomem *cpumac_reg; - struct cpu_mac_mems __iomem *cpumac_mem; - struct cpu_mac_unit_regs *cpumacu_reg; + struct CpuMac_regs __iomem *cpumac_reg; + struct CpuMac_mems __iomem *cpumac_mem; + struct CpuMacUnit_regs *cpumacu_reg; u32 device_flags; int irq_num; int index; @@ -213,9 +248,10 @@ struct ctcmac_private { struct work_struct reset_task; struct platform_device *ofdev; - struct napi_struct napi_rx; - struct napi_struct napi_tx; struct ctcmac_irqinfo irqinfo[CTCMAC_NUM_IRQS]; + struct napi_struct napi_tx; + struct napi_struct napi_rx; + struct napi_struct napi_rx1; int hwts_rx_en; int hwts_tx_en; @@ -223,8 +259,16 @@ struct ctcmac_private { u32 supported; u32 msg_enable; u32 int_type; + u32 rx_int_coalesce_cnt; + u32 tx_int_coalesce_cnt; u8 dfe_enable; + u8 tx_pol_inv; + u8 rx_pol_inv; struct timer_list token_timer; + u8 version; + u8 pause_aneg_en; + u8 tx_pause_en; + u8 rx_pause_en; }; struct ctcmac_pkt_stats { diff --git a/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac_reg.h b/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac_reg.h index 2778f0bb4553..302d5d17a9e4 100644 --- a/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac_reg.h +++ b/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac_reg.h @@ -4,147 +4,158 @@ #define CPUMAC_MEM_BASE 0x00004000 #define CPUMAC_REG_BASE 0x00000000 -struct cpu_mac_regs { - u32 cpu_mac_axi_cfg; /* 0x00000000 */ - u32 cpu_mac_axi_mon; /* 0x00000004 */ - u32 cpu_mac_desc_cfg[2]; /* 0x00000008 */ - u32 cpu_mac_buffer_cfg[3]; /* 0x00000010 */ +struct CpuMac_regs { + u32 CpuMacAxiCfg; /* 0x00000000 */ + u32 CpuMacAxiMon; /* 0x00000004 */ + u32 CpuMacDescCfg[2]; /* 0x00000008 */ + u32 CpuMacBufferCfg[3]; /* 0x00000010 */ u32 rsv7; - u32 cpu_mac_debug_stats[3]; /* 0x00000020 */ + u32 CpuMacDebugStats[3]; /* 0x00000020 */ u32 rsv11; - u32 cpu_mac_desc_mon[3]; /* 0x00000030 */ + u32 CpuMacDescMon[3]; /* 0x00000030 */ u32 rsv15; - u32 cpu_mac_dma_weight_cfg; /* 0x00000040 */ - u32 cpu_mac_init; /* 0x00000044 */ - u32 cpu_mac_init_done; /* 0x00000048 */ - u32 cpu_mac_parity_ctl; /* 0x0000004c */ - u32 cpu_mac_ext_ram_cfg[2]; /* 0x00000050 */ + u32 CpuMacDmaWeightCfg; /* 0x00000040 */ + u32 CpuMacInit; /* 0x00000044 */ + u32 CpuMacInitDone; /* 0x00000048 */ + u32 CpuMacParityCtl; /* 0x0000004c */ + u32 CpuMacExtRamCfg[2]; /* 0x00000050 */ u32 rsv22; u32 rsv23; - u32 cpu_mac_fifo_ctl[4]; /* 0x00000060 */ - u32 cpu_mac_gmac_cfg[4]; /* 0x00000070 */ - u32 cpu_mac_ram_chk_rec; /* 0x00000080 */ - u32 cpu_mac_reset; /* 0x00000084 */ - u32 cpu_mac_sgmii_auto_neg_cfg; /* 0x00000088 */ - u32 cpu_mac_reserved; /* 0x0000008c */ - u32 cpu_mac_gmac_mon[2]; /* 0x00000090 */ - u32 cpu_mac_credit_ctl; /* 0x00000098 */ - u32 cpu_mac_credit_status; /* 0x0000009c */ - u32 cpu_mac_pause_cfg[4]; /* 0x000000a0 */ - u32 cpu_mac_pause_mon[3]; /* 0x000000b0 */ + u32 CpuMacFifoCtl[4]; /* 0x00000060 */ + u32 CpuMacGmacCfg[4]; /* 0x00000070 */ + u32 CpuMacRamChkRec; /* 0x00000080 */ + u32 CpuMacReset; /* 0x00000084 */ + u32 CpuMacSgmiiAutoNegCfg; /* 0x00000088 */ + u32 CpuMacReserved; /* 0x0000008c */ + u32 CpuMacGmacMon[2]; /* 0x00000090 */ + u32 CpuMacCreditCtl; /* 0x00000098 */ + u32 CpuMacCreditStatus; /* 0x0000009c */ + u32 CpuMacPauseCfg[4]; /* 0x000000a0 */ + u32 CpuMacPauseMon[3]; /* 0x000000b0 */ u32 rsv47; - u32 cpu_mac_sgmii_cfg[2]; /* 0x000000c0 */ - u32 cpu_mac_sgmii_mon[2]; /* 0x000000c8 */ - u32 cpu_mac_stats_cfg[2]; /* 0x000000d0 */ + u32 CpuMacSgmiiCfg[2]; /* 0x000000c0 */ + u32 CpuMacSgmiiMon[2]; /* 0x000000c8 */ + u32 CpuMacStatsCfg[2]; /* 0x000000d0 */ u32 rsv54; u32 rsv55; - u32 cpu_mac_interrupt_func[4]; /* 0x000000e0 */ - u32 cpu_mac_interrupt_normal[4]; /* 0x000000f0 */ - u32 cpu_mac_fifo_status[3]; /* 0x00000100 */ + u32 CpuMacInterruptFunc[4]; /* 0x000000e0 */ + u32 CpuMacInterruptNormal[4]; /* 0x000000f0 */ + u32 CpuMacFifoStatus[3]; /* 0x00000100 */ + u32 rsv67; + u32 CpuMacDescCfg1[3]; /* 0x00000110 */ + u32 rsv71; + u32 CpuMacInterruptFunc0[4]; /* 0x00000120 */ + u32 CpuMacInterruptFunc1[4]; /* 0x00000130 */ }; -/* cpu_mac_axi_cfg Definition */ -#define CPU_MAC_AXI_CFG_W0_CFG_AXI_WR_BURST_LEN BIT(0) -#define CPU_MAC_AXI_CFG_W0_CFG_AXI_WR_WORD_SWAP_EN BIT(18) -#define CPU_MAC_AXI_CFG_W0_CFG_AXI_WR_D_WORD_SWAP_EN BIT(19) -#define CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_D_WORD_SWAP_EN BIT(17) -#define CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_ADDR_ALIGN_EN BIT(20) -#define CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_BURST_LEN BIT(8) -#define CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_WORD_SWAP_EN BIT(16) +/* ################################################################################ + * # CpuMacAxiCfg Definition */ +#define CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_ADDR_ALIGN_EN_BIT 20 +#define CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_BURST_LEN_BIT 8 +#define CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_D_WORD_SWAP_EN_BIT 17 +#define CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_WORD_SWAP_EN_BIT 16 +#define CPU_MAC_AXI_CFG_W0_CFG_AXI_WR_BURST_LEN_BIT 0 +#define CPU_MAC_AXI_CFG_W0_CFG_AXI_WR_D_WORD_SWAP_EN_BIT 19 +#define CPU_MAC_AXI_CFG_W0_CFG_AXI_WR_WORD_SWAP_EN_BIT 18 -#define CPU_MAC_AXI_CFG_W0_CFG_AXI_WR_BURST_LEN_MASK 0x000000ff -#define CPU_MAC_AXI_CFG_W0_CFG_AXI_WR_WORD_SWAP_EN_MASK 0x00040000 -#define CPU_MAC_AXI_CFG_W0_CFG_AXI_WR_D_WORD_SWAP_EN_MASK 0x00080000 -#define CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_D_WORD_SWAP_EN_MASK 0x00020000 #define CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_ADDR_ALIGN_EN_MASK 0x00100000 #define CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_BURST_LEN_MASK 0x0000ff00 +#define CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_D_WORD_SWAP_EN_MASK 0x00020000 #define CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_WORD_SWAP_EN_MASK 0x00010000 +#define CPU_MAC_AXI_CFG_W0_CFG_AXI_WR_BURST_LEN_MASK 0x000000ff +#define CPU_MAC_AXI_CFG_W0_CFG_AXI_WR_D_WORD_SWAP_EN_MASK 0x00080000 +#define CPU_MAC_AXI_CFG_W0_CFG_AXI_WR_WORD_SWAP_EN_MASK 0x00040000 -/* cpu_mac_axi_mon Definition */ -#define CPU_MAC_AXI_MON_W0_MON_AXI_WR_RESP BIT(4) -#define CPU_MAC_AXI_MON_W0_MON_AXI_RD_RESP BIT(0) +/* ################################################################################ + * # CpuMacAxiMon Definition */ +#define CPU_MAC_AXI_MON_W0_MON_AXI_RD_RESP_BIT 0 +#define CPU_MAC_AXI_MON_W0_MON_AXI_WR_RESP_BIT 4 -#define CPU_MAC_AXI_MON_W0_MON_AXI_WR_RESP_MASK 0x00000070 #define CPU_MAC_AXI_MON_W0_MON_AXI_RD_RESP_MASK 0x00000007 +#define CPU_MAC_AXI_MON_W0_MON_AXI_WR_RESP_MASK 0x00000070 -/* cpu_mac_desc_cfg Definition */ -#define CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_DONE_INTR_EOP_EN BIT(30) -#define CPU_MAC_DESC_CFG_W0_CFG_RX_DESC_DONE_INTR_EOP_EN BIT(29) -#define CPU_MAC_DESC_CFG_W0_CFG_RX_DESC0_DONE_INTR_THRD BIT(8) -#define CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_DONE_INTR_THRD BIT(0) -#define CPU_MAC_DESC_CFG_W0_CFG_RX_DESC1_DONE_INTR_THRD BIT(16) -#define CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_ACK_EN BIT(31) -#define CPU_MAC_DESC_CFG_W1_CFG_RX_DESC0_REQ_INTR_THRD BIT(0) -#define CPU_MAC_DESC_CFG_W1_CFG_RX_DESC1_REQ_INTR_THRD BIT(8) +/* ################################################################################ + * # CpuMacDescCfg Definition */ +#define CPU_MAC_DESC_CFG_W0_CFG_RX_DESC0_DONE_INTR_THRD_BIT 8 +#define CPU_MAC_DESC_CFG_W0_CFG_RX_DESC1_DONE_INTR_THRD_BIT 16 +#define CPU_MAC_DESC_CFG_W0_CFG_RX_DESC_DONE_INTR_EOP_EN_BIT 29 +#define CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_ACK_EN_BIT 31 +#define CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_DONE_INTR_EOP_EN_BIT 30 +#define CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_DONE_INTR_THRD_BIT 0 +#define CPU_MAC_DESC_CFG_W1_CFG_RX_DESC0_REQ_INTR_THRD_BIT 0 +#define CPU_MAC_DESC_CFG_W1_CFG_RX_DESC1_REQ_INTR_THRD_BIT 8 -#define CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_DONE_INTR_EOP_EN_MASK 0x40000000 -#define CPU_MAC_DESC_CFG_W0_CFG_RX_DESC_DONE_INTR_EOP_EN_MASK 0x20000000 #define CPU_MAC_DESC_CFG_W0_CFG_RX_DESC0_DONE_INTR_THRD_MASK 0x0000ff00 -#define CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_DONE_INTR_THRD_MASK 0x000000ff #define CPU_MAC_DESC_CFG_W0_CFG_RX_DESC1_DONE_INTR_THRD_MASK 0x00ff0000 +#define CPU_MAC_DESC_CFG_W0_CFG_RX_DESC_DONE_INTR_EOP_EN_MASK 0x20000000 #define CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_ACK_EN_MASK 0x80000000 +#define CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_DONE_INTR_EOP_EN_MASK 0x40000000 +#define CPU_MAC_DESC_CFG_W0_CFG_TX_DESC_DONE_INTR_THRD_MASK 0x000000ff #define CPU_MAC_DESC_CFG_W1_CFG_RX_DESC0_REQ_INTR_THRD_MASK 0x000000ff #define CPU_MAC_DESC_CFG_W1_CFG_RX_DESC1_REQ_INTR_THRD_MASK 0x0000ff00 -/* cpu_mac_buffer_cfg Definition */ -#define CPU_MAC_BUFFER_CFG_W0_CFG_RX_X_OFF_THRD BIT(16) -#define CPU_MAC_BUFFER_CFG_W0_CFG_RX_X_ON_THRD BIT(0) -#define CPU_MAC_BUFFER_CFG_W1_CFG_RX_RSV_THRD BIT(0) -#define CPU_MAC_BUFFER_CFG_W1_CFG_RX_FLUSH_THRD BIT(16) -#define CPU_MAC_BUFFER_CFG_W2_CFG_RX_FLUSH_EN BIT(0) +/* ################################################################################ + * # CpuMacBufferCfg Definition */ +#define CPU_MAC_BUFFER_CFG_W0_CFG_RX_X_OFF_THRD_BIT 16 +#define CPU_MAC_BUFFER_CFG_W0_CFG_RX_X_ON_THRD_BIT 0 +#define CPU_MAC_BUFFER_CFG_W1_CFG_RX_FLUSH_THRD_BIT 16 +#define CPU_MAC_BUFFER_CFG_W1_CFG_RX_RSV_THRD_BIT 0 +#define CPU_MAC_BUFFER_CFG_W2_CFG_RX_FLUSH_EN_BIT 0 #define CPU_MAC_BUFFER_CFG_W0_CFG_RX_X_OFF_THRD_MASK 0x3fff0000 #define CPU_MAC_BUFFER_CFG_W0_CFG_RX_X_ON_THRD_MASK 0x00003fff -#define CPU_MAC_BUFFER_CFG_W1_CFG_RX_RSV_THRD_MASK 0x00003fff #define CPU_MAC_BUFFER_CFG_W1_CFG_RX_FLUSH_THRD_MASK 0x3fff0000 +#define CPU_MAC_BUFFER_CFG_W1_CFG_RX_RSV_THRD_MASK 0x00003fff #define CPU_MAC_BUFFER_CFG_W2_CFG_RX_FLUSH_EN_MASK 0x00000001 -/* cpu_mac_debug_stats Definition */ -#define CPU_MAC_DEBUG_STATS_W0_DMA_RX_ERROR_CNT BIT(20) -#define CPU_MAC_DEBUG_STATS_W0_GMAC_TX_SOP_CNT BIT(24) -#define CPU_MAC_DEBUG_STATS_W0_GMAC_RX_SOP_CNT BIT(0) -#define CPU_MAC_DEBUG_STATS_W0_GMAC_RX_EOP_CNT BIT(4) -#define CPU_MAC_DEBUG_STATS_W0_GMAC_TX_EOP_CNT BIT(28) -#define CPU_MAC_DEBUG_STATS_W0_DMA_RX_EOP_CNT BIT(16) -#define CPU_MAC_DEBUG_STATS_W0_GMAC_RX_ERROR_CNT BIT(8) -#define CPU_MAC_DEBUG_STATS_W0_DMA_RX_SOP_CNT BIT(12) -#define CPU_MAC_DEBUG_STATS_W1_DMA_TX_EOP_CNT BIT(8) -#define CPU_MAC_DEBUG_STATS_W1_GMAC_TX_PTP_ERR_CNT BIT(16) -#define CPU_MAC_DEBUG_STATS_W1_DMA_TX_SOP_CNT BIT(4) -#define CPU_MAC_DEBUG_STATS_W1_DMA_TX_ERROR_CNT BIT(12) -#define CPU_MAC_DEBUG_STATS_W1_GMAC_TX_ERROR_CNT BIT(0) -#define CPU_MAC_DEBUG_STATS_W2_AXI_RD_BURST_CNT BIT(8) -#define CPU_MAC_DEBUG_STATS_W2_EXT_RAM_SBE_CNT BIT(16) -#define CPU_MAC_DEBUG_STATS_W2_AXI_RD_BURST_ERR_CNT BIT(12) -#define CPU_MAC_DEBUG_STATS_W2_AXI_WR_BURST_CNT BIT(0) -#define CPU_MAC_DEBUG_STATS_W2_AXI_WR_BURST_ERR_CNT BIT(4) +/* ################################################################################ + * # CpuMacDebugStats Definition */ +#define CPU_MAC_DEBUG_STATS_W0_DMA_RX_EOP_CNT_BIT 16 +#define CPU_MAC_DEBUG_STATS_W0_DMA_RX_ERROR_CNT_BIT 20 +#define CPU_MAC_DEBUG_STATS_W0_DMA_RX_SOP_CNT_BIT 12 +#define CPU_MAC_DEBUG_STATS_W0_GMAC_RX_EOP_CNT_BIT 4 +#define CPU_MAC_DEBUG_STATS_W0_GMAC_RX_ERROR_CNT_BIT 8 +#define CPU_MAC_DEBUG_STATS_W0_GMAC_RX_SOP_CNT_BIT 0 +#define CPU_MAC_DEBUG_STATS_W0_GMAC_TX_EOP_CNT_BIT 28 +#define CPU_MAC_DEBUG_STATS_W0_GMAC_TX_SOP_CNT_BIT 24 +#define CPU_MAC_DEBUG_STATS_W1_DMA_TX_EOP_CNT_BIT 8 +#define CPU_MAC_DEBUG_STATS_W1_DMA_TX_ERROR_CNT_BIT 12 +#define CPU_MAC_DEBUG_STATS_W1_DMA_TX_SOP_CNT_BIT 4 +#define CPU_MAC_DEBUG_STATS_W1_GMAC_TX_ERROR_CNT_BIT 0 +#define CPU_MAC_DEBUG_STATS_W1_GMAC_TX_PTP_ERR_CNT_BIT 16 +#define CPU_MAC_DEBUG_STATS_W2_AXI_RD_BURST_CNT_BIT 8 +#define CPU_MAC_DEBUG_STATS_W2_AXI_RD_BURST_ERR_CNT_BIT 12 +#define CPU_MAC_DEBUG_STATS_W2_AXI_WR_BURST_CNT_BIT 0 +#define CPU_MAC_DEBUG_STATS_W2_AXI_WR_BURST_ERR_CNT_BIT 4 +#define CPU_MAC_DEBUG_STATS_W2_EXT_RAM_SBE_CNT_BIT 16 +#define CPU_MAC_DEBUG_STATS_W0_DMA_RX_EOP_CNT_MASK 0x000f0000 #define CPU_MAC_DEBUG_STATS_W0_DMA_RX_ERROR_CNT_MASK 0x00f00000 -#define CPU_MAC_DEBUG_STATS_W0_GMAC_TX_SOP_CNT_MASK 0x0f000000 -#define CPU_MAC_DEBUG_STATS_W0_GMAC_RX_SOP_CNT_MASK 0x0000000f +#define CPU_MAC_DEBUG_STATS_W0_DMA_RX_SOP_CNT_MASK 0x0000f000 #define CPU_MAC_DEBUG_STATS_W0_GMAC_RX_EOP_CNT_MASK 0x000000f0 -#define CPU_MAC_DEBUG_STATS_W0_GMAC_TX_EOP_CNT_MASK 0xf0000000 -#define CPU_MAC_DEBUG_STATS_W0_DMA_RX_EOP_CNT_MASK 0x000f0000 #define CPU_MAC_DEBUG_STATS_W0_GMAC_RX_ERROR_CNT_MASK 0x00000f00 -#define CPU_MAC_DEBUG_STATS_W0_DMA_RX_SOP_CNT_MASK 0x0000f000 +#define CPU_MAC_DEBUG_STATS_W0_GMAC_RX_SOP_CNT_MASK 0x0000000f +#define CPU_MAC_DEBUG_STATS_W0_GMAC_TX_EOP_CNT_MASK 0xf0000000 +#define CPU_MAC_DEBUG_STATS_W0_GMAC_TX_SOP_CNT_MASK 0x0f000000 #define CPU_MAC_DEBUG_STATS_W1_DMA_TX_EOP_CNT_MASK 0x00000f00 -#define CPU_MAC_DEBUG_STATS_W1_GMAC_TX_PTP_ERR_CNT_MASK 0x000f0000 -#define CPU_MAC_DEBUG_STATS_W1_DMA_TX_SOP_CNT_MASK 0x000000f0 #define CPU_MAC_DEBUG_STATS_W1_DMA_TX_ERROR_CNT_MASK 0x0000f000 +#define CPU_MAC_DEBUG_STATS_W1_DMA_TX_SOP_CNT_MASK 0x000000f0 #define CPU_MAC_DEBUG_STATS_W1_GMAC_TX_ERROR_CNT_MASK 0x0000000f +#define CPU_MAC_DEBUG_STATS_W1_GMAC_TX_PTP_ERR_CNT_MASK 0x000f0000 #define CPU_MAC_DEBUG_STATS_W2_AXI_RD_BURST_CNT_MASK 0x00000f00 -#define CPU_MAC_DEBUG_STATS_W2_EXT_RAM_SBE_CNT_MASK 0x000f0000 #define CPU_MAC_DEBUG_STATS_W2_AXI_RD_BURST_ERR_CNT_MASK 0x0000f000 #define CPU_MAC_DEBUG_STATS_W2_AXI_WR_BURST_CNT_MASK 0x0000000f #define CPU_MAC_DEBUG_STATS_W2_AXI_WR_BURST_ERR_CNT_MASK 0x000000f0 +#define CPU_MAC_DEBUG_STATS_W2_EXT_RAM_SBE_CNT_MASK 0x000f0000 -/* cpu_mac_desc_mon Definition */ -#define CPU_MAC_DESC_MON_W0_MON_DESC_AVAIL_NUM0 BIT(0) -#define CPU_MAC_DESC_MON_W0_MON_DESC_AVAIL_NUM1 BIT(16) -#define CPU_MAC_DESC_MON_W1_MON_DESC_AVAIL_NUM2 BIT(0) -#define CPU_MAC_DESC_MON_W1_MON_DESC_DONE_NUM0 BIT(16) -#define CPU_MAC_DESC_MON_W2_MON_DESC_DONE_NUM1 BIT(0) -#define CPU_MAC_DESC_MON_W2_MON_DESC_DONE_NUM2 BIT(16) +/* ################################################################################ + * # CpuMacDescMon Definition */ +#define CPU_MAC_DESC_MON_W0_MON_DESC_AVAIL_NUM0_BIT 0 +#define CPU_MAC_DESC_MON_W0_MON_DESC_AVAIL_NUM1_BIT 16 +#define CPU_MAC_DESC_MON_W1_MON_DESC_AVAIL_NUM2_BIT 0 +#define CPU_MAC_DESC_MON_W1_MON_DESC_DONE_NUM0_BIT 16 +#define CPU_MAC_DESC_MON_W2_MON_DESC_DONE_NUM1_BIT 0 +#define CPU_MAC_DESC_MON_W2_MON_DESC_DONE_NUM2_BIT 16 #define CPU_MAC_DESC_MON_W0_MON_DESC_AVAIL_NUM0_MASK 0x0000ffff #define CPU_MAC_DESC_MON_W0_MON_DESC_AVAIL_NUM1_MASK 0xffff0000 @@ -153,1645 +164,1708 @@ struct cpu_mac_regs { #define CPU_MAC_DESC_MON_W2_MON_DESC_DONE_NUM1_MASK 0x0000ffff #define CPU_MAC_DESC_MON_W2_MON_DESC_DONE_NUM2_MASK 0xffff0000 -/* cpu_mac_dma_weight_cfg Definition */ -#define CPU_MAC_DMA_WEIGHT_CFG_W0_CFG_DMA_RX_WEIGHT1 BIT(8) -#define CPU_MAC_DMA_WEIGHT_CFG_W0_CFG_DMA_RX_WEIGHT0 BIT(0) +/* ################################################################################ + * # CpuMacDmaWeightCfg Definition */ +#define CPU_MAC_DMA_WEIGHT_CFG_W0_CFG_DMA_RX_WEIGHT0_BIT 0 +#define CPU_MAC_DMA_WEIGHT_CFG_W0_CFG_DMA_RX_WEIGHT1_BIT 8 -#define CPU_MAC_DMA_WEIGHT_CFG_W0_CFG_DMA_RX_WEIGHT1_MASK 0x00000f00 #define CPU_MAC_DMA_WEIGHT_CFG_W0_CFG_DMA_RX_WEIGHT0_MASK 0x0000000f +#define CPU_MAC_DMA_WEIGHT_CFG_W0_CFG_DMA_RX_WEIGHT1_MASK 0x00000f00 -/* cpu_mac_init Definition */ -#define CPU_MAC_INIT_W0_INIT BIT(0) +/* ################################################################################ + * # CpuMacInit Definition */ +#define CPU_MAC_INIT_W0_INIT_BIT 0 #define CPU_MAC_INIT_W0_INIT_MASK 0x00000001 -/* cpu_mac_init_done Definition */ -#define CPU_MAC_INIT_DONE_W0_INIT_DONE BIT(0) +/* ################################################################################ + * # CpuMacInitDone Definition */ +#define CPU_MAC_INIT_DONE_W0_INIT_DONE_BIT 0 #define CPU_MAC_INIT_DONE_W0_INIT_DONE_MASK 0x00000001 -/* cpu_mac_parity_ctl Definition */ -#define CPU_MAC_PARITY_CTL_W0_RX_PKT_MSG_FIFO_PARITY_EN BIT(2) -#define CPU_MAC_PARITY_CTL_W0_TX_PKT_FIFO_PARITY_EN BIT(4) -#define CPU_MAC_PARITY_CTL_W0_EXT_RAM_ECC_DETECT_DIS BIT(8) -#define CPU_MAC_PARITY_CTL_W0_CPU_MAC_STATS_RAM_PARITY_EN BIT(0) -#define CPU_MAC_PARITY_CTL_W0_RX_DESC0_CFG_FIFO_PARITY_EN BIT(5) -#define CPU_MAC_PARITY_CTL_W0_RX_PKT_DATA_FIFO_PARITY_EN BIT(1) -#define CPU_MAC_PARITY_CTL_W0_TX_DESC_CFG_FIFO_PARITY_EN BIT(7) -#define CPU_MAC_PARITY_CTL_W0_RX_DESC1_CFG_FIFO_PARITY_EN BIT(6) -#define CPU_MAC_PARITY_CTL_W0_EXT_RAM_ECC_CORRECT_DIS BIT(9) +/* ################################################################################ + * # CpuMacParityCtl Definition */ +#define CPU_MAC_PARITY_CTL_W0_CPU_MAC_STATS_RAM_PARITY_EN_BIT 0 +#define CPU_MAC_PARITY_CTL_W0_EXT_RAM_ECC_CORRECT_DIS_BIT 9 +#define CPU_MAC_PARITY_CTL_W0_EXT_RAM_ECC_DETECT_DIS_BIT 8 +#define CPU_MAC_PARITY_CTL_W0_RX_DESC0_CFG_FIFO_PARITY_EN_BIT 5 +#define CPU_MAC_PARITY_CTL_W0_RX_DESC1_CFG_FIFO_PARITY_EN_BIT 6 +#define CPU_MAC_PARITY_CTL_W0_RX_PKT_DATA_FIFO_PARITY_EN_BIT 1 +#define CPU_MAC_PARITY_CTL_W0_RX_PKT_MSG_FIFO_PARITY_EN_BIT 2 +#define CPU_MAC_PARITY_CTL_W0_TX_DESC_CFG_FIFO_PARITY_EN_BIT 7 +#define CPU_MAC_PARITY_CTL_W0_TX_PKT_FIFO_PARITY_EN_BIT 4 -#define CPU_MAC_PARITY_CTL_W0_RX_PKT_MSG_FIFO_PARITY_EN_MASK 0x00000004 -#define CPU_MAC_PARITY_CTL_W0_TX_PKT_FIFO_PARITY_EN_MASK 0x00000010 -#define CPU_MAC_PARITY_CTL_W0_EXT_RAM_ECC_DETECT_DIS_MASK 0x00000100 #define CPU_MAC_PARITY_CTL_W0_CPU_MAC_STATS_RAM_PARITY_EN_MASK 0x00000001 +#define CPU_MAC_PARITY_CTL_W0_EXT_RAM_ECC_CORRECT_DIS_MASK 0x00000200 +#define CPU_MAC_PARITY_CTL_W0_EXT_RAM_ECC_DETECT_DIS_MASK 0x00000100 #define CPU_MAC_PARITY_CTL_W0_RX_DESC0_CFG_FIFO_PARITY_EN_MASK 0x00000020 +#define CPU_MAC_PARITY_CTL_W0_RX_DESC1_CFG_FIFO_PARITY_EN_MASK 0x00000040 #define CPU_MAC_PARITY_CTL_W0_RX_PKT_DATA_FIFO_PARITY_EN_MASK 0x00000002 +#define CPU_MAC_PARITY_CTL_W0_RX_PKT_MSG_FIFO_PARITY_EN_MASK 0x00000004 #define CPU_MAC_PARITY_CTL_W0_TX_DESC_CFG_FIFO_PARITY_EN_MASK 0x00000080 -#define CPU_MAC_PARITY_CTL_W0_RX_DESC1_CFG_FIFO_PARITY_EN_MASK 0x00000040 -#define CPU_MAC_PARITY_CTL_W0_EXT_RAM_ECC_CORRECT_DIS_MASK 0x00000200 +#define CPU_MAC_PARITY_CTL_W0_TX_PKT_FIFO_PARITY_EN_MASK 0x00000010 -/* cpu_mac_ext_ram_cfg Definition */ -#define CPU_MAC_EXT_RAM_CFG_W0_CFG_EXT_RAM_EN BIT(31) -#define CPU_MAC_EXT_RAM_CFG_W0_CFG_EXT_RAM_BASE_SIZE BIT(0) -#define CPU_MAC_EXT_RAM_CFG_W1_CFG_EXT_RAM_BASE_ADDR BIT(0) +/* ################################################################################ + * # CpuMacExtRamCfg Definition */ +#define CPU_MAC_EXT_RAM_CFG_W0_CFG_EXT_RAM_BASE_SIZE_BIT 0 +#define CPU_MAC_EXT_RAM_CFG_W0_CFG_EXT_RAM_EN_BIT 31 +#define CPU_MAC_EXT_RAM_CFG_W1_CFG_EXT_RAM_BASE_ADDR_BIT 0 -#define CPU_MAC_EXT_RAM_CFG_W0_CFG_EXT_RAM_EN_MASK 0x80000000 #define CPU_MAC_EXT_RAM_CFG_W0_CFG_EXT_RAM_BASE_SIZE_MASK 0x000003ff +#define CPU_MAC_EXT_RAM_CFG_W0_CFG_EXT_RAM_EN_MASK 0x80000000 #define CPU_MAC_EXT_RAM_CFG_W1_CFG_EXT_RAM_BASE_ADDR_MASK 0x000fffff -/* cpu_mac_fifo_ctl Definition */ -#define CPU_MAC_FIFO_CTL_W0_RX_PKT_DATA_FIFO_A_FULL_THRD BIT(0) -#define CPU_MAC_FIFO_CTL_W1_RX_PKT_MSG_FIFO_A_FULL_THRD BIT(0) -#define CPU_MAC_FIFO_CTL_W2_TX_PKT_FIFO_A_FULL_THRD BIT(0) -#define CPU_MAC_FIFO_CTL_W3_RX_PKT_FIFO_A_FULL_THRD BIT(0) +/* ################################################################################ + * # CpuMacFifoCtl Definition */ +#define CPU_MAC_FIFO_CTL_W0_RX_PKT_DATA_FIFO_A_FULL_THRD_BIT 0 +#define CPU_MAC_FIFO_CTL_W1_RX_PKT_MSG_FIFO_A_FULL_THRD_BIT 0 +#define CPU_MAC_FIFO_CTL_W2_TX_PKT_FIFO_A_FULL_THRD_BIT 0 +#define CPU_MAC_FIFO_CTL_W3_RX_PKT_FIFO_A_FULL_THRD_BIT 0 #define CPU_MAC_FIFO_CTL_W0_RX_PKT_DATA_FIFO_A_FULL_THRD_MASK 0x00001fff #define CPU_MAC_FIFO_CTL_W1_RX_PKT_MSG_FIFO_A_FULL_THRD_MASK 0x000003ff #define CPU_MAC_FIFO_CTL_W2_TX_PKT_FIFO_A_FULL_THRD_MASK 0x000007ff #define CPU_MAC_FIFO_CTL_W3_RX_PKT_FIFO_A_FULL_THRD_MASK 0x000003ff -/* cpu_mac_gmac_cfg Definition */ -#define CPU_MAC_GMAC_CFG_W0_CFG_RX_CUT_THROUGH_EN BIT(4) -#define CPU_MAC_GMAC_CFG_W0_CFG_RX_UNDERSIZE_DROP_EN BIT(3) -#define CPU_MAC_GMAC_CFG_W0_CFG_RX_ERROR_DROP_EN BIT(5) -#define CPU_MAC_GMAC_CFG_W0_CFG_RX_TS_EN BIT(0) -#define CPU_MAC_GMAC_CFG_W0_CFG_RX_OVERSIZE_DROP_EN BIT(2) -#define CPU_MAC_GMAC_CFG_W0_CFG_RX_PAUSE_DROP_EN BIT(6) -#define CPU_MAC_GMAC_CFG_W0_CFG_RX_OVERRUN_DROP_EN BIT(1) -#define CPU_MAC_GMAC_CFG_W1_CFG_RX_MAX_PKT_LEN_CHK_EN BIT(0) -#define CPU_MAC_GMAC_CFG_W1_CFG_RX_MIN_PKT_LEN BIT(17) -#define CPU_MAC_GMAC_CFG_W1_CFG_RX_MIN_PKT_LEN_CHK_EN BIT(16) -#define CPU_MAC_GMAC_CFG_W1_CFG_RX_MAX_PKT_LEN BIT(1) -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_START_THRD BIT(16) -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_ERR_MASK_OFF BIT(1) -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_PTP_ERR_EN BIT(6) -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_KEEP_TS_EN BIT(12) -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_PAUSE_STALL_EN BIT(4) -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_CUT_THROUGH_EN BIT(10) -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_STRIP_CRC_EN BIT(8) -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_PKT_EN BIT(5) -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_PAD_EN BIT(3) -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_WAIT_CAPTURE_TS BIT(9) -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_HDR_INFO_EN BIT(11) -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_LPI_EN BIT(2) -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_APPEND_CRC_EN BIT(0) -#define CPU_MAC_GMAC_CFG_W3_CFG_TX_SLEEP_TIMER BIT(0) -#define CPU_MAC_GMAC_CFG_W3_CFG_TX_WAKEUP_TIMER BIT(16) +/* ################################################################################ + * # CpuMacGmacCfg Definition */ +#define CPU_MAC_GMAC_CFG_W0_CFG_RX_CUT_THROUGH_EN_BIT 4 +#define CPU_MAC_GMAC_CFG_W0_CFG_RX_ERROR_DROP_EN_BIT 5 +#define CPU_MAC_GMAC_CFG_W0_CFG_RX_OVERRUN_DROP_EN_BIT 1 +#define CPU_MAC_GMAC_CFG_W0_CFG_RX_OVERSIZE_DROP_EN_BIT 2 +#define CPU_MAC_GMAC_CFG_W0_CFG_RX_PAUSE_DROP_EN_BIT 6 +#define CPU_MAC_GMAC_CFG_W0_CFG_RX_TS_EN_BIT 0 +#define CPU_MAC_GMAC_CFG_W0_CFG_RX_UNDERSIZE_DROP_EN_BIT 3 +#define CPU_MAC_GMAC_CFG_W1_CFG_RX_MAX_PKT_LEN_BIT 1 +#define CPU_MAC_GMAC_CFG_W1_CFG_RX_MAX_PKT_LEN_CHK_EN_BIT 0 +#define CPU_MAC_GMAC_CFG_W1_CFG_RX_MIN_PKT_LEN_BIT 17 +#define CPU_MAC_GMAC_CFG_W1_CFG_RX_MIN_PKT_LEN_CHK_EN_BIT 16 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_APPEND_CRC_EN_BIT 0 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_CUT_THROUGH_EN_BIT 10 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_ERR_MASK_OFF_BIT 1 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_HDR_INFO_EN_BIT 11 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_KEEP_TS_EN_BIT 12 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_LPI_EN_BIT 2 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_PAD_EN_BIT 3 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_PAUSE_STALL_EN_BIT 4 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_PKT_EN_BIT 5 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_PTP_ERR_EN_BIT 6 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_START_THRD_BIT 16 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_STRIP_CRC_EN_BIT 8 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_WAIT_CAPTURE_TS_BIT 9 +#define CPU_MAC_GMAC_CFG_W3_CFG_TX_SLEEP_TIMER_BIT 0 +#define CPU_MAC_GMAC_CFG_W3_CFG_TX_WAKEUP_TIMER_BIT 16 #define CPU_MAC_GMAC_CFG_W0_CFG_RX_CUT_THROUGH_EN_MASK 0x00000010 -#define CPU_MAC_GMAC_CFG_W0_CFG_RX_UNDERSIZE_DROP_EN_MASK 0x00000008 #define CPU_MAC_GMAC_CFG_W0_CFG_RX_ERROR_DROP_EN_MASK 0x00000020 -#define CPU_MAC_GMAC_CFG_W0_CFG_RX_TS_EN_MASK 0x00000001 +#define CPU_MAC_GMAC_CFG_W0_CFG_RX_OVERRUN_DROP_EN_MASK 0x00000002 #define CPU_MAC_GMAC_CFG_W0_CFG_RX_OVERSIZE_DROP_EN_MASK 0x00000004 #define CPU_MAC_GMAC_CFG_W0_CFG_RX_PAUSE_DROP_EN_MASK 0x00000040 -#define CPU_MAC_GMAC_CFG_W0_CFG_RX_OVERRUN_DROP_EN_MASK 0x00000002 +#define CPU_MAC_GMAC_CFG_W0_CFG_RX_TS_EN_MASK 0x00000001 +#define CPU_MAC_GMAC_CFG_W0_CFG_RX_UNDERSIZE_DROP_EN_MASK 0x00000008 +#define CPU_MAC_GMAC_CFG_W1_CFG_RX_MAX_PKT_LEN_MASK 0x0000fffe #define CPU_MAC_GMAC_CFG_W1_CFG_RX_MAX_PKT_LEN_CHK_EN_MASK 0x00000001 #define CPU_MAC_GMAC_CFG_W1_CFG_RX_MIN_PKT_LEN_MASK 0x00fe0000 #define CPU_MAC_GMAC_CFG_W1_CFG_RX_MIN_PKT_LEN_CHK_EN_MASK 0x00010000 -#define CPU_MAC_GMAC_CFG_W1_CFG_RX_MAX_PKT_LEN_MASK 0x0000fffe -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_START_THRD_MASK 0x07ff0000 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_APPEND_CRC_EN_MASK 0x00000001 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_CUT_THROUGH_EN_MASK 0x00000400 #define CPU_MAC_GMAC_CFG_W2_CFG_TX_ERR_MASK_OFF_MASK 0x00000002 -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_PTP_ERR_EN_MASK 0x00000040 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_HDR_INFO_EN_MASK 0x00000800 #define CPU_MAC_GMAC_CFG_W2_CFG_TX_KEEP_TS_EN_MASK 0x00001000 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_LPI_EN_MASK 0x00000004 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_PAD_EN_MASK 0x00000008 #define CPU_MAC_GMAC_CFG_W2_CFG_TX_PAUSE_STALL_EN_MASK 0x00000010 -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_CUT_THROUGH_EN_MASK 0x00000400 -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_STRIP_CRC_EN_MASK 0x00000100 #define CPU_MAC_GMAC_CFG_W2_CFG_TX_PKT_EN_MASK 0x00000020 -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_PAD_EN_MASK 0x00000008 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_PTP_ERR_EN_MASK 0x00000040 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_START_THRD_MASK 0x07ff0000 +#define CPU_MAC_GMAC_CFG_W2_CFG_TX_STRIP_CRC_EN_MASK 0x00000100 #define CPU_MAC_GMAC_CFG_W2_CFG_TX_WAIT_CAPTURE_TS_MASK 0x00000200 -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_HDR_INFO_EN_MASK 0x00000800 -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_LPI_EN_MASK 0x00000004 -#define CPU_MAC_GMAC_CFG_W2_CFG_TX_APPEND_CRC_EN_MASK 0x00000001 #define CPU_MAC_GMAC_CFG_W3_CFG_TX_SLEEP_TIMER_MASK 0x0000ffff #define CPU_MAC_GMAC_CFG_W3_CFG_TX_WAKEUP_TIMER_MASK 0xffff0000 -/* cpu_mac_ram_chk_rec Definition */ -#define CPU_MAC_RAM_CHK_REC_W0_CPU_MAC_STATS_RAM_PARITY_FAIL BIT(31) -#define CPU_MAC_RAM_CHK_REC_W0_CPU_MAC_STATS_RAM_PARITY_FAIL_ADDR BIT(0) +/* ################################################################################ + * # CpuMacRamChkRec Definition */ +#define CPU_MAC_RAM_CHK_REC_W0_CPU_MAC_STATS_RAM_PARITY_FAIL_BIT 31 +#define CPU_MAC_RAM_CHK_REC_W0_CPU_MAC_STATS_RAM_PARITY_FAIL_ADDR_BIT 0 #define CPU_MAC_RAM_CHK_REC_W0_CPU_MAC_STATS_RAM_PARITY_FAIL_MASK 0x80000000 #define CPU_MAC_RAM_CHK_REC_W0_CPU_MAC_STATS_RAM_PARITY_FAIL_ADDR_MASK 0x0000003f -/* cpu_mac_reset Definition */ -#define CPU_MAC_RESET_W0_SOFT_RST_TX BIT(1) -#define CPU_MAC_RESET_W0_SOFT_RST_RX BIT(0) +/* ################################################################################ + * # CpuMacReset Definition */ +#define CPU_MAC_RESET_W0_SOFT_RST_RX_BIT 0 +#define CPU_MAC_RESET_W0_SOFT_RST_TX_BIT 1 -#define CPU_MAC_RESET_W0_SOFT_RST_TX_MASK 0x00000002 #define CPU_MAC_RESET_W0_SOFT_RST_RX_MASK 0x00000001 +#define CPU_MAC_RESET_W0_SOFT_RST_TX_MASK 0x00000002 -/* cpu_mac_sgmii_auto_neg_cfg Definition */ -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_RESTART BIT(1) -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_SPEED_MODE BIT(7) -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LINK_TIMER_CNT BIT(16) -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_MODE BIT(2) -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_REMOTE_LINKUP_EN BIT(25) -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_IGNORE_LINK_FAILURE BIT(5) -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_PARALLEL_DETECT_EN BIT(24) -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_TX_XMIT_LOAD_USE_ASYNC_FIFO BIT(14) -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_EEE_ABILITY BIT(9) -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_ENABLE BIT(0) -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_OFFLINE BIT(6) -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_IGNORE_ANEG_ERR BIT(4) -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_TX_CONFIG_REG_BIT14 BIT(13) -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_EEE_CLK_STOP BIT(10) -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_PAUSE_ABILITY BIT(11) +/* ################################################################################ + * # CpuMacSgmiiAutoNegCfg Definition */ +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_ENABLE_BIT 0 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_MODE_BIT 2 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_PARALLEL_DETECT_EN_BIT 24 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_REMOTE_LINKUP_EN_BIT 25 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_RESTART_BIT 1 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_IGNORE_ANEG_ERR_BIT 4 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_IGNORE_LINK_FAILURE_BIT 5 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LINK_TIMER_CNT_BIT 16 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_EEE_ABILITY_BIT 9 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_EEE_CLK_STOP_BIT 10 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_OFFLINE_BIT 6 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_PAUSE_ABILITY_BIT 11 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_SPEED_MODE_BIT 7 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_TX_CONFIG_REG_BIT14_BIT 13 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_TX_XMIT_LOAD_USE_ASYNC_FIFO_BIT 14 -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_RESTART_MASK 0x00000002 -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_SPEED_MODE_MASK 0x00000180 -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LINK_TIMER_CNT_MASK 0x00ff0000 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_ENABLE_MASK 0x00000001 #define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_MODE_MASK 0x0000000c +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_PARALLEL_DETECT_EN_MASK 0x01000000 #define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_REMOTE_LINKUP_EN_MASK 0x02000000 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_RESTART_MASK 0x00000002 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_IGNORE_ANEG_ERR_MASK 0x00000010 #define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_IGNORE_LINK_FAILURE_MASK 0x00000020 -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_PARALLEL_DETECT_EN_MASK 0x01000000 -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_TX_XMIT_LOAD_USE_ASYNC_FIFO_MASK 0x00004000 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LINK_TIMER_CNT_MASK 0x00ff0000 #define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_EEE_ABILITY_MASK 0x00000200 -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_ENABLE_MASK 0x00000001 -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_OFFLINE_MASK 0x00000040 -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_IGNORE_ANEG_ERR_MASK 0x00000010 -#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_TX_CONFIG_REG_BIT14_MASK 0x00002000 #define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_EEE_CLK_STOP_MASK 0x00000400 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_OFFLINE_MASK 0x00000040 #define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_PAUSE_ABILITY_MASK 0x00001800 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_LOCAL_SPEED_MODE_MASK 0x00000180 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_TX_CONFIG_REG_BIT14_MASK 0x00002000 +#define CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_TX_XMIT_LOAD_USE_ASYNC_FIFO_MASK 0x00004000 -/* cpu_mac_reserved Definition */ -#define CPU_MAC_RESERVED_W0_RESERVED BIT(0) +/* ################################################################################ + * # CpuMacReserved Definition */ +#define CPU_MAC_RESERVED_W0_RESERVED_BIT 0 #define CPU_MAC_RESERVED_W0_RESERVED_MASK 0xffffffff -/* cpu_mac_gmac_mon Definition */ -#define CPU_MAC_GMAC_MON_W0_MON_TX_LPI_STATE BIT(6) -#define CPU_MAC_GMAC_MON_W0_MON_RX_METER_TOKEN BIT(8) -#define CPU_MAC_GMAC_MON_W0_MON_RX_PKT_STATE BIT(0) -#define CPU_MAC_GMAC_MON_W1_GMAC_RX_BUF_FULL_DROP_CNT BIT(20) -#define CPU_MAC_GMAC_MON_W1_GMAC_RX_FILTER_DROP_CNT BIT(24) -#define CPU_MAC_GMAC_MON_W1_MON_TX_LPI_STATUS BIT(0) -#define CPU_MAC_GMAC_MON_W1_MON_RX_BUF_RD_STATE BIT(2) -#define CPU_MAC_GMAC_MON_W1_MON_TX_POP_STATE BIT(5) -#define CPU_MAC_GMAC_MON_W1_GMAC_RX_RUNT_DROP_CNT BIT(16) -#define CPU_MAC_GMAC_MON_W1_MON_TX_STATS_UNDERRUN BIT(1) -#define CPU_MAC_GMAC_MON_W1_MON_RX_PKT_LEN BIT(8) -#define CPU_MAC_GMAC_MON_W1_GMAC_RX_PAUSE_DROP_CNT BIT(28) +/* ################################################################################ + * # CpuMacGmacMon Definition */ +#define CPU_MAC_GMAC_MON_W0_MON_RX_METER_TOKEN_BIT 8 +#define CPU_MAC_GMAC_MON_W0_MON_RX_PKT_STATE_BIT 0 +#define CPU_MAC_GMAC_MON_W0_MON_TX_LPI_STATE_BIT 6 +#define CPU_MAC_GMAC_MON_W1_GMAC_RX_BUF_FULL_DROP_CNT_BIT 20 +#define CPU_MAC_GMAC_MON_W1_GMAC_RX_FILTER_DROP_CNT_BIT 24 +#define CPU_MAC_GMAC_MON_W1_GMAC_RX_PAUSE_DROP_CNT_BIT 28 +#define CPU_MAC_GMAC_MON_W1_GMAC_RX_RUNT_DROP_CNT_BIT 16 +#define CPU_MAC_GMAC_MON_W1_MON_RX_BUF_RD_STATE_BIT 2 +#define CPU_MAC_GMAC_MON_W1_MON_RX_PKT_LEN_BIT 8 +#define CPU_MAC_GMAC_MON_W1_MON_TX_LPI_STATUS_BIT 0 +#define CPU_MAC_GMAC_MON_W1_MON_TX_POP_STATE_BIT 5 +#define CPU_MAC_GMAC_MON_W1_MON_TX_STATS_UNDERRUN_BIT 1 -#define CPU_MAC_GMAC_MON_W0_MON_TX_LPI_STATE_MASK 0x000000c0 #define CPU_MAC_GMAC_MON_W0_MON_RX_METER_TOKEN_MASK 0xffffff00 #define CPU_MAC_GMAC_MON_W0_MON_RX_PKT_STATE_MASK 0x0000000f +#define CPU_MAC_GMAC_MON_W0_MON_TX_LPI_STATE_MASK 0x000000c0 #define CPU_MAC_GMAC_MON_W1_GMAC_RX_BUF_FULL_DROP_CNT_MASK 0x00f00000 #define CPU_MAC_GMAC_MON_W1_GMAC_RX_FILTER_DROP_CNT_MASK 0x0f000000 -#define CPU_MAC_GMAC_MON_W1_MON_TX_LPI_STATUS_MASK 0x00000001 +#define CPU_MAC_GMAC_MON_W1_GMAC_RX_PAUSE_DROP_CNT_MASK 0xf0000000 +#define CPU_MAC_GMAC_MON_W1_GMAC_RX_RUNT_DROP_CNT_MASK 0x000f0000 #define CPU_MAC_GMAC_MON_W1_MON_RX_BUF_RD_STATE_MASK 0x0000001c +#define CPU_MAC_GMAC_MON_W1_MON_RX_PKT_LEN_MASK 0x0000ff00 +#define CPU_MAC_GMAC_MON_W1_MON_TX_LPI_STATUS_MASK 0x00000001 #define CPU_MAC_GMAC_MON_W1_MON_TX_POP_STATE_MASK 0x000000e0 -#define CPU_MAC_GMAC_MON_W1_GMAC_RX_RUNT_DROP_CNT_MASK 0x000f0000 #define CPU_MAC_GMAC_MON_W1_MON_TX_STATS_UNDERRUN_MASK 0x00000002 -#define CPU_MAC_GMAC_MON_W1_MON_RX_PKT_LEN_MASK 0x0000ff00 -#define CPU_MAC_GMAC_MON_W1_GMAC_RX_PAUSE_DROP_CNT_MASK 0xf0000000 -/* cpu_mac_credit_ctl Definition */ -#define CPU_MAC_CREDIT_CTL_W0_CPU_MAC_CPU_RAM_CREDIT_THRD BIT(0) +/* ################################################################################ + * # CpuMacCreditCtl Definition */ +#define CPU_MAC_CREDIT_CTL_W0_CPU_MAC_CPU_RAM_CREDIT_THRD_BIT 0 #define CPU_MAC_CREDIT_CTL_W0_CPU_MAC_CPU_RAM_CREDIT_THRD_MASK 0x000000ff -/* cpu_mac_credit_status Definition */ -#define CPU_MAC_CREDIT_STATUS_W0_CPU_MAC_CPU_RAM_CREDIT_USED BIT(0) +/* ################################################################################ + * # CpuMacCreditStatus Definition */ +#define CPU_MAC_CREDIT_STATUS_W0_CPU_MAC_CPU_RAM_CREDIT_USED_BIT 0 #define CPU_MAC_CREDIT_STATUS_W0_CPU_MAC_CPU_RAM_CREDIT_USED_MASK 0x000000ff -/* cpu_mac_pause_cfg Definition */ -#define CPU_MAC_PAUSE_CFG_W0_CFG_RX_PAUSE_TIMER_ADJ_VALUE BIT(1) -#define CPU_MAC_PAUSE_CFG_W0_CFG_RX_NORM_PAUSE_EN BIT(0) -#define CPU_MAC_PAUSE_CFG_W0_CFG_RX_PAUSE_TIMER_DEC_VALUE BIT(11) -#define CPU_MAC_PAUSE_CFG_W1_CFG_TX_PAUSE_TIMER_ADJ_VALUE BIT(1) -#define CPU_MAC_PAUSE_CFG_W1_CFG_TX_PAUSE_TIMER_DEC_VALUE BIT(18) -#define CPU_MAC_PAUSE_CFG_W1_CFG_TX_PAUSE_EN BIT(0) -#define CPU_MAC_PAUSE_CFG_W2_CFG_TX_PAUSE_MAC_SA_31_0 BIT(0) -#define CPU_MAC_PAUSE_CFG_W3_CFG_TX_PAUSE_MAC_SA_47_32 BIT(0) -#define CPU_MAC_PAUSE_CFG_W3_CFG_TX_PAUSE_QUANTA BIT(16) +/* ################################################################################ + * # CpuMacPauseCfg Definition */ +#define CPU_MAC_PAUSE_CFG_W0_CFG_RX_NORM_PAUSE_EN_BIT 0 +#define CPU_MAC_PAUSE_CFG_W0_CFG_RX_PAUSE_TIMER_ADJ_VALUE_BIT 1 +#define CPU_MAC_PAUSE_CFG_W0_CFG_RX_PAUSE_TIMER_DEC_VALUE_BIT 11 +#define CPU_MAC_PAUSE_CFG_W1_CFG_TX_PAUSE_EN_BIT 0 +#define CPU_MAC_PAUSE_CFG_W1_CFG_TX_PAUSE_TIMER_ADJ_VALUE_BIT 1 +#define CPU_MAC_PAUSE_CFG_W1_CFG_TX_PAUSE_TIMER_DEC_VALUE_BIT 18 +#define CPU_MAC_PAUSE_CFG_W2_CFG_TX_PAUSE_MAC_SA_31_0_BIT 0 +#define CPU_MAC_PAUSE_CFG_W3_CFG_TX_PAUSE_MAC_SA_47_32_BIT 0 +#define CPU_MAC_PAUSE_CFG_W3_CFG_TX_PAUSE_QUANTA_BIT 16 -#define CPU_MAC_PAUSE_CFG_W0_CFG_RX_PAUSE_TIMER_ADJ_VALUE_MASK 0x000007fe #define CPU_MAC_PAUSE_CFG_W0_CFG_RX_NORM_PAUSE_EN_MASK 0x00000001 +#define CPU_MAC_PAUSE_CFG_W0_CFG_RX_PAUSE_TIMER_ADJ_VALUE_MASK 0x000007fe #define CPU_MAC_PAUSE_CFG_W0_CFG_RX_PAUSE_TIMER_DEC_VALUE_MASK 0x0007f800 +#define CPU_MAC_PAUSE_CFG_W1_CFG_TX_PAUSE_EN_MASK 0x00000001 #define CPU_MAC_PAUSE_CFG_W1_CFG_TX_PAUSE_TIMER_ADJ_VALUE_MASK 0x0003fffe #define CPU_MAC_PAUSE_CFG_W1_CFG_TX_PAUSE_TIMER_DEC_VALUE_MASK 0x03fc0000 -#define CPU_MAC_PAUSE_CFG_W1_CFG_TX_PAUSE_EN_MASK 0x00000001 -#define CPU_MAC_PAUSE_CFG_W2_CFG_TX_PAUSE_MAC_SA_31_0_MASK 0x00000001 -#define CPU_MAC_PAUSE_CFG_W3_CFG_TX_PAUSE_MAC_SA_47_32_MASK 0x00000001 +#define CPU_MAC_PAUSE_CFG_W2_CFG_TX_PAUSE_MAC_SA_31_0_MASK 0xffffffff +#define CPU_MAC_PAUSE_CFG_W3_CFG_TX_PAUSE_MAC_SA_47_32_MASK 0x0000ffff #define CPU_MAC_PAUSE_CFG_W3_CFG_TX_PAUSE_QUANTA_MASK 0xffff0000 -/* cpu_mac_pause_mon Definition */ -#define CPU_MAC_PAUSE_MON_W0_MON_TX_PAUSE_TIMER BIT(0) -#define CPU_MAC_PAUSE_MON_W1_MON_RX_PAUSE_TIMER BIT(0) -#define CPU_MAC_PAUSE_MON_W2_MON_TX_PAUSE_CUR_STATUS BIT(0) -#define CPU_MAC_PAUSE_MON_W2_MON_TX_PAUSE_LOG_STATUS BIT(1) +/* ################################################################################ + * # CpuMacPauseMon Definition */ +#define CPU_MAC_PAUSE_MON_W0_MON_TX_PAUSE_TIMER_BIT 0 +#define CPU_MAC_PAUSE_MON_W1_MON_RX_PAUSE_TIMER_BIT 0 +#define CPU_MAC_PAUSE_MON_W2_MON_TX_PAUSE_CUR_STATUS_BIT 0 +#define CPU_MAC_PAUSE_MON_W2_MON_TX_PAUSE_LOG_STATUS_BIT 1 #define CPU_MAC_PAUSE_MON_W0_MON_TX_PAUSE_TIMER_MASK 0x0001ffff #define CPU_MAC_PAUSE_MON_W1_MON_RX_PAUSE_TIMER_MASK 0x0000ffff #define CPU_MAC_PAUSE_MON_W2_MON_TX_PAUSE_CUR_STATUS_MASK 0x00000001 #define CPU_MAC_PAUSE_MON_W2_MON_TX_PAUSE_LOG_STATUS_MASK 0x00000002 -/* cpu_mac_sgmii_cfg Definition */ -#define CPU_MAC_SGMII_CFG_W0_CFG_TX_EVEN_IGNORE BIT(3) -#define CPU_MAC_SGMII_CFG_W0_CFG_TX_IPG_LEN BIT(14) -#define CPU_MAC_SGMII_CFG_W0_CFG_TX_PREAMBLE_LEN BIT(18) -#define CPU_MAC_SGMII_CFG_W0_CFG_UNIDIRECTION_EN BIT(4) -#define CPU_MAC_SGMII_CFG_W0_CFG_MII_RX_CHK_LINK_FOR_SOP BIT(31) -#define CPU_MAC_SGMII_CFG_W0_CFG_FORCE_RELOCK BIT(0) -#define CPU_MAC_SGMII_CFG_W0_CFG_FORCE_SIGNAL_DETECT BIT(1) -#define CPU_MAC_SGMII_CFG_W0_CFG_TX_REPLICATE_CNT BIT(22) -#define CPU_MAC_SGMII_CFG_W0_CFG_MII_RX_LINK_FILTER_TIMER BIT(6) -#define CPU_MAC_SGMII_CFG_W0_CFG_SIG_DET_ACTIVE_VALUE BIT(2) -#define CPU_MAC_SGMII_CFG_W0_CFG_MII_RX_LINK_FILTER_EN BIT(5) -#define CPU_MAC_SGMII_CFG_W1_CFG_MII_RX_SAMPLE_CNT BIT(22) -#define CPU_MAC_SGMII_CFG_W1_CFG_TX_THRESHOLD BIT(0) -#define CPU_MAC_SGMII_CFG_W1_CFG_MII_TX_A_FULL_THRD BIT(5) +/* ################################################################################ + * # CpuMacSgmiiCfg Definition */ +#define CPU_MAC_SGMII_CFG_W0_CFG_FORCE_RELOCK_BIT 0 +#define CPU_MAC_SGMII_CFG_W0_CFG_FORCE_SIGNAL_DETECT_BIT 1 +#define CPU_MAC_SGMII_CFG_W0_CFG_MII_RX_CHK_LINK_FOR_SOP_BIT 31 +#define CPU_MAC_SGMII_CFG_W0_CFG_MII_RX_LINK_FILTER_EN_BIT 5 +#define CPU_MAC_SGMII_CFG_W0_CFG_MII_RX_LINK_FILTER_TIMER_BIT 6 +#define CPU_MAC_SGMII_CFG_W0_CFG_SIG_DET_ACTIVE_VALUE_BIT 2 +#define CPU_MAC_SGMII_CFG_W0_CFG_TX_EVEN_IGNORE_BIT 3 +#define CPU_MAC_SGMII_CFG_W0_CFG_TX_IPG_LEN_BIT 14 +#define CPU_MAC_SGMII_CFG_W0_CFG_TX_PREAMBLE_LEN_BIT 18 +#define CPU_MAC_SGMII_CFG_W0_CFG_TX_REPLICATE_CNT_BIT 22 +#define CPU_MAC_SGMII_CFG_W0_CFG_UNIDIRECTION_EN_BIT 4 +#define CPU_MAC_SGMII_CFG_W1_CFG_MII_RX_SAMPLE_CNT_BIT 22 +#define CPU_MAC_SGMII_CFG_W1_CFG_MII_TX_A_FULL_THRD_BIT 5 +#define CPU_MAC_SGMII_CFG_W1_CFG_TX_THRESHOLD_BIT 0 -#define CPU_MAC_SGMII_CFG_W0_CFG_TX_EVEN_IGNORE_MASK 0x00000008 -#define CPU_MAC_SGMII_CFG_W0_CFG_TX_IPG_LEN_MASK 0x0003c000 -#define CPU_MAC_SGMII_CFG_W0_CFG_TX_PREAMBLE_LEN_MASK 0x003c0000 -#define CPU_MAC_SGMII_CFG_W0_CFG_UNIDIRECTION_EN_MASK 0x00000010 -#define CPU_MAC_SGMII_CFG_W0_CFG_MII_RX_CHK_LINK_FOR_SOP_MASK 0x80000000 #define CPU_MAC_SGMII_CFG_W0_CFG_FORCE_RELOCK_MASK 0x00000001 #define CPU_MAC_SGMII_CFG_W0_CFG_FORCE_SIGNAL_DETECT_MASK 0x00000002 -#define CPU_MAC_SGMII_CFG_W0_CFG_TX_REPLICATE_CNT_MASK 0x1fc00000 +#define CPU_MAC_SGMII_CFG_W0_CFG_MII_RX_CHK_LINK_FOR_SOP_MASK 0x80000000 +#define CPU_MAC_SGMII_CFG_W0_CFG_MII_RX_LINK_FILTER_EN_MASK 0x00000020 #define CPU_MAC_SGMII_CFG_W0_CFG_MII_RX_LINK_FILTER_TIMER_MASK 0x00003fc0 #define CPU_MAC_SGMII_CFG_W0_CFG_SIG_DET_ACTIVE_VALUE_MASK 0x00000004 -#define CPU_MAC_SGMII_CFG_W0_CFG_MII_RX_LINK_FILTER_EN_MASK 0x00000020 +#define CPU_MAC_SGMII_CFG_W0_CFG_TX_EVEN_IGNORE_MASK 0x00000008 +#define CPU_MAC_SGMII_CFG_W0_CFG_TX_IPG_LEN_MASK 0x0003c000 +#define CPU_MAC_SGMII_CFG_W0_CFG_TX_PREAMBLE_LEN_MASK 0x003c0000 +#define CPU_MAC_SGMII_CFG_W0_CFG_TX_REPLICATE_CNT_MASK 0x1fc00000 +#define CPU_MAC_SGMII_CFG_W0_CFG_UNIDIRECTION_EN_MASK 0x00000010 #define CPU_MAC_SGMII_CFG_W1_CFG_MII_RX_SAMPLE_CNT_MASK 0x1fc00000 -#define CPU_MAC_SGMII_CFG_W1_CFG_TX_THRESHOLD_MASK 0x0000001f #define CPU_MAC_SGMII_CFG_W1_CFG_MII_TX_A_FULL_THRD_MASK 0x000003e0 +#define CPU_MAC_SGMII_CFG_W1_CFG_TX_THRESHOLD_MASK 0x0000001f -/* cpu_mac_sgmii_mon Definition */ -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_CODE_STATE BIT(23) -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_SOP_FLAG BIT(18) -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_EOP_FLAG BIT(19) -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_EOP_FLAG BIT(9) -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_SFD_FLAG BIT(11) -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_LPI_STATE BIT(20) -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_LPI_STATE BIT(12) -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_PKT_STATE BIT(15) -#define CPU_MAC_SGMII_MON_W0_MON_ANEG_STATE BIT(0) -#define CPU_MAC_SGMII_MON_W0_MON_CODE_ERR_CNT BIT(4) -#define CPU_MAC_SGMII_MON_W0_MON_LINK_STATUS BIT(8) -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_SOP_FLAG BIT(10) -#define CPU_MAC_SGMII_MON_W1_MON_AN_RX_REMOTE_CFG BIT(0) +/* ################################################################################ + * # CpuMacSgmiiMon Definition */ +#define CPU_MAC_SGMII_MON_W0_MON_ANEG_STATE_BIT 0 +#define CPU_MAC_SGMII_MON_W0_MON_CODE_ERR_CNT_BIT 4 +#define CPU_MAC_SGMII_MON_W0_MON_LINK_STATUS_BIT 8 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_EOP_FLAG_BIT 9 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_LPI_STATE_BIT 12 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_PKT_STATE_BIT 15 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_SFD_FLAG_BIT 11 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_SOP_FLAG_BIT 10 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_CODE_STATE_BIT 23 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_EOP_FLAG_BIT 19 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_LPI_STATE_BIT 20 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_SOP_FLAG_BIT 18 +#define CPU_MAC_SGMII_MON_W1_MON_AN_RX_REMOTE_CFG_BIT 0 -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_CODE_STATE_MASK 0x03800000 -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_SOP_FLAG_MASK 0x00040000 -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_EOP_FLAG_MASK 0x00080000 -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_EOP_FLAG_MASK 0x00000200 -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_SFD_FLAG_MASK 0x00000800 -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_LPI_STATE_MASK 0x00700000 -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_LPI_STATE_MASK 0x00007000 -#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_PKT_STATE_MASK 0x00038000 #define CPU_MAC_SGMII_MON_W0_MON_ANEG_STATE_MASK 0x00000007 #define CPU_MAC_SGMII_MON_W0_MON_CODE_ERR_CNT_MASK 0x000000f0 #define CPU_MAC_SGMII_MON_W0_MON_LINK_STATUS_MASK 0x00000100 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_EOP_FLAG_MASK 0x00000200 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_LPI_STATE_MASK 0x00007000 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_PKT_STATE_MASK 0x00038000 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_SFD_FLAG_MASK 0x00000800 #define CPU_MAC_SGMII_MON_W0_MON_SGMII_RX_SOP_FLAG_MASK 0x00000400 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_CODE_STATE_MASK 0x03800000 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_EOP_FLAG_MASK 0x00080000 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_LPI_STATE_MASK 0x00700000 +#define CPU_MAC_SGMII_MON_W0_MON_SGMII_TX_SOP_FLAG_MASK 0x00040000 #define CPU_MAC_SGMII_MON_W1_MON_AN_RX_REMOTE_CFG_MASK 0x0000ffff -/* cpu_mac_stats_cfg Definition */ -#define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS64_B_PKT_HI_PRI BIT(4) -#define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS_INCR_SATURATE BIT(1) -#define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS_INCR_HOLD BIT(2) -#define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS_CLEAR_ON_READ BIT(0) -#define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS_OVER_WRITE_EN BIT(3) -#define CPU_MAC_STATS_CFG_W1_CFG_GMAC_STATS_MTU1 BIT(0) -#define CPU_MAC_STATS_CFG_W1_CFG_GMAC_STATS_MTU2 BIT(16) +/* ################################################################################ + * # CpuMacStatsCfg Definition */ +#define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS64_B_PKT_HI_PRI_BIT 4 +#define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS_CLEAR_ON_READ_BIT 0 +#define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS_INCR_HOLD_BIT 2 +#define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS_INCR_SATURATE_BIT 1 +#define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS_OVER_WRITE_EN_BIT 3 +#define CPU_MAC_STATS_CFG_W1_CFG_GMAC_STATS_MTU1_BIT 0 +#define CPU_MAC_STATS_CFG_W1_CFG_GMAC_STATS_MTU2_BIT 16 #define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS64_B_PKT_HI_PRI_MASK 0x00000010 -#define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS_INCR_SATURATE_MASK 0x00000002 -#define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS_INCR_HOLD_MASK 0x00000004 #define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS_CLEAR_ON_READ_MASK 0x00000001 +#define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS_INCR_HOLD_MASK 0x00000004 +#define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS_INCR_SATURATE_MASK 0x00000002 #define CPU_MAC_STATS_CFG_W0_CFG_GMAC_STATS_OVER_WRITE_EN_MASK 0x00000008 #define CPU_MAC_STATS_CFG_W1_CFG_GMAC_STATS_MTU1_MASK 0x00003fff #define CPU_MAC_STATS_CFG_W1_CFG_GMAC_STATS_MTU2_MASK 0x3fff0000 -/* cpu_mac_interrupt_func Definition */ -#define CPU_MAC_INTERRUPT_FUNC_W0_VALUE_SET0_CPU_MAC_INTERRUPT_FUNC BIT(0) -#define CPU_MAC_INTERRUPT_FUNC_W1_VALUE_RESET0_CPU_MAC_INTERRUPT_FUNC BIT(0) -#define CPU_MAC_INTERRUPT_FUNC_W2_MASK_SET0_CPU_MAC_INTERRUPT_FUNC BIT(0) -#define CPU_MAC_INTERRUPT_FUNC_W3_MASK_RESET0_CPU_MAC_INTERRUPT_FUNC BIT(0) +/* ################################################################################ + * # CpuMacInterruptFunc Definition */ +#define CPU_MAC_INTERRUPT_FUNC_W0_VALUE_SET0_CPU_MAC_INTERRUPT_FUNC_BIT 0 +#define CPU_MAC_INTERRUPT_FUNC_W1_VALUE_RESET0_CPU_MAC_INTERRUPT_FUNC_BIT 0 +#define CPU_MAC_INTERRUPT_FUNC_W2_MASK_SET0_CPU_MAC_INTERRUPT_FUNC_BIT 0 +#define CPU_MAC_INTERRUPT_FUNC_W3_MASK_RESET0_CPU_MAC_INTERRUPT_FUNC_BIT 0 #define CPU_MAC_INTERRUPT_FUNC_W0_VALUE_SET0_CPU_MAC_INTERRUPT_FUNC_MASK 0x000000ff #define CPU_MAC_INTERRUPT_FUNC_W1_VALUE_RESET0_CPU_MAC_INTERRUPT_FUNC_MASK 0x000000ff #define CPU_MAC_INTERRUPT_FUNC_W2_MASK_SET0_CPU_MAC_INTERRUPT_FUNC_MASK 0x000000ff #define CPU_MAC_INTERRUPT_FUNC_W3_MASK_RESET0_CPU_MAC_INTERRUPT_FUNC_MASK 0x000000ff -/* cpu_mac_interrupt_normal Definition */ -#define CPU_MAC_INTERRUPT_NORMAL_W0_VALUE_SET0_CPU_MAC_INTERRUPT_NORMAL BIT(0) -#define CPU_MAC_INTERRUPT_NORMAL_W1_VALUE_RESET0_CPU_MAC_INTERRUPT_NORMAL BIT(0) -#define CPU_MAC_INTERRUPT_NORMAL_W2_MASK_SET0_CPU_MAC_INTERRUPT_NORMAL BIT(0) -#define CPU_MAC_INTERRUPT_NORMAL_W3_MASK_RESET0_CPU_MAC_INTERRUPT_NORMAL BIT(0) +/* ################################################################################ + * # CpuMacInterruptNormal Definition */ +#define CPU_MAC_INTERRUPT_NORMAL_W0_VALUE_SET0_CPU_MAC_INTERRUPT_NORMAL_BIT 0 +#define CPU_MAC_INTERRUPT_NORMAL_W1_VALUE_RESET0_CPU_MAC_INTERRUPT_NORMAL_BIT 0 +#define CPU_MAC_INTERRUPT_NORMAL_W2_MASK_SET0_CPU_MAC_INTERRUPT_NORMAL_BIT 0 +#define CPU_MAC_INTERRUPT_NORMAL_W3_MASK_RESET0_CPU_MAC_INTERRUPT_NORMAL_BIT 0 #define CPU_MAC_INTERRUPT_NORMAL_W0_VALUE_SET0_CPU_MAC_INTERRUPT_NORMAL_MASK 0xffffffff #define CPU_MAC_INTERRUPT_NORMAL_W1_VALUE_RESET0_CPU_MAC_INTERRUPT_NORMAL_MASK 0xffffffff #define CPU_MAC_INTERRUPT_NORMAL_W2_MASK_SET0_CPU_MAC_INTERRUPT_NORMAL_MASK 0xffffffff #define CPU_MAC_INTERRUPT_NORMAL_W3_MASK_RESET0_CPU_MAC_INTERRUPT_NORMAL_MASK 0xffffffff -/* cpu_mac_fifo_status Definition */ -#define CPU_MAC_FIFO_STATUS_W0_RX_PKT_MSG_FIFO_FIFO_DEPTH BIT(0) -#define CPU_MAC_FIFO_STATUS_W0_RX_PKT_DATA_FIFO_FIFO_DEPTH BIT(20) -#define CPU_MAC_FIFO_STATUS_W0_TX_DESC_ACK_FIFO_FIFO_DEPTH BIT(10) -#define CPU_MAC_FIFO_STATUS_W0_EXT_RAM_RD_TRACK_FIFO_FIFO_DEPTH BIT(16) -#define CPU_MAC_FIFO_STATUS_W1_RX_DESC0_ACK_FIFO_FIFO_DEPTH BIT(12) -#define CPU_MAC_FIFO_STATUS_W1_RX_DESC1_CFG_FIFO_FIFO_DEPTH BIT(18) -#define CPU_MAC_FIFO_STATUS_W1_RX_DESC0_CFG_FIFO_FIFO_DEPTH BIT(6) -#define CPU_MAC_FIFO_STATUS_W1_RX_DESC1_ACK_FIFO_FIFO_DEPTH BIT(24) -#define CPU_MAC_FIFO_STATUS_W1_TX_DESC_CFG_FIFO_FIFO_DEPTH BIT(0) -#define CPU_MAC_FIFO_STATUS_W2_TX_PKT_FIFO_FIFO_DEPTH BIT(16) -#define CPU_MAC_FIFO_STATUS_W2_RX_PKT_FIFO_FIFO_DEPTH BIT(0) +/* ################################################################################ + * # CpuMacFifoStatus Definition */ +#define CPU_MAC_FIFO_STATUS_W0_EXT_RAM_RD_TRACK_FIFO_FIFO_DEPTH_BIT 16 +#define CPU_MAC_FIFO_STATUS_W0_RX_PKT_DATA_FIFO_FIFO_DEPTH_BIT 20 +#define CPU_MAC_FIFO_STATUS_W0_RX_PKT_MSG_FIFO_FIFO_DEPTH_BIT 0 +#define CPU_MAC_FIFO_STATUS_W0_TX_DESC_ACK_FIFO_FIFO_DEPTH_BIT 10 +#define CPU_MAC_FIFO_STATUS_W1_RX_DESC0_ACK_FIFO_FIFO_DEPTH_BIT 12 +#define CPU_MAC_FIFO_STATUS_W1_RX_DESC0_CFG_FIFO_FIFO_DEPTH_BIT 6 +#define CPU_MAC_FIFO_STATUS_W1_RX_DESC1_ACK_FIFO_FIFO_DEPTH_BIT 24 +#define CPU_MAC_FIFO_STATUS_W1_RX_DESC1_CFG_FIFO_FIFO_DEPTH_BIT 18 +#define CPU_MAC_FIFO_STATUS_W1_TX_DESC_CFG_FIFO_FIFO_DEPTH_BIT 0 +#define CPU_MAC_FIFO_STATUS_W2_RX_PKT_FIFO_FIFO_DEPTH_BIT 0 +#define CPU_MAC_FIFO_STATUS_W2_TX_PKT_FIFO_FIFO_DEPTH_BIT 16 -#define CPU_MAC_FIFO_STATUS_W0_RX_PKT_MSG_FIFO_FIFO_DEPTH_MASK 0x000003ff +#define CPU_MAC_FIFO_STATUS_W0_EXT_RAM_RD_TRACK_FIFO_FIFO_DEPTH_MASK 0x000f0000 #define CPU_MAC_FIFO_STATUS_W0_RX_PKT_DATA_FIFO_FIFO_DEPTH_MASK 0xfff00000 +#define CPU_MAC_FIFO_STATUS_W0_RX_PKT_MSG_FIFO_FIFO_DEPTH_MASK 0x000003ff #define CPU_MAC_FIFO_STATUS_W0_TX_DESC_ACK_FIFO_FIFO_DEPTH_MASK 0x0000fc00 -#define CPU_MAC_FIFO_STATUS_W0_EXT_RAM_RD_TRACK_FIFO_FIFO_DEPTH_MASK 0x000f0000 #define CPU_MAC_FIFO_STATUS_W1_RX_DESC0_ACK_FIFO_FIFO_DEPTH_MASK 0x0003f000 -#define CPU_MAC_FIFO_STATUS_W1_RX_DESC1_CFG_FIFO_FIFO_DEPTH_MASK 0x00fc0000 #define CPU_MAC_FIFO_STATUS_W1_RX_DESC0_CFG_FIFO_FIFO_DEPTH_MASK 0x00000fc0 #define CPU_MAC_FIFO_STATUS_W1_RX_DESC1_ACK_FIFO_FIFO_DEPTH_MASK 0x3f000000 +#define CPU_MAC_FIFO_STATUS_W1_RX_DESC1_CFG_FIFO_FIFO_DEPTH_MASK 0x00fc0000 #define CPU_MAC_FIFO_STATUS_W1_TX_DESC_CFG_FIFO_FIFO_DEPTH_MASK 0x0000003f -#define CPU_MAC_FIFO_STATUS_W2_TX_PKT_FIFO_FIFO_DEPTH_MASK 0x03ff0000 #define CPU_MAC_FIFO_STATUS_W2_RX_PKT_FIFO_FIFO_DEPTH_MASK 0x000003ff +#define CPU_MAC_FIFO_STATUS_W2_TX_PKT_FIFO_FIFO_DEPTH_MASK 0x03ff0000 -struct cpu_mac_mems { - u32 tx_pkt_fifo_0[3]; /* 0x00004000 */ - u32 tx_pkt_fifo_0_rsv3; - u32 tx_pkt_fifo_1[3]; /* 0x00004010 */ - u32 tx_pkt_fifo_1_rsv3; - u32 tx_pkt_fifo_2[3]; /* 0x00004020 */ - u32 tx_pkt_fifo_2_rsv3; - u32 tx_pkt_fifo_3[3]; /* 0x00004030 */ - u32 tx_pkt_fifo_3_rsv3; - u32 tx_pkt_fifo_4[3]; /* 0x00004040 */ - u32 tx_pkt_fifo_4_rsv3; - u32 tx_pkt_fifo_5[3]; /* 0x00004050 */ - u32 tx_pkt_fifo_5_rsv3; - u32 tx_pkt_fifo_6[3]; /* 0x00004060 */ - u32 tx_pkt_fifo_6_rsv3; - u32 tx_pkt_fifo_7[3]; /* 0x00004070 */ - u32 tx_pkt_fifo_7_rsv3; - u32 tx_pkt_fifo_8[3]; /* 0x00004080 */ - u32 tx_pkt_fifo_8_rsv3; - u32 tx_pkt_fifo_9[3]; /* 0x00004090 */ - u32 tx_pkt_fifo_9_rsv3; - u32 tx_pkt_fifo_10[3]; /* 0x000040a0 */ - u32 tx_pkt_fifo_10_rsv3; - u32 tx_pkt_fifo_11[3]; /* 0x000040b0 */ - u32 tx_pkt_fifo_11_rsv3; - u32 tx_pkt_fifo_12[3]; /* 0x000040c0 */ - u32 tx_pkt_fifo_12_rsv3; - u32 tx_pkt_fifo_13[3]; /* 0x000040d0 */ - u32 tx_pkt_fifo_13_rsv3; - u32 tx_pkt_fifo_14[3]; /* 0x000040e0 */ - u32 tx_pkt_fifo_14_rsv3; - u32 tx_pkt_fifo_15[3]; /* 0x000040f0 */ - u32 tx_pkt_fifo_15_rsv3; - u32 tx_pkt_fifo_16[3]; /* 0x00004100 */ - u32 tx_pkt_fifo_16_rsv3; - u32 tx_pkt_fifo_17[3]; /* 0x00004110 */ - u32 tx_pkt_fifo_17_rsv3; - u32 tx_pkt_fifo_18[3]; /* 0x00004120 */ - u32 tx_pkt_fifo_18_rsv3; - u32 tx_pkt_fifo_19[3]; /* 0x00004130 */ - u32 tx_pkt_fifo_19_rsv3; - u32 tx_pkt_fifo_20[3]; /* 0x00004140 */ - u32 tx_pkt_fifo_20_rsv3; - u32 tx_pkt_fifo_21[3]; /* 0x00004150 */ - u32 tx_pkt_fifo_21_rsv3; - u32 tx_pkt_fifo_22[3]; /* 0x00004160 */ - u32 tx_pkt_fifo_22_rsv3; - u32 tx_pkt_fifo_23[3]; /* 0x00004170 */ - u32 tx_pkt_fifo_23_rsv3; - u32 tx_pkt_fifo_24[3]; /* 0x00004180 */ - u32 tx_pkt_fifo_24_rsv3; - u32 tx_pkt_fifo_25[3]; /* 0x00004190 */ - u32 tx_pkt_fifo_25_rsv3; - u32 tx_pkt_fifo_26[3]; /* 0x000041a0 */ - u32 tx_pkt_fifo_26_rsv3; - u32 tx_pkt_fifo_27[3]; /* 0x000041b0 */ - u32 tx_pkt_fifo_27_rsv3; - u32 tx_pkt_fifo_28[3]; /* 0x000041c0 */ - u32 tx_pkt_fifo_28_rsv3; - u32 tx_pkt_fifo_29[3]; /* 0x000041d0 */ - u32 tx_pkt_fifo_29_rsv3; - u32 tx_pkt_fifo_30[3]; /* 0x000041e0 */ - u32 tx_pkt_fifo_30_rsv3; - u32 tx_pkt_fifo_31[3]; /* 0x000041f0 */ - u32 tx_pkt_fifo_31_rsv3; - u32 tx_pkt_fifo_32[3]; /* 0x00004200 */ - u32 tx_pkt_fifo_32_rsv3; - u32 tx_pkt_fifo_33[3]; /* 0x00004210 */ - u32 tx_pkt_fifo_33_rsv3; - u32 tx_pkt_fifo_34[3]; /* 0x00004220 */ - u32 tx_pkt_fifo_34_rsv3; - u32 tx_pkt_fifo_35[3]; /* 0x00004230 */ - u32 tx_pkt_fifo_35_rsv3; - u32 tx_pkt_fifo_36[3]; /* 0x00004240 */ - u32 tx_pkt_fifo_36_rsv3; - u32 tx_pkt_fifo_37[3]; /* 0x00004250 */ - u32 tx_pkt_fifo_37_rsv3; - u32 tx_pkt_fifo_38[3]; /* 0x00004260 */ - u32 tx_pkt_fifo_38_rsv3; - u32 tx_pkt_fifo_39[3]; /* 0x00004270 */ - u32 tx_pkt_fifo_39_rsv3; - u32 tx_pkt_fifo_40[3]; /* 0x00004280 */ - u32 tx_pkt_fifo_40_rsv3; - u32 tx_pkt_fifo_41[3]; /* 0x00004290 */ - u32 tx_pkt_fifo_41_rsv3; - u32 tx_pkt_fifo_42[3]; /* 0x000042a0 */ - u32 tx_pkt_fifo_42_rsv3; - u32 tx_pkt_fifo_43[3]; /* 0x000042b0 */ - u32 tx_pkt_fifo_43_rsv3; - u32 tx_pkt_fifo_44[3]; /* 0x000042c0 */ - u32 tx_pkt_fifo_44_rsv3; - u32 tx_pkt_fifo_45[3]; /* 0x000042d0 */ - u32 tx_pkt_fifo_45_rsv3; - u32 tx_pkt_fifo_46[3]; /* 0x000042e0 */ - u32 tx_pkt_fifo_46_rsv3; - u32 tx_pkt_fifo_47[3]; /* 0x000042f0 */ - u32 tx_pkt_fifo_47_rsv3; - u32 tx_pkt_fifo_48[3]; /* 0x00004300 */ - u32 tx_pkt_fifo_48_rsv3; - u32 tx_pkt_fifo_49[3]; /* 0x00004310 */ - u32 tx_pkt_fifo_49_rsv3; - u32 tx_pkt_fifo_50[3]; /* 0x00004320 */ - u32 tx_pkt_fifo_50_rsv3; - u32 tx_pkt_fifo_51[3]; /* 0x00004330 */ - u32 tx_pkt_fifo_51_rsv3; - u32 tx_pkt_fifo_52[3]; /* 0x00004340 */ - u32 tx_pkt_fifo_52_rsv3; - u32 tx_pkt_fifo_53[3]; /* 0x00004350 */ - u32 tx_pkt_fifo_53_rsv3; - u32 tx_pkt_fifo_54[3]; /* 0x00004360 */ - u32 tx_pkt_fifo_54_rsv3; - u32 tx_pkt_fifo_55[3]; /* 0x00004370 */ - u32 tx_pkt_fifo_55_rsv3; - u32 tx_pkt_fifo_56[3]; /* 0x00004380 */ - u32 tx_pkt_fifo_56_rsv3; - u32 tx_pkt_fifo_57[3]; /* 0x00004390 */ - u32 tx_pkt_fifo_57_rsv3; - u32 tx_pkt_fifo_58[3]; /* 0x000043a0 */ - u32 tx_pkt_fifo_58_rsv3; - u32 tx_pkt_fifo_59[3]; /* 0x000043b0 */ - u32 tx_pkt_fifo_59_rsv3; - u32 tx_pkt_fifo_60[3]; /* 0x000043c0 */ - u32 tx_pkt_fifo_60_rsv3; - u32 tx_pkt_fifo_61[3]; /* 0x000043d0 */ - u32 tx_pkt_fifo_61_rsv3; - u32 tx_pkt_fifo_62[3]; /* 0x000043e0 */ - u32 tx_pkt_fifo_62_rsv3; - u32 tx_pkt_fifo_63[3]; /* 0x000043f0 */ - u32 tx_pkt_fifo_63_rsv3; - u32 tx_pkt_fifo_64[3]; /* 0x00004400 */ - u32 tx_pkt_fifo_64_rsv3; - u32 tx_pkt_fifo_65[3]; /* 0x00004410 */ - u32 tx_pkt_fifo_65_rsv3; - u32 tx_pkt_fifo_66[3]; /* 0x00004420 */ - u32 tx_pkt_fifo_66_rsv3; - u32 tx_pkt_fifo_67[3]; /* 0x00004430 */ - u32 tx_pkt_fifo_67_rsv3; - u32 tx_pkt_fifo_68[3]; /* 0x00004440 */ - u32 tx_pkt_fifo_68_rsv3; - u32 tx_pkt_fifo_69[3]; /* 0x00004450 */ - u32 tx_pkt_fifo_69_rsv3; - u32 tx_pkt_fifo_70[3]; /* 0x00004460 */ - u32 tx_pkt_fifo_70_rsv3; - u32 tx_pkt_fifo_71[3]; /* 0x00004470 */ - u32 tx_pkt_fifo_71_rsv3; - u32 tx_pkt_fifo_72[3]; /* 0x00004480 */ - u32 tx_pkt_fifo_72_rsv3; - u32 tx_pkt_fifo_73[3]; /* 0x00004490 */ - u32 tx_pkt_fifo_73_rsv3; - u32 tx_pkt_fifo_74[3]; /* 0x000044a0 */ - u32 tx_pkt_fifo_74_rsv3; - u32 tx_pkt_fifo_75[3]; /* 0x000044b0 */ - u32 tx_pkt_fifo_75_rsv3; - u32 tx_pkt_fifo_76[3]; /* 0x000044c0 */ - u32 tx_pkt_fifo_76_rsv3; - u32 tx_pkt_fifo_77[3]; /* 0x000044d0 */ - u32 tx_pkt_fifo_77_rsv3; - u32 tx_pkt_fifo_78[3]; /* 0x000044e0 */ - u32 tx_pkt_fifo_78_rsv3; - u32 tx_pkt_fifo_79[3]; /* 0x000044f0 */ - u32 tx_pkt_fifo_79_rsv3; - u32 tx_pkt_fifo_80[3]; /* 0x00004500 */ - u32 tx_pkt_fifo_80_rsv3; - u32 tx_pkt_fifo_81[3]; /* 0x00004510 */ - u32 tx_pkt_fifo_81_rsv3; - u32 tx_pkt_fifo_82[3]; /* 0x00004520 */ - u32 tx_pkt_fifo_82_rsv3; - u32 tx_pkt_fifo_83[3]; /* 0x00004530 */ - u32 tx_pkt_fifo_83_rsv3; - u32 tx_pkt_fifo_84[3]; /* 0x00004540 */ - u32 tx_pkt_fifo_84_rsv3; - u32 tx_pkt_fifo_85[3]; /* 0x00004550 */ - u32 tx_pkt_fifo_85_rsv3; - u32 tx_pkt_fifo_86[3]; /* 0x00004560 */ - u32 tx_pkt_fifo_86_rsv3; - u32 tx_pkt_fifo_87[3]; /* 0x00004570 */ - u32 tx_pkt_fifo_87_rsv3; - u32 tx_pkt_fifo_88[3]; /* 0x00004580 */ - u32 tx_pkt_fifo_88_rsv3; - u32 tx_pkt_fifo_89[3]; /* 0x00004590 */ - u32 tx_pkt_fifo_89_rsv3; - u32 tx_pkt_fifo_90[3]; /* 0x000045a0 */ - u32 tx_pkt_fifo_90_rsv3; - u32 tx_pkt_fifo_91[3]; /* 0x000045b0 */ - u32 tx_pkt_fifo_91_rsv3; - u32 tx_pkt_fifo_92[3]; /* 0x000045c0 */ - u32 tx_pkt_fifo_92_rsv3; - u32 tx_pkt_fifo_93[3]; /* 0x000045d0 */ - u32 tx_pkt_fifo_93_rsv3; - u32 tx_pkt_fifo_94[3]; /* 0x000045e0 */ - u32 tx_pkt_fifo_94_rsv3; - u32 tx_pkt_fifo_95[3]; /* 0x000045f0 */ - u32 tx_pkt_fifo_95_rsv3; - u32 tx_pkt_fifo_96[3]; /* 0x00004600 */ - u32 tx_pkt_fifo_96_rsv3; - u32 tx_pkt_fifo_97[3]; /* 0x00004610 */ - u32 tx_pkt_fifo_97_rsv3; - u32 tx_pkt_fifo_98[3]; /* 0x00004620 */ - u32 tx_pkt_fifo_98_rsv3; - u32 tx_pkt_fifo_99[3]; /* 0x00004630 */ - u32 tx_pkt_fifo_99_rsv3; - u32 tx_pkt_fifo_100[3]; /* 0x00004640 */ - u32 tx_pkt_fifo_100_rsv3; - u32 tx_pkt_fifo_101[3]; /* 0x00004650 */ - u32 tx_pkt_fifo_101_rsv3; - u32 tx_pkt_fifo_102[3]; /* 0x00004660 */ - u32 tx_pkt_fifo_102_rsv3; - u32 tx_pkt_fifo_103[3]; /* 0x00004670 */ - u32 tx_pkt_fifo_103_rsv3; - u32 tx_pkt_fifo_104[3]; /* 0x00004680 */ - u32 tx_pkt_fifo_104_rsv3; - u32 tx_pkt_fifo_105[3]; /* 0x00004690 */ - u32 tx_pkt_fifo_105_rsv3; - u32 tx_pkt_fifo_106[3]; /* 0x000046a0 */ - u32 tx_pkt_fifo_106_rsv3; - u32 tx_pkt_fifo_107[3]; /* 0x000046b0 */ - u32 tx_pkt_fifo_107_rsv3; - u32 tx_pkt_fifo_108[3]; /* 0x000046c0 */ - u32 tx_pkt_fifo_108_rsv3; - u32 tx_pkt_fifo_109[3]; /* 0x000046d0 */ - u32 tx_pkt_fifo_109_rsv3; - u32 tx_pkt_fifo_110[3]; /* 0x000046e0 */ - u32 tx_pkt_fifo_110_rsv3; - u32 tx_pkt_fifo_111[3]; /* 0x000046f0 */ - u32 tx_pkt_fifo_111_rsv3; - u32 tx_pkt_fifo_112[3]; /* 0x00004700 */ - u32 tx_pkt_fifo_112_rsv3; - u32 tx_pkt_fifo_113[3]; /* 0x00004710 */ - u32 tx_pkt_fifo_113_rsv3; - u32 tx_pkt_fifo_114[3]; /* 0x00004720 */ - u32 tx_pkt_fifo_114_rsv3; - u32 tx_pkt_fifo_115[3]; /* 0x00004730 */ - u32 tx_pkt_fifo_115_rsv3; - u32 tx_pkt_fifo_116[3]; /* 0x00004740 */ - u32 tx_pkt_fifo_116_rsv3; - u32 tx_pkt_fifo_117[3]; /* 0x00004750 */ - u32 tx_pkt_fifo_117_rsv3; - u32 tx_pkt_fifo_118[3]; /* 0x00004760 */ - u32 tx_pkt_fifo_118_rsv3; - u32 tx_pkt_fifo_119[3]; /* 0x00004770 */ - u32 tx_pkt_fifo_119_rsv3; - u32 tx_pkt_fifo_120[3]; /* 0x00004780 */ - u32 tx_pkt_fifo_120_rsv3; - u32 tx_pkt_fifo_121[3]; /* 0x00004790 */ - u32 tx_pkt_fifo_121_rsv3; - u32 tx_pkt_fifo_122[3]; /* 0x000047a0 */ - u32 tx_pkt_fifo_122_rsv3; - u32 tx_pkt_fifo_123[3]; /* 0x000047b0 */ - u32 tx_pkt_fifo_123_rsv3; - u32 tx_pkt_fifo_124[3]; /* 0x000047c0 */ - u32 tx_pkt_fifo_124_rsv3; - u32 tx_pkt_fifo_125[3]; /* 0x000047d0 */ - u32 tx_pkt_fifo_125_rsv3; - u32 tx_pkt_fifo_126[3]; /* 0x000047e0 */ - u32 tx_pkt_fifo_126_rsv3; - u32 tx_pkt_fifo_127[3]; /* 0x000047f0 */ - u32 tx_pkt_fifo_127_rsv3; - u32 tx_pkt_fifo_128[3]; /* 0x00004800 */ - u32 tx_pkt_fifo_128_rsv3; - u32 tx_pkt_fifo_129[3]; /* 0x00004810 */ - u32 tx_pkt_fifo_129_rsv3; - u32 tx_pkt_fifo_130[3]; /* 0x00004820 */ - u32 tx_pkt_fifo_130_rsv3; - u32 tx_pkt_fifo_131[3]; /* 0x00004830 */ - u32 tx_pkt_fifo_131_rsv3; - u32 tx_pkt_fifo_132[3]; /* 0x00004840 */ - u32 tx_pkt_fifo_132_rsv3; - u32 tx_pkt_fifo_133[3]; /* 0x00004850 */ - u32 tx_pkt_fifo_133_rsv3; - u32 tx_pkt_fifo_134[3]; /* 0x00004860 */ - u32 tx_pkt_fifo_134_rsv3; - u32 tx_pkt_fifo_135[3]; /* 0x00004870 */ - u32 tx_pkt_fifo_135_rsv3; - u32 tx_pkt_fifo_136[3]; /* 0x00004880 */ - u32 tx_pkt_fifo_136_rsv3; - u32 tx_pkt_fifo_137[3]; /* 0x00004890 */ - u32 tx_pkt_fifo_137_rsv3; - u32 tx_pkt_fifo_138[3]; /* 0x000048a0 */ - u32 tx_pkt_fifo_138_rsv3; - u32 tx_pkt_fifo_139[3]; /* 0x000048b0 */ - u32 tx_pkt_fifo_139_rsv3; - u32 tx_pkt_fifo_140[3]; /* 0x000048c0 */ - u32 tx_pkt_fifo_140_rsv3; - u32 tx_pkt_fifo_141[3]; /* 0x000048d0 */ - u32 tx_pkt_fifo_141_rsv3; - u32 tx_pkt_fifo_142[3]; /* 0x000048e0 */ - u32 tx_pkt_fifo_142_rsv3; - u32 tx_pkt_fifo_143[3]; /* 0x000048f0 */ - u32 tx_pkt_fifo_143_rsv3; - u32 tx_pkt_fifo_144[3]; /* 0x00004900 */ - u32 tx_pkt_fifo_144_rsv3; - u32 tx_pkt_fifo_145[3]; /* 0x00004910 */ - u32 tx_pkt_fifo_145_rsv3; - u32 tx_pkt_fifo_146[3]; /* 0x00004920 */ - u32 tx_pkt_fifo_146_rsv3; - u32 tx_pkt_fifo_147[3]; /* 0x00004930 */ - u32 tx_pkt_fifo_147_rsv3; - u32 tx_pkt_fifo_148[3]; /* 0x00004940 */ - u32 tx_pkt_fifo_148_rsv3; - u32 tx_pkt_fifo_149[3]; /* 0x00004950 */ - u32 tx_pkt_fifo_149_rsv3; - u32 tx_pkt_fifo_150[3]; /* 0x00004960 */ - u32 tx_pkt_fifo_150_rsv3; - u32 tx_pkt_fifo_151[3]; /* 0x00004970 */ - u32 tx_pkt_fifo_151_rsv3; - u32 tx_pkt_fifo_152[3]; /* 0x00004980 */ - u32 tx_pkt_fifo_152_rsv3; - u32 tx_pkt_fifo_153[3]; /* 0x00004990 */ - u32 tx_pkt_fifo_153_rsv3; - u32 tx_pkt_fifo_154[3]; /* 0x000049a0 */ - u32 tx_pkt_fifo_154_rsv3; - u32 tx_pkt_fifo_155[3]; /* 0x000049b0 */ - u32 tx_pkt_fifo_155_rsv3; - u32 tx_pkt_fifo_156[3]; /* 0x000049c0 */ - u32 tx_pkt_fifo_156_rsv3; - u32 tx_pkt_fifo_157[3]; /* 0x000049d0 */ - u32 tx_pkt_fifo_157_rsv3; - u32 tx_pkt_fifo_158[3]; /* 0x000049e0 */ - u32 tx_pkt_fifo_158_rsv3; - u32 tx_pkt_fifo_159[3]; /* 0x000049f0 */ - u32 tx_pkt_fifo_159_rsv3; - u32 tx_pkt_fifo_160[3]; /* 0x00004a00 */ - u32 tx_pkt_fifo_160_rsv3; - u32 tx_pkt_fifo_161[3]; /* 0x00004a10 */ - u32 tx_pkt_fifo_161_rsv3; - u32 tx_pkt_fifo_162[3]; /* 0x00004a20 */ - u32 tx_pkt_fifo_162_rsv3; - u32 tx_pkt_fifo_163[3]; /* 0x00004a30 */ - u32 tx_pkt_fifo_163_rsv3; - u32 tx_pkt_fifo_164[3]; /* 0x00004a40 */ - u32 tx_pkt_fifo_164_rsv3; - u32 tx_pkt_fifo_165[3]; /* 0x00004a50 */ - u32 tx_pkt_fifo_165_rsv3; - u32 tx_pkt_fifo_166[3]; /* 0x00004a60 */ - u32 tx_pkt_fifo_166_rsv3; - u32 tx_pkt_fifo_167[3]; /* 0x00004a70 */ - u32 tx_pkt_fifo_167_rsv3; - u32 tx_pkt_fifo_168[3]; /* 0x00004a80 */ - u32 tx_pkt_fifo_168_rsv3; - u32 tx_pkt_fifo_169[3]; /* 0x00004a90 */ - u32 tx_pkt_fifo_169_rsv3; - u32 tx_pkt_fifo_170[3]; /* 0x00004aa0 */ - u32 tx_pkt_fifo_170_rsv3; - u32 tx_pkt_fifo_171[3]; /* 0x00004ab0 */ - u32 tx_pkt_fifo_171_rsv3; - u32 tx_pkt_fifo_172[3]; /* 0x00004ac0 */ - u32 tx_pkt_fifo_172_rsv3; - u32 tx_pkt_fifo_173[3]; /* 0x00004ad0 */ - u32 tx_pkt_fifo_173_rsv3; - u32 tx_pkt_fifo_174[3]; /* 0x00004ae0 */ - u32 tx_pkt_fifo_174_rsv3; - u32 tx_pkt_fifo_175[3]; /* 0x00004af0 */ - u32 tx_pkt_fifo_175_rsv3; - u32 tx_pkt_fifo_176[3]; /* 0x00004b00 */ - u32 tx_pkt_fifo_176_rsv3; - u32 tx_pkt_fifo_177[3]; /* 0x00004b10 */ - u32 tx_pkt_fifo_177_rsv3; - u32 tx_pkt_fifo_178[3]; /* 0x00004b20 */ - u32 tx_pkt_fifo_178_rsv3; - u32 tx_pkt_fifo_179[3]; /* 0x00004b30 */ - u32 tx_pkt_fifo_179_rsv3; - u32 tx_pkt_fifo_180[3]; /* 0x00004b40 */ - u32 tx_pkt_fifo_180_rsv3; - u32 tx_pkt_fifo_181[3]; /* 0x00004b50 */ - u32 tx_pkt_fifo_181_rsv3; - u32 tx_pkt_fifo_182[3]; /* 0x00004b60 */ - u32 tx_pkt_fifo_182_rsv3; - u32 tx_pkt_fifo_183[3]; /* 0x00004b70 */ - u32 tx_pkt_fifo_183_rsv3; - u32 tx_pkt_fifo_184[3]; /* 0x00004b80 */ - u32 tx_pkt_fifo_184_rsv3; - u32 tx_pkt_fifo_185[3]; /* 0x00004b90 */ - u32 tx_pkt_fifo_185_rsv3; - u32 tx_pkt_fifo_186[3]; /* 0x00004ba0 */ - u32 tx_pkt_fifo_186_rsv3; - u32 tx_pkt_fifo_187[3]; /* 0x00004bb0 */ - u32 tx_pkt_fifo_187_rsv3; - u32 tx_pkt_fifo_188[3]; /* 0x00004bc0 */ - u32 tx_pkt_fifo_188_rsv3; - u32 tx_pkt_fifo_189[3]; /* 0x00004bd0 */ - u32 tx_pkt_fifo_189_rsv3; - u32 tx_pkt_fifo_190[3]; /* 0x00004be0 */ - u32 tx_pkt_fifo_190_rsv3; - u32 tx_pkt_fifo_191[3]; /* 0x00004bf0 */ - u32 tx_pkt_fifo_191_rsv3; - u32 tx_pkt_fifo_192[3]; /* 0x00004c00 */ - u32 tx_pkt_fifo_192_rsv3; - u32 tx_pkt_fifo_193[3]; /* 0x00004c10 */ - u32 tx_pkt_fifo_193_rsv3; - u32 tx_pkt_fifo_194[3]; /* 0x00004c20 */ - u32 tx_pkt_fifo_194_rsv3; - u32 tx_pkt_fifo_195[3]; /* 0x00004c30 */ - u32 tx_pkt_fifo_195_rsv3; - u32 tx_pkt_fifo_196[3]; /* 0x00004c40 */ - u32 tx_pkt_fifo_196_rsv3; - u32 tx_pkt_fifo_197[3]; /* 0x00004c50 */ - u32 tx_pkt_fifo_197_rsv3; - u32 tx_pkt_fifo_198[3]; /* 0x00004c60 */ - u32 tx_pkt_fifo_198_rsv3; - u32 tx_pkt_fifo_199[3]; /* 0x00004c70 */ - u32 tx_pkt_fifo_199_rsv3; - u32 tx_pkt_fifo_200[3]; /* 0x00004c80 */ - u32 tx_pkt_fifo_200_rsv3; - u32 tx_pkt_fifo_201[3]; /* 0x00004c90 */ - u32 tx_pkt_fifo_201_rsv3; - u32 tx_pkt_fifo_202[3]; /* 0x00004ca0 */ - u32 tx_pkt_fifo_202_rsv3; - u32 tx_pkt_fifo_203[3]; /* 0x00004cb0 */ - u32 tx_pkt_fifo_203_rsv3; - u32 tx_pkt_fifo_204[3]; /* 0x00004cc0 */ - u32 tx_pkt_fifo_204_rsv3; - u32 tx_pkt_fifo_205[3]; /* 0x00004cd0 */ - u32 tx_pkt_fifo_205_rsv3; - u32 tx_pkt_fifo_206[3]; /* 0x00004ce0 */ - u32 tx_pkt_fifo_206_rsv3; - u32 tx_pkt_fifo_207[3]; /* 0x00004cf0 */ - u32 tx_pkt_fifo_207_rsv3; - u32 tx_pkt_fifo_208[3]; /* 0x00004d00 */ - u32 tx_pkt_fifo_208_rsv3; - u32 tx_pkt_fifo_209[3]; /* 0x00004d10 */ - u32 tx_pkt_fifo_209_rsv3; - u32 tx_pkt_fifo_210[3]; /* 0x00004d20 */ - u32 tx_pkt_fifo_210_rsv3; - u32 tx_pkt_fifo_211[3]; /* 0x00004d30 */ - u32 tx_pkt_fifo_211_rsv3; - u32 tx_pkt_fifo_212[3]; /* 0x00004d40 */ - u32 tx_pkt_fifo_212_rsv3; - u32 tx_pkt_fifo_213[3]; /* 0x00004d50 */ - u32 tx_pkt_fifo_213_rsv3; - u32 tx_pkt_fifo_214[3]; /* 0x00004d60 */ - u32 tx_pkt_fifo_214_rsv3; - u32 tx_pkt_fifo_215[3]; /* 0x00004d70 */ - u32 tx_pkt_fifo_215_rsv3; - u32 tx_pkt_fifo_216[3]; /* 0x00004d80 */ - u32 tx_pkt_fifo_216_rsv3; - u32 tx_pkt_fifo_217[3]; /* 0x00004d90 */ - u32 tx_pkt_fifo_217_rsv3; - u32 tx_pkt_fifo_218[3]; /* 0x00004da0 */ - u32 tx_pkt_fifo_218_rsv3; - u32 tx_pkt_fifo_219[3]; /* 0x00004db0 */ - u32 tx_pkt_fifo_219_rsv3; - u32 tx_pkt_fifo_220[3]; /* 0x00004dc0 */ - u32 tx_pkt_fifo_220_rsv3; - u32 tx_pkt_fifo_221[3]; /* 0x00004dd0 */ - u32 tx_pkt_fifo_221_rsv3; - u32 tx_pkt_fifo_222[3]; /* 0x00004de0 */ - u32 tx_pkt_fifo_222_rsv3; - u32 tx_pkt_fifo_223[3]; /* 0x00004df0 */ - u32 tx_pkt_fifo_223_rsv3; - u32 tx_pkt_fifo_224[3]; /* 0x00004e00 */ - u32 tx_pkt_fifo_224_rsv3; - u32 tx_pkt_fifo_225[3]; /* 0x00004e10 */ - u32 tx_pkt_fifo_225_rsv3; - u32 tx_pkt_fifo_226[3]; /* 0x00004e20 */ - u32 tx_pkt_fifo_226_rsv3; - u32 tx_pkt_fifo_227[3]; /* 0x00004e30 */ - u32 tx_pkt_fifo_227_rsv3; - u32 tx_pkt_fifo_228[3]; /* 0x00004e40 */ - u32 tx_pkt_fifo_228_rsv3; - u32 tx_pkt_fifo_229[3]; /* 0x00004e50 */ - u32 tx_pkt_fifo_229_rsv3; - u32 tx_pkt_fifo_230[3]; /* 0x00004e60 */ - u32 tx_pkt_fifo_230_rsv3; - u32 tx_pkt_fifo_231[3]; /* 0x00004e70 */ - u32 tx_pkt_fifo_231_rsv3; - u32 tx_pkt_fifo_232[3]; /* 0x00004e80 */ - u32 tx_pkt_fifo_232_rsv3; - u32 tx_pkt_fifo_233[3]; /* 0x00004e90 */ - u32 tx_pkt_fifo_233_rsv3; - u32 tx_pkt_fifo_234[3]; /* 0x00004ea0 */ - u32 tx_pkt_fifo_234_rsv3; - u32 tx_pkt_fifo_235[3]; /* 0x00004eb0 */ - u32 tx_pkt_fifo_235_rsv3; - u32 tx_pkt_fifo_236[3]; /* 0x00004ec0 */ - u32 tx_pkt_fifo_236_rsv3; - u32 tx_pkt_fifo_237[3]; /* 0x00004ed0 */ - u32 tx_pkt_fifo_237_rsv3; - u32 tx_pkt_fifo_238[3]; /* 0x00004ee0 */ - u32 tx_pkt_fifo_238_rsv3; - u32 tx_pkt_fifo_239[3]; /* 0x00004ef0 */ - u32 tx_pkt_fifo_239_rsv3; - u32 tx_pkt_fifo_240[3]; /* 0x00004f00 */ - u32 tx_pkt_fifo_240_rsv3; - u32 tx_pkt_fifo_241[3]; /* 0x00004f10 */ - u32 tx_pkt_fifo_241_rsv3; - u32 tx_pkt_fifo_242[3]; /* 0x00004f20 */ - u32 tx_pkt_fifo_242_rsv3; - u32 tx_pkt_fifo_243[3]; /* 0x00004f30 */ - u32 tx_pkt_fifo_243_rsv3; - u32 tx_pkt_fifo_244[3]; /* 0x00004f40 */ - u32 tx_pkt_fifo_244_rsv3; - u32 tx_pkt_fifo_245[3]; /* 0x00004f50 */ - u32 tx_pkt_fifo_245_rsv3; - u32 tx_pkt_fifo_246[3]; /* 0x00004f60 */ - u32 tx_pkt_fifo_246_rsv3; - u32 tx_pkt_fifo_247[3]; /* 0x00004f70 */ - u32 tx_pkt_fifo_247_rsv3; - u32 tx_pkt_fifo_248[3]; /* 0x00004f80 */ - u32 tx_pkt_fifo_248_rsv3; - u32 tx_pkt_fifo_249[3]; /* 0x00004f90 */ - u32 tx_pkt_fifo_249_rsv3; - u32 tx_pkt_fifo_250[3]; /* 0x00004fa0 */ - u32 tx_pkt_fifo_250_rsv3; - u32 tx_pkt_fifo_251[3]; /* 0x00004fb0 */ - u32 tx_pkt_fifo_251_rsv3; - u32 tx_pkt_fifo_252[3]; /* 0x00004fc0 */ - u32 tx_pkt_fifo_252_rsv3; - u32 tx_pkt_fifo_253[3]; /* 0x00004fd0 */ - u32 tx_pkt_fifo_253_rsv3; - u32 tx_pkt_fifo_254[3]; /* 0x00004fe0 */ - u32 tx_pkt_fifo_254_rsv3; - u32 tx_pkt_fifo_255[3]; /* 0x00004ff0 */ - u32 tx_pkt_fifo_255_rsv3; - u32 tx_pkt_fifo_256[3]; /* 0x00005000 */ - u32 tx_pkt_fifo_256_rsv3; - u32 tx_pkt_fifo_257[3]; /* 0x00005010 */ - u32 tx_pkt_fifo_257_rsv3; - u32 tx_pkt_fifo_258[3]; /* 0x00005020 */ - u32 tx_pkt_fifo_258_rsv3; - u32 tx_pkt_fifo_259[3]; /* 0x00005030 */ - u32 tx_pkt_fifo_259_rsv3; - u32 tx_pkt_fifo_260[3]; /* 0x00005040 */ - u32 tx_pkt_fifo_260_rsv3; - u32 tx_pkt_fifo_261[3]; /* 0x00005050 */ - u32 tx_pkt_fifo_261_rsv3; - u32 tx_pkt_fifo_262[3]; /* 0x00005060 */ - u32 tx_pkt_fifo_262_rsv3; - u32 tx_pkt_fifo_263[3]; /* 0x00005070 */ - u32 tx_pkt_fifo_263_rsv3; - u32 tx_pkt_fifo_264[3]; /* 0x00005080 */ - u32 tx_pkt_fifo_264_rsv3; - u32 tx_pkt_fifo_265[3]; /* 0x00005090 */ - u32 tx_pkt_fifo_265_rsv3; - u32 tx_pkt_fifo_266[3]; /* 0x000050a0 */ - u32 tx_pkt_fifo_266_rsv3; - u32 tx_pkt_fifo_267[3]; /* 0x000050b0 */ - u32 tx_pkt_fifo_267_rsv3; - u32 tx_pkt_fifo_268[3]; /* 0x000050c0 */ - u32 tx_pkt_fifo_268_rsv3; - u32 tx_pkt_fifo_269[3]; /* 0x000050d0 */ - u32 tx_pkt_fifo_269_rsv3; - u32 tx_pkt_fifo_270[3]; /* 0x000050e0 */ - u32 tx_pkt_fifo_270_rsv3; - u32 tx_pkt_fifo_271[3]; /* 0x000050f0 */ - u32 tx_pkt_fifo_271_rsv3; - u32 tx_pkt_fifo_272[3]; /* 0x00005100 */ - u32 tx_pkt_fifo_272_rsv3; - u32 tx_pkt_fifo_273[3]; /* 0x00005110 */ - u32 tx_pkt_fifo_273_rsv3; - u32 tx_pkt_fifo_274[3]; /* 0x00005120 */ - u32 tx_pkt_fifo_274_rsv3; - u32 tx_pkt_fifo_275[3]; /* 0x00005130 */ - u32 tx_pkt_fifo_275_rsv3; - u32 tx_pkt_fifo_276[3]; /* 0x00005140 */ - u32 tx_pkt_fifo_276_rsv3; - u32 tx_pkt_fifo_277[3]; /* 0x00005150 */ - u32 tx_pkt_fifo_277_rsv3; - u32 tx_pkt_fifo_278[3]; /* 0x00005160 */ - u32 tx_pkt_fifo_278_rsv3; - u32 tx_pkt_fifo_279[3]; /* 0x00005170 */ - u32 tx_pkt_fifo_279_rsv3; - u32 tx_pkt_fifo_280[3]; /* 0x00005180 */ - u32 tx_pkt_fifo_280_rsv3; - u32 tx_pkt_fifo_281[3]; /* 0x00005190 */ - u32 tx_pkt_fifo_281_rsv3; - u32 tx_pkt_fifo_282[3]; /* 0x000051a0 */ - u32 tx_pkt_fifo_282_rsv3; - u32 tx_pkt_fifo_283[3]; /* 0x000051b0 */ - u32 tx_pkt_fifo_283_rsv3; - u32 tx_pkt_fifo_284[3]; /* 0x000051c0 */ - u32 tx_pkt_fifo_284_rsv3; - u32 tx_pkt_fifo_285[3]; /* 0x000051d0 */ - u32 tx_pkt_fifo_285_rsv3; - u32 tx_pkt_fifo_286[3]; /* 0x000051e0 */ - u32 tx_pkt_fifo_286_rsv3; - u32 tx_pkt_fifo_287[3]; /* 0x000051f0 */ - u32 tx_pkt_fifo_287_rsv3; - u32 tx_pkt_fifo_288[3]; /* 0x00005200 */ - u32 tx_pkt_fifo_288_rsv3; - u32 tx_pkt_fifo_289[3]; /* 0x00005210 */ - u32 tx_pkt_fifo_289_rsv3; - u32 tx_pkt_fifo_290[3]; /* 0x00005220 */ - u32 tx_pkt_fifo_290_rsv3; - u32 tx_pkt_fifo_291[3]; /* 0x00005230 */ - u32 tx_pkt_fifo_291_rsv3; - u32 tx_pkt_fifo_292[3]; /* 0x00005240 */ - u32 tx_pkt_fifo_292_rsv3; - u32 tx_pkt_fifo_293[3]; /* 0x00005250 */ - u32 tx_pkt_fifo_293_rsv3; - u32 tx_pkt_fifo_294[3]; /* 0x00005260 */ - u32 tx_pkt_fifo_294_rsv3; - u32 tx_pkt_fifo_295[3]; /* 0x00005270 */ - u32 tx_pkt_fifo_295_rsv3; - u32 tx_pkt_fifo_296[3]; /* 0x00005280 */ - u32 tx_pkt_fifo_296_rsv3; - u32 tx_pkt_fifo_297[3]; /* 0x00005290 */ - u32 tx_pkt_fifo_297_rsv3; - u32 tx_pkt_fifo_298[3]; /* 0x000052a0 */ - u32 tx_pkt_fifo_298_rsv3; - u32 tx_pkt_fifo_299[3]; /* 0x000052b0 */ - u32 tx_pkt_fifo_299_rsv3; - u32 tx_pkt_fifo_300[3]; /* 0x000052c0 */ - u32 tx_pkt_fifo_300_rsv3; - u32 tx_pkt_fifo_301[3]; /* 0x000052d0 */ - u32 tx_pkt_fifo_301_rsv3; - u32 tx_pkt_fifo_302[3]; /* 0x000052e0 */ - u32 tx_pkt_fifo_302_rsv3; - u32 tx_pkt_fifo_303[3]; /* 0x000052f0 */ - u32 tx_pkt_fifo_303_rsv3; - u32 tx_pkt_fifo_304[3]; /* 0x00005300 */ - u32 tx_pkt_fifo_304_rsv3; - u32 tx_pkt_fifo_305[3]; /* 0x00005310 */ - u32 tx_pkt_fifo_305_rsv3; - u32 tx_pkt_fifo_306[3]; /* 0x00005320 */ - u32 tx_pkt_fifo_306_rsv3; - u32 tx_pkt_fifo_307[3]; /* 0x00005330 */ - u32 tx_pkt_fifo_307_rsv3; - u32 tx_pkt_fifo_308[3]; /* 0x00005340 */ - u32 tx_pkt_fifo_308_rsv3; - u32 tx_pkt_fifo_309[3]; /* 0x00005350 */ - u32 tx_pkt_fifo_309_rsv3; - u32 tx_pkt_fifo_310[3]; /* 0x00005360 */ - u32 tx_pkt_fifo_310_rsv3; - u32 tx_pkt_fifo_311[3]; /* 0x00005370 */ - u32 tx_pkt_fifo_311_rsv3; - u32 tx_pkt_fifo_312[3]; /* 0x00005380 */ - u32 tx_pkt_fifo_312_rsv3; - u32 tx_pkt_fifo_313[3]; /* 0x00005390 */ - u32 tx_pkt_fifo_313_rsv3; - u32 tx_pkt_fifo_314[3]; /* 0x000053a0 */ - u32 tx_pkt_fifo_314_rsv3; - u32 tx_pkt_fifo_315[3]; /* 0x000053b0 */ - u32 tx_pkt_fifo_315_rsv3; - u32 tx_pkt_fifo_316[3]; /* 0x000053c0 */ - u32 tx_pkt_fifo_316_rsv3; - u32 tx_pkt_fifo_317[3]; /* 0x000053d0 */ - u32 tx_pkt_fifo_317_rsv3; - u32 tx_pkt_fifo_318[3]; /* 0x000053e0 */ - u32 tx_pkt_fifo_318_rsv3; - u32 tx_pkt_fifo_319[3]; /* 0x000053f0 */ - u32 tx_pkt_fifo_319_rsv3; - u32 tx_pkt_fifo_320[3]; /* 0x00005400 */ - u32 tx_pkt_fifo_320_rsv3; - u32 tx_pkt_fifo_321[3]; /* 0x00005410 */ - u32 tx_pkt_fifo_321_rsv3; - u32 tx_pkt_fifo_322[3]; /* 0x00005420 */ - u32 tx_pkt_fifo_322_rsv3; - u32 tx_pkt_fifo_323[3]; /* 0x00005430 */ - u32 tx_pkt_fifo_323_rsv3; - u32 tx_pkt_fifo_324[3]; /* 0x00005440 */ - u32 tx_pkt_fifo_324_rsv3; - u32 tx_pkt_fifo_325[3]; /* 0x00005450 */ - u32 tx_pkt_fifo_325_rsv3; - u32 tx_pkt_fifo_326[3]; /* 0x00005460 */ - u32 tx_pkt_fifo_326_rsv3; - u32 tx_pkt_fifo_327[3]; /* 0x00005470 */ - u32 tx_pkt_fifo_327_rsv3; - u32 tx_pkt_fifo_328[3]; /* 0x00005480 */ - u32 tx_pkt_fifo_328_rsv3; - u32 tx_pkt_fifo_329[3]; /* 0x00005490 */ - u32 tx_pkt_fifo_329_rsv3; - u32 tx_pkt_fifo_330[3]; /* 0x000054a0 */ - u32 tx_pkt_fifo_330_rsv3; - u32 tx_pkt_fifo_331[3]; /* 0x000054b0 */ - u32 tx_pkt_fifo_331_rsv3; - u32 tx_pkt_fifo_332[3]; /* 0x000054c0 */ - u32 tx_pkt_fifo_332_rsv3; - u32 tx_pkt_fifo_333[3]; /* 0x000054d0 */ - u32 tx_pkt_fifo_333_rsv3; - u32 tx_pkt_fifo_334[3]; /* 0x000054e0 */ - u32 tx_pkt_fifo_334_rsv3; - u32 tx_pkt_fifo_335[3]; /* 0x000054f0 */ - u32 tx_pkt_fifo_335_rsv3; - u32 tx_pkt_fifo_336[3]; /* 0x00005500 */ - u32 tx_pkt_fifo_336_rsv3; - u32 tx_pkt_fifo_337[3]; /* 0x00005510 */ - u32 tx_pkt_fifo_337_rsv3; - u32 tx_pkt_fifo_338[3]; /* 0x00005520 */ - u32 tx_pkt_fifo_338_rsv3; - u32 tx_pkt_fifo_339[3]; /* 0x00005530 */ - u32 tx_pkt_fifo_339_rsv3; - u32 tx_pkt_fifo_340[3]; /* 0x00005540 */ - u32 tx_pkt_fifo_340_rsv3; - u32 tx_pkt_fifo_341[3]; /* 0x00005550 */ - u32 tx_pkt_fifo_341_rsv3; - u32 tx_pkt_fifo_342[3]; /* 0x00005560 */ - u32 tx_pkt_fifo_342_rsv3; - u32 tx_pkt_fifo_343[3]; /* 0x00005570 */ - u32 tx_pkt_fifo_343_rsv3; - u32 tx_pkt_fifo_344[3]; /* 0x00005580 */ - u32 tx_pkt_fifo_344_rsv3; - u32 tx_pkt_fifo_345[3]; /* 0x00005590 */ - u32 tx_pkt_fifo_345_rsv3; - u32 tx_pkt_fifo_346[3]; /* 0x000055a0 */ - u32 tx_pkt_fifo_346_rsv3; - u32 tx_pkt_fifo_347[3]; /* 0x000055b0 */ - u32 tx_pkt_fifo_347_rsv3; - u32 tx_pkt_fifo_348[3]; /* 0x000055c0 */ - u32 tx_pkt_fifo_348_rsv3; - u32 tx_pkt_fifo_349[3]; /* 0x000055d0 */ - u32 tx_pkt_fifo_349_rsv3; - u32 tx_pkt_fifo_350[3]; /* 0x000055e0 */ - u32 tx_pkt_fifo_350_rsv3; - u32 tx_pkt_fifo_351[3]; /* 0x000055f0 */ - u32 tx_pkt_fifo_351_rsv3; - u32 tx_pkt_fifo_352[3]; /* 0x00005600 */ - u32 tx_pkt_fifo_352_rsv3; - u32 tx_pkt_fifo_353[3]; /* 0x00005610 */ - u32 tx_pkt_fifo_353_rsv3; - u32 tx_pkt_fifo_354[3]; /* 0x00005620 */ - u32 tx_pkt_fifo_354_rsv3; - u32 tx_pkt_fifo_355[3]; /* 0x00005630 */ - u32 tx_pkt_fifo_355_rsv3; - u32 tx_pkt_fifo_356[3]; /* 0x00005640 */ - u32 tx_pkt_fifo_356_rsv3; - u32 tx_pkt_fifo_357[3]; /* 0x00005650 */ - u32 tx_pkt_fifo_357_rsv3; - u32 tx_pkt_fifo_358[3]; /* 0x00005660 */ - u32 tx_pkt_fifo_358_rsv3; - u32 tx_pkt_fifo_359[3]; /* 0x00005670 */ - u32 tx_pkt_fifo_359_rsv3; - u32 tx_pkt_fifo_360[3]; /* 0x00005680 */ - u32 tx_pkt_fifo_360_rsv3; - u32 tx_pkt_fifo_361[3]; /* 0x00005690 */ - u32 tx_pkt_fifo_361_rsv3; - u32 tx_pkt_fifo_362[3]; /* 0x000056a0 */ - u32 tx_pkt_fifo_362_rsv3; - u32 tx_pkt_fifo_363[3]; /* 0x000056b0 */ - u32 tx_pkt_fifo_363_rsv3; - u32 tx_pkt_fifo_364[3]; /* 0x000056c0 */ - u32 tx_pkt_fifo_364_rsv3; - u32 tx_pkt_fifo_365[3]; /* 0x000056d0 */ - u32 tx_pkt_fifo_365_rsv3; - u32 tx_pkt_fifo_366[3]; /* 0x000056e0 */ - u32 tx_pkt_fifo_366_rsv3; - u32 tx_pkt_fifo_367[3]; /* 0x000056f0 */ - u32 tx_pkt_fifo_367_rsv3; - u32 tx_pkt_fifo_368[3]; /* 0x00005700 */ - u32 tx_pkt_fifo_368_rsv3; - u32 tx_pkt_fifo_369[3]; /* 0x00005710 */ - u32 tx_pkt_fifo_369_rsv3; - u32 tx_pkt_fifo_370[3]; /* 0x00005720 */ - u32 tx_pkt_fifo_370_rsv3; - u32 tx_pkt_fifo_371[3]; /* 0x00005730 */ - u32 tx_pkt_fifo_371_rsv3; - u32 tx_pkt_fifo_372[3]; /* 0x00005740 */ - u32 tx_pkt_fifo_372_rsv3; - u32 tx_pkt_fifo_373[3]; /* 0x00005750 */ - u32 tx_pkt_fifo_373_rsv3; - u32 tx_pkt_fifo_374[3]; /* 0x00005760 */ - u32 tx_pkt_fifo_374_rsv3; - u32 tx_pkt_fifo_375[3]; /* 0x00005770 */ - u32 tx_pkt_fifo_375_rsv3; - u32 tx_pkt_fifo_376[3]; /* 0x00005780 */ - u32 tx_pkt_fifo_376_rsv3; - u32 tx_pkt_fifo_377[3]; /* 0x00005790 */ - u32 tx_pkt_fifo_377_rsv3; - u32 tx_pkt_fifo_378[3]; /* 0x000057a0 */ - u32 tx_pkt_fifo_378_rsv3; - u32 tx_pkt_fifo_379[3]; /* 0x000057b0 */ - u32 tx_pkt_fifo_379_rsv3; - u32 tx_pkt_fifo_380[3]; /* 0x000057c0 */ - u32 tx_pkt_fifo_380_rsv3; - u32 tx_pkt_fifo_381[3]; /* 0x000057d0 */ - u32 tx_pkt_fifo_381_rsv3; - u32 tx_pkt_fifo_382[3]; /* 0x000057e0 */ - u32 tx_pkt_fifo_382_rsv3; - u32 tx_pkt_fifo_383[3]; /* 0x000057f0 */ - u32 tx_pkt_fifo_383_rsv3; - u32 tx_pkt_fifo_384[3]; /* 0x00005800 */ - u32 tx_pkt_fifo_384_rsv3; - u32 tx_pkt_fifo_385[3]; /* 0x00005810 */ - u32 tx_pkt_fifo_385_rsv3; - u32 tx_pkt_fifo_386[3]; /* 0x00005820 */ - u32 tx_pkt_fifo_386_rsv3; - u32 tx_pkt_fifo_387[3]; /* 0x00005830 */ - u32 tx_pkt_fifo_387_rsv3; - u32 tx_pkt_fifo_388[3]; /* 0x00005840 */ - u32 tx_pkt_fifo_388_rsv3; - u32 tx_pkt_fifo_389[3]; /* 0x00005850 */ - u32 tx_pkt_fifo_389_rsv3; - u32 tx_pkt_fifo_390[3]; /* 0x00005860 */ - u32 tx_pkt_fifo_390_rsv3; - u32 tx_pkt_fifo_391[3]; /* 0x00005870 */ - u32 tx_pkt_fifo_391_rsv3; - u32 tx_pkt_fifo_392[3]; /* 0x00005880 */ - u32 tx_pkt_fifo_392_rsv3; - u32 tx_pkt_fifo_393[3]; /* 0x00005890 */ - u32 tx_pkt_fifo_393_rsv3; - u32 tx_pkt_fifo_394[3]; /* 0x000058a0 */ - u32 tx_pkt_fifo_394_rsv3; - u32 tx_pkt_fifo_395[3]; /* 0x000058b0 */ - u32 tx_pkt_fifo_395_rsv3; - u32 tx_pkt_fifo_396[3]; /* 0x000058c0 */ - u32 tx_pkt_fifo_396_rsv3; - u32 tx_pkt_fifo_397[3]; /* 0x000058d0 */ - u32 tx_pkt_fifo_397_rsv3; - u32 tx_pkt_fifo_398[3]; /* 0x000058e0 */ - u32 tx_pkt_fifo_398_rsv3; - u32 tx_pkt_fifo_399[3]; /* 0x000058f0 */ - u32 tx_pkt_fifo_399_rsv3; - u32 tx_pkt_fifo_400[3]; /* 0x00005900 */ - u32 tx_pkt_fifo_400_rsv3; - u32 tx_pkt_fifo_401[3]; /* 0x00005910 */ - u32 tx_pkt_fifo_401_rsv3; - u32 tx_pkt_fifo_402[3]; /* 0x00005920 */ - u32 tx_pkt_fifo_402_rsv3; - u32 tx_pkt_fifo_403[3]; /* 0x00005930 */ - u32 tx_pkt_fifo_403_rsv3; - u32 tx_pkt_fifo_404[3]; /* 0x00005940 */ - u32 tx_pkt_fifo_404_rsv3; - u32 tx_pkt_fifo_405[3]; /* 0x00005950 */ - u32 tx_pkt_fifo_405_rsv3; - u32 tx_pkt_fifo_406[3]; /* 0x00005960 */ - u32 tx_pkt_fifo_406_rsv3; - u32 tx_pkt_fifo_407[3]; /* 0x00005970 */ - u32 tx_pkt_fifo_407_rsv3; - u32 tx_pkt_fifo_408[3]; /* 0x00005980 */ - u32 tx_pkt_fifo_408_rsv3; - u32 tx_pkt_fifo_409[3]; /* 0x00005990 */ - u32 tx_pkt_fifo_409_rsv3; - u32 tx_pkt_fifo_410[3]; /* 0x000059a0 */ - u32 tx_pkt_fifo_410_rsv3; - u32 tx_pkt_fifo_411[3]; /* 0x000059b0 */ - u32 tx_pkt_fifo_411_rsv3; - u32 tx_pkt_fifo_412[3]; /* 0x000059c0 */ - u32 tx_pkt_fifo_412_rsv3; - u32 tx_pkt_fifo_413[3]; /* 0x000059d0 */ - u32 tx_pkt_fifo_413_rsv3; - u32 tx_pkt_fifo_414[3]; /* 0x000059e0 */ - u32 tx_pkt_fifo_414_rsv3; - u32 tx_pkt_fifo_415[3]; /* 0x000059f0 */ - u32 tx_pkt_fifo_415_rsv3; - u32 tx_pkt_fifo_416[3]; /* 0x00005a00 */ - u32 tx_pkt_fifo_416_rsv3; - u32 tx_pkt_fifo_417[3]; /* 0x00005a10 */ - u32 tx_pkt_fifo_417_rsv3; - u32 tx_pkt_fifo_418[3]; /* 0x00005a20 */ - u32 tx_pkt_fifo_418_rsv3; - u32 tx_pkt_fifo_419[3]; /* 0x00005a30 */ - u32 tx_pkt_fifo_419_rsv3; - u32 tx_pkt_fifo_420[3]; /* 0x00005a40 */ - u32 tx_pkt_fifo_420_rsv3; - u32 tx_pkt_fifo_421[3]; /* 0x00005a50 */ - u32 tx_pkt_fifo_421_rsv3; - u32 tx_pkt_fifo_422[3]; /* 0x00005a60 */ - u32 tx_pkt_fifo_422_rsv3; - u32 tx_pkt_fifo_423[3]; /* 0x00005a70 */ - u32 tx_pkt_fifo_423_rsv3; - u32 tx_pkt_fifo_424[3]; /* 0x00005a80 */ - u32 tx_pkt_fifo_424_rsv3; - u32 tx_pkt_fifo_425[3]; /* 0x00005a90 */ - u32 tx_pkt_fifo_425_rsv3; - u32 tx_pkt_fifo_426[3]; /* 0x00005aa0 */ - u32 tx_pkt_fifo_426_rsv3; - u32 tx_pkt_fifo_427[3]; /* 0x00005ab0 */ - u32 tx_pkt_fifo_427_rsv3; - u32 tx_pkt_fifo_428[3]; /* 0x00005ac0 */ - u32 tx_pkt_fifo_428_rsv3; - u32 tx_pkt_fifo_429[3]; /* 0x00005ad0 */ - u32 tx_pkt_fifo_429_rsv3; - u32 tx_pkt_fifo_430[3]; /* 0x00005ae0 */ - u32 tx_pkt_fifo_430_rsv3; - u32 tx_pkt_fifo_431[3]; /* 0x00005af0 */ - u32 tx_pkt_fifo_431_rsv3; - u32 tx_pkt_fifo_432[3]; /* 0x00005b00 */ - u32 tx_pkt_fifo_432_rsv3; - u32 tx_pkt_fifo_433[3]; /* 0x00005b10 */ - u32 tx_pkt_fifo_433_rsv3; - u32 tx_pkt_fifo_434[3]; /* 0x00005b20 */ - u32 tx_pkt_fifo_434_rsv3; - u32 tx_pkt_fifo_435[3]; /* 0x00005b30 */ - u32 tx_pkt_fifo_435_rsv3; - u32 tx_pkt_fifo_436[3]; /* 0x00005b40 */ - u32 tx_pkt_fifo_436_rsv3; - u32 tx_pkt_fifo_437[3]; /* 0x00005b50 */ - u32 tx_pkt_fifo_437_rsv3; - u32 tx_pkt_fifo_438[3]; /* 0x00005b60 */ - u32 tx_pkt_fifo_438_rsv3; - u32 tx_pkt_fifo_439[3]; /* 0x00005b70 */ - u32 tx_pkt_fifo_439_rsv3; - u32 tx_pkt_fifo_440[3]; /* 0x00005b80 */ - u32 tx_pkt_fifo_440_rsv3; - u32 tx_pkt_fifo_441[3]; /* 0x00005b90 */ - u32 tx_pkt_fifo_441_rsv3; - u32 tx_pkt_fifo_442[3]; /* 0x00005ba0 */ - u32 tx_pkt_fifo_442_rsv3; - u32 tx_pkt_fifo_443[3]; /* 0x00005bb0 */ - u32 tx_pkt_fifo_443_rsv3; - u32 tx_pkt_fifo_444[3]; /* 0x00005bc0 */ - u32 tx_pkt_fifo_444_rsv3; - u32 tx_pkt_fifo_445[3]; /* 0x00005bd0 */ - u32 tx_pkt_fifo_445_rsv3; - u32 tx_pkt_fifo_446[3]; /* 0x00005be0 */ - u32 tx_pkt_fifo_446_rsv3; - u32 tx_pkt_fifo_447[3]; /* 0x00005bf0 */ - u32 tx_pkt_fifo_447_rsv3; - u32 tx_pkt_fifo_448[3]; /* 0x00005c00 */ - u32 tx_pkt_fifo_448_rsv3; - u32 tx_pkt_fifo_449[3]; /* 0x00005c10 */ - u32 tx_pkt_fifo_449_rsv3; - u32 tx_pkt_fifo_450[3]; /* 0x00005c20 */ - u32 tx_pkt_fifo_450_rsv3; - u32 tx_pkt_fifo_451[3]; /* 0x00005c30 */ - u32 tx_pkt_fifo_451_rsv3; - u32 tx_pkt_fifo_452[3]; /* 0x00005c40 */ - u32 tx_pkt_fifo_452_rsv3; - u32 tx_pkt_fifo_453[3]; /* 0x00005c50 */ - u32 tx_pkt_fifo_453_rsv3; - u32 tx_pkt_fifo_454[3]; /* 0x00005c60 */ - u32 tx_pkt_fifo_454_rsv3; - u32 tx_pkt_fifo_455[3]; /* 0x00005c70 */ - u32 tx_pkt_fifo_455_rsv3; - u32 tx_pkt_fifo_456[3]; /* 0x00005c80 */ - u32 tx_pkt_fifo_456_rsv3; - u32 tx_pkt_fifo_457[3]; /* 0x00005c90 */ - u32 tx_pkt_fifo_457_rsv3; - u32 tx_pkt_fifo_458[3]; /* 0x00005ca0 */ - u32 tx_pkt_fifo_458_rsv3; - u32 tx_pkt_fifo_459[3]; /* 0x00005cb0 */ - u32 tx_pkt_fifo_459_rsv3; - u32 tx_pkt_fifo_460[3]; /* 0x00005cc0 */ - u32 tx_pkt_fifo_460_rsv3; - u32 tx_pkt_fifo_461[3]; /* 0x00005cd0 */ - u32 tx_pkt_fifo_461_rsv3; - u32 tx_pkt_fifo_462[3]; /* 0x00005ce0 */ - u32 tx_pkt_fifo_462_rsv3; - u32 tx_pkt_fifo_463[3]; /* 0x00005cf0 */ - u32 tx_pkt_fifo_463_rsv3; - u32 tx_pkt_fifo_464[3]; /* 0x00005d00 */ - u32 tx_pkt_fifo_464_rsv3; - u32 tx_pkt_fifo_465[3]; /* 0x00005d10 */ - u32 tx_pkt_fifo_465_rsv3; - u32 tx_pkt_fifo_466[3]; /* 0x00005d20 */ - u32 tx_pkt_fifo_466_rsv3; - u32 tx_pkt_fifo_467[3]; /* 0x00005d30 */ - u32 tx_pkt_fifo_467_rsv3; - u32 tx_pkt_fifo_468[3]; /* 0x00005d40 */ - u32 tx_pkt_fifo_468_rsv3; - u32 tx_pkt_fifo_469[3]; /* 0x00005d50 */ - u32 tx_pkt_fifo_469_rsv3; - u32 tx_pkt_fifo_470[3]; /* 0x00005d60 */ - u32 tx_pkt_fifo_470_rsv3; - u32 tx_pkt_fifo_471[3]; /* 0x00005d70 */ - u32 tx_pkt_fifo_471_rsv3; - u32 tx_pkt_fifo_472[3]; /* 0x00005d80 */ - u32 tx_pkt_fifo_472_rsv3; - u32 tx_pkt_fifo_473[3]; /* 0x00005d90 */ - u32 tx_pkt_fifo_473_rsv3; - u32 tx_pkt_fifo_474[3]; /* 0x00005da0 */ - u32 tx_pkt_fifo_474_rsv3; - u32 tx_pkt_fifo_475[3]; /* 0x00005db0 */ - u32 tx_pkt_fifo_475_rsv3; - u32 tx_pkt_fifo_476[3]; /* 0x00005dc0 */ - u32 tx_pkt_fifo_476_rsv3; - u32 tx_pkt_fifo_477[3]; /* 0x00005dd0 */ - u32 tx_pkt_fifo_477_rsv3; - u32 tx_pkt_fifo_478[3]; /* 0x00005de0 */ - u32 tx_pkt_fifo_478_rsv3; - u32 tx_pkt_fifo_479[3]; /* 0x00005df0 */ - u32 tx_pkt_fifo_479_rsv3; - u32 tx_pkt_fifo_480[3]; /* 0x00005e00 */ - u32 tx_pkt_fifo_480_rsv3; - u32 tx_pkt_fifo_481[3]; /* 0x00005e10 */ - u32 tx_pkt_fifo_481_rsv3; - u32 tx_pkt_fifo_482[3]; /* 0x00005e20 */ - u32 tx_pkt_fifo_482_rsv3; - u32 tx_pkt_fifo_483[3]; /* 0x00005e30 */ - u32 tx_pkt_fifo_483_rsv3; - u32 tx_pkt_fifo_484[3]; /* 0x00005e40 */ - u32 tx_pkt_fifo_484_rsv3; - u32 tx_pkt_fifo_485[3]; /* 0x00005e50 */ - u32 tx_pkt_fifo_485_rsv3; - u32 tx_pkt_fifo_486[3]; /* 0x00005e60 */ - u32 tx_pkt_fifo_486_rsv3; - u32 tx_pkt_fifo_487[3]; /* 0x00005e70 */ - u32 tx_pkt_fifo_487_rsv3; - u32 tx_pkt_fifo_488[3]; /* 0x00005e80 */ - u32 tx_pkt_fifo_488_rsv3; - u32 tx_pkt_fifo_489[3]; /* 0x00005e90 */ - u32 tx_pkt_fifo_489_rsv3; - u32 tx_pkt_fifo_490[3]; /* 0x00005ea0 */ - u32 tx_pkt_fifo_490_rsv3; - u32 tx_pkt_fifo_491[3]; /* 0x00005eb0 */ - u32 tx_pkt_fifo_491_rsv3; - u32 tx_pkt_fifo_492[3]; /* 0x00005ec0 */ - u32 tx_pkt_fifo_492_rsv3; - u32 tx_pkt_fifo_493[3]; /* 0x00005ed0 */ - u32 tx_pkt_fifo_493_rsv3; - u32 tx_pkt_fifo_494[3]; /* 0x00005ee0 */ - u32 tx_pkt_fifo_494_rsv3; - u32 tx_pkt_fifo_495[3]; /* 0x00005ef0 */ - u32 tx_pkt_fifo_495_rsv3; - u32 tx_pkt_fifo_496[3]; /* 0x00005f00 */ - u32 tx_pkt_fifo_496_rsv3; - u32 tx_pkt_fifo_497[3]; /* 0x00005f10 */ - u32 tx_pkt_fifo_497_rsv3; - u32 tx_pkt_fifo_498[3]; /* 0x00005f20 */ - u32 tx_pkt_fifo_498_rsv3; - u32 tx_pkt_fifo_499[3]; /* 0x00005f30 */ - u32 tx_pkt_fifo_499_rsv3; - u32 tx_pkt_fifo_500[3]; /* 0x00005f40 */ - u32 tx_pkt_fifo_500_rsv3; - u32 tx_pkt_fifo_501[3]; /* 0x00005f50 */ - u32 tx_pkt_fifo_501_rsv3; - u32 tx_pkt_fifo_502[3]; /* 0x00005f60 */ - u32 tx_pkt_fifo_502_rsv3; - u32 tx_pkt_fifo_503[3]; /* 0x00005f70 */ - u32 tx_pkt_fifo_503_rsv3; - u32 tx_pkt_fifo_504[3]; /* 0x00005f80 */ - u32 tx_pkt_fifo_504_rsv3; - u32 tx_pkt_fifo_505[3]; /* 0x00005f90 */ - u32 tx_pkt_fifo_505_rsv3; - u32 tx_pkt_fifo_506[3]; /* 0x00005fa0 */ - u32 tx_pkt_fifo_506_rsv3; - u32 tx_pkt_fifo_507[3]; /* 0x00005fb0 */ - u32 tx_pkt_fifo_507_rsv3; - u32 tx_pkt_fifo_508[3]; /* 0x00005fc0 */ - u32 tx_pkt_fifo_508_rsv3; - u32 tx_pkt_fifo_509[3]; /* 0x00005fd0 */ - u32 tx_pkt_fifo_509_rsv3; - u32 tx_pkt_fifo_510[3]; /* 0x00005fe0 */ - u32 tx_pkt_fifo_510_rsv3; - u32 tx_pkt_fifo_511[3]; /* 0x00005ff0 */ - u32 tx_pkt_fifo_511_rsv3; - u32 tx_pkt_fifo_512[3]; /* 0x00006000 */ - u32 tx_pkt_fifo_512_rsv3; - u32 tx_pkt_fifo_513[3]; /* 0x00006010 */ - u32 tx_pkt_fifo_513_rsv3; - u32 tx_pkt_fifo_514[3]; /* 0x00006020 */ - u32 tx_pkt_fifo_514_rsv3; - u32 tx_pkt_fifo_515[3]; /* 0x00006030 */ - u32 tx_pkt_fifo_515_rsv3; - u32 tx_pkt_fifo_516[3]; /* 0x00006040 */ - u32 tx_pkt_fifo_516_rsv3; - u32 tx_pkt_fifo_517[3]; /* 0x00006050 */ - u32 tx_pkt_fifo_517_rsv3; - u32 tx_pkt_fifo_518[3]; /* 0x00006060 */ - u32 tx_pkt_fifo_518_rsv3; - u32 tx_pkt_fifo_519[3]; /* 0x00006070 */ - u32 tx_pkt_fifo_519_rsv3; - u32 tx_pkt_fifo_520[3]; /* 0x00006080 */ - u32 tx_pkt_fifo_520_rsv3; - u32 tx_pkt_fifo_521[3]; /* 0x00006090 */ - u32 tx_pkt_fifo_521_rsv3; - u32 tx_pkt_fifo_522[3]; /* 0x000060a0 */ - u32 tx_pkt_fifo_522_rsv3; - u32 tx_pkt_fifo_523[3]; /* 0x000060b0 */ - u32 tx_pkt_fifo_523_rsv3; - u32 tx_pkt_fifo_524[3]; /* 0x000060c0 */ - u32 tx_pkt_fifo_524_rsv3; - u32 tx_pkt_fifo_525[3]; /* 0x000060d0 */ - u32 tx_pkt_fifo_525_rsv3; - u32 tx_pkt_fifo_526[3]; /* 0x000060e0 */ - u32 tx_pkt_fifo_526_rsv3; - u32 tx_pkt_fifo_527[3]; /* 0x000060f0 */ - u32 tx_pkt_fifo_527_rsv3; - u32 tx_pkt_fifo_528[3]; /* 0x00006100 */ - u32 tx_pkt_fifo_528_rsv3; - u32 tx_pkt_fifo_529[3]; /* 0x00006110 */ - u32 tx_pkt_fifo_529_rsv3; - u32 tx_pkt_fifo_530[3]; /* 0x00006120 */ - u32 tx_pkt_fifo_530_rsv3; - u32 tx_pkt_fifo_531[3]; /* 0x00006130 */ - u32 tx_pkt_fifo_531_rsv3; - u32 tx_pkt_fifo_532[3]; /* 0x00006140 */ - u32 tx_pkt_fifo_532_rsv3; - u32 tx_pkt_fifo_533[3]; /* 0x00006150 */ - u32 tx_pkt_fifo_533_rsv3; - u32 tx_pkt_fifo_534[3]; /* 0x00006160 */ - u32 tx_pkt_fifo_534_rsv3; - u32 tx_pkt_fifo_535[3]; /* 0x00006170 */ - u32 tx_pkt_fifo_535_rsv3; - u32 tx_pkt_fifo_536[3]; /* 0x00006180 */ - u32 tx_pkt_fifo_536_rsv3; - u32 tx_pkt_fifo_537[3]; /* 0x00006190 */ - u32 tx_pkt_fifo_537_rsv3; - u32 tx_pkt_fifo_538[3]; /* 0x000061a0 */ - u32 tx_pkt_fifo_538_rsv3; - u32 tx_pkt_fifo_539[3]; /* 0x000061b0 */ - u32 tx_pkt_fifo_539_rsv3; - u32 tx_pkt_fifo_540[3]; /* 0x000061c0 */ - u32 tx_pkt_fifo_540_rsv3; - u32 tx_pkt_fifo_541[3]; /* 0x000061d0 */ - u32 tx_pkt_fifo_541_rsv3; - u32 tx_pkt_fifo_542[3]; /* 0x000061e0 */ - u32 tx_pkt_fifo_542_rsv3; - u32 tx_pkt_fifo_543[3]; /* 0x000061f0 */ - u32 tx_pkt_fifo_543_rsv3; - u32 tx_pkt_fifo_544[3]; /* 0x00006200 */ - u32 tx_pkt_fifo_544_rsv3; - u32 tx_pkt_fifo_545[3]; /* 0x00006210 */ - u32 tx_pkt_fifo_545_rsv3; - u32 tx_pkt_fifo_546[3]; /* 0x00006220 */ - u32 tx_pkt_fifo_546_rsv3; - u32 tx_pkt_fifo_547[3]; /* 0x00006230 */ - u32 tx_pkt_fifo_547_rsv3; - u32 tx_pkt_fifo_548[3]; /* 0x00006240 */ - u32 tx_pkt_fifo_548_rsv3; - u32 tx_pkt_fifo_549[3]; /* 0x00006250 */ - u32 tx_pkt_fifo_549_rsv3; - u32 tx_pkt_fifo_550[3]; /* 0x00006260 */ - u32 tx_pkt_fifo_550_rsv3; - u32 tx_pkt_fifo_551[3]; /* 0x00006270 */ - u32 tx_pkt_fifo_551_rsv3; - u32 tx_pkt_fifo_552[3]; /* 0x00006280 */ - u32 tx_pkt_fifo_552_rsv3; - u32 tx_pkt_fifo_553[3]; /* 0x00006290 */ - u32 tx_pkt_fifo_553_rsv3; - u32 tx_pkt_fifo_554[3]; /* 0x000062a0 */ - u32 tx_pkt_fifo_554_rsv3; - u32 tx_pkt_fifo_555[3]; /* 0x000062b0 */ - u32 tx_pkt_fifo_555_rsv3; - u32 tx_pkt_fifo_556[3]; /* 0x000062c0 */ - u32 tx_pkt_fifo_556_rsv3; - u32 tx_pkt_fifo_557[3]; /* 0x000062d0 */ - u32 tx_pkt_fifo_557_rsv3; - u32 tx_pkt_fifo_558[3]; /* 0x000062e0 */ - u32 tx_pkt_fifo_558_rsv3; - u32 tx_pkt_fifo_559[3]; /* 0x000062f0 */ - u32 tx_pkt_fifo_559_rsv3; - u32 tx_pkt_fifo_560[3]; /* 0x00006300 */ - u32 tx_pkt_fifo_560_rsv3; - u32 tx_pkt_fifo_561[3]; /* 0x00006310 */ - u32 tx_pkt_fifo_561_rsv3; - u32 tx_pkt_fifo_562[3]; /* 0x00006320 */ - u32 tx_pkt_fifo_562_rsv3; - u32 tx_pkt_fifo_563[3]; /* 0x00006330 */ - u32 tx_pkt_fifo_563_rsv3; - u32 tx_pkt_fifo_564[3]; /* 0x00006340 */ - u32 tx_pkt_fifo_564_rsv3; - u32 tx_pkt_fifo_565[3]; /* 0x00006350 */ - u32 tx_pkt_fifo_565_rsv3; - u32 tx_pkt_fifo_566[3]; /* 0x00006360 */ - u32 tx_pkt_fifo_566_rsv3; - u32 tx_pkt_fifo_567[3]; /* 0x00006370 */ - u32 tx_pkt_fifo_567_rsv3; - u32 tx_pkt_fifo_568[3]; /* 0x00006380 */ - u32 tx_pkt_fifo_568_rsv3; - u32 tx_pkt_fifo_569[3]; /* 0x00006390 */ - u32 tx_pkt_fifo_569_rsv3; - u32 tx_pkt_fifo_570[3]; /* 0x000063a0 */ - u32 tx_pkt_fifo_570_rsv3; - u32 tx_pkt_fifo_571[3]; /* 0x000063b0 */ - u32 tx_pkt_fifo_571_rsv3; - u32 tx_pkt_fifo_572[3]; /* 0x000063c0 */ - u32 tx_pkt_fifo_572_rsv3; - u32 tx_pkt_fifo_573[3]; /* 0x000063d0 */ - u32 tx_pkt_fifo_573_rsv3; - u32 tx_pkt_fifo_574[3]; /* 0x000063e0 */ - u32 tx_pkt_fifo_574_rsv3; - u32 tx_pkt_fifo_575[3]; /* 0x000063f0 */ - u32 tx_pkt_fifo_575_rsv3; - u32 tx_pkt_fifo_576[3]; /* 0x00006400 */ - u32 tx_pkt_fifo_576_rsv3; - u32 tx_pkt_fifo_577[3]; /* 0x00006410 */ - u32 tx_pkt_fifo_577_rsv3; - u32 tx_pkt_fifo_578[3]; /* 0x00006420 */ - u32 tx_pkt_fifo_578_rsv3; - u32 tx_pkt_fifo_579[3]; /* 0x00006430 */ - u32 tx_pkt_fifo_579_rsv3; - u32 tx_pkt_fifo_580[3]; /* 0x00006440 */ - u32 tx_pkt_fifo_580_rsv3; - u32 tx_pkt_fifo_581[3]; /* 0x00006450 */ - u32 tx_pkt_fifo_581_rsv3; - u32 tx_pkt_fifo_582[3]; /* 0x00006460 */ - u32 tx_pkt_fifo_582_rsv3; - u32 tx_pkt_fifo_583[3]; /* 0x00006470 */ - u32 tx_pkt_fifo_583_rsv3; - u32 tx_pkt_fifo_584[3]; /* 0x00006480 */ - u32 tx_pkt_fifo_584_rsv3; - u32 tx_pkt_fifo_585[3]; /* 0x00006490 */ - u32 tx_pkt_fifo_585_rsv3; - u32 tx_pkt_fifo_586[3]; /* 0x000064a0 */ - u32 tx_pkt_fifo_586_rsv3; - u32 tx_pkt_fifo_587[3]; /* 0x000064b0 */ - u32 tx_pkt_fifo_587_rsv3; - u32 tx_pkt_fifo_588[3]; /* 0x000064c0 */ - u32 tx_pkt_fifo_588_rsv3; - u32 tx_pkt_fifo_589[3]; /* 0x000064d0 */ - u32 tx_pkt_fifo_589_rsv3; - u32 tx_pkt_fifo_590[3]; /* 0x000064e0 */ - u32 tx_pkt_fifo_590_rsv3; - u32 tx_pkt_fifo_591[3]; /* 0x000064f0 */ - u32 tx_pkt_fifo_591_rsv3; - u32 tx_pkt_fifo_592[3]; /* 0x00006500 */ - u32 tx_pkt_fifo_592_rsv3; - u32 tx_pkt_fifo_593[3]; /* 0x00006510 */ - u32 tx_pkt_fifo_593_rsv3; - u32 tx_pkt_fifo_594[3]; /* 0x00006520 */ - u32 tx_pkt_fifo_594_rsv3; - u32 tx_pkt_fifo_595[3]; /* 0x00006530 */ - u32 tx_pkt_fifo_595_rsv3; - u32 tx_pkt_fifo_596[3]; /* 0x00006540 */ - u32 tx_pkt_fifo_596_rsv3; - u32 tx_pkt_fifo_597[3]; /* 0x00006550 */ - u32 tx_pkt_fifo_597_rsv3; - u32 tx_pkt_fifo_598[3]; /* 0x00006560 */ - u32 tx_pkt_fifo_598_rsv3; - u32 tx_pkt_fifo_599[3]; /* 0x00006570 */ - u32 tx_pkt_fifo_599_rsv3; - u32 tx_pkt_fifo_600[3]; /* 0x00006580 */ - u32 tx_pkt_fifo_600_rsv3; - u32 tx_pkt_fifo_601[3]; /* 0x00006590 */ - u32 tx_pkt_fifo_601_rsv3; - u32 tx_pkt_fifo_602[3]; /* 0x000065a0 */ - u32 tx_pkt_fifo_602_rsv3; - u32 tx_pkt_fifo_603[3]; /* 0x000065b0 */ - u32 tx_pkt_fifo_603_rsv3; - u32 tx_pkt_fifo_604[3]; /* 0x000065c0 */ - u32 tx_pkt_fifo_604_rsv3; - u32 tx_pkt_fifo_605[3]; /* 0x000065d0 */ - u32 tx_pkt_fifo_605_rsv3; - u32 tx_pkt_fifo_606[3]; /* 0x000065e0 */ - u32 tx_pkt_fifo_606_rsv3; - u32 tx_pkt_fifo_607[3]; /* 0x000065f0 */ - u32 tx_pkt_fifo_607_rsv3; - u32 tx_pkt_fifo_608[3]; /* 0x00006600 */ - u32 tx_pkt_fifo_608_rsv3; - u32 tx_pkt_fifo_609[3]; /* 0x00006610 */ - u32 tx_pkt_fifo_609_rsv3; - u32 tx_pkt_fifo_610[3]; /* 0x00006620 */ - u32 tx_pkt_fifo_610_rsv3; - u32 tx_pkt_fifo_611[3]; /* 0x00006630 */ - u32 tx_pkt_fifo_611_rsv3; - u32 tx_pkt_fifo_612[3]; /* 0x00006640 */ - u32 tx_pkt_fifo_612_rsv3; - u32 tx_pkt_fifo_613[3]; /* 0x00006650 */ - u32 tx_pkt_fifo_613_rsv3; - u32 tx_pkt_fifo_614[3]; /* 0x00006660 */ - u32 tx_pkt_fifo_614_rsv3; - u32 tx_pkt_fifo_615[3]; /* 0x00006670 */ - u32 tx_pkt_fifo_615_rsv3; - u32 tx_pkt_fifo_616[3]; /* 0x00006680 */ - u32 tx_pkt_fifo_616_rsv3; - u32 tx_pkt_fifo_617[3]; /* 0x00006690 */ - u32 tx_pkt_fifo_617_rsv3; - u32 tx_pkt_fifo_618[3]; /* 0x000066a0 */ - u32 tx_pkt_fifo_618_rsv3; - u32 tx_pkt_fifo_619[3]; /* 0x000066b0 */ - u32 tx_pkt_fifo_619_rsv3; - u32 tx_pkt_fifo_620[3]; /* 0x000066c0 */ - u32 tx_pkt_fifo_620_rsv3; - u32 tx_pkt_fifo_621[3]; /* 0x000066d0 */ - u32 tx_pkt_fifo_621_rsv3; - u32 tx_pkt_fifo_622[3]; /* 0x000066e0 */ - u32 tx_pkt_fifo_622_rsv3; - u32 tx_pkt_fifo_623[3]; /* 0x000066f0 */ - u32 tx_pkt_fifo_623_rsv3; - u32 tx_pkt_fifo_624[3]; /* 0x00006700 */ - u32 tx_pkt_fifo_624_rsv3; - u32 tx_pkt_fifo_625[3]; /* 0x00006710 */ - u32 tx_pkt_fifo_625_rsv3; - u32 tx_pkt_fifo_626[3]; /* 0x00006720 */ - u32 tx_pkt_fifo_626_rsv3; - u32 tx_pkt_fifo_627[3]; /* 0x00006730 */ - u32 tx_pkt_fifo_627_rsv3; - u32 tx_pkt_fifo_628[3]; /* 0x00006740 */ - u32 tx_pkt_fifo_628_rsv3; - u32 tx_pkt_fifo_629[3]; /* 0x00006750 */ - u32 tx_pkt_fifo_629_rsv3; - u32 tx_pkt_fifo_630[3]; /* 0x00006760 */ - u32 tx_pkt_fifo_630_rsv3; - u32 tx_pkt_fifo_631[3]; /* 0x00006770 */ - u32 tx_pkt_fifo_631_rsv3; - u32 tx_pkt_fifo_632[3]; /* 0x00006780 */ - u32 tx_pkt_fifo_632_rsv3; - u32 tx_pkt_fifo_633[3]; /* 0x00006790 */ - u32 tx_pkt_fifo_633_rsv3; - u32 tx_pkt_fifo_634[3]; /* 0x000067a0 */ - u32 tx_pkt_fifo_634_rsv3; - u32 tx_pkt_fifo_635[3]; /* 0x000067b0 */ - u32 tx_pkt_fifo_635_rsv3; - u32 tx_pkt_fifo_636[3]; /* 0x000067c0 */ - u32 tx_pkt_fifo_636_rsv3; - u32 tx_pkt_fifo_637[3]; /* 0x000067d0 */ - u32 tx_pkt_fifo_637_rsv3; - u32 tx_pkt_fifo_638[3]; /* 0x000067e0 */ - u32 tx_pkt_fifo_638_rsv3; - u32 tx_pkt_fifo_639[3]; /* 0x000067f0 */ - u32 tx_pkt_fifo_639_rsv3; +/* ################################################################################ + * # CpuMacDescCfg1 Definition + */ +#define CPU_MAC_DESC_CFG1_W0_CFG_DESC_SLICE_EN 2 +#define CPU_MAC_DESC_CFG1_W0_CFG_RX_DESC_DONE_INTR_TIMER_EN 0 +#define CPU_MAC_DESC_CFG1_W0_CFG_TX_DESC_DONE_INTR_TIMER_EN 1 +#define CPU_MAC_DESC_CFG1_W1_CFG_RX_DESC_DONE_TIMER_THRD 0 +#define CPU_MAC_DESC_CFG1_W2_CFG_TX_DESC_DONE_TIMER_THRD 0 + +#define CPU_MAC_DESC_CFG1_W0_CFG_DESC_SLICE_EN_MASK 0x00000004 +#define CPU_MAC_DESC_CFG1_W0_CFG_RX_DESC_DONE_INTR_TIMER_EN_MASK 0x00000001 +#define CPU_MAC_DESC_CFG1_W0_CFG_TX_DESC_DONE_INTR_TIMER_EN_MASK 0x00000002 +#define CPU_MAC_DESC_CFG1_W1_CFG_RX_DESC_DONE_TIMER_THRD_MASK 0xffffffff +#define CPU_MAC_DESC_CFG1_W2_CFG_TX_DESC_DONE_TIMER_THRD_MASK 0xffffffff + +/* ################################################################################ + * # CpuMacInterruptFunc0 Definition + */ +#define CPU_MAC_INTERRUPT_FUNC0_W0_VALUE_SET0_CPU_MAC_INTERRUPT_FUNC0 0 +#define CPU_MAC_INTERRUPT_FUNC0_W1_VALUE_RESET0_CPU_MAC_INTERRUPT_FUNC0 0 +#define CPU_MAC_INTERRUPT_FUNC0_W2_MASK_SET0_CPU_MAC_INTERRUPT_FUNC0 0 +#define CPU_MAC_INTERRUPT_FUNC0_W3_MASK_RESET0_CPU_MAC_INTERRUPT_FUNC0 0 + +#define CPU_MAC_INTERRUPT_FUNC0_W0_VALUE_SET0_CPU_MAC_INTERRUPT_FUNC0_MASK 0x00000003 +#define CPU_MAC_INTERRUPT_FUNC0_W1_VALUE_RESET0_CPU_MAC_INTERRUPT_FUNC0_MASK 0x00000003 +#define CPU_MAC_INTERRUPT_FUNC0_W2_MASK_SET0_CPU_MAC_INTERRUPT_FUNC0_MASK 0x00000003 +#define CPU_MAC_INTERRUPT_FUNC0_W3_MASK_RESET0_CPU_MAC_INTERRUPT_FUNC0_MASK 0x00000003 + +/* ################################################################################ + * # CpuMacInterruptFunc1 Definition + */ +#define CPU_MAC_INTERRUPT_FUNC1_W0_VALUE_SET0_CPU_MAC_INTERRUPT_FUNC1 0 +#define CPU_MAC_INTERRUPT_FUNC1_W1_VALUE_RESET0_CPU_MAC_INTERRUPT_FUNC1 0 +#define CPU_MAC_INTERRUPT_FUNC1_W2_MASK_SET0_CPU_MAC_INTERRUPT_FUNC1 0 +#define CPU_MAC_INTERRUPT_FUNC1_W3_MASK_RESET0_CPU_MAC_INTERRUPT_FUNC1 0 + +#define CPU_MAC_INTERRUPT_FUNC1_W0_VALUE_SET0_CPU_MAC_INTERRUPT_FUNC1_MASK 0x00000003 +#define CPU_MAC_INTERRUPT_FUNC1_W1_VALUE_RESET0_CPU_MAC_INTERRUPT_FUNC1_MASK 0x00000003 +#define CPU_MAC_INTERRUPT_FUNC1_W2_MASK_SET0_CPU_MAC_INTERRUPT_FUNC1_MASK 0x00000003 +#define CPU_MAC_INTERRUPT_FUNC1_W3_MASK_RESET0_CPU_MAC_INTERRUPT_FUNC1_MASK 0x00000003 + +struct CpuMac_mems { + u32 TxPktFifo0[3]; /* 0x00004000 */ + u32 TxPktFifo0_rsv3; + u32 TxPktFifo1[3]; /* 0x00004010 */ + u32 TxPktFifo1_rsv3; + u32 TxPktFifo2[3]; /* 0x00004020 */ + u32 TxPktFifo2_rsv3; + u32 TxPktFifo3[3]; /* 0x00004030 */ + u32 TxPktFifo3_rsv3; + u32 TxPktFifo4[3]; /* 0x00004040 */ + u32 TxPktFifo4_rsv3; + u32 TxPktFifo5[3]; /* 0x00004050 */ + u32 TxPktFifo5_rsv3; + u32 TxPktFifo6[3]; /* 0x00004060 */ + u32 TxPktFifo6_rsv3; + u32 TxPktFifo7[3]; /* 0x00004070 */ + u32 TxPktFifo7_rsv3; + u32 TxPktFifo8[3]; /* 0x00004080 */ + u32 TxPktFifo8_rsv3; + u32 TxPktFifo9[3]; /* 0x00004090 */ + u32 TxPktFifo9_rsv3; + u32 TxPktFifo10[3]; /* 0x000040a0 */ + u32 TxPktFifo10_rsv3; + u32 TxPktFifo11[3]; /* 0x000040b0 */ + u32 TxPktFifo11_rsv3; + u32 TxPktFifo12[3]; /* 0x000040c0 */ + u32 TxPktFifo12_rsv3; + u32 TxPktFifo13[3]; /* 0x000040d0 */ + u32 TxPktFifo13_rsv3; + u32 TxPktFifo14[3]; /* 0x000040e0 */ + u32 TxPktFifo14_rsv3; + u32 TxPktFifo15[3]; /* 0x000040f0 */ + u32 TxPktFifo15_rsv3; + u32 TxPktFifo16[3]; /* 0x00004100 */ + u32 TxPktFifo16_rsv3; + u32 TxPktFifo17[3]; /* 0x00004110 */ + u32 TxPktFifo17_rsv3; + u32 TxPktFifo18[3]; /* 0x00004120 */ + u32 TxPktFifo18_rsv3; + u32 TxPktFifo19[3]; /* 0x00004130 */ + u32 TxPktFifo19_rsv3; + u32 TxPktFifo20[3]; /* 0x00004140 */ + u32 TxPktFifo20_rsv3; + u32 TxPktFifo21[3]; /* 0x00004150 */ + u32 TxPktFifo21_rsv3; + u32 TxPktFifo22[3]; /* 0x00004160 */ + u32 TxPktFifo22_rsv3; + u32 TxPktFifo23[3]; /* 0x00004170 */ + u32 TxPktFifo23_rsv3; + u32 TxPktFifo24[3]; /* 0x00004180 */ + u32 TxPktFifo24_rsv3; + u32 TxPktFifo25[3]; /* 0x00004190 */ + u32 TxPktFifo25_rsv3; + u32 TxPktFifo26[3]; /* 0x000041a0 */ + u32 TxPktFifo26_rsv3; + u32 TxPktFifo27[3]; /* 0x000041b0 */ + u32 TxPktFifo27_rsv3; + u32 TxPktFifo28[3]; /* 0x000041c0 */ + u32 TxPktFifo28_rsv3; + u32 TxPktFifo29[3]; /* 0x000041d0 */ + u32 TxPktFifo29_rsv3; + u32 TxPktFifo30[3]; /* 0x000041e0 */ + u32 TxPktFifo30_rsv3; + u32 TxPktFifo31[3]; /* 0x000041f0 */ + u32 TxPktFifo31_rsv3; + u32 TxPktFifo32[3]; /* 0x00004200 */ + u32 TxPktFifo32_rsv3; + u32 TxPktFifo33[3]; /* 0x00004210 */ + u32 TxPktFifo33_rsv3; + u32 TxPktFifo34[3]; /* 0x00004220 */ + u32 TxPktFifo34_rsv3; + u32 TxPktFifo35[3]; /* 0x00004230 */ + u32 TxPktFifo35_rsv3; + u32 TxPktFifo36[3]; /* 0x00004240 */ + u32 TxPktFifo36_rsv3; + u32 TxPktFifo37[3]; /* 0x00004250 */ + u32 TxPktFifo37_rsv3; + u32 TxPktFifo38[3]; /* 0x00004260 */ + u32 TxPktFifo38_rsv3; + u32 TxPktFifo39[3]; /* 0x00004270 */ + u32 TxPktFifo39_rsv3; + u32 TxPktFifo40[3]; /* 0x00004280 */ + u32 TxPktFifo40_rsv3; + u32 TxPktFifo41[3]; /* 0x00004290 */ + u32 TxPktFifo41_rsv3; + u32 TxPktFifo42[3]; /* 0x000042a0 */ + u32 TxPktFifo42_rsv3; + u32 TxPktFifo43[3]; /* 0x000042b0 */ + u32 TxPktFifo43_rsv3; + u32 TxPktFifo44[3]; /* 0x000042c0 */ + u32 TxPktFifo44_rsv3; + u32 TxPktFifo45[3]; /* 0x000042d0 */ + u32 TxPktFifo45_rsv3; + u32 TxPktFifo46[3]; /* 0x000042e0 */ + u32 TxPktFifo46_rsv3; + u32 TxPktFifo47[3]; /* 0x000042f0 */ + u32 TxPktFifo47_rsv3; + u32 TxPktFifo48[3]; /* 0x00004300 */ + u32 TxPktFifo48_rsv3; + u32 TxPktFifo49[3]; /* 0x00004310 */ + u32 TxPktFifo49_rsv3; + u32 TxPktFifo50[3]; /* 0x00004320 */ + u32 TxPktFifo50_rsv3; + u32 TxPktFifo51[3]; /* 0x00004330 */ + u32 TxPktFifo51_rsv3; + u32 TxPktFifo52[3]; /* 0x00004340 */ + u32 TxPktFifo52_rsv3; + u32 TxPktFifo53[3]; /* 0x00004350 */ + u32 TxPktFifo53_rsv3; + u32 TxPktFifo54[3]; /* 0x00004360 */ + u32 TxPktFifo54_rsv3; + u32 TxPktFifo55[3]; /* 0x00004370 */ + u32 TxPktFifo55_rsv3; + u32 TxPktFifo56[3]; /* 0x00004380 */ + u32 TxPktFifo56_rsv3; + u32 TxPktFifo57[3]; /* 0x00004390 */ + u32 TxPktFifo57_rsv3; + u32 TxPktFifo58[3]; /* 0x000043a0 */ + u32 TxPktFifo58_rsv3; + u32 TxPktFifo59[3]; /* 0x000043b0 */ + u32 TxPktFifo59_rsv3; + u32 TxPktFifo60[3]; /* 0x000043c0 */ + u32 TxPktFifo60_rsv3; + u32 TxPktFifo61[3]; /* 0x000043d0 */ + u32 TxPktFifo61_rsv3; + u32 TxPktFifo62[3]; /* 0x000043e0 */ + u32 TxPktFifo62_rsv3; + u32 TxPktFifo63[3]; /* 0x000043f0 */ + u32 TxPktFifo63_rsv3; + u32 TxPktFifo64[3]; /* 0x00004400 */ + u32 TxPktFifo64_rsv3; + u32 TxPktFifo65[3]; /* 0x00004410 */ + u32 TxPktFifo65_rsv3; + u32 TxPktFifo66[3]; /* 0x00004420 */ + u32 TxPktFifo66_rsv3; + u32 TxPktFifo67[3]; /* 0x00004430 */ + u32 TxPktFifo67_rsv3; + u32 TxPktFifo68[3]; /* 0x00004440 */ + u32 TxPktFifo68_rsv3; + u32 TxPktFifo69[3]; /* 0x00004450 */ + u32 TxPktFifo69_rsv3; + u32 TxPktFifo70[3]; /* 0x00004460 */ + u32 TxPktFifo70_rsv3; + u32 TxPktFifo71[3]; /* 0x00004470 */ + u32 TxPktFifo71_rsv3; + u32 TxPktFifo72[3]; /* 0x00004480 */ + u32 TxPktFifo72_rsv3; + u32 TxPktFifo73[3]; /* 0x00004490 */ + u32 TxPktFifo73_rsv3; + u32 TxPktFifo74[3]; /* 0x000044a0 */ + u32 TxPktFifo74_rsv3; + u32 TxPktFifo75[3]; /* 0x000044b0 */ + u32 TxPktFifo75_rsv3; + u32 TxPktFifo76[3]; /* 0x000044c0 */ + u32 TxPktFifo76_rsv3; + u32 TxPktFifo77[3]; /* 0x000044d0 */ + u32 TxPktFifo77_rsv3; + u32 TxPktFifo78[3]; /* 0x000044e0 */ + u32 TxPktFifo78_rsv3; + u32 TxPktFifo79[3]; /* 0x000044f0 */ + u32 TxPktFifo79_rsv3; + u32 TxPktFifo80[3]; /* 0x00004500 */ + u32 TxPktFifo80_rsv3; + u32 TxPktFifo81[3]; /* 0x00004510 */ + u32 TxPktFifo81_rsv3; + u32 TxPktFifo82[3]; /* 0x00004520 */ + u32 TxPktFifo82_rsv3; + u32 TxPktFifo83[3]; /* 0x00004530 */ + u32 TxPktFifo83_rsv3; + u32 TxPktFifo84[3]; /* 0x00004540 */ + u32 TxPktFifo84_rsv3; + u32 TxPktFifo85[3]; /* 0x00004550 */ + u32 TxPktFifo85_rsv3; + u32 TxPktFifo86[3]; /* 0x00004560 */ + u32 TxPktFifo86_rsv3; + u32 TxPktFifo87[3]; /* 0x00004570 */ + u32 TxPktFifo87_rsv3; + u32 TxPktFifo88[3]; /* 0x00004580 */ + u32 TxPktFifo88_rsv3; + u32 TxPktFifo89[3]; /* 0x00004590 */ + u32 TxPktFifo89_rsv3; + u32 TxPktFifo90[3]; /* 0x000045a0 */ + u32 TxPktFifo90_rsv3; + u32 TxPktFifo91[3]; /* 0x000045b0 */ + u32 TxPktFifo91_rsv3; + u32 TxPktFifo92[3]; /* 0x000045c0 */ + u32 TxPktFifo92_rsv3; + u32 TxPktFifo93[3]; /* 0x000045d0 */ + u32 TxPktFifo93_rsv3; + u32 TxPktFifo94[3]; /* 0x000045e0 */ + u32 TxPktFifo94_rsv3; + u32 TxPktFifo95[3]; /* 0x000045f0 */ + u32 TxPktFifo95_rsv3; + u32 TxPktFifo96[3]; /* 0x00004600 */ + u32 TxPktFifo96_rsv3; + u32 TxPktFifo97[3]; /* 0x00004610 */ + u32 TxPktFifo97_rsv3; + u32 TxPktFifo98[3]; /* 0x00004620 */ + u32 TxPktFifo98_rsv3; + u32 TxPktFifo99[3]; /* 0x00004630 */ + u32 TxPktFifo99_rsv3; + u32 TxPktFifo100[3]; /* 0x00004640 */ + u32 TxPktFifo100_rsv3; + u32 TxPktFifo101[3]; /* 0x00004650 */ + u32 TxPktFifo101_rsv3; + u32 TxPktFifo102[3]; /* 0x00004660 */ + u32 TxPktFifo102_rsv3; + u32 TxPktFifo103[3]; /* 0x00004670 */ + u32 TxPktFifo103_rsv3; + u32 TxPktFifo104[3]; /* 0x00004680 */ + u32 TxPktFifo104_rsv3; + u32 TxPktFifo105[3]; /* 0x00004690 */ + u32 TxPktFifo105_rsv3; + u32 TxPktFifo106[3]; /* 0x000046a0 */ + u32 TxPktFifo106_rsv3; + u32 TxPktFifo107[3]; /* 0x000046b0 */ + u32 TxPktFifo107_rsv3; + u32 TxPktFifo108[3]; /* 0x000046c0 */ + u32 TxPktFifo108_rsv3; + u32 TxPktFifo109[3]; /* 0x000046d0 */ + u32 TxPktFifo109_rsv3; + u32 TxPktFifo110[3]; /* 0x000046e0 */ + u32 TxPktFifo110_rsv3; + u32 TxPktFifo111[3]; /* 0x000046f0 */ + u32 TxPktFifo111_rsv3; + u32 TxPktFifo112[3]; /* 0x00004700 */ + u32 TxPktFifo112_rsv3; + u32 TxPktFifo113[3]; /* 0x00004710 */ + u32 TxPktFifo113_rsv3; + u32 TxPktFifo114[3]; /* 0x00004720 */ + u32 TxPktFifo114_rsv3; + u32 TxPktFifo115[3]; /* 0x00004730 */ + u32 TxPktFifo115_rsv3; + u32 TxPktFifo116[3]; /* 0x00004740 */ + u32 TxPktFifo116_rsv3; + u32 TxPktFifo117[3]; /* 0x00004750 */ + u32 TxPktFifo117_rsv3; + u32 TxPktFifo118[3]; /* 0x00004760 */ + u32 TxPktFifo118_rsv3; + u32 TxPktFifo119[3]; /* 0x00004770 */ + u32 TxPktFifo119_rsv3; + u32 TxPktFifo120[3]; /* 0x00004780 */ + u32 TxPktFifo120_rsv3; + u32 TxPktFifo121[3]; /* 0x00004790 */ + u32 TxPktFifo121_rsv3; + u32 TxPktFifo122[3]; /* 0x000047a0 */ + u32 TxPktFifo122_rsv3; + u32 TxPktFifo123[3]; /* 0x000047b0 */ + u32 TxPktFifo123_rsv3; + u32 TxPktFifo124[3]; /* 0x000047c0 */ + u32 TxPktFifo124_rsv3; + u32 TxPktFifo125[3]; /* 0x000047d0 */ + u32 TxPktFifo125_rsv3; + u32 TxPktFifo126[3]; /* 0x000047e0 */ + u32 TxPktFifo126_rsv3; + u32 TxPktFifo127[3]; /* 0x000047f0 */ + u32 TxPktFifo127_rsv3; + u32 TxPktFifo128[3]; /* 0x00004800 */ + u32 TxPktFifo128_rsv3; + u32 TxPktFifo129[3]; /* 0x00004810 */ + u32 TxPktFifo129_rsv3; + u32 TxPktFifo130[3]; /* 0x00004820 */ + u32 TxPktFifo130_rsv3; + u32 TxPktFifo131[3]; /* 0x00004830 */ + u32 TxPktFifo131_rsv3; + u32 TxPktFifo132[3]; /* 0x00004840 */ + u32 TxPktFifo132_rsv3; + u32 TxPktFifo133[3]; /* 0x00004850 */ + u32 TxPktFifo133_rsv3; + u32 TxPktFifo134[3]; /* 0x00004860 */ + u32 TxPktFifo134_rsv3; + u32 TxPktFifo135[3]; /* 0x00004870 */ + u32 TxPktFifo135_rsv3; + u32 TxPktFifo136[3]; /* 0x00004880 */ + u32 TxPktFifo136_rsv3; + u32 TxPktFifo137[3]; /* 0x00004890 */ + u32 TxPktFifo137_rsv3; + u32 TxPktFifo138[3]; /* 0x000048a0 */ + u32 TxPktFifo138_rsv3; + u32 TxPktFifo139[3]; /* 0x000048b0 */ + u32 TxPktFifo139_rsv3; + u32 TxPktFifo140[3]; /* 0x000048c0 */ + u32 TxPktFifo140_rsv3; + u32 TxPktFifo141[3]; /* 0x000048d0 */ + u32 TxPktFifo141_rsv3; + u32 TxPktFifo142[3]; /* 0x000048e0 */ + u32 TxPktFifo142_rsv3; + u32 TxPktFifo143[3]; /* 0x000048f0 */ + u32 TxPktFifo143_rsv3; + u32 TxPktFifo144[3]; /* 0x00004900 */ + u32 TxPktFifo144_rsv3; + u32 TxPktFifo145[3]; /* 0x00004910 */ + u32 TxPktFifo145_rsv3; + u32 TxPktFifo146[3]; /* 0x00004920 */ + u32 TxPktFifo146_rsv3; + u32 TxPktFifo147[3]; /* 0x00004930 */ + u32 TxPktFifo147_rsv3; + u32 TxPktFifo148[3]; /* 0x00004940 */ + u32 TxPktFifo148_rsv3; + u32 TxPktFifo149[3]; /* 0x00004950 */ + u32 TxPktFifo149_rsv3; + u32 TxPktFifo150[3]; /* 0x00004960 */ + u32 TxPktFifo150_rsv3; + u32 TxPktFifo151[3]; /* 0x00004970 */ + u32 TxPktFifo151_rsv3; + u32 TxPktFifo152[3]; /* 0x00004980 */ + u32 TxPktFifo152_rsv3; + u32 TxPktFifo153[3]; /* 0x00004990 */ + u32 TxPktFifo153_rsv3; + u32 TxPktFifo154[3]; /* 0x000049a0 */ + u32 TxPktFifo154_rsv3; + u32 TxPktFifo155[3]; /* 0x000049b0 */ + u32 TxPktFifo155_rsv3; + u32 TxPktFifo156[3]; /* 0x000049c0 */ + u32 TxPktFifo156_rsv3; + u32 TxPktFifo157[3]; /* 0x000049d0 */ + u32 TxPktFifo157_rsv3; + u32 TxPktFifo158[3]; /* 0x000049e0 */ + u32 TxPktFifo158_rsv3; + u32 TxPktFifo159[3]; /* 0x000049f0 */ + u32 TxPktFifo159_rsv3; + u32 TxPktFifo160[3]; /* 0x00004a00 */ + u32 TxPktFifo160_rsv3; + u32 TxPktFifo161[3]; /* 0x00004a10 */ + u32 TxPktFifo161_rsv3; + u32 TxPktFifo162[3]; /* 0x00004a20 */ + u32 TxPktFifo162_rsv3; + u32 TxPktFifo163[3]; /* 0x00004a30 */ + u32 TxPktFifo163_rsv3; + u32 TxPktFifo164[3]; /* 0x00004a40 */ + u32 TxPktFifo164_rsv3; + u32 TxPktFifo165[3]; /* 0x00004a50 */ + u32 TxPktFifo165_rsv3; + u32 TxPktFifo166[3]; /* 0x00004a60 */ + u32 TxPktFifo166_rsv3; + u32 TxPktFifo167[3]; /* 0x00004a70 */ + u32 TxPktFifo167_rsv3; + u32 TxPktFifo168[3]; /* 0x00004a80 */ + u32 TxPktFifo168_rsv3; + u32 TxPktFifo169[3]; /* 0x00004a90 */ + u32 TxPktFifo169_rsv3; + u32 TxPktFifo170[3]; /* 0x00004aa0 */ + u32 TxPktFifo170_rsv3; + u32 TxPktFifo171[3]; /* 0x00004ab0 */ + u32 TxPktFifo171_rsv3; + u32 TxPktFifo172[3]; /* 0x00004ac0 */ + u32 TxPktFifo172_rsv3; + u32 TxPktFifo173[3]; /* 0x00004ad0 */ + u32 TxPktFifo173_rsv3; + u32 TxPktFifo174[3]; /* 0x00004ae0 */ + u32 TxPktFifo174_rsv3; + u32 TxPktFifo175[3]; /* 0x00004af0 */ + u32 TxPktFifo175_rsv3; + u32 TxPktFifo176[3]; /* 0x00004b00 */ + u32 TxPktFifo176_rsv3; + u32 TxPktFifo177[3]; /* 0x00004b10 */ + u32 TxPktFifo177_rsv3; + u32 TxPktFifo178[3]; /* 0x00004b20 */ + u32 TxPktFifo178_rsv3; + u32 TxPktFifo179[3]; /* 0x00004b30 */ + u32 TxPktFifo179_rsv3; + u32 TxPktFifo180[3]; /* 0x00004b40 */ + u32 TxPktFifo180_rsv3; + u32 TxPktFifo181[3]; /* 0x00004b50 */ + u32 TxPktFifo181_rsv3; + u32 TxPktFifo182[3]; /* 0x00004b60 */ + u32 TxPktFifo182_rsv3; + u32 TxPktFifo183[3]; /* 0x00004b70 */ + u32 TxPktFifo183_rsv3; + u32 TxPktFifo184[3]; /* 0x00004b80 */ + u32 TxPktFifo184_rsv3; + u32 TxPktFifo185[3]; /* 0x00004b90 */ + u32 TxPktFifo185_rsv3; + u32 TxPktFifo186[3]; /* 0x00004ba0 */ + u32 TxPktFifo186_rsv3; + u32 TxPktFifo187[3]; /* 0x00004bb0 */ + u32 TxPktFifo187_rsv3; + u32 TxPktFifo188[3]; /* 0x00004bc0 */ + u32 TxPktFifo188_rsv3; + u32 TxPktFifo189[3]; /* 0x00004bd0 */ + u32 TxPktFifo189_rsv3; + u32 TxPktFifo190[3]; /* 0x00004be0 */ + u32 TxPktFifo190_rsv3; + u32 TxPktFifo191[3]; /* 0x00004bf0 */ + u32 TxPktFifo191_rsv3; + u32 TxPktFifo192[3]; /* 0x00004c00 */ + u32 TxPktFifo192_rsv3; + u32 TxPktFifo193[3]; /* 0x00004c10 */ + u32 TxPktFifo193_rsv3; + u32 TxPktFifo194[3]; /* 0x00004c20 */ + u32 TxPktFifo194_rsv3; + u32 TxPktFifo195[3]; /* 0x00004c30 */ + u32 TxPktFifo195_rsv3; + u32 TxPktFifo196[3]; /* 0x00004c40 */ + u32 TxPktFifo196_rsv3; + u32 TxPktFifo197[3]; /* 0x00004c50 */ + u32 TxPktFifo197_rsv3; + u32 TxPktFifo198[3]; /* 0x00004c60 */ + u32 TxPktFifo198_rsv3; + u32 TxPktFifo199[3]; /* 0x00004c70 */ + u32 TxPktFifo199_rsv3; + u32 TxPktFifo200[3]; /* 0x00004c80 */ + u32 TxPktFifo200_rsv3; + u32 TxPktFifo201[3]; /* 0x00004c90 */ + u32 TxPktFifo201_rsv3; + u32 TxPktFifo202[3]; /* 0x00004ca0 */ + u32 TxPktFifo202_rsv3; + u32 TxPktFifo203[3]; /* 0x00004cb0 */ + u32 TxPktFifo203_rsv3; + u32 TxPktFifo204[3]; /* 0x00004cc0 */ + u32 TxPktFifo204_rsv3; + u32 TxPktFifo205[3]; /* 0x00004cd0 */ + u32 TxPktFifo205_rsv3; + u32 TxPktFifo206[3]; /* 0x00004ce0 */ + u32 TxPktFifo206_rsv3; + u32 TxPktFifo207[3]; /* 0x00004cf0 */ + u32 TxPktFifo207_rsv3; + u32 TxPktFifo208[3]; /* 0x00004d00 */ + u32 TxPktFifo208_rsv3; + u32 TxPktFifo209[3]; /* 0x00004d10 */ + u32 TxPktFifo209_rsv3; + u32 TxPktFifo210[3]; /* 0x00004d20 */ + u32 TxPktFifo210_rsv3; + u32 TxPktFifo211[3]; /* 0x00004d30 */ + u32 TxPktFifo211_rsv3; + u32 TxPktFifo212[3]; /* 0x00004d40 */ + u32 TxPktFifo212_rsv3; + u32 TxPktFifo213[3]; /* 0x00004d50 */ + u32 TxPktFifo213_rsv3; + u32 TxPktFifo214[3]; /* 0x00004d60 */ + u32 TxPktFifo214_rsv3; + u32 TxPktFifo215[3]; /* 0x00004d70 */ + u32 TxPktFifo215_rsv3; + u32 TxPktFifo216[3]; /* 0x00004d80 */ + u32 TxPktFifo216_rsv3; + u32 TxPktFifo217[3]; /* 0x00004d90 */ + u32 TxPktFifo217_rsv3; + u32 TxPktFifo218[3]; /* 0x00004da0 */ + u32 TxPktFifo218_rsv3; + u32 TxPktFifo219[3]; /* 0x00004db0 */ + u32 TxPktFifo219_rsv3; + u32 TxPktFifo220[3]; /* 0x00004dc0 */ + u32 TxPktFifo220_rsv3; + u32 TxPktFifo221[3]; /* 0x00004dd0 */ + u32 TxPktFifo221_rsv3; + u32 TxPktFifo222[3]; /* 0x00004de0 */ + u32 TxPktFifo222_rsv3; + u32 TxPktFifo223[3]; /* 0x00004df0 */ + u32 TxPktFifo223_rsv3; + u32 TxPktFifo224[3]; /* 0x00004e00 */ + u32 TxPktFifo224_rsv3; + u32 TxPktFifo225[3]; /* 0x00004e10 */ + u32 TxPktFifo225_rsv3; + u32 TxPktFifo226[3]; /* 0x00004e20 */ + u32 TxPktFifo226_rsv3; + u32 TxPktFifo227[3]; /* 0x00004e30 */ + u32 TxPktFifo227_rsv3; + u32 TxPktFifo228[3]; /* 0x00004e40 */ + u32 TxPktFifo228_rsv3; + u32 TxPktFifo229[3]; /* 0x00004e50 */ + u32 TxPktFifo229_rsv3; + u32 TxPktFifo230[3]; /* 0x00004e60 */ + u32 TxPktFifo230_rsv3; + u32 TxPktFifo231[3]; /* 0x00004e70 */ + u32 TxPktFifo231_rsv3; + u32 TxPktFifo232[3]; /* 0x00004e80 */ + u32 TxPktFifo232_rsv3; + u32 TxPktFifo233[3]; /* 0x00004e90 */ + u32 TxPktFifo233_rsv3; + u32 TxPktFifo234[3]; /* 0x00004ea0 */ + u32 TxPktFifo234_rsv3; + u32 TxPktFifo235[3]; /* 0x00004eb0 */ + u32 TxPktFifo235_rsv3; + u32 TxPktFifo236[3]; /* 0x00004ec0 */ + u32 TxPktFifo236_rsv3; + u32 TxPktFifo237[3]; /* 0x00004ed0 */ + u32 TxPktFifo237_rsv3; + u32 TxPktFifo238[3]; /* 0x00004ee0 */ + u32 TxPktFifo238_rsv3; + u32 TxPktFifo239[3]; /* 0x00004ef0 */ + u32 TxPktFifo239_rsv3; + u32 TxPktFifo240[3]; /* 0x00004f00 */ + u32 TxPktFifo240_rsv3; + u32 TxPktFifo241[3]; /* 0x00004f10 */ + u32 TxPktFifo241_rsv3; + u32 TxPktFifo242[3]; /* 0x00004f20 */ + u32 TxPktFifo242_rsv3; + u32 TxPktFifo243[3]; /* 0x00004f30 */ + u32 TxPktFifo243_rsv3; + u32 TxPktFifo244[3]; /* 0x00004f40 */ + u32 TxPktFifo244_rsv3; + u32 TxPktFifo245[3]; /* 0x00004f50 */ + u32 TxPktFifo245_rsv3; + u32 TxPktFifo246[3]; /* 0x00004f60 */ + u32 TxPktFifo246_rsv3; + u32 TxPktFifo247[3]; /* 0x00004f70 */ + u32 TxPktFifo247_rsv3; + u32 TxPktFifo248[3]; /* 0x00004f80 */ + u32 TxPktFifo248_rsv3; + u32 TxPktFifo249[3]; /* 0x00004f90 */ + u32 TxPktFifo249_rsv3; + u32 TxPktFifo250[3]; /* 0x00004fa0 */ + u32 TxPktFifo250_rsv3; + u32 TxPktFifo251[3]; /* 0x00004fb0 */ + u32 TxPktFifo251_rsv3; + u32 TxPktFifo252[3]; /* 0x00004fc0 */ + u32 TxPktFifo252_rsv3; + u32 TxPktFifo253[3]; /* 0x00004fd0 */ + u32 TxPktFifo253_rsv3; + u32 TxPktFifo254[3]; /* 0x00004fe0 */ + u32 TxPktFifo254_rsv3; + u32 TxPktFifo255[3]; /* 0x00004ff0 */ + u32 TxPktFifo255_rsv3; + u32 TxPktFifo256[3]; /* 0x00005000 */ + u32 TxPktFifo256_rsv3; + u32 TxPktFifo257[3]; /* 0x00005010 */ + u32 TxPktFifo257_rsv3; + u32 TxPktFifo258[3]; /* 0x00005020 */ + u32 TxPktFifo258_rsv3; + u32 TxPktFifo259[3]; /* 0x00005030 */ + u32 TxPktFifo259_rsv3; + u32 TxPktFifo260[3]; /* 0x00005040 */ + u32 TxPktFifo260_rsv3; + u32 TxPktFifo261[3]; /* 0x00005050 */ + u32 TxPktFifo261_rsv3; + u32 TxPktFifo262[3]; /* 0x00005060 */ + u32 TxPktFifo262_rsv3; + u32 TxPktFifo263[3]; /* 0x00005070 */ + u32 TxPktFifo263_rsv3; + u32 TxPktFifo264[3]; /* 0x00005080 */ + u32 TxPktFifo264_rsv3; + u32 TxPktFifo265[3]; /* 0x00005090 */ + u32 TxPktFifo265_rsv3; + u32 TxPktFifo266[3]; /* 0x000050a0 */ + u32 TxPktFifo266_rsv3; + u32 TxPktFifo267[3]; /* 0x000050b0 */ + u32 TxPktFifo267_rsv3; + u32 TxPktFifo268[3]; /* 0x000050c0 */ + u32 TxPktFifo268_rsv3; + u32 TxPktFifo269[3]; /* 0x000050d0 */ + u32 TxPktFifo269_rsv3; + u32 TxPktFifo270[3]; /* 0x000050e0 */ + u32 TxPktFifo270_rsv3; + u32 TxPktFifo271[3]; /* 0x000050f0 */ + u32 TxPktFifo271_rsv3; + u32 TxPktFifo272[3]; /* 0x00005100 */ + u32 TxPktFifo272_rsv3; + u32 TxPktFifo273[3]; /* 0x00005110 */ + u32 TxPktFifo273_rsv3; + u32 TxPktFifo274[3]; /* 0x00005120 */ + u32 TxPktFifo274_rsv3; + u32 TxPktFifo275[3]; /* 0x00005130 */ + u32 TxPktFifo275_rsv3; + u32 TxPktFifo276[3]; /* 0x00005140 */ + u32 TxPktFifo276_rsv3; + u32 TxPktFifo277[3]; /* 0x00005150 */ + u32 TxPktFifo277_rsv3; + u32 TxPktFifo278[3]; /* 0x00005160 */ + u32 TxPktFifo278_rsv3; + u32 TxPktFifo279[3]; /* 0x00005170 */ + u32 TxPktFifo279_rsv3; + u32 TxPktFifo280[3]; /* 0x00005180 */ + u32 TxPktFifo280_rsv3; + u32 TxPktFifo281[3]; /* 0x00005190 */ + u32 TxPktFifo281_rsv3; + u32 TxPktFifo282[3]; /* 0x000051a0 */ + u32 TxPktFifo282_rsv3; + u32 TxPktFifo283[3]; /* 0x000051b0 */ + u32 TxPktFifo283_rsv3; + u32 TxPktFifo284[3]; /* 0x000051c0 */ + u32 TxPktFifo284_rsv3; + u32 TxPktFifo285[3]; /* 0x000051d0 */ + u32 TxPktFifo285_rsv3; + u32 TxPktFifo286[3]; /* 0x000051e0 */ + u32 TxPktFifo286_rsv3; + u32 TxPktFifo287[3]; /* 0x000051f0 */ + u32 TxPktFifo287_rsv3; + u32 TxPktFifo288[3]; /* 0x00005200 */ + u32 TxPktFifo288_rsv3; + u32 TxPktFifo289[3]; /* 0x00005210 */ + u32 TxPktFifo289_rsv3; + u32 TxPktFifo290[3]; /* 0x00005220 */ + u32 TxPktFifo290_rsv3; + u32 TxPktFifo291[3]; /* 0x00005230 */ + u32 TxPktFifo291_rsv3; + u32 TxPktFifo292[3]; /* 0x00005240 */ + u32 TxPktFifo292_rsv3; + u32 TxPktFifo293[3]; /* 0x00005250 */ + u32 TxPktFifo293_rsv3; + u32 TxPktFifo294[3]; /* 0x00005260 */ + u32 TxPktFifo294_rsv3; + u32 TxPktFifo295[3]; /* 0x00005270 */ + u32 TxPktFifo295_rsv3; + u32 TxPktFifo296[3]; /* 0x00005280 */ + u32 TxPktFifo296_rsv3; + u32 TxPktFifo297[3]; /* 0x00005290 */ + u32 TxPktFifo297_rsv3; + u32 TxPktFifo298[3]; /* 0x000052a0 */ + u32 TxPktFifo298_rsv3; + u32 TxPktFifo299[3]; /* 0x000052b0 */ + u32 TxPktFifo299_rsv3; + u32 TxPktFifo300[3]; /* 0x000052c0 */ + u32 TxPktFifo300_rsv3; + u32 TxPktFifo301[3]; /* 0x000052d0 */ + u32 TxPktFifo301_rsv3; + u32 TxPktFifo302[3]; /* 0x000052e0 */ + u32 TxPktFifo302_rsv3; + u32 TxPktFifo303[3]; /* 0x000052f0 */ + u32 TxPktFifo303_rsv3; + u32 TxPktFifo304[3]; /* 0x00005300 */ + u32 TxPktFifo304_rsv3; + u32 TxPktFifo305[3]; /* 0x00005310 */ + u32 TxPktFifo305_rsv3; + u32 TxPktFifo306[3]; /* 0x00005320 */ + u32 TxPktFifo306_rsv3; + u32 TxPktFifo307[3]; /* 0x00005330 */ + u32 TxPktFifo307_rsv3; + u32 TxPktFifo308[3]; /* 0x00005340 */ + u32 TxPktFifo308_rsv3; + u32 TxPktFifo309[3]; /* 0x00005350 */ + u32 TxPktFifo309_rsv3; + u32 TxPktFifo310[3]; /* 0x00005360 */ + u32 TxPktFifo310_rsv3; + u32 TxPktFifo311[3]; /* 0x00005370 */ + u32 TxPktFifo311_rsv3; + u32 TxPktFifo312[3]; /* 0x00005380 */ + u32 TxPktFifo312_rsv3; + u32 TxPktFifo313[3]; /* 0x00005390 */ + u32 TxPktFifo313_rsv3; + u32 TxPktFifo314[3]; /* 0x000053a0 */ + u32 TxPktFifo314_rsv3; + u32 TxPktFifo315[3]; /* 0x000053b0 */ + u32 TxPktFifo315_rsv3; + u32 TxPktFifo316[3]; /* 0x000053c0 */ + u32 TxPktFifo316_rsv3; + u32 TxPktFifo317[3]; /* 0x000053d0 */ + u32 TxPktFifo317_rsv3; + u32 TxPktFifo318[3]; /* 0x000053e0 */ + u32 TxPktFifo318_rsv3; + u32 TxPktFifo319[3]; /* 0x000053f0 */ + u32 TxPktFifo319_rsv3; + u32 TxPktFifo320[3]; /* 0x00005400 */ + u32 TxPktFifo320_rsv3; + u32 TxPktFifo321[3]; /* 0x00005410 */ + u32 TxPktFifo321_rsv3; + u32 TxPktFifo322[3]; /* 0x00005420 */ + u32 TxPktFifo322_rsv3; + u32 TxPktFifo323[3]; /* 0x00005430 */ + u32 TxPktFifo323_rsv3; + u32 TxPktFifo324[3]; /* 0x00005440 */ + u32 TxPktFifo324_rsv3; + u32 TxPktFifo325[3]; /* 0x00005450 */ + u32 TxPktFifo325_rsv3; + u32 TxPktFifo326[3]; /* 0x00005460 */ + u32 TxPktFifo326_rsv3; + u32 TxPktFifo327[3]; /* 0x00005470 */ + u32 TxPktFifo327_rsv3; + u32 TxPktFifo328[3]; /* 0x00005480 */ + u32 TxPktFifo328_rsv3; + u32 TxPktFifo329[3]; /* 0x00005490 */ + u32 TxPktFifo329_rsv3; + u32 TxPktFifo330[3]; /* 0x000054a0 */ + u32 TxPktFifo330_rsv3; + u32 TxPktFifo331[3]; /* 0x000054b0 */ + u32 TxPktFifo331_rsv3; + u32 TxPktFifo332[3]; /* 0x000054c0 */ + u32 TxPktFifo332_rsv3; + u32 TxPktFifo333[3]; /* 0x000054d0 */ + u32 TxPktFifo333_rsv3; + u32 TxPktFifo334[3]; /* 0x000054e0 */ + u32 TxPktFifo334_rsv3; + u32 TxPktFifo335[3]; /* 0x000054f0 */ + u32 TxPktFifo335_rsv3; + u32 TxPktFifo336[3]; /* 0x00005500 */ + u32 TxPktFifo336_rsv3; + u32 TxPktFifo337[3]; /* 0x00005510 */ + u32 TxPktFifo337_rsv3; + u32 TxPktFifo338[3]; /* 0x00005520 */ + u32 TxPktFifo338_rsv3; + u32 TxPktFifo339[3]; /* 0x00005530 */ + u32 TxPktFifo339_rsv3; + u32 TxPktFifo340[3]; /* 0x00005540 */ + u32 TxPktFifo340_rsv3; + u32 TxPktFifo341[3]; /* 0x00005550 */ + u32 TxPktFifo341_rsv3; + u32 TxPktFifo342[3]; /* 0x00005560 */ + u32 TxPktFifo342_rsv3; + u32 TxPktFifo343[3]; /* 0x00005570 */ + u32 TxPktFifo343_rsv3; + u32 TxPktFifo344[3]; /* 0x00005580 */ + u32 TxPktFifo344_rsv3; + u32 TxPktFifo345[3]; /* 0x00005590 */ + u32 TxPktFifo345_rsv3; + u32 TxPktFifo346[3]; /* 0x000055a0 */ + u32 TxPktFifo346_rsv3; + u32 TxPktFifo347[3]; /* 0x000055b0 */ + u32 TxPktFifo347_rsv3; + u32 TxPktFifo348[3]; /* 0x000055c0 */ + u32 TxPktFifo348_rsv3; + u32 TxPktFifo349[3]; /* 0x000055d0 */ + u32 TxPktFifo349_rsv3; + u32 TxPktFifo350[3]; /* 0x000055e0 */ + u32 TxPktFifo350_rsv3; + u32 TxPktFifo351[3]; /* 0x000055f0 */ + u32 TxPktFifo351_rsv3; + u32 TxPktFifo352[3]; /* 0x00005600 */ + u32 TxPktFifo352_rsv3; + u32 TxPktFifo353[3]; /* 0x00005610 */ + u32 TxPktFifo353_rsv3; + u32 TxPktFifo354[3]; /* 0x00005620 */ + u32 TxPktFifo354_rsv3; + u32 TxPktFifo355[3]; /* 0x00005630 */ + u32 TxPktFifo355_rsv3; + u32 TxPktFifo356[3]; /* 0x00005640 */ + u32 TxPktFifo356_rsv3; + u32 TxPktFifo357[3]; /* 0x00005650 */ + u32 TxPktFifo357_rsv3; + u32 TxPktFifo358[3]; /* 0x00005660 */ + u32 TxPktFifo358_rsv3; + u32 TxPktFifo359[3]; /* 0x00005670 */ + u32 TxPktFifo359_rsv3; + u32 TxPktFifo360[3]; /* 0x00005680 */ + u32 TxPktFifo360_rsv3; + u32 TxPktFifo361[3]; /* 0x00005690 */ + u32 TxPktFifo361_rsv3; + u32 TxPktFifo362[3]; /* 0x000056a0 */ + u32 TxPktFifo362_rsv3; + u32 TxPktFifo363[3]; /* 0x000056b0 */ + u32 TxPktFifo363_rsv3; + u32 TxPktFifo364[3]; /* 0x000056c0 */ + u32 TxPktFifo364_rsv3; + u32 TxPktFifo365[3]; /* 0x000056d0 */ + u32 TxPktFifo365_rsv3; + u32 TxPktFifo366[3]; /* 0x000056e0 */ + u32 TxPktFifo366_rsv3; + u32 TxPktFifo367[3]; /* 0x000056f0 */ + u32 TxPktFifo367_rsv3; + u32 TxPktFifo368[3]; /* 0x00005700 */ + u32 TxPktFifo368_rsv3; + u32 TxPktFifo369[3]; /* 0x00005710 */ + u32 TxPktFifo369_rsv3; + u32 TxPktFifo370[3]; /* 0x00005720 */ + u32 TxPktFifo370_rsv3; + u32 TxPktFifo371[3]; /* 0x00005730 */ + u32 TxPktFifo371_rsv3; + u32 TxPktFifo372[3]; /* 0x00005740 */ + u32 TxPktFifo372_rsv3; + u32 TxPktFifo373[3]; /* 0x00005750 */ + u32 TxPktFifo373_rsv3; + u32 TxPktFifo374[3]; /* 0x00005760 */ + u32 TxPktFifo374_rsv3; + u32 TxPktFifo375[3]; /* 0x00005770 */ + u32 TxPktFifo375_rsv3; + u32 TxPktFifo376[3]; /* 0x00005780 */ + u32 TxPktFifo376_rsv3; + u32 TxPktFifo377[3]; /* 0x00005790 */ + u32 TxPktFifo377_rsv3; + u32 TxPktFifo378[3]; /* 0x000057a0 */ + u32 TxPktFifo378_rsv3; + u32 TxPktFifo379[3]; /* 0x000057b0 */ + u32 TxPktFifo379_rsv3; + u32 TxPktFifo380[3]; /* 0x000057c0 */ + u32 TxPktFifo380_rsv3; + u32 TxPktFifo381[3]; /* 0x000057d0 */ + u32 TxPktFifo381_rsv3; + u32 TxPktFifo382[3]; /* 0x000057e0 */ + u32 TxPktFifo382_rsv3; + u32 TxPktFifo383[3]; /* 0x000057f0 */ + u32 TxPktFifo383_rsv3; + u32 TxPktFifo384[3]; /* 0x00005800 */ + u32 TxPktFifo384_rsv3; + u32 TxPktFifo385[3]; /* 0x00005810 */ + u32 TxPktFifo385_rsv3; + u32 TxPktFifo386[3]; /* 0x00005820 */ + u32 TxPktFifo386_rsv3; + u32 TxPktFifo387[3]; /* 0x00005830 */ + u32 TxPktFifo387_rsv3; + u32 TxPktFifo388[3]; /* 0x00005840 */ + u32 TxPktFifo388_rsv3; + u32 TxPktFifo389[3]; /* 0x00005850 */ + u32 TxPktFifo389_rsv3; + u32 TxPktFifo390[3]; /* 0x00005860 */ + u32 TxPktFifo390_rsv3; + u32 TxPktFifo391[3]; /* 0x00005870 */ + u32 TxPktFifo391_rsv3; + u32 TxPktFifo392[3]; /* 0x00005880 */ + u32 TxPktFifo392_rsv3; + u32 TxPktFifo393[3]; /* 0x00005890 */ + u32 TxPktFifo393_rsv3; + u32 TxPktFifo394[3]; /* 0x000058a0 */ + u32 TxPktFifo394_rsv3; + u32 TxPktFifo395[3]; /* 0x000058b0 */ + u32 TxPktFifo395_rsv3; + u32 TxPktFifo396[3]; /* 0x000058c0 */ + u32 TxPktFifo396_rsv3; + u32 TxPktFifo397[3]; /* 0x000058d0 */ + u32 TxPktFifo397_rsv3; + u32 TxPktFifo398[3]; /* 0x000058e0 */ + u32 TxPktFifo398_rsv3; + u32 TxPktFifo399[3]; /* 0x000058f0 */ + u32 TxPktFifo399_rsv3; + u32 TxPktFifo400[3]; /* 0x00005900 */ + u32 TxPktFifo400_rsv3; + u32 TxPktFifo401[3]; /* 0x00005910 */ + u32 TxPktFifo401_rsv3; + u32 TxPktFifo402[3]; /* 0x00005920 */ + u32 TxPktFifo402_rsv3; + u32 TxPktFifo403[3]; /* 0x00005930 */ + u32 TxPktFifo403_rsv3; + u32 TxPktFifo404[3]; /* 0x00005940 */ + u32 TxPktFifo404_rsv3; + u32 TxPktFifo405[3]; /* 0x00005950 */ + u32 TxPktFifo405_rsv3; + u32 TxPktFifo406[3]; /* 0x00005960 */ + u32 TxPktFifo406_rsv3; + u32 TxPktFifo407[3]; /* 0x00005970 */ + u32 TxPktFifo407_rsv3; + u32 TxPktFifo408[3]; /* 0x00005980 */ + u32 TxPktFifo408_rsv3; + u32 TxPktFifo409[3]; /* 0x00005990 */ + u32 TxPktFifo409_rsv3; + u32 TxPktFifo410[3]; /* 0x000059a0 */ + u32 TxPktFifo410_rsv3; + u32 TxPktFifo411[3]; /* 0x000059b0 */ + u32 TxPktFifo411_rsv3; + u32 TxPktFifo412[3]; /* 0x000059c0 */ + u32 TxPktFifo412_rsv3; + u32 TxPktFifo413[3]; /* 0x000059d0 */ + u32 TxPktFifo413_rsv3; + u32 TxPktFifo414[3]; /* 0x000059e0 */ + u32 TxPktFifo414_rsv3; + u32 TxPktFifo415[3]; /* 0x000059f0 */ + u32 TxPktFifo415_rsv3; + u32 TxPktFifo416[3]; /* 0x00005a00 */ + u32 TxPktFifo416_rsv3; + u32 TxPktFifo417[3]; /* 0x00005a10 */ + u32 TxPktFifo417_rsv3; + u32 TxPktFifo418[3]; /* 0x00005a20 */ + u32 TxPktFifo418_rsv3; + u32 TxPktFifo419[3]; /* 0x00005a30 */ + u32 TxPktFifo419_rsv3; + u32 TxPktFifo420[3]; /* 0x00005a40 */ + u32 TxPktFifo420_rsv3; + u32 TxPktFifo421[3]; /* 0x00005a50 */ + u32 TxPktFifo421_rsv3; + u32 TxPktFifo422[3]; /* 0x00005a60 */ + u32 TxPktFifo422_rsv3; + u32 TxPktFifo423[3]; /* 0x00005a70 */ + u32 TxPktFifo423_rsv3; + u32 TxPktFifo424[3]; /* 0x00005a80 */ + u32 TxPktFifo424_rsv3; + u32 TxPktFifo425[3]; /* 0x00005a90 */ + u32 TxPktFifo425_rsv3; + u32 TxPktFifo426[3]; /* 0x00005aa0 */ + u32 TxPktFifo426_rsv3; + u32 TxPktFifo427[3]; /* 0x00005ab0 */ + u32 TxPktFifo427_rsv3; + u32 TxPktFifo428[3]; /* 0x00005ac0 */ + u32 TxPktFifo428_rsv3; + u32 TxPktFifo429[3]; /* 0x00005ad0 */ + u32 TxPktFifo429_rsv3; + u32 TxPktFifo430[3]; /* 0x00005ae0 */ + u32 TxPktFifo430_rsv3; + u32 TxPktFifo431[3]; /* 0x00005af0 */ + u32 TxPktFifo431_rsv3; + u32 TxPktFifo432[3]; /* 0x00005b00 */ + u32 TxPktFifo432_rsv3; + u32 TxPktFifo433[3]; /* 0x00005b10 */ + u32 TxPktFifo433_rsv3; + u32 TxPktFifo434[3]; /* 0x00005b20 */ + u32 TxPktFifo434_rsv3; + u32 TxPktFifo435[3]; /* 0x00005b30 */ + u32 TxPktFifo435_rsv3; + u32 TxPktFifo436[3]; /* 0x00005b40 */ + u32 TxPktFifo436_rsv3; + u32 TxPktFifo437[3]; /* 0x00005b50 */ + u32 TxPktFifo437_rsv3; + u32 TxPktFifo438[3]; /* 0x00005b60 */ + u32 TxPktFifo438_rsv3; + u32 TxPktFifo439[3]; /* 0x00005b70 */ + u32 TxPktFifo439_rsv3; + u32 TxPktFifo440[3]; /* 0x00005b80 */ + u32 TxPktFifo440_rsv3; + u32 TxPktFifo441[3]; /* 0x00005b90 */ + u32 TxPktFifo441_rsv3; + u32 TxPktFifo442[3]; /* 0x00005ba0 */ + u32 TxPktFifo442_rsv3; + u32 TxPktFifo443[3]; /* 0x00005bb0 */ + u32 TxPktFifo443_rsv3; + u32 TxPktFifo444[3]; /* 0x00005bc0 */ + u32 TxPktFifo444_rsv3; + u32 TxPktFifo445[3]; /* 0x00005bd0 */ + u32 TxPktFifo445_rsv3; + u32 TxPktFifo446[3]; /* 0x00005be0 */ + u32 TxPktFifo446_rsv3; + u32 TxPktFifo447[3]; /* 0x00005bf0 */ + u32 TxPktFifo447_rsv3; + u32 TxPktFifo448[3]; /* 0x00005c00 */ + u32 TxPktFifo448_rsv3; + u32 TxPktFifo449[3]; /* 0x00005c10 */ + u32 TxPktFifo449_rsv3; + u32 TxPktFifo450[3]; /* 0x00005c20 */ + u32 TxPktFifo450_rsv3; + u32 TxPktFifo451[3]; /* 0x00005c30 */ + u32 TxPktFifo451_rsv3; + u32 TxPktFifo452[3]; /* 0x00005c40 */ + u32 TxPktFifo452_rsv3; + u32 TxPktFifo453[3]; /* 0x00005c50 */ + u32 TxPktFifo453_rsv3; + u32 TxPktFifo454[3]; /* 0x00005c60 */ + u32 TxPktFifo454_rsv3; + u32 TxPktFifo455[3]; /* 0x00005c70 */ + u32 TxPktFifo455_rsv3; + u32 TxPktFifo456[3]; /* 0x00005c80 */ + u32 TxPktFifo456_rsv3; + u32 TxPktFifo457[3]; /* 0x00005c90 */ + u32 TxPktFifo457_rsv3; + u32 TxPktFifo458[3]; /* 0x00005ca0 */ + u32 TxPktFifo458_rsv3; + u32 TxPktFifo459[3]; /* 0x00005cb0 */ + u32 TxPktFifo459_rsv3; + u32 TxPktFifo460[3]; /* 0x00005cc0 */ + u32 TxPktFifo460_rsv3; + u32 TxPktFifo461[3]; /* 0x00005cd0 */ + u32 TxPktFifo461_rsv3; + u32 TxPktFifo462[3]; /* 0x00005ce0 */ + u32 TxPktFifo462_rsv3; + u32 TxPktFifo463[3]; /* 0x00005cf0 */ + u32 TxPktFifo463_rsv3; + u32 TxPktFifo464[3]; /* 0x00005d00 */ + u32 TxPktFifo464_rsv3; + u32 TxPktFifo465[3]; /* 0x00005d10 */ + u32 TxPktFifo465_rsv3; + u32 TxPktFifo466[3]; /* 0x00005d20 */ + u32 TxPktFifo466_rsv3; + u32 TxPktFifo467[3]; /* 0x00005d30 */ + u32 TxPktFifo467_rsv3; + u32 TxPktFifo468[3]; /* 0x00005d40 */ + u32 TxPktFifo468_rsv3; + u32 TxPktFifo469[3]; /* 0x00005d50 */ + u32 TxPktFifo469_rsv3; + u32 TxPktFifo470[3]; /* 0x00005d60 */ + u32 TxPktFifo470_rsv3; + u32 TxPktFifo471[3]; /* 0x00005d70 */ + u32 TxPktFifo471_rsv3; + u32 TxPktFifo472[3]; /* 0x00005d80 */ + u32 TxPktFifo472_rsv3; + u32 TxPktFifo473[3]; /* 0x00005d90 */ + u32 TxPktFifo473_rsv3; + u32 TxPktFifo474[3]; /* 0x00005da0 */ + u32 TxPktFifo474_rsv3; + u32 TxPktFifo475[3]; /* 0x00005db0 */ + u32 TxPktFifo475_rsv3; + u32 TxPktFifo476[3]; /* 0x00005dc0 */ + u32 TxPktFifo476_rsv3; + u32 TxPktFifo477[3]; /* 0x00005dd0 */ + u32 TxPktFifo477_rsv3; + u32 TxPktFifo478[3]; /* 0x00005de0 */ + u32 TxPktFifo478_rsv3; + u32 TxPktFifo479[3]; /* 0x00005df0 */ + u32 TxPktFifo479_rsv3; + u32 TxPktFifo480[3]; /* 0x00005e00 */ + u32 TxPktFifo480_rsv3; + u32 TxPktFifo481[3]; /* 0x00005e10 */ + u32 TxPktFifo481_rsv3; + u32 TxPktFifo482[3]; /* 0x00005e20 */ + u32 TxPktFifo482_rsv3; + u32 TxPktFifo483[3]; /* 0x00005e30 */ + u32 TxPktFifo483_rsv3; + u32 TxPktFifo484[3]; /* 0x00005e40 */ + u32 TxPktFifo484_rsv3; + u32 TxPktFifo485[3]; /* 0x00005e50 */ + u32 TxPktFifo485_rsv3; + u32 TxPktFifo486[3]; /* 0x00005e60 */ + u32 TxPktFifo486_rsv3; + u32 TxPktFifo487[3]; /* 0x00005e70 */ + u32 TxPktFifo487_rsv3; + u32 TxPktFifo488[3]; /* 0x00005e80 */ + u32 TxPktFifo488_rsv3; + u32 TxPktFifo489[3]; /* 0x00005e90 */ + u32 TxPktFifo489_rsv3; + u32 TxPktFifo490[3]; /* 0x00005ea0 */ + u32 TxPktFifo490_rsv3; + u32 TxPktFifo491[3]; /* 0x00005eb0 */ + u32 TxPktFifo491_rsv3; + u32 TxPktFifo492[3]; /* 0x00005ec0 */ + u32 TxPktFifo492_rsv3; + u32 TxPktFifo493[3]; /* 0x00005ed0 */ + u32 TxPktFifo493_rsv3; + u32 TxPktFifo494[3]; /* 0x00005ee0 */ + u32 TxPktFifo494_rsv3; + u32 TxPktFifo495[3]; /* 0x00005ef0 */ + u32 TxPktFifo495_rsv3; + u32 TxPktFifo496[3]; /* 0x00005f00 */ + u32 TxPktFifo496_rsv3; + u32 TxPktFifo497[3]; /* 0x00005f10 */ + u32 TxPktFifo497_rsv3; + u32 TxPktFifo498[3]; /* 0x00005f20 */ + u32 TxPktFifo498_rsv3; + u32 TxPktFifo499[3]; /* 0x00005f30 */ + u32 TxPktFifo499_rsv3; + u32 TxPktFifo500[3]; /* 0x00005f40 */ + u32 TxPktFifo500_rsv3; + u32 TxPktFifo501[3]; /* 0x00005f50 */ + u32 TxPktFifo501_rsv3; + u32 TxPktFifo502[3]; /* 0x00005f60 */ + u32 TxPktFifo502_rsv3; + u32 TxPktFifo503[3]; /* 0x00005f70 */ + u32 TxPktFifo503_rsv3; + u32 TxPktFifo504[3]; /* 0x00005f80 */ + u32 TxPktFifo504_rsv3; + u32 TxPktFifo505[3]; /* 0x00005f90 */ + u32 TxPktFifo505_rsv3; + u32 TxPktFifo506[3]; /* 0x00005fa0 */ + u32 TxPktFifo506_rsv3; + u32 TxPktFifo507[3]; /* 0x00005fb0 */ + u32 TxPktFifo507_rsv3; + u32 TxPktFifo508[3]; /* 0x00005fc0 */ + u32 TxPktFifo508_rsv3; + u32 TxPktFifo509[3]; /* 0x00005fd0 */ + u32 TxPktFifo509_rsv3; + u32 TxPktFifo510[3]; /* 0x00005fe0 */ + u32 TxPktFifo510_rsv3; + u32 TxPktFifo511[3]; /* 0x00005ff0 */ + u32 TxPktFifo511_rsv3; + u32 TxPktFifo512[3]; /* 0x00006000 */ + u32 TxPktFifo512_rsv3; + u32 TxPktFifo513[3]; /* 0x00006010 */ + u32 TxPktFifo513_rsv3; + u32 TxPktFifo514[3]; /* 0x00006020 */ + u32 TxPktFifo514_rsv3; + u32 TxPktFifo515[3]; /* 0x00006030 */ + u32 TxPktFifo515_rsv3; + u32 TxPktFifo516[3]; /* 0x00006040 */ + u32 TxPktFifo516_rsv3; + u32 TxPktFifo517[3]; /* 0x00006050 */ + u32 TxPktFifo517_rsv3; + u32 TxPktFifo518[3]; /* 0x00006060 */ + u32 TxPktFifo518_rsv3; + u32 TxPktFifo519[3]; /* 0x00006070 */ + u32 TxPktFifo519_rsv3; + u32 TxPktFifo520[3]; /* 0x00006080 */ + u32 TxPktFifo520_rsv3; + u32 TxPktFifo521[3]; /* 0x00006090 */ + u32 TxPktFifo521_rsv3; + u32 TxPktFifo522[3]; /* 0x000060a0 */ + u32 TxPktFifo522_rsv3; + u32 TxPktFifo523[3]; /* 0x000060b0 */ + u32 TxPktFifo523_rsv3; + u32 TxPktFifo524[3]; /* 0x000060c0 */ + u32 TxPktFifo524_rsv3; + u32 TxPktFifo525[3]; /* 0x000060d0 */ + u32 TxPktFifo525_rsv3; + u32 TxPktFifo526[3]; /* 0x000060e0 */ + u32 TxPktFifo526_rsv3; + u32 TxPktFifo527[3]; /* 0x000060f0 */ + u32 TxPktFifo527_rsv3; + u32 TxPktFifo528[3]; /* 0x00006100 */ + u32 TxPktFifo528_rsv3; + u32 TxPktFifo529[3]; /* 0x00006110 */ + u32 TxPktFifo529_rsv3; + u32 TxPktFifo530[3]; /* 0x00006120 */ + u32 TxPktFifo530_rsv3; + u32 TxPktFifo531[3]; /* 0x00006130 */ + u32 TxPktFifo531_rsv3; + u32 TxPktFifo532[3]; /* 0x00006140 */ + u32 TxPktFifo532_rsv3; + u32 TxPktFifo533[3]; /* 0x00006150 */ + u32 TxPktFifo533_rsv3; + u32 TxPktFifo534[3]; /* 0x00006160 */ + u32 TxPktFifo534_rsv3; + u32 TxPktFifo535[3]; /* 0x00006170 */ + u32 TxPktFifo535_rsv3; + u32 TxPktFifo536[3]; /* 0x00006180 */ + u32 TxPktFifo536_rsv3; + u32 TxPktFifo537[3]; /* 0x00006190 */ + u32 TxPktFifo537_rsv3; + u32 TxPktFifo538[3]; /* 0x000061a0 */ + u32 TxPktFifo538_rsv3; + u32 TxPktFifo539[3]; /* 0x000061b0 */ + u32 TxPktFifo539_rsv3; + u32 TxPktFifo540[3]; /* 0x000061c0 */ + u32 TxPktFifo540_rsv3; + u32 TxPktFifo541[3]; /* 0x000061d0 */ + u32 TxPktFifo541_rsv3; + u32 TxPktFifo542[3]; /* 0x000061e0 */ + u32 TxPktFifo542_rsv3; + u32 TxPktFifo543[3]; /* 0x000061f0 */ + u32 TxPktFifo543_rsv3; + u32 TxPktFifo544[3]; /* 0x00006200 */ + u32 TxPktFifo544_rsv3; + u32 TxPktFifo545[3]; /* 0x00006210 */ + u32 TxPktFifo545_rsv3; + u32 TxPktFifo546[3]; /* 0x00006220 */ + u32 TxPktFifo546_rsv3; + u32 TxPktFifo547[3]; /* 0x00006230 */ + u32 TxPktFifo547_rsv3; + u32 TxPktFifo548[3]; /* 0x00006240 */ + u32 TxPktFifo548_rsv3; + u32 TxPktFifo549[3]; /* 0x00006250 */ + u32 TxPktFifo549_rsv3; + u32 TxPktFifo550[3]; /* 0x00006260 */ + u32 TxPktFifo550_rsv3; + u32 TxPktFifo551[3]; /* 0x00006270 */ + u32 TxPktFifo551_rsv3; + u32 TxPktFifo552[3]; /* 0x00006280 */ + u32 TxPktFifo552_rsv3; + u32 TxPktFifo553[3]; /* 0x00006290 */ + u32 TxPktFifo553_rsv3; + u32 TxPktFifo554[3]; /* 0x000062a0 */ + u32 TxPktFifo554_rsv3; + u32 TxPktFifo555[3]; /* 0x000062b0 */ + u32 TxPktFifo555_rsv3; + u32 TxPktFifo556[3]; /* 0x000062c0 */ + u32 TxPktFifo556_rsv3; + u32 TxPktFifo557[3]; /* 0x000062d0 */ + u32 TxPktFifo557_rsv3; + u32 TxPktFifo558[3]; /* 0x000062e0 */ + u32 TxPktFifo558_rsv3; + u32 TxPktFifo559[3]; /* 0x000062f0 */ + u32 TxPktFifo559_rsv3; + u32 TxPktFifo560[3]; /* 0x00006300 */ + u32 TxPktFifo560_rsv3; + u32 TxPktFifo561[3]; /* 0x00006310 */ + u32 TxPktFifo561_rsv3; + u32 TxPktFifo562[3]; /* 0x00006320 */ + u32 TxPktFifo562_rsv3; + u32 TxPktFifo563[3]; /* 0x00006330 */ + u32 TxPktFifo563_rsv3; + u32 TxPktFifo564[3]; /* 0x00006340 */ + u32 TxPktFifo564_rsv3; + u32 TxPktFifo565[3]; /* 0x00006350 */ + u32 TxPktFifo565_rsv3; + u32 TxPktFifo566[3]; /* 0x00006360 */ + u32 TxPktFifo566_rsv3; + u32 TxPktFifo567[3]; /* 0x00006370 */ + u32 TxPktFifo567_rsv3; + u32 TxPktFifo568[3]; /* 0x00006380 */ + u32 TxPktFifo568_rsv3; + u32 TxPktFifo569[3]; /* 0x00006390 */ + u32 TxPktFifo569_rsv3; + u32 TxPktFifo570[3]; /* 0x000063a0 */ + u32 TxPktFifo570_rsv3; + u32 TxPktFifo571[3]; /* 0x000063b0 */ + u32 TxPktFifo571_rsv3; + u32 TxPktFifo572[3]; /* 0x000063c0 */ + u32 TxPktFifo572_rsv3; + u32 TxPktFifo573[3]; /* 0x000063d0 */ + u32 TxPktFifo573_rsv3; + u32 TxPktFifo574[3]; /* 0x000063e0 */ + u32 TxPktFifo574_rsv3; + u32 TxPktFifo575[3]; /* 0x000063f0 */ + u32 TxPktFifo575_rsv3; + u32 TxPktFifo576[3]; /* 0x00006400 */ + u32 TxPktFifo576_rsv3; + u32 TxPktFifo577[3]; /* 0x00006410 */ + u32 TxPktFifo577_rsv3; + u32 TxPktFifo578[3]; /* 0x00006420 */ + u32 TxPktFifo578_rsv3; + u32 TxPktFifo579[3]; /* 0x00006430 */ + u32 TxPktFifo579_rsv3; + u32 TxPktFifo580[3]; /* 0x00006440 */ + u32 TxPktFifo580_rsv3; + u32 TxPktFifo581[3]; /* 0x00006450 */ + u32 TxPktFifo581_rsv3; + u32 TxPktFifo582[3]; /* 0x00006460 */ + u32 TxPktFifo582_rsv3; + u32 TxPktFifo583[3]; /* 0x00006470 */ + u32 TxPktFifo583_rsv3; + u32 TxPktFifo584[3]; /* 0x00006480 */ + u32 TxPktFifo584_rsv3; + u32 TxPktFifo585[3]; /* 0x00006490 */ + u32 TxPktFifo585_rsv3; + u32 TxPktFifo586[3]; /* 0x000064a0 */ + u32 TxPktFifo586_rsv3; + u32 TxPktFifo587[3]; /* 0x000064b0 */ + u32 TxPktFifo587_rsv3; + u32 TxPktFifo588[3]; /* 0x000064c0 */ + u32 TxPktFifo588_rsv3; + u32 TxPktFifo589[3]; /* 0x000064d0 */ + u32 TxPktFifo589_rsv3; + u32 TxPktFifo590[3]; /* 0x000064e0 */ + u32 TxPktFifo590_rsv3; + u32 TxPktFifo591[3]; /* 0x000064f0 */ + u32 TxPktFifo591_rsv3; + u32 TxPktFifo592[3]; /* 0x00006500 */ + u32 TxPktFifo592_rsv3; + u32 TxPktFifo593[3]; /* 0x00006510 */ + u32 TxPktFifo593_rsv3; + u32 TxPktFifo594[3]; /* 0x00006520 */ + u32 TxPktFifo594_rsv3; + u32 TxPktFifo595[3]; /* 0x00006530 */ + u32 TxPktFifo595_rsv3; + u32 TxPktFifo596[3]; /* 0x00006540 */ + u32 TxPktFifo596_rsv3; + u32 TxPktFifo597[3]; /* 0x00006550 */ + u32 TxPktFifo597_rsv3; + u32 TxPktFifo598[3]; /* 0x00006560 */ + u32 TxPktFifo598_rsv3; + u32 TxPktFifo599[3]; /* 0x00006570 */ + u32 TxPktFifo599_rsv3; + u32 TxPktFifo600[3]; /* 0x00006580 */ + u32 TxPktFifo600_rsv3; + u32 TxPktFifo601[3]; /* 0x00006590 */ + u32 TxPktFifo601_rsv3; + u32 TxPktFifo602[3]; /* 0x000065a0 */ + u32 TxPktFifo602_rsv3; + u32 TxPktFifo603[3]; /* 0x000065b0 */ + u32 TxPktFifo603_rsv3; + u32 TxPktFifo604[3]; /* 0x000065c0 */ + u32 TxPktFifo604_rsv3; + u32 TxPktFifo605[3]; /* 0x000065d0 */ + u32 TxPktFifo605_rsv3; + u32 TxPktFifo606[3]; /* 0x000065e0 */ + u32 TxPktFifo606_rsv3; + u32 TxPktFifo607[3]; /* 0x000065f0 */ + u32 TxPktFifo607_rsv3; + u32 TxPktFifo608[3]; /* 0x00006600 */ + u32 TxPktFifo608_rsv3; + u32 TxPktFifo609[3]; /* 0x00006610 */ + u32 TxPktFifo609_rsv3; + u32 TxPktFifo610[3]; /* 0x00006620 */ + u32 TxPktFifo610_rsv3; + u32 TxPktFifo611[3]; /* 0x00006630 */ + u32 TxPktFifo611_rsv3; + u32 TxPktFifo612[3]; /* 0x00006640 */ + u32 TxPktFifo612_rsv3; + u32 TxPktFifo613[3]; /* 0x00006650 */ + u32 TxPktFifo613_rsv3; + u32 TxPktFifo614[3]; /* 0x00006660 */ + u32 TxPktFifo614_rsv3; + u32 TxPktFifo615[3]; /* 0x00006670 */ + u32 TxPktFifo615_rsv3; + u32 TxPktFifo616[3]; /* 0x00006680 */ + u32 TxPktFifo616_rsv3; + u32 TxPktFifo617[3]; /* 0x00006690 */ + u32 TxPktFifo617_rsv3; + u32 TxPktFifo618[3]; /* 0x000066a0 */ + u32 TxPktFifo618_rsv3; + u32 TxPktFifo619[3]; /* 0x000066b0 */ + u32 TxPktFifo619_rsv3; + u32 TxPktFifo620[3]; /* 0x000066c0 */ + u32 TxPktFifo620_rsv3; + u32 TxPktFifo621[3]; /* 0x000066d0 */ + u32 TxPktFifo621_rsv3; + u32 TxPktFifo622[3]; /* 0x000066e0 */ + u32 TxPktFifo622_rsv3; + u32 TxPktFifo623[3]; /* 0x000066f0 */ + u32 TxPktFifo623_rsv3; + u32 TxPktFifo624[3]; /* 0x00006700 */ + u32 TxPktFifo624_rsv3; + u32 TxPktFifo625[3]; /* 0x00006710 */ + u32 TxPktFifo625_rsv3; + u32 TxPktFifo626[3]; /* 0x00006720 */ + u32 TxPktFifo626_rsv3; + u32 TxPktFifo627[3]; /* 0x00006730 */ + u32 TxPktFifo627_rsv3; + u32 TxPktFifo628[3]; /* 0x00006740 */ + u32 TxPktFifo628_rsv3; + u32 TxPktFifo629[3]; /* 0x00006750 */ + u32 TxPktFifo629_rsv3; + u32 TxPktFifo630[3]; /* 0x00006760 */ + u32 TxPktFifo630_rsv3; + u32 TxPktFifo631[3]; /* 0x00006770 */ + u32 TxPktFifo631_rsv3; + u32 TxPktFifo632[3]; /* 0x00006780 */ + u32 TxPktFifo632_rsv3; + u32 TxPktFifo633[3]; /* 0x00006790 */ + u32 TxPktFifo633_rsv3; + u32 TxPktFifo634[3]; /* 0x000067a0 */ + u32 TxPktFifo634_rsv3; + u32 TxPktFifo635[3]; /* 0x000067b0 */ + u32 TxPktFifo635_rsv3; + u32 TxPktFifo636[3]; /* 0x000067c0 */ + u32 TxPktFifo636_rsv3; + u32 TxPktFifo637[3]; /* 0x000067d0 */ + u32 TxPktFifo637_rsv3; + u32 TxPktFifo638[3]; /* 0x000067e0 */ + u32 TxPktFifo638_rsv3; + u32 TxPktFifo639[3]; /* 0x000067f0 */ + u32 TxPktFifo639_rsv3; u32 rsv6656; u32 rsv6657; u32 rsv6658; @@ -3328,331 +3402,331 @@ struct cpu_mac_mems { u32 rsv8189; u32 rsv8190; u32 rsv8191; - u32 rx_pkt_msg_fifo_0[1]; /* 0x00008000 */ - u32 rx_pkt_msg_fifo_1[1]; /* 0x00008004 */ - u32 rx_pkt_msg_fifo_2[1]; /* 0x00008008 */ - u32 rx_pkt_msg_fifo_3[1]; /* 0x0000800c */ - u32 rx_pkt_msg_fifo_4[1]; /* 0x00008010 */ - u32 rx_pkt_msg_fifo_5[1]; /* 0x00008014 */ - u32 rx_pkt_msg_fifo_6[1]; /* 0x00008018 */ - u32 rx_pkt_msg_fifo_7[1]; /* 0x0000801c */ - u32 rx_pkt_msg_fifo_8[1]; /* 0x00008020 */ - u32 rx_pkt_msg_fifo_9[1]; /* 0x00008024 */ - u32 rx_pkt_msg_fifo_10[1]; /* 0x00008028 */ - u32 rx_pkt_msg_fifo_11[1]; /* 0x0000802c */ - u32 rx_pkt_msg_fifo_12[1]; /* 0x00008030 */ - u32 rx_pkt_msg_fifo_13[1]; /* 0x00008034 */ - u32 rx_pkt_msg_fifo_14[1]; /* 0x00008038 */ - u32 rx_pkt_msg_fifo_15[1]; /* 0x0000803c */ - u32 rx_pkt_msg_fifo_16[1]; /* 0x00008040 */ - u32 rx_pkt_msg_fifo_17[1]; /* 0x00008044 */ - u32 rx_pkt_msg_fifo_18[1]; /* 0x00008048 */ - u32 rx_pkt_msg_fifo_19[1]; /* 0x0000804c */ - u32 rx_pkt_msg_fifo_20[1]; /* 0x00008050 */ - u32 rx_pkt_msg_fifo_21[1]; /* 0x00008054 */ - u32 rx_pkt_msg_fifo_22[1]; /* 0x00008058 */ - u32 rx_pkt_msg_fifo_23[1]; /* 0x0000805c */ - u32 rx_pkt_msg_fifo_24[1]; /* 0x00008060 */ - u32 rx_pkt_msg_fifo_25[1]; /* 0x00008064 */ - u32 rx_pkt_msg_fifo_26[1]; /* 0x00008068 */ - u32 rx_pkt_msg_fifo_27[1]; /* 0x0000806c */ - u32 rx_pkt_msg_fifo_28[1]; /* 0x00008070 */ - u32 rx_pkt_msg_fifo_29[1]; /* 0x00008074 */ - u32 rx_pkt_msg_fifo_30[1]; /* 0x00008078 */ - u32 rx_pkt_msg_fifo_31[1]; /* 0x0000807c */ - u32 rx_pkt_msg_fifo_32[1]; /* 0x00008080 */ - u32 rx_pkt_msg_fifo_33[1]; /* 0x00008084 */ - u32 rx_pkt_msg_fifo_34[1]; /* 0x00008088 */ - u32 rx_pkt_msg_fifo_35[1]; /* 0x0000808c */ - u32 rx_pkt_msg_fifo_36[1]; /* 0x00008090 */ - u32 rx_pkt_msg_fifo_37[1]; /* 0x00008094 */ - u32 rx_pkt_msg_fifo_38[1]; /* 0x00008098 */ - u32 rx_pkt_msg_fifo_39[1]; /* 0x0000809c */ - u32 rx_pkt_msg_fifo_40[1]; /* 0x000080a0 */ - u32 rx_pkt_msg_fifo_41[1]; /* 0x000080a4 */ - u32 rx_pkt_msg_fifo_42[1]; /* 0x000080a8 */ - u32 rx_pkt_msg_fifo_43[1]; /* 0x000080ac */ - u32 rx_pkt_msg_fifo_44[1]; /* 0x000080b0 */ - u32 rx_pkt_msg_fifo_45[1]; /* 0x000080b4 */ - u32 rx_pkt_msg_fifo_46[1]; /* 0x000080b8 */ - u32 rx_pkt_msg_fifo_47[1]; /* 0x000080bc */ - u32 rx_pkt_msg_fifo_48[1]; /* 0x000080c0 */ - u32 rx_pkt_msg_fifo_49[1]; /* 0x000080c4 */ - u32 rx_pkt_msg_fifo_50[1]; /* 0x000080c8 */ - u32 rx_pkt_msg_fifo_51[1]; /* 0x000080cc */ - u32 rx_pkt_msg_fifo_52[1]; /* 0x000080d0 */ - u32 rx_pkt_msg_fifo_53[1]; /* 0x000080d4 */ - u32 rx_pkt_msg_fifo_54[1]; /* 0x000080d8 */ - u32 rx_pkt_msg_fifo_55[1]; /* 0x000080dc */ - u32 rx_pkt_msg_fifo_56[1]; /* 0x000080e0 */ - u32 rx_pkt_msg_fifo_57[1]; /* 0x000080e4 */ - u32 rx_pkt_msg_fifo_58[1]; /* 0x000080e8 */ - u32 rx_pkt_msg_fifo_59[1]; /* 0x000080ec */ - u32 rx_pkt_msg_fifo_60[1]; /* 0x000080f0 */ - u32 rx_pkt_msg_fifo_61[1]; /* 0x000080f4 */ - u32 rx_pkt_msg_fifo_62[1]; /* 0x000080f8 */ - u32 rx_pkt_msg_fifo_63[1]; /* 0x000080fc */ - u32 rx_pkt_msg_fifo_64[1]; /* 0x00008100 */ - u32 rx_pkt_msg_fifo_65[1]; /* 0x00008104 */ - u32 rx_pkt_msg_fifo_66[1]; /* 0x00008108 */ - u32 rx_pkt_msg_fifo_67[1]; /* 0x0000810c */ - u32 rx_pkt_msg_fifo_68[1]; /* 0x00008110 */ - u32 rx_pkt_msg_fifo_69[1]; /* 0x00008114 */ - u32 rx_pkt_msg_fifo_70[1]; /* 0x00008118 */ - u32 rx_pkt_msg_fifo_71[1]; /* 0x0000811c */ - u32 rx_pkt_msg_fifo_72[1]; /* 0x00008120 */ - u32 rx_pkt_msg_fifo_73[1]; /* 0x00008124 */ - u32 rx_pkt_msg_fifo_74[1]; /* 0x00008128 */ - u32 rx_pkt_msg_fifo_75[1]; /* 0x0000812c */ - u32 rx_pkt_msg_fifo_76[1]; /* 0x00008130 */ - u32 rx_pkt_msg_fifo_77[1]; /* 0x00008134 */ - u32 rx_pkt_msg_fifo_78[1]; /* 0x00008138 */ - u32 rx_pkt_msg_fifo_79[1]; /* 0x0000813c */ - u32 rx_pkt_msg_fifo_80[1]; /* 0x00008140 */ - u32 rx_pkt_msg_fifo_81[1]; /* 0x00008144 */ - u32 rx_pkt_msg_fifo_82[1]; /* 0x00008148 */ - u32 rx_pkt_msg_fifo_83[1]; /* 0x0000814c */ - u32 rx_pkt_msg_fifo_84[1]; /* 0x00008150 */ - u32 rx_pkt_msg_fifo_85[1]; /* 0x00008154 */ - u32 rx_pkt_msg_fifo_86[1]; /* 0x00008158 */ - u32 rx_pkt_msg_fifo_87[1]; /* 0x0000815c */ - u32 rx_pkt_msg_fifo_88[1]; /* 0x00008160 */ - u32 rx_pkt_msg_fifo_89[1]; /* 0x00008164 */ - u32 rx_pkt_msg_fifo_90[1]; /* 0x00008168 */ - u32 rx_pkt_msg_fifo_91[1]; /* 0x0000816c */ - u32 rx_pkt_msg_fifo_92[1]; /* 0x00008170 */ - u32 rx_pkt_msg_fifo_93[1]; /* 0x00008174 */ - u32 rx_pkt_msg_fifo_94[1]; /* 0x00008178 */ - u32 rx_pkt_msg_fifo_95[1]; /* 0x0000817c */ - u32 rx_pkt_msg_fifo_96[1]; /* 0x00008180 */ - u32 rx_pkt_msg_fifo_97[1]; /* 0x00008184 */ - u32 rx_pkt_msg_fifo_98[1]; /* 0x00008188 */ - u32 rx_pkt_msg_fifo_99[1]; /* 0x0000818c */ - u32 rx_pkt_msg_fifo_100[1]; /* 0x00008190 */ - u32 rx_pkt_msg_fifo_101[1]; /* 0x00008194 */ - u32 rx_pkt_msg_fifo_102[1]; /* 0x00008198 */ - u32 rx_pkt_msg_fifo_103[1]; /* 0x0000819c */ - u32 rx_pkt_msg_fifo_104[1]; /* 0x000081a0 */ - u32 rx_pkt_msg_fifo_105[1]; /* 0x000081a4 */ - u32 rx_pkt_msg_fifo_106[1]; /* 0x000081a8 */ - u32 rx_pkt_msg_fifo_107[1]; /* 0x000081ac */ - u32 rx_pkt_msg_fifo_108[1]; /* 0x000081b0 */ - u32 rx_pkt_msg_fifo_109[1]; /* 0x000081b4 */ - u32 rx_pkt_msg_fifo_110[1]; /* 0x000081b8 */ - u32 rx_pkt_msg_fifo_111[1]; /* 0x000081bc */ - u32 rx_pkt_msg_fifo_112[1]; /* 0x000081c0 */ - u32 rx_pkt_msg_fifo_113[1]; /* 0x000081c4 */ - u32 rx_pkt_msg_fifo_114[1]; /* 0x000081c8 */ - u32 rx_pkt_msg_fifo_115[1]; /* 0x000081cc */ - u32 rx_pkt_msg_fifo_116[1]; /* 0x000081d0 */ - u32 rx_pkt_msg_fifo_117[1]; /* 0x000081d4 */ - u32 rx_pkt_msg_fifo_118[1]; /* 0x000081d8 */ - u32 rx_pkt_msg_fifo_119[1]; /* 0x000081dc */ - u32 rx_pkt_msg_fifo_120[1]; /* 0x000081e0 */ - u32 rx_pkt_msg_fifo_121[1]; /* 0x000081e4 */ - u32 rx_pkt_msg_fifo_122[1]; /* 0x000081e8 */ - u32 rx_pkt_msg_fifo_123[1]; /* 0x000081ec */ - u32 rx_pkt_msg_fifo_124[1]; /* 0x000081f0 */ - u32 rx_pkt_msg_fifo_125[1]; /* 0x000081f4 */ - u32 rx_pkt_msg_fifo_126[1]; /* 0x000081f8 */ - u32 rx_pkt_msg_fifo_127[1]; /* 0x000081fc */ - u32 rx_pkt_msg_fifo_128[1]; /* 0x00008200 */ - u32 rx_pkt_msg_fifo_129[1]; /* 0x00008204 */ - u32 rx_pkt_msg_fifo_130[1]; /* 0x00008208 */ - u32 rx_pkt_msg_fifo_131[1]; /* 0x0000820c */ - u32 rx_pkt_msg_fifo_132[1]; /* 0x00008210 */ - u32 rx_pkt_msg_fifo_133[1]; /* 0x00008214 */ - u32 rx_pkt_msg_fifo_134[1]; /* 0x00008218 */ - u32 rx_pkt_msg_fifo_135[1]; /* 0x0000821c */ - u32 rx_pkt_msg_fifo_136[1]; /* 0x00008220 */ - u32 rx_pkt_msg_fifo_137[1]; /* 0x00008224 */ - u32 rx_pkt_msg_fifo_138[1]; /* 0x00008228 */ - u32 rx_pkt_msg_fifo_139[1]; /* 0x0000822c */ - u32 rx_pkt_msg_fifo_140[1]; /* 0x00008230 */ - u32 rx_pkt_msg_fifo_141[1]; /* 0x00008234 */ - u32 rx_pkt_msg_fifo_142[1]; /* 0x00008238 */ - u32 rx_pkt_msg_fifo_143[1]; /* 0x0000823c */ - u32 rx_pkt_msg_fifo_144[1]; /* 0x00008240 */ - u32 rx_pkt_msg_fifo_145[1]; /* 0x00008244 */ - u32 rx_pkt_msg_fifo_146[1]; /* 0x00008248 */ - u32 rx_pkt_msg_fifo_147[1]; /* 0x0000824c */ - u32 rx_pkt_msg_fifo_148[1]; /* 0x00008250 */ - u32 rx_pkt_msg_fifo_149[1]; /* 0x00008254 */ - u32 rx_pkt_msg_fifo_150[1]; /* 0x00008258 */ - u32 rx_pkt_msg_fifo_151[1]; /* 0x0000825c */ - u32 rx_pkt_msg_fifo_152[1]; /* 0x00008260 */ - u32 rx_pkt_msg_fifo_153[1]; /* 0x00008264 */ - u32 rx_pkt_msg_fifo_154[1]; /* 0x00008268 */ - u32 rx_pkt_msg_fifo_155[1]; /* 0x0000826c */ - u32 rx_pkt_msg_fifo_156[1]; /* 0x00008270 */ - u32 rx_pkt_msg_fifo_157[1]; /* 0x00008274 */ - u32 rx_pkt_msg_fifo_158[1]; /* 0x00008278 */ - u32 rx_pkt_msg_fifo_159[1]; /* 0x0000827c */ - u32 rx_pkt_msg_fifo_160[1]; /* 0x00008280 */ - u32 rx_pkt_msg_fifo_161[1]; /* 0x00008284 */ - u32 rx_pkt_msg_fifo_162[1]; /* 0x00008288 */ - u32 rx_pkt_msg_fifo_163[1]; /* 0x0000828c */ - u32 rx_pkt_msg_fifo_164[1]; /* 0x00008290 */ - u32 rx_pkt_msg_fifo_165[1]; /* 0x00008294 */ - u32 rx_pkt_msg_fifo_166[1]; /* 0x00008298 */ - u32 rx_pkt_msg_fifo_167[1]; /* 0x0000829c */ - u32 rx_pkt_msg_fifo_168[1]; /* 0x000082a0 */ - u32 rx_pkt_msg_fifo_169[1]; /* 0x000082a4 */ - u32 rx_pkt_msg_fifo_170[1]; /* 0x000082a8 */ - u32 rx_pkt_msg_fifo_171[1]; /* 0x000082ac */ - u32 rx_pkt_msg_fifo_172[1]; /* 0x000082b0 */ - u32 rx_pkt_msg_fifo_173[1]; /* 0x000082b4 */ - u32 rx_pkt_msg_fifo_174[1]; /* 0x000082b8 */ - u32 rx_pkt_msg_fifo_175[1]; /* 0x000082bc */ - u32 rx_pkt_msg_fifo_176[1]; /* 0x000082c0 */ - u32 rx_pkt_msg_fifo_177[1]; /* 0x000082c4 */ - u32 rx_pkt_msg_fifo_178[1]; /* 0x000082c8 */ - u32 rx_pkt_msg_fifo_179[1]; /* 0x000082cc */ - u32 rx_pkt_msg_fifo_180[1]; /* 0x000082d0 */ - u32 rx_pkt_msg_fifo_181[1]; /* 0x000082d4 */ - u32 rx_pkt_msg_fifo_182[1]; /* 0x000082d8 */ - u32 rx_pkt_msg_fifo_183[1]; /* 0x000082dc */ - u32 rx_pkt_msg_fifo_184[1]; /* 0x000082e0 */ - u32 rx_pkt_msg_fifo_185[1]; /* 0x000082e4 */ - u32 rx_pkt_msg_fifo_186[1]; /* 0x000082e8 */ - u32 rx_pkt_msg_fifo_187[1]; /* 0x000082ec */ - u32 rx_pkt_msg_fifo_188[1]; /* 0x000082f0 */ - u32 rx_pkt_msg_fifo_189[1]; /* 0x000082f4 */ - u32 rx_pkt_msg_fifo_190[1]; /* 0x000082f8 */ - u32 rx_pkt_msg_fifo_191[1]; /* 0x000082fc */ - u32 rx_pkt_msg_fifo_192[1]; /* 0x00008300 */ - u32 rx_pkt_msg_fifo_193[1]; /* 0x00008304 */ - u32 rx_pkt_msg_fifo_194[1]; /* 0x00008308 */ - u32 rx_pkt_msg_fifo_195[1]; /* 0x0000830c */ - u32 rx_pkt_msg_fifo_196[1]; /* 0x00008310 */ - u32 rx_pkt_msg_fifo_197[1]; /* 0x00008314 */ - u32 rx_pkt_msg_fifo_198[1]; /* 0x00008318 */ - u32 rx_pkt_msg_fifo_199[1]; /* 0x0000831c */ - u32 rx_pkt_msg_fifo_200[1]; /* 0x00008320 */ - u32 rx_pkt_msg_fifo_201[1]; /* 0x00008324 */ - u32 rx_pkt_msg_fifo_202[1]; /* 0x00008328 */ - u32 rx_pkt_msg_fifo_203[1]; /* 0x0000832c */ - u32 rx_pkt_msg_fifo_204[1]; /* 0x00008330 */ - u32 rx_pkt_msg_fifo_205[1]; /* 0x00008334 */ - u32 rx_pkt_msg_fifo_206[1]; /* 0x00008338 */ - u32 rx_pkt_msg_fifo_207[1]; /* 0x0000833c */ - u32 rx_pkt_msg_fifo_208[1]; /* 0x00008340 */ - u32 rx_pkt_msg_fifo_209[1]; /* 0x00008344 */ - u32 rx_pkt_msg_fifo_210[1]; /* 0x00008348 */ - u32 rx_pkt_msg_fifo_211[1]; /* 0x0000834c */ - u32 rx_pkt_msg_fifo_212[1]; /* 0x00008350 */ - u32 rx_pkt_msg_fifo_213[1]; /* 0x00008354 */ - u32 rx_pkt_msg_fifo_214[1]; /* 0x00008358 */ - u32 rx_pkt_msg_fifo_215[1]; /* 0x0000835c */ - u32 rx_pkt_msg_fifo_216[1]; /* 0x00008360 */ - u32 rx_pkt_msg_fifo_217[1]; /* 0x00008364 */ - u32 rx_pkt_msg_fifo_218[1]; /* 0x00008368 */ - u32 rx_pkt_msg_fifo_219[1]; /* 0x0000836c */ - u32 rx_pkt_msg_fifo_220[1]; /* 0x00008370 */ - u32 rx_pkt_msg_fifo_221[1]; /* 0x00008374 */ - u32 rx_pkt_msg_fifo_222[1]; /* 0x00008378 */ - u32 rx_pkt_msg_fifo_223[1]; /* 0x0000837c */ - u32 rx_pkt_msg_fifo_224[1]; /* 0x00008380 */ - u32 rx_pkt_msg_fifo_225[1]; /* 0x00008384 */ - u32 rx_pkt_msg_fifo_226[1]; /* 0x00008388 */ - u32 rx_pkt_msg_fifo_227[1]; /* 0x0000838c */ - u32 rx_pkt_msg_fifo_228[1]; /* 0x00008390 */ - u32 rx_pkt_msg_fifo_229[1]; /* 0x00008394 */ - u32 rx_pkt_msg_fifo_230[1]; /* 0x00008398 */ - u32 rx_pkt_msg_fifo_231[1]; /* 0x0000839c */ - u32 rx_pkt_msg_fifo_232[1]; /* 0x000083a0 */ - u32 rx_pkt_msg_fifo_233[1]; /* 0x000083a4 */ - u32 rx_pkt_msg_fifo_234[1]; /* 0x000083a8 */ - u32 rx_pkt_msg_fifo_235[1]; /* 0x000083ac */ - u32 rx_pkt_msg_fifo_236[1]; /* 0x000083b0 */ - u32 rx_pkt_msg_fifo_237[1]; /* 0x000083b4 */ - u32 rx_pkt_msg_fifo_238[1]; /* 0x000083b8 */ - u32 rx_pkt_msg_fifo_239[1]; /* 0x000083bc */ - u32 rx_pkt_msg_fifo_240[1]; /* 0x000083c0 */ - u32 rx_pkt_msg_fifo_241[1]; /* 0x000083c4 */ - u32 rx_pkt_msg_fifo_242[1]; /* 0x000083c8 */ - u32 rx_pkt_msg_fifo_243[1]; /* 0x000083cc */ - u32 rx_pkt_msg_fifo_244[1]; /* 0x000083d0 */ - u32 rx_pkt_msg_fifo_245[1]; /* 0x000083d4 */ - u32 rx_pkt_msg_fifo_246[1]; /* 0x000083d8 */ - u32 rx_pkt_msg_fifo_247[1]; /* 0x000083dc */ - u32 rx_pkt_msg_fifo_248[1]; /* 0x000083e0 */ - u32 rx_pkt_msg_fifo_249[1]; /* 0x000083e4 */ - u32 rx_pkt_msg_fifo_250[1]; /* 0x000083e8 */ - u32 rx_pkt_msg_fifo_251[1]; /* 0x000083ec */ - u32 rx_pkt_msg_fifo_252[1]; /* 0x000083f0 */ - u32 rx_pkt_msg_fifo_253[1]; /* 0x000083f4 */ - u32 rx_pkt_msg_fifo_254[1]; /* 0x000083f8 */ - u32 rx_pkt_msg_fifo_255[1]; /* 0x000083fc */ - u32 rx_pkt_msg_fifo_256[1]; /* 0x00008400 */ - u32 rx_pkt_msg_fifo_257[1]; /* 0x00008404 */ - u32 rx_pkt_msg_fifo_258[1]; /* 0x00008408 */ - u32 rx_pkt_msg_fifo_259[1]; /* 0x0000840c */ - u32 rx_pkt_msg_fifo_260[1]; /* 0x00008410 */ - u32 rx_pkt_msg_fifo_261[1]; /* 0x00008414 */ - u32 rx_pkt_msg_fifo_262[1]; /* 0x00008418 */ - u32 rx_pkt_msg_fifo_263[1]; /* 0x0000841c */ - u32 rx_pkt_msg_fifo_264[1]; /* 0x00008420 */ - u32 rx_pkt_msg_fifo_265[1]; /* 0x00008424 */ - u32 rx_pkt_msg_fifo_266[1]; /* 0x00008428 */ - u32 rx_pkt_msg_fifo_267[1]; /* 0x0000842c */ - u32 rx_pkt_msg_fifo_268[1]; /* 0x00008430 */ - u32 rx_pkt_msg_fifo_269[1]; /* 0x00008434 */ - u32 rx_pkt_msg_fifo_270[1]; /* 0x00008438 */ - u32 rx_pkt_msg_fifo_271[1]; /* 0x0000843c */ - u32 rx_pkt_msg_fifo_272[1]; /* 0x00008440 */ - u32 rx_pkt_msg_fifo_273[1]; /* 0x00008444 */ - u32 rx_pkt_msg_fifo_274[1]; /* 0x00008448 */ - u32 rx_pkt_msg_fifo_275[1]; /* 0x0000844c */ - u32 rx_pkt_msg_fifo_276[1]; /* 0x00008450 */ - u32 rx_pkt_msg_fifo_277[1]; /* 0x00008454 */ - u32 rx_pkt_msg_fifo_278[1]; /* 0x00008458 */ - u32 rx_pkt_msg_fifo_279[1]; /* 0x0000845c */ - u32 rx_pkt_msg_fifo_280[1]; /* 0x00008460 */ - u32 rx_pkt_msg_fifo_281[1]; /* 0x00008464 */ - u32 rx_pkt_msg_fifo_282[1]; /* 0x00008468 */ - u32 rx_pkt_msg_fifo_283[1]; /* 0x0000846c */ - u32 rx_pkt_msg_fifo_284[1]; /* 0x00008470 */ - u32 rx_pkt_msg_fifo_285[1]; /* 0x00008474 */ - u32 rx_pkt_msg_fifo_286[1]; /* 0x00008478 */ - u32 rx_pkt_msg_fifo_287[1]; /* 0x0000847c */ - u32 rx_pkt_msg_fifo_288[1]; /* 0x00008480 */ - u32 rx_pkt_msg_fifo_289[1]; /* 0x00008484 */ - u32 rx_pkt_msg_fifo_290[1]; /* 0x00008488 */ - u32 rx_pkt_msg_fifo_291[1]; /* 0x0000848c */ - u32 rx_pkt_msg_fifo_292[1]; /* 0x00008490 */ - u32 rx_pkt_msg_fifo_293[1]; /* 0x00008494 */ - u32 rx_pkt_msg_fifo_294[1]; /* 0x00008498 */ - u32 rx_pkt_msg_fifo_295[1]; /* 0x0000849c */ - u32 rx_pkt_msg_fifo_296[1]; /* 0x000084a0 */ - u32 rx_pkt_msg_fifo_297[1]; /* 0x000084a4 */ - u32 rx_pkt_msg_fifo_298[1]; /* 0x000084a8 */ - u32 rx_pkt_msg_fifo_299[1]; /* 0x000084ac */ - u32 rx_pkt_msg_fifo_300[1]; /* 0x000084b0 */ - u32 rx_pkt_msg_fifo_301[1]; /* 0x000084b4 */ - u32 rx_pkt_msg_fifo_302[1]; /* 0x000084b8 */ - u32 rx_pkt_msg_fifo_303[1]; /* 0x000084bc */ - u32 rx_pkt_msg_fifo_304[1]; /* 0x000084c0 */ - u32 rx_pkt_msg_fifo_305[1]; /* 0x000084c4 */ - u32 rx_pkt_msg_fifo_306[1]; /* 0x000084c8 */ - u32 rx_pkt_msg_fifo_307[1]; /* 0x000084cc */ - u32 rx_pkt_msg_fifo_308[1]; /* 0x000084d0 */ - u32 rx_pkt_msg_fifo_309[1]; /* 0x000084d4 */ - u32 rx_pkt_msg_fifo_310[1]; /* 0x000084d8 */ - u32 rx_pkt_msg_fifo_311[1]; /* 0x000084dc */ - u32 rx_pkt_msg_fifo_312[1]; /* 0x000084e0 */ - u32 rx_pkt_msg_fifo_313[1]; /* 0x000084e4 */ - u32 rx_pkt_msg_fifo_314[1]; /* 0x000084e8 */ - u32 rx_pkt_msg_fifo_315[1]; /* 0x000084ec */ - u32 rx_pkt_msg_fifo_316[1]; /* 0x000084f0 */ - u32 rx_pkt_msg_fifo_317[1]; /* 0x000084f4 */ - u32 rx_pkt_msg_fifo_318[1]; /* 0x000084f8 */ - u32 rx_pkt_msg_fifo_319[1]; /* 0x000084fc */ - u32 rx_pkt_msg_fifo_320[1]; /* 0x00008500 */ - u32 rx_pkt_msg_fifo_321[1]; /* 0x00008504 */ - u32 rx_pkt_msg_fifo_322[1]; /* 0x00008508 */ - u32 rx_pkt_msg_fifo_323[1]; /* 0x0000850c */ - u32 rx_pkt_msg_fifo_324[1]; /* 0x00008510 */ + u32 RxPktMsgFifo0[1]; /* 0x00008000 */ + u32 RxPktMsgFifo1[1]; /* 0x00008004 */ + u32 RxPktMsgFifo2[1]; /* 0x00008008 */ + u32 RxPktMsgFifo3[1]; /* 0x0000800c */ + u32 RxPktMsgFifo4[1]; /* 0x00008010 */ + u32 RxPktMsgFifo5[1]; /* 0x00008014 */ + u32 RxPktMsgFifo6[1]; /* 0x00008018 */ + u32 RxPktMsgFifo7[1]; /* 0x0000801c */ + u32 RxPktMsgFifo8[1]; /* 0x00008020 */ + u32 RxPktMsgFifo9[1]; /* 0x00008024 */ + u32 RxPktMsgFifo10[1]; /* 0x00008028 */ + u32 RxPktMsgFifo11[1]; /* 0x0000802c */ + u32 RxPktMsgFifo12[1]; /* 0x00008030 */ + u32 RxPktMsgFifo13[1]; /* 0x00008034 */ + u32 RxPktMsgFifo14[1]; /* 0x00008038 */ + u32 RxPktMsgFifo15[1]; /* 0x0000803c */ + u32 RxPktMsgFifo16[1]; /* 0x00008040 */ + u32 RxPktMsgFifo17[1]; /* 0x00008044 */ + u32 RxPktMsgFifo18[1]; /* 0x00008048 */ + u32 RxPktMsgFifo19[1]; /* 0x0000804c */ + u32 RxPktMsgFifo20[1]; /* 0x00008050 */ + u32 RxPktMsgFifo21[1]; /* 0x00008054 */ + u32 RxPktMsgFifo22[1]; /* 0x00008058 */ + u32 RxPktMsgFifo23[1]; /* 0x0000805c */ + u32 RxPktMsgFifo24[1]; /* 0x00008060 */ + u32 RxPktMsgFifo25[1]; /* 0x00008064 */ + u32 RxPktMsgFifo26[1]; /* 0x00008068 */ + u32 RxPktMsgFifo27[1]; /* 0x0000806c */ + u32 RxPktMsgFifo28[1]; /* 0x00008070 */ + u32 RxPktMsgFifo29[1]; /* 0x00008074 */ + u32 RxPktMsgFifo30[1]; /* 0x00008078 */ + u32 RxPktMsgFifo31[1]; /* 0x0000807c */ + u32 RxPktMsgFifo32[1]; /* 0x00008080 */ + u32 RxPktMsgFifo33[1]; /* 0x00008084 */ + u32 RxPktMsgFifo34[1]; /* 0x00008088 */ + u32 RxPktMsgFifo35[1]; /* 0x0000808c */ + u32 RxPktMsgFifo36[1]; /* 0x00008090 */ + u32 RxPktMsgFifo37[1]; /* 0x00008094 */ + u32 RxPktMsgFifo38[1]; /* 0x00008098 */ + u32 RxPktMsgFifo39[1]; /* 0x0000809c */ + u32 RxPktMsgFifo40[1]; /* 0x000080a0 */ + u32 RxPktMsgFifo41[1]; /* 0x000080a4 */ + u32 RxPktMsgFifo42[1]; /* 0x000080a8 */ + u32 RxPktMsgFifo43[1]; /* 0x000080ac */ + u32 RxPktMsgFifo44[1]; /* 0x000080b0 */ + u32 RxPktMsgFifo45[1]; /* 0x000080b4 */ + u32 RxPktMsgFifo46[1]; /* 0x000080b8 */ + u32 RxPktMsgFifo47[1]; /* 0x000080bc */ + u32 RxPktMsgFifo48[1]; /* 0x000080c0 */ + u32 RxPktMsgFifo49[1]; /* 0x000080c4 */ + u32 RxPktMsgFifo50[1]; /* 0x000080c8 */ + u32 RxPktMsgFifo51[1]; /* 0x000080cc */ + u32 RxPktMsgFifo52[1]; /* 0x000080d0 */ + u32 RxPktMsgFifo53[1]; /* 0x000080d4 */ + u32 RxPktMsgFifo54[1]; /* 0x000080d8 */ + u32 RxPktMsgFifo55[1]; /* 0x000080dc */ + u32 RxPktMsgFifo56[1]; /* 0x000080e0 */ + u32 RxPktMsgFifo57[1]; /* 0x000080e4 */ + u32 RxPktMsgFifo58[1]; /* 0x000080e8 */ + u32 RxPktMsgFifo59[1]; /* 0x000080ec */ + u32 RxPktMsgFifo60[1]; /* 0x000080f0 */ + u32 RxPktMsgFifo61[1]; /* 0x000080f4 */ + u32 RxPktMsgFifo62[1]; /* 0x000080f8 */ + u32 RxPktMsgFifo63[1]; /* 0x000080fc */ + u32 RxPktMsgFifo64[1]; /* 0x00008100 */ + u32 RxPktMsgFifo65[1]; /* 0x00008104 */ + u32 RxPktMsgFifo66[1]; /* 0x00008108 */ + u32 RxPktMsgFifo67[1]; /* 0x0000810c */ + u32 RxPktMsgFifo68[1]; /* 0x00008110 */ + u32 RxPktMsgFifo69[1]; /* 0x00008114 */ + u32 RxPktMsgFifo70[1]; /* 0x00008118 */ + u32 RxPktMsgFifo71[1]; /* 0x0000811c */ + u32 RxPktMsgFifo72[1]; /* 0x00008120 */ + u32 RxPktMsgFifo73[1]; /* 0x00008124 */ + u32 RxPktMsgFifo74[1]; /* 0x00008128 */ + u32 RxPktMsgFifo75[1]; /* 0x0000812c */ + u32 RxPktMsgFifo76[1]; /* 0x00008130 */ + u32 RxPktMsgFifo77[1]; /* 0x00008134 */ + u32 RxPktMsgFifo78[1]; /* 0x00008138 */ + u32 RxPktMsgFifo79[1]; /* 0x0000813c */ + u32 RxPktMsgFifo80[1]; /* 0x00008140 */ + u32 RxPktMsgFifo81[1]; /* 0x00008144 */ + u32 RxPktMsgFifo82[1]; /* 0x00008148 */ + u32 RxPktMsgFifo83[1]; /* 0x0000814c */ + u32 RxPktMsgFifo84[1]; /* 0x00008150 */ + u32 RxPktMsgFifo85[1]; /* 0x00008154 */ + u32 RxPktMsgFifo86[1]; /* 0x00008158 */ + u32 RxPktMsgFifo87[1]; /* 0x0000815c */ + u32 RxPktMsgFifo88[1]; /* 0x00008160 */ + u32 RxPktMsgFifo89[1]; /* 0x00008164 */ + u32 RxPktMsgFifo90[1]; /* 0x00008168 */ + u32 RxPktMsgFifo91[1]; /* 0x0000816c */ + u32 RxPktMsgFifo92[1]; /* 0x00008170 */ + u32 RxPktMsgFifo93[1]; /* 0x00008174 */ + u32 RxPktMsgFifo94[1]; /* 0x00008178 */ + u32 RxPktMsgFifo95[1]; /* 0x0000817c */ + u32 RxPktMsgFifo96[1]; /* 0x00008180 */ + u32 RxPktMsgFifo97[1]; /* 0x00008184 */ + u32 RxPktMsgFifo98[1]; /* 0x00008188 */ + u32 RxPktMsgFifo99[1]; /* 0x0000818c */ + u32 RxPktMsgFifo100[1]; /* 0x00008190 */ + u32 RxPktMsgFifo101[1]; /* 0x00008194 */ + u32 RxPktMsgFifo102[1]; /* 0x00008198 */ + u32 RxPktMsgFifo103[1]; /* 0x0000819c */ + u32 RxPktMsgFifo104[1]; /* 0x000081a0 */ + u32 RxPktMsgFifo105[1]; /* 0x000081a4 */ + u32 RxPktMsgFifo106[1]; /* 0x000081a8 */ + u32 RxPktMsgFifo107[1]; /* 0x000081ac */ + u32 RxPktMsgFifo108[1]; /* 0x000081b0 */ + u32 RxPktMsgFifo109[1]; /* 0x000081b4 */ + u32 RxPktMsgFifo110[1]; /* 0x000081b8 */ + u32 RxPktMsgFifo111[1]; /* 0x000081bc */ + u32 RxPktMsgFifo112[1]; /* 0x000081c0 */ + u32 RxPktMsgFifo113[1]; /* 0x000081c4 */ + u32 RxPktMsgFifo114[1]; /* 0x000081c8 */ + u32 RxPktMsgFifo115[1]; /* 0x000081cc */ + u32 RxPktMsgFifo116[1]; /* 0x000081d0 */ + u32 RxPktMsgFifo117[1]; /* 0x000081d4 */ + u32 RxPktMsgFifo118[1]; /* 0x000081d8 */ + u32 RxPktMsgFifo119[1]; /* 0x000081dc */ + u32 RxPktMsgFifo120[1]; /* 0x000081e0 */ + u32 RxPktMsgFifo121[1]; /* 0x000081e4 */ + u32 RxPktMsgFifo122[1]; /* 0x000081e8 */ + u32 RxPktMsgFifo123[1]; /* 0x000081ec */ + u32 RxPktMsgFifo124[1]; /* 0x000081f0 */ + u32 RxPktMsgFifo125[1]; /* 0x000081f4 */ + u32 RxPktMsgFifo126[1]; /* 0x000081f8 */ + u32 RxPktMsgFifo127[1]; /* 0x000081fc */ + u32 RxPktMsgFifo128[1]; /* 0x00008200 */ + u32 RxPktMsgFifo129[1]; /* 0x00008204 */ + u32 RxPktMsgFifo130[1]; /* 0x00008208 */ + u32 RxPktMsgFifo131[1]; /* 0x0000820c */ + u32 RxPktMsgFifo132[1]; /* 0x00008210 */ + u32 RxPktMsgFifo133[1]; /* 0x00008214 */ + u32 RxPktMsgFifo134[1]; /* 0x00008218 */ + u32 RxPktMsgFifo135[1]; /* 0x0000821c */ + u32 RxPktMsgFifo136[1]; /* 0x00008220 */ + u32 RxPktMsgFifo137[1]; /* 0x00008224 */ + u32 RxPktMsgFifo138[1]; /* 0x00008228 */ + u32 RxPktMsgFifo139[1]; /* 0x0000822c */ + u32 RxPktMsgFifo140[1]; /* 0x00008230 */ + u32 RxPktMsgFifo141[1]; /* 0x00008234 */ + u32 RxPktMsgFifo142[1]; /* 0x00008238 */ + u32 RxPktMsgFifo143[1]; /* 0x0000823c */ + u32 RxPktMsgFifo144[1]; /* 0x00008240 */ + u32 RxPktMsgFifo145[1]; /* 0x00008244 */ + u32 RxPktMsgFifo146[1]; /* 0x00008248 */ + u32 RxPktMsgFifo147[1]; /* 0x0000824c */ + u32 RxPktMsgFifo148[1]; /* 0x00008250 */ + u32 RxPktMsgFifo149[1]; /* 0x00008254 */ + u32 RxPktMsgFifo150[1]; /* 0x00008258 */ + u32 RxPktMsgFifo151[1]; /* 0x0000825c */ + u32 RxPktMsgFifo152[1]; /* 0x00008260 */ + u32 RxPktMsgFifo153[1]; /* 0x00008264 */ + u32 RxPktMsgFifo154[1]; /* 0x00008268 */ + u32 RxPktMsgFifo155[1]; /* 0x0000826c */ + u32 RxPktMsgFifo156[1]; /* 0x00008270 */ + u32 RxPktMsgFifo157[1]; /* 0x00008274 */ + u32 RxPktMsgFifo158[1]; /* 0x00008278 */ + u32 RxPktMsgFifo159[1]; /* 0x0000827c */ + u32 RxPktMsgFifo160[1]; /* 0x00008280 */ + u32 RxPktMsgFifo161[1]; /* 0x00008284 */ + u32 RxPktMsgFifo162[1]; /* 0x00008288 */ + u32 RxPktMsgFifo163[1]; /* 0x0000828c */ + u32 RxPktMsgFifo164[1]; /* 0x00008290 */ + u32 RxPktMsgFifo165[1]; /* 0x00008294 */ + u32 RxPktMsgFifo166[1]; /* 0x00008298 */ + u32 RxPktMsgFifo167[1]; /* 0x0000829c */ + u32 RxPktMsgFifo168[1]; /* 0x000082a0 */ + u32 RxPktMsgFifo169[1]; /* 0x000082a4 */ + u32 RxPktMsgFifo170[1]; /* 0x000082a8 */ + u32 RxPktMsgFifo171[1]; /* 0x000082ac */ + u32 RxPktMsgFifo172[1]; /* 0x000082b0 */ + u32 RxPktMsgFifo173[1]; /* 0x000082b4 */ + u32 RxPktMsgFifo174[1]; /* 0x000082b8 */ + u32 RxPktMsgFifo175[1]; /* 0x000082bc */ + u32 RxPktMsgFifo176[1]; /* 0x000082c0 */ + u32 RxPktMsgFifo177[1]; /* 0x000082c4 */ + u32 RxPktMsgFifo178[1]; /* 0x000082c8 */ + u32 RxPktMsgFifo179[1]; /* 0x000082cc */ + u32 RxPktMsgFifo180[1]; /* 0x000082d0 */ + u32 RxPktMsgFifo181[1]; /* 0x000082d4 */ + u32 RxPktMsgFifo182[1]; /* 0x000082d8 */ + u32 RxPktMsgFifo183[1]; /* 0x000082dc */ + u32 RxPktMsgFifo184[1]; /* 0x000082e0 */ + u32 RxPktMsgFifo185[1]; /* 0x000082e4 */ + u32 RxPktMsgFifo186[1]; /* 0x000082e8 */ + u32 RxPktMsgFifo187[1]; /* 0x000082ec */ + u32 RxPktMsgFifo188[1]; /* 0x000082f0 */ + u32 RxPktMsgFifo189[1]; /* 0x000082f4 */ + u32 RxPktMsgFifo190[1]; /* 0x000082f8 */ + u32 RxPktMsgFifo191[1]; /* 0x000082fc */ + u32 RxPktMsgFifo192[1]; /* 0x00008300 */ + u32 RxPktMsgFifo193[1]; /* 0x00008304 */ + u32 RxPktMsgFifo194[1]; /* 0x00008308 */ + u32 RxPktMsgFifo195[1]; /* 0x0000830c */ + u32 RxPktMsgFifo196[1]; /* 0x00008310 */ + u32 RxPktMsgFifo197[1]; /* 0x00008314 */ + u32 RxPktMsgFifo198[1]; /* 0x00008318 */ + u32 RxPktMsgFifo199[1]; /* 0x0000831c */ + u32 RxPktMsgFifo200[1]; /* 0x00008320 */ + u32 RxPktMsgFifo201[1]; /* 0x00008324 */ + u32 RxPktMsgFifo202[1]; /* 0x00008328 */ + u32 RxPktMsgFifo203[1]; /* 0x0000832c */ + u32 RxPktMsgFifo204[1]; /* 0x00008330 */ + u32 RxPktMsgFifo205[1]; /* 0x00008334 */ + u32 RxPktMsgFifo206[1]; /* 0x00008338 */ + u32 RxPktMsgFifo207[1]; /* 0x0000833c */ + u32 RxPktMsgFifo208[1]; /* 0x00008340 */ + u32 RxPktMsgFifo209[1]; /* 0x00008344 */ + u32 RxPktMsgFifo210[1]; /* 0x00008348 */ + u32 RxPktMsgFifo211[1]; /* 0x0000834c */ + u32 RxPktMsgFifo212[1]; /* 0x00008350 */ + u32 RxPktMsgFifo213[1]; /* 0x00008354 */ + u32 RxPktMsgFifo214[1]; /* 0x00008358 */ + u32 RxPktMsgFifo215[1]; /* 0x0000835c */ + u32 RxPktMsgFifo216[1]; /* 0x00008360 */ + u32 RxPktMsgFifo217[1]; /* 0x00008364 */ + u32 RxPktMsgFifo218[1]; /* 0x00008368 */ + u32 RxPktMsgFifo219[1]; /* 0x0000836c */ + u32 RxPktMsgFifo220[1]; /* 0x00008370 */ + u32 RxPktMsgFifo221[1]; /* 0x00008374 */ + u32 RxPktMsgFifo222[1]; /* 0x00008378 */ + u32 RxPktMsgFifo223[1]; /* 0x0000837c */ + u32 RxPktMsgFifo224[1]; /* 0x00008380 */ + u32 RxPktMsgFifo225[1]; /* 0x00008384 */ + u32 RxPktMsgFifo226[1]; /* 0x00008388 */ + u32 RxPktMsgFifo227[1]; /* 0x0000838c */ + u32 RxPktMsgFifo228[1]; /* 0x00008390 */ + u32 RxPktMsgFifo229[1]; /* 0x00008394 */ + u32 RxPktMsgFifo230[1]; /* 0x00008398 */ + u32 RxPktMsgFifo231[1]; /* 0x0000839c */ + u32 RxPktMsgFifo232[1]; /* 0x000083a0 */ + u32 RxPktMsgFifo233[1]; /* 0x000083a4 */ + u32 RxPktMsgFifo234[1]; /* 0x000083a8 */ + u32 RxPktMsgFifo235[1]; /* 0x000083ac */ + u32 RxPktMsgFifo236[1]; /* 0x000083b0 */ + u32 RxPktMsgFifo237[1]; /* 0x000083b4 */ + u32 RxPktMsgFifo238[1]; /* 0x000083b8 */ + u32 RxPktMsgFifo239[1]; /* 0x000083bc */ + u32 RxPktMsgFifo240[1]; /* 0x000083c0 */ + u32 RxPktMsgFifo241[1]; /* 0x000083c4 */ + u32 RxPktMsgFifo242[1]; /* 0x000083c8 */ + u32 RxPktMsgFifo243[1]; /* 0x000083cc */ + u32 RxPktMsgFifo244[1]; /* 0x000083d0 */ + u32 RxPktMsgFifo245[1]; /* 0x000083d4 */ + u32 RxPktMsgFifo246[1]; /* 0x000083d8 */ + u32 RxPktMsgFifo247[1]; /* 0x000083dc */ + u32 RxPktMsgFifo248[1]; /* 0x000083e0 */ + u32 RxPktMsgFifo249[1]; /* 0x000083e4 */ + u32 RxPktMsgFifo250[1]; /* 0x000083e8 */ + u32 RxPktMsgFifo251[1]; /* 0x000083ec */ + u32 RxPktMsgFifo252[1]; /* 0x000083f0 */ + u32 RxPktMsgFifo253[1]; /* 0x000083f4 */ + u32 RxPktMsgFifo254[1]; /* 0x000083f8 */ + u32 RxPktMsgFifo255[1]; /* 0x000083fc */ + u32 RxPktMsgFifo256[1]; /* 0x00008400 */ + u32 RxPktMsgFifo257[1]; /* 0x00008404 */ + u32 RxPktMsgFifo258[1]; /* 0x00008408 */ + u32 RxPktMsgFifo259[1]; /* 0x0000840c */ + u32 RxPktMsgFifo260[1]; /* 0x00008410 */ + u32 RxPktMsgFifo261[1]; /* 0x00008414 */ + u32 RxPktMsgFifo262[1]; /* 0x00008418 */ + u32 RxPktMsgFifo263[1]; /* 0x0000841c */ + u32 RxPktMsgFifo264[1]; /* 0x00008420 */ + u32 RxPktMsgFifo265[1]; /* 0x00008424 */ + u32 RxPktMsgFifo266[1]; /* 0x00008428 */ + u32 RxPktMsgFifo267[1]; /* 0x0000842c */ + u32 RxPktMsgFifo268[1]; /* 0x00008430 */ + u32 RxPktMsgFifo269[1]; /* 0x00008434 */ + u32 RxPktMsgFifo270[1]; /* 0x00008438 */ + u32 RxPktMsgFifo271[1]; /* 0x0000843c */ + u32 RxPktMsgFifo272[1]; /* 0x00008440 */ + u32 RxPktMsgFifo273[1]; /* 0x00008444 */ + u32 RxPktMsgFifo274[1]; /* 0x00008448 */ + u32 RxPktMsgFifo275[1]; /* 0x0000844c */ + u32 RxPktMsgFifo276[1]; /* 0x00008450 */ + u32 RxPktMsgFifo277[1]; /* 0x00008454 */ + u32 RxPktMsgFifo278[1]; /* 0x00008458 */ + u32 RxPktMsgFifo279[1]; /* 0x0000845c */ + u32 RxPktMsgFifo280[1]; /* 0x00008460 */ + u32 RxPktMsgFifo281[1]; /* 0x00008464 */ + u32 RxPktMsgFifo282[1]; /* 0x00008468 */ + u32 RxPktMsgFifo283[1]; /* 0x0000846c */ + u32 RxPktMsgFifo284[1]; /* 0x00008470 */ + u32 RxPktMsgFifo285[1]; /* 0x00008474 */ + u32 RxPktMsgFifo286[1]; /* 0x00008478 */ + u32 RxPktMsgFifo287[1]; /* 0x0000847c */ + u32 RxPktMsgFifo288[1]; /* 0x00008480 */ + u32 RxPktMsgFifo289[1]; /* 0x00008484 */ + u32 RxPktMsgFifo290[1]; /* 0x00008488 */ + u32 RxPktMsgFifo291[1]; /* 0x0000848c */ + u32 RxPktMsgFifo292[1]; /* 0x00008490 */ + u32 RxPktMsgFifo293[1]; /* 0x00008494 */ + u32 RxPktMsgFifo294[1]; /* 0x00008498 */ + u32 RxPktMsgFifo295[1]; /* 0x0000849c */ + u32 RxPktMsgFifo296[1]; /* 0x000084a0 */ + u32 RxPktMsgFifo297[1]; /* 0x000084a4 */ + u32 RxPktMsgFifo298[1]; /* 0x000084a8 */ + u32 RxPktMsgFifo299[1]; /* 0x000084ac */ + u32 RxPktMsgFifo300[1]; /* 0x000084b0 */ + u32 RxPktMsgFifo301[1]; /* 0x000084b4 */ + u32 RxPktMsgFifo302[1]; /* 0x000084b8 */ + u32 RxPktMsgFifo303[1]; /* 0x000084bc */ + u32 RxPktMsgFifo304[1]; /* 0x000084c0 */ + u32 RxPktMsgFifo305[1]; /* 0x000084c4 */ + u32 RxPktMsgFifo306[1]; /* 0x000084c8 */ + u32 RxPktMsgFifo307[1]; /* 0x000084cc */ + u32 RxPktMsgFifo308[1]; /* 0x000084d0 */ + u32 RxPktMsgFifo309[1]; /* 0x000084d4 */ + u32 RxPktMsgFifo310[1]; /* 0x000084d8 */ + u32 RxPktMsgFifo311[1]; /* 0x000084dc */ + u32 RxPktMsgFifo312[1]; /* 0x000084e0 */ + u32 RxPktMsgFifo313[1]; /* 0x000084e4 */ + u32 RxPktMsgFifo314[1]; /* 0x000084e8 */ + u32 RxPktMsgFifo315[1]; /* 0x000084ec */ + u32 RxPktMsgFifo316[1]; /* 0x000084f0 */ + u32 RxPktMsgFifo317[1]; /* 0x000084f4 */ + u32 RxPktMsgFifo318[1]; /* 0x000084f8 */ + u32 RxPktMsgFifo319[1]; /* 0x000084fc */ + u32 RxPktMsgFifo320[1]; /* 0x00008500 */ + u32 RxPktMsgFifo321[1]; /* 0x00008504 */ + u32 RxPktMsgFifo322[1]; /* 0x00008508 */ + u32 RxPktMsgFifo323[1]; /* 0x0000850c */ + u32 RxPktMsgFifo324[1]; /* 0x00008510 */ u32 rsv8517; u32 rsv8518; u32 rsv8519; @@ -3840,46 +3914,46 @@ struct cpu_mac_mems { u32 rsv8701; u32 rsv8702; u32 rsv8703; - u32 cpu_mac_stats_ram_0[4]; /* 0x00008800 */ - u32 cpu_mac_stats_ram_1[4]; /* 0x00008810 */ - u32 cpu_mac_stats_ram_2[4]; /* 0x00008820 */ - u32 cpu_mac_stats_ram_3[4]; /* 0x00008830 */ - u32 cpu_mac_stats_ram_4[4]; /* 0x00008840 */ - u32 cpu_mac_stats_ram_5[4]; /* 0x00008850 */ - u32 cpu_mac_stats_ram_6[4]; /* 0x00008860 */ - u32 cpu_mac_stats_ram_7[4]; /* 0x00008870 */ - u32 cpu_mac_stats_ram_8[4]; /* 0x00008880 */ - u32 cpu_mac_stats_ram_9[4]; /* 0x00008890 */ - u32 cpu_mac_stats_ram_10[4]; /* 0x000088a0 */ - u32 cpu_mac_stats_ram_11[4]; /* 0x000088b0 */ - u32 cpu_mac_stats_ram_12[4]; /* 0x000088c0 */ - u32 cpu_mac_stats_ram_13[4]; /* 0x000088d0 */ - u32 cpu_mac_stats_ram_14[4]; /* 0x000088e0 */ - u32 cpu_mac_stats_ram_15[4]; /* 0x000088f0 */ - u32 cpu_mac_stats_ram_16[4]; /* 0x00008900 */ - u32 cpu_mac_stats_ram_17[4]; /* 0x00008910 */ - u32 cpu_mac_stats_ram_18[4]; /* 0x00008920 */ - u32 cpu_mac_stats_ram_19[4]; /* 0x00008930 */ - u32 cpu_mac_stats_ram_20[4]; /* 0x00008940 */ - u32 cpu_mac_stats_ram_21[4]; /* 0x00008950 */ - u32 cpu_mac_stats_ram_22[4]; /* 0x00008960 */ - u32 cpu_mac_stats_ram_23[4]; /* 0x00008970 */ - u32 cpu_mac_stats_ram_24[4]; /* 0x00008980 */ - u32 cpu_mac_stats_ram_25[4]; /* 0x00008990 */ - u32 cpu_mac_stats_ram_26[4]; /* 0x000089a0 */ - u32 cpu_mac_stats_ram_27[4]; /* 0x000089b0 */ - u32 cpu_mac_stats_ram_28[4]; /* 0x000089c0 */ - u32 cpu_mac_stats_ram_29[4]; /* 0x000089d0 */ - u32 cpu_mac_stats_ram_30[4]; /* 0x000089e0 */ - u32 cpu_mac_stats_ram_31[4]; /* 0x000089f0 */ - u32 cpu_mac_stats_ram_32[4]; /* 0x00008a00 */ - u32 cpu_mac_stats_ram_33[4]; /* 0x00008a10 */ - u32 cpu_mac_stats_ram_34[4]; /* 0x00008a20 */ - u32 cpu_mac_stats_ram_35[4]; /* 0x00008a30 */ - u32 cpu_mac_stats_ram_36[4]; /* 0x00008a40 */ - u32 cpu_mac_stats_ram_37[4]; /* 0x00008a50 */ - u32 cpu_mac_stats_ram_38[4]; /* 0x00008a60 */ - u32 cpu_mac_stats_ram_39[4]; /* 0x00008a70 */ + u32 CpuMacStatsRam0[4]; /* 0x00008800 */ + u32 CpuMacStatsRam1[4]; /* 0x00008810 */ + u32 CpuMacStatsRam2[4]; /* 0x00008820 */ + u32 CpuMacStatsRam3[4]; /* 0x00008830 */ + u32 CpuMacStatsRam4[4]; /* 0x00008840 */ + u32 CpuMacStatsRam5[4]; /* 0x00008850 */ + u32 CpuMacStatsRam6[4]; /* 0x00008860 */ + u32 CpuMacStatsRam7[4]; /* 0x00008870 */ + u32 CpuMacStatsRam8[4]; /* 0x00008880 */ + u32 CpuMacStatsRam9[4]; /* 0x00008890 */ + u32 CpuMacStatsRam10[4]; /* 0x000088a0 */ + u32 CpuMacStatsRam11[4]; /* 0x000088b0 */ + u32 CpuMacStatsRam12[4]; /* 0x000088c0 */ + u32 CpuMacStatsRam13[4]; /* 0x000088d0 */ + u32 CpuMacStatsRam14[4]; /* 0x000088e0 */ + u32 CpuMacStatsRam15[4]; /* 0x000088f0 */ + u32 CpuMacStatsRam16[4]; /* 0x00008900 */ + u32 CpuMacStatsRam17[4]; /* 0x00008910 */ + u32 CpuMacStatsRam18[4]; /* 0x00008920 */ + u32 CpuMacStatsRam19[4]; /* 0x00008930 */ + u32 CpuMacStatsRam20[4]; /* 0x00008940 */ + u32 CpuMacStatsRam21[4]; /* 0x00008950 */ + u32 CpuMacStatsRam22[4]; /* 0x00008960 */ + u32 CpuMacStatsRam23[4]; /* 0x00008970 */ + u32 CpuMacStatsRam24[4]; /* 0x00008980 */ + u32 CpuMacStatsRam25[4]; /* 0x00008990 */ + u32 CpuMacStatsRam26[4]; /* 0x000089a0 */ + u32 CpuMacStatsRam27[4]; /* 0x000089b0 */ + u32 CpuMacStatsRam28[4]; /* 0x000089c0 */ + u32 CpuMacStatsRam29[4]; /* 0x000089d0 */ + u32 CpuMacStatsRam30[4]; /* 0x000089e0 */ + u32 CpuMacStatsRam31[4]; /* 0x000089f0 */ + u32 CpuMacStatsRam32[4]; /* 0x00008a00 */ + u32 CpuMacStatsRam33[4]; /* 0x00008a10 */ + u32 CpuMacStatsRam34[4]; /* 0x00008a20 */ + u32 CpuMacStatsRam35[4]; /* 0x00008a30 */ + u32 CpuMacStatsRam36[4]; /* 0x00008a40 */ + u32 CpuMacStatsRam37[4]; /* 0x00008a50 */ + u32 CpuMacStatsRam38[4]; /* 0x00008a60 */ + u32 CpuMacStatsRam39[4]; /* 0x00008a70 */ u32 rsv8864; u32 rsv8865; u32 rsv8866; @@ -3976,729 +4050,681 @@ struct cpu_mac_mems { u32 rsv8957; u32 rsv8958; u32 rsv8959; - u32 tx_desc_cfg_fifo_0[2]; /* 0x00008c00 */ - u32 tx_desc_cfg_fifo_1[2]; /* 0x00008c08 */ - u32 tx_desc_cfg_fifo_2[2]; /* 0x00008c10 */ - u32 tx_desc_cfg_fifo_3[2]; /* 0x00008c18 */ - u32 tx_desc_cfg_fifo_4[2]; /* 0x00008c20 */ - u32 tx_desc_cfg_fifo_5[2]; /* 0x00008c28 */ - u32 tx_desc_cfg_fifo_6[2]; /* 0x00008c30 */ - u32 tx_desc_cfg_fifo_7[2]; /* 0x00008c38 */ - u32 tx_desc_cfg_fifo_8[2]; /* 0x00008c40 */ - u32 tx_desc_cfg_fifo_9[2]; /* 0x00008c48 */ - u32 tx_desc_cfg_fifo_10[2]; /* 0x00008c50 */ - u32 tx_desc_cfg_fifo_11[2]; /* 0x00008c58 */ - u32 tx_desc_cfg_fifo_12[2]; /* 0x00008c60 */ - u32 tx_desc_cfg_fifo_13[2]; /* 0x00008c68 */ - u32 tx_desc_cfg_fifo_14[2]; /* 0x00008c70 */ - u32 tx_desc_cfg_fifo_15[2]; /* 0x00008c78 */ - u32 tx_desc_cfg_fifo_16[2]; /* 0x00008c80 */ - u32 tx_desc_cfg_fifo_17[2]; /* 0x00008c88 */ - u32 tx_desc_cfg_fifo_18[2]; /* 0x00008c90 */ - u32 tx_desc_cfg_fifo_19[2]; /* 0x00008c98 */ - u32 tx_desc_cfg_fifo_20[2]; /* 0x00008ca0 */ - u32 tx_desc_cfg_fifo_21[2]; /* 0x00008ca8 */ - u32 tx_desc_cfg_fifo_22[2]; /* 0x00008cb0 */ - u32 tx_desc_cfg_fifo_23[2]; /* 0x00008cb8 */ - u32 tx_desc_cfg_fifo_24[2]; /* 0x00008cc0 */ - u32 tx_desc_cfg_fifo_25[2]; /* 0x00008cc8 */ - u32 tx_desc_cfg_fifo_26[2]; /* 0x00008cd0 */ - u32 tx_desc_cfg_fifo_27[2]; /* 0x00008cd8 */ - u32 tx_desc_cfg_fifo_28[2]; /* 0x00008ce0 */ - u32 tx_desc_cfg_fifo_29[2]; /* 0x00008ce8 */ - u32 tx_desc_cfg_fifo_30[2]; /* 0x00008cf0 */ - u32 tx_desc_cfg_fifo_31[2]; /* 0x00008cf8 */ - u32 tx_desc_cfg_fifo_32[2]; /* 0x00008d00 */ - u32 tx_desc_cfg_fifo_33[2]; /* 0x00008d08 */ - u32 tx_desc_cfg_fifo_34[2]; /* 0x00008d10 */ - u32 tx_desc_cfg_fifo_35[2]; /* 0x00008d18 */ - u32 tx_desc_cfg_fifo_36[2]; /* 0x00008d20 */ - u32 tx_desc_cfg_fifo_37[2]; /* 0x00008d28 */ - u32 tx_desc_cfg_fifo_38[2]; /* 0x00008d30 */ - u32 tx_desc_cfg_fifo_39[2]; /* 0x00008d38 */ - u32 tx_desc_cfg_fifo_40[2]; /* 0x00008d40 */ - u32 tx_desc_cfg_fifo_41[2]; /* 0x00008d48 */ - u32 tx_desc_cfg_fifo_42[2]; /* 0x00008d50 */ - u32 tx_desc_cfg_fifo_43[2]; /* 0x00008d58 */ - u32 tx_desc_cfg_fifo_44[2]; /* 0x00008d60 */ - u32 tx_desc_cfg_fifo_45[2]; /* 0x00008d68 */ - u32 tx_desc_cfg_fifo_46[2]; /* 0x00008d70 */ - u32 tx_desc_cfg_fifo_47[2]; /* 0x00008d78 */ - u32 tx_desc_cfg_fifo_48[2]; /* 0x00008d80 */ - u32 tx_desc_cfg_fifo_49[2]; /* 0x00008d88 */ - u32 tx_desc_cfg_fifo_50[2]; /* 0x00008d90 */ - u32 tx_desc_cfg_fifo_51[2]; /* 0x00008d98 */ - u32 tx_desc_cfg_fifo_52[2]; /* 0x00008da0 */ - u32 tx_desc_cfg_fifo_53[2]; /* 0x00008da8 */ - u32 tx_desc_cfg_fifo_54[2]; /* 0x00008db0 */ - u32 tx_desc_cfg_fifo_55[2]; /* 0x00008db8 */ - u32 tx_desc_cfg_fifo_56[2]; /* 0x00008dc0 */ - u32 tx_desc_cfg_fifo_57[2]; /* 0x00008dc8 */ - u32 tx_desc_cfg_fifo_58[2]; /* 0x00008dd0 */ - u32 tx_desc_cfg_fifo_59[2]; /* 0x00008dd8 */ - u32 tx_desc_cfg_fifo_60[2]; /* 0x00008de0 */ - u32 tx_desc_cfg_fifo_61[2]; /* 0x00008de8 */ - u32 tx_desc_cfg_fifo_62[2]; /* 0x00008df0 */ - u32 tx_desc_cfg_fifo_63[2]; /* 0x00008df8 */ - u32 rx_desc_0_cfg_fifo_0[2]; /* 0x00008e00 */ - u32 rx_desc_0_cfg_fifo_1[2]; /* 0x00008e08 */ - u32 rx_desc_0_cfg_fifo_2[2]; /* 0x00008e10 */ - u32 rx_desc_0_cfg_fifo_3[2]; /* 0x00008e18 */ - u32 rx_desc_0_cfg_fifo_4[2]; /* 0x00008e20 */ - u32 rx_desc_0_cfg_fifo_5[2]; /* 0x00008e28 */ - u32 rx_desc_0_cfg_fifo_6[2]; /* 0x00008e30 */ - u32 rx_desc_0_cfg_fifo_7[2]; /* 0x00008e38 */ - u32 rx_desc_0_cfg_fifo_8[2]; /* 0x00008e40 */ - u32 rx_desc_0_cfg_fifo_9[2]; /* 0x00008e48 */ - u32 rx_desc_0_cfg_fifo_10[2]; /* 0x00008e50 */ - u32 rx_desc_0_cfg_fifo_11[2]; /* 0x00008e58 */ - u32 rx_desc_0_cfg_fifo_12[2]; /* 0x00008e60 */ - u32 rx_desc_0_cfg_fifo_13[2]; /* 0x00008e68 */ - u32 rx_desc_0_cfg_fifo_14[2]; /* 0x00008e70 */ - u32 rx_desc_0_cfg_fifo_15[2]; /* 0x00008e78 */ - u32 rx_desc_0_cfg_fifo_16[2]; /* 0x00008e80 */ - u32 rx_desc_0_cfg_fifo_17[2]; /* 0x00008e88 */ - u32 rx_desc_0_cfg_fifo_18[2]; /* 0x00008e90 */ - u32 rx_desc_0_cfg_fifo_19[2]; /* 0x00008e98 */ - u32 rx_desc_0_cfg_fifo_20[2]; /* 0x00008ea0 */ - u32 rx_desc_0_cfg_fifo_21[2]; /* 0x00008ea8 */ - u32 rx_desc_0_cfg_fifo_22[2]; /* 0x00008eb0 */ - u32 rx_desc_0_cfg_fifo_23[2]; /* 0x00008eb8 */ - u32 rx_desc_0_cfg_fifo_24[2]; /* 0x00008ec0 */ - u32 rx_desc_0_cfg_fifo_25[2]; /* 0x00008ec8 */ - u32 rx_desc_0_cfg_fifo_26[2]; /* 0x00008ed0 */ - u32 rx_desc_0_cfg_fifo_27[2]; /* 0x00008ed8 */ - u32 rx_desc_0_cfg_fifo_28[2]; /* 0x00008ee0 */ - u32 rx_desc_0_cfg_fifo_29[2]; /* 0x00008ee8 */ - u32 rx_desc_0_cfg_fifo_30[2]; /* 0x00008ef0 */ - u32 rx_desc_0_cfg_fifo_31[2]; /* 0x00008ef8 */ - u32 rx_desc_0_cfg_fifo_32[2]; /* 0x00008f00 */ - u32 rx_desc_0_cfg_fifo_33[2]; /* 0x00008f08 */ - u32 rx_desc_0_cfg_fifo_34[2]; /* 0x00008f10 */ - u32 rx_desc_0_cfg_fifo_35[2]; /* 0x00008f18 */ - u32 rx_desc_0_cfg_fifo_36[2]; /* 0x00008f20 */ - u32 rx_desc_0_cfg_fifo_37[2]; /* 0x00008f28 */ - u32 rx_desc_0_cfg_fifo_38[2]; /* 0x00008f30 */ - u32 rx_desc_0_cfg_fifo_39[2]; /* 0x00008f38 */ - u32 rx_desc_0_cfg_fifo_40[2]; /* 0x00008f40 */ - u32 rx_desc_0_cfg_fifo_41[2]; /* 0x00008f48 */ - u32 rx_desc_0_cfg_fifo_42[2]; /* 0x00008f50 */ - u32 rx_desc_0_cfg_fifo_43[2]; /* 0x00008f58 */ - u32 rx_desc_0_cfg_fifo_44[2]; /* 0x00008f60 */ - u32 rx_desc_0_cfg_fifo_45[2]; /* 0x00008f68 */ - u32 rx_desc_0_cfg_fifo_46[2]; /* 0x00008f70 */ - u32 rx_desc_0_cfg_fifo_47[2]; /* 0x00008f78 */ - u32 rx_desc_0_cfg_fifo_48[2]; /* 0x00008f80 */ - u32 rx_desc_0_cfg_fifo_49[2]; /* 0x00008f88 */ - u32 rx_desc_0_cfg_fifo_50[2]; /* 0x00008f90 */ - u32 rx_desc_0_cfg_fifo_51[2]; /* 0x00008f98 */ - u32 rx_desc_0_cfg_fifo_52[2]; /* 0x00008fa0 */ - u32 rx_desc_0_cfg_fifo_53[2]; /* 0x00008fa8 */ - u32 rx_desc_0_cfg_fifo_54[2]; /* 0x00008fb0 */ - u32 rx_desc_0_cfg_fifo_55[2]; /* 0x00008fb8 */ - u32 rx_desc_0_cfg_fifo_56[2]; /* 0x00008fc0 */ - u32 rx_desc_0_cfg_fifo_57[2]; /* 0x00008fc8 */ - u32 rx_desc_0_cfg_fifo_58[2]; /* 0x00008fd0 */ - u32 rx_desc_0_cfg_fifo_59[2]; /* 0x00008fd8 */ - u32 rx_desc_0_cfg_fifo_60[2]; /* 0x00008fe0 */ - u32 rx_desc_0_cfg_fifo_61[2]; /* 0x00008fe8 */ - u32 rx_desc_0_cfg_fifo_62[2]; /* 0x00008ff0 */ - u32 rx_desc_0_cfg_fifo_63[2]; /* 0x00008ff8 */ - u32 rx_desc_1_cfg_fifo_0[2]; /* 0x00009000 */ - u32 rx_desc_1_cfg_fifo_1[2]; /* 0x00009008 */ - u32 rx_desc_1_cfg_fifo_2[2]; /* 0x00009010 */ - u32 rx_desc_1_cfg_fifo_3[2]; /* 0x00009018 */ - u32 rx_desc_1_cfg_fifo_4[2]; /* 0x00009020 */ - u32 rx_desc_1_cfg_fifo_5[2]; /* 0x00009028 */ - u32 rx_desc_1_cfg_fifo_6[2]; /* 0x00009030 */ - u32 rx_desc_1_cfg_fifo_7[2]; /* 0x00009038 */ - u32 rx_desc_1_cfg_fifo_8[2]; /* 0x00009040 */ - u32 rx_desc_1_cfg_fifo_9[2]; /* 0x00009048 */ - u32 rx_desc_1_cfg_fifo_10[2]; /* 0x00009050 */ - u32 rx_desc_1_cfg_fifo_11[2]; /* 0x00009058 */ - u32 rx_desc_1_cfg_fifo_12[2]; /* 0x00009060 */ - u32 rx_desc_1_cfg_fifo_13[2]; /* 0x00009068 */ - u32 rx_desc_1_cfg_fifo_14[2]; /* 0x00009070 */ - u32 rx_desc_1_cfg_fifo_15[2]; /* 0x00009078 */ - u32 rx_desc_1_cfg_fifo_16[2]; /* 0x00009080 */ - u32 rx_desc_1_cfg_fifo_17[2]; /* 0x00009088 */ - u32 rx_desc_1_cfg_fifo_18[2]; /* 0x00009090 */ - u32 rx_desc_1_cfg_fifo_19[2]; /* 0x00009098 */ - u32 rx_desc_1_cfg_fifo_20[2]; /* 0x000090a0 */ - u32 rx_desc_1_cfg_fifo_21[2]; /* 0x000090a8 */ - u32 rx_desc_1_cfg_fifo_22[2]; /* 0x000090b0 */ - u32 rx_desc_1_cfg_fifo_23[2]; /* 0x000090b8 */ - u32 rx_desc_1_cfg_fifo_24[2]; /* 0x000090c0 */ - u32 rx_desc_1_cfg_fifo_25[2]; /* 0x000090c8 */ - u32 rx_desc_1_cfg_fifo_26[2]; /* 0x000090d0 */ - u32 rx_desc_1_cfg_fifo_27[2]; /* 0x000090d8 */ - u32 rx_desc_1_cfg_fifo_28[2]; /* 0x000090e0 */ - u32 rx_desc_1_cfg_fifo_29[2]; /* 0x000090e8 */ - u32 rx_desc_1_cfg_fifo_30[2]; /* 0x000090f0 */ - u32 rx_desc_1_cfg_fifo_31[2]; /* 0x000090f8 */ - u32 rx_desc_1_cfg_fifo_32[2]; /* 0x00009100 */ - u32 rx_desc_1_cfg_fifo_33[2]; /* 0x00009108 */ - u32 rx_desc_1_cfg_fifo_34[2]; /* 0x00009110 */ - u32 rx_desc_1_cfg_fifo_35[2]; /* 0x00009118 */ - u32 rx_desc_1_cfg_fifo_36[2]; /* 0x00009120 */ - u32 rx_desc_1_cfg_fifo_37[2]; /* 0x00009128 */ - u32 rx_desc_1_cfg_fifo_38[2]; /* 0x00009130 */ - u32 rx_desc_1_cfg_fifo_39[2]; /* 0x00009138 */ - u32 rx_desc_1_cfg_fifo_40[2]; /* 0x00009140 */ - u32 rx_desc_1_cfg_fifo_41[2]; /* 0x00009148 */ - u32 rx_desc_1_cfg_fifo_42[2]; /* 0x00009150 */ - u32 rx_desc_1_cfg_fifo_43[2]; /* 0x00009158 */ - u32 rx_desc_1_cfg_fifo_44[2]; /* 0x00009160 */ - u32 rx_desc_1_cfg_fifo_45[2]; /* 0x00009168 */ - u32 rx_desc_1_cfg_fifo_46[2]; /* 0x00009170 */ - u32 rx_desc_1_cfg_fifo_47[2]; /* 0x00009178 */ - u32 rx_desc_1_cfg_fifo_48[2]; /* 0x00009180 */ - u32 rx_desc_1_cfg_fifo_49[2]; /* 0x00009188 */ - u32 rx_desc_1_cfg_fifo_50[2]; /* 0x00009190 */ - u32 rx_desc_1_cfg_fifo_51[2]; /* 0x00009198 */ - u32 rx_desc_1_cfg_fifo_52[2]; /* 0x000091a0 */ - u32 rx_desc_1_cfg_fifo_53[2]; /* 0x000091a8 */ - u32 rx_desc_1_cfg_fifo_54[2]; /* 0x000091b0 */ - u32 rx_desc_1_cfg_fifo_55[2]; /* 0x000091b8 */ - u32 rx_desc_1_cfg_fifo_56[2]; /* 0x000091c0 */ - u32 rx_desc_1_cfg_fifo_57[2]; /* 0x000091c8 */ - u32 rx_desc_1_cfg_fifo_58[2]; /* 0x000091d0 */ - u32 rx_desc_1_cfg_fifo_59[2]; /* 0x000091d8 */ - u32 rx_desc_1_cfg_fifo_60[2]; /* 0x000091e0 */ - u32 rx_desc_1_cfg_fifo_61[2]; /* 0x000091e8 */ - u32 rx_desc_1_cfg_fifo_62[2]; /* 0x000091f0 */ - u32 rx_desc_1_cfg_fifo_63[2]; /* 0x000091f8 */ - u32 rx_desc_0_ack_fifo_0[1]; /* 0x00009200 */ - u32 rx_desc_0_ack_fifo_1[1]; /* 0x00009204 */ - u32 rx_desc_0_ack_fifo_2[1]; /* 0x00009208 */ - u32 rx_desc_0_ack_fifo_3[1]; /* 0x0000920c */ - u32 rx_desc_0_ack_fifo_4[1]; /* 0x00009210 */ - u32 rx_desc_0_ack_fifo_5[1]; /* 0x00009214 */ - u32 rx_desc_0_ack_fifo_6[1]; /* 0x00009218 */ - u32 rx_desc_0_ack_fifo_7[1]; /* 0x0000921c */ - u32 rx_desc_0_ack_fifo_8[1]; /* 0x00009220 */ - u32 rx_desc_0_ack_fifo_9[1]; /* 0x00009224 */ - u32 rx_desc_0_ack_fifo_10[1]; /* 0x00009228 */ - u32 rx_desc_0_ack_fifo_11[1]; /* 0x0000922c */ - u32 rx_desc_0_ack_fifo_12[1]; /* 0x00009230 */ - u32 rx_desc_0_ack_fifo_13[1]; /* 0x00009234 */ - u32 rx_desc_0_ack_fifo_14[1]; /* 0x00009238 */ - u32 rx_desc_0_ack_fifo_15[1]; /* 0x0000923c */ - u32 rx_desc_0_ack_fifo_16[1]; /* 0x00009240 */ - u32 rx_desc_0_ack_fifo_17[1]; /* 0x00009244 */ - u32 rx_desc_0_ack_fifo_18[1]; /* 0x00009248 */ - u32 rx_desc_0_ack_fifo_19[1]; /* 0x0000924c */ - u32 rx_desc_0_ack_fifo_20[1]; /* 0x00009250 */ - u32 rx_desc_0_ack_fifo_21[1]; /* 0x00009254 */ - u32 rx_desc_0_ack_fifo_22[1]; /* 0x00009258 */ - u32 rx_desc_0_ack_fifo_23[1]; /* 0x0000925c */ - u32 rx_desc_0_ack_fifo_24[1]; /* 0x00009260 */ - u32 rx_desc_0_ack_fifo_25[1]; /* 0x00009264 */ - u32 rx_desc_0_ack_fifo_26[1]; /* 0x00009268 */ - u32 rx_desc_0_ack_fifo_27[1]; /* 0x0000926c */ - u32 rx_desc_0_ack_fifo_28[1]; /* 0x00009270 */ - u32 rx_desc_0_ack_fifo_29[1]; /* 0x00009274 */ - u32 rx_desc_0_ack_fifo_30[1]; /* 0x00009278 */ - u32 rx_desc_0_ack_fifo_31[1]; /* 0x0000927c */ - u32 rx_desc_0_ack_fifo_32[1]; /* 0x00009280 */ - u32 rx_desc_0_ack_fifo_33[1]; /* 0x00009284 */ - u32 rx_desc_0_ack_fifo_34[1]; /* 0x00009288 */ - u32 rx_desc_0_ack_fifo_35[1]; /* 0x0000928c */ - u32 rx_desc_0_ack_fifo_36[1]; /* 0x00009290 */ - u32 rx_desc_0_ack_fifo_37[1]; /* 0x00009294 */ - u32 rx_desc_0_ack_fifo_38[1]; /* 0x00009298 */ - u32 rx_desc_0_ack_fifo_39[1]; /* 0x0000929c */ - u32 rx_desc_0_ack_fifo_40[1]; /* 0x000092a0 */ - u32 rx_desc_0_ack_fifo_41[1]; /* 0x000092a4 */ - u32 rx_desc_0_ack_fifo_42[1]; /* 0x000092a8 */ - u32 rx_desc_0_ack_fifo_43[1]; /* 0x000092ac */ - u32 rx_desc_0_ack_fifo_44[1]; /* 0x000092b0 */ - u32 rx_desc_0_ack_fifo_45[1]; /* 0x000092b4 */ - u32 rx_desc_0_ack_fifo_46[1]; /* 0x000092b8 */ - u32 rx_desc_0_ack_fifo_47[1]; /* 0x000092bc */ - u32 rx_desc_0_ack_fifo_48[1]; /* 0x000092c0 */ - u32 rx_desc_0_ack_fifo_49[1]; /* 0x000092c4 */ - u32 rx_desc_0_ack_fifo_50[1]; /* 0x000092c8 */ - u32 rx_desc_0_ack_fifo_51[1]; /* 0x000092cc */ - u32 rx_desc_0_ack_fifo_52[1]; /* 0x000092d0 */ - u32 rx_desc_0_ack_fifo_53[1]; /* 0x000092d4 */ - u32 rx_desc_0_ack_fifo_54[1]; /* 0x000092d8 */ - u32 rx_desc_0_ack_fifo_55[1]; /* 0x000092dc */ - u32 rx_desc_0_ack_fifo_56[1]; /* 0x000092e0 */ - u32 rx_desc_0_ack_fifo_57[1]; /* 0x000092e4 */ - u32 rx_desc_0_ack_fifo_58[1]; /* 0x000092e8 */ - u32 rx_desc_0_ack_fifo_59[1]; /* 0x000092ec */ - u32 rx_desc_0_ack_fifo_60[1]; /* 0x000092f0 */ - u32 rx_desc_0_ack_fifo_61[1]; /* 0x000092f4 */ - u32 rx_desc_0_ack_fifo_62[1]; /* 0x000092f8 */ - u32 rx_desc_0_ack_fifo_63[1]; /* 0x000092fc */ - u32 rx_desc_1_ack_fifo_0[1]; /* 0x00009300 */ - u32 rx_desc_1_ack_fifo_1[1]; /* 0x00009304 */ - u32 rx_desc_1_ack_fifo_2[1]; /* 0x00009308 */ - u32 rx_desc_1_ack_fifo_3[1]; /* 0x0000930c */ - u32 rx_desc_1_ack_fifo_4[1]; /* 0x00009310 */ - u32 rx_desc_1_ack_fifo_5[1]; /* 0x00009314 */ - u32 rx_desc_1_ack_fifo_6[1]; /* 0x00009318 */ - u32 rx_desc_1_ack_fifo_7[1]; /* 0x0000931c */ - u32 rx_desc_1_ack_fifo_8[1]; /* 0x00009320 */ - u32 rx_desc_1_ack_fifo_9[1]; /* 0x00009324 */ - u32 rx_desc_1_ack_fifo_10[1]; /* 0x00009328 */ - u32 rx_desc_1_ack_fifo_11[1]; /* 0x0000932c */ - u32 rx_desc_1_ack_fifo_12[1]; /* 0x00009330 */ - u32 rx_desc_1_ack_fifo_13[1]; /* 0x00009334 */ - u32 rx_desc_1_ack_fifo_14[1]; /* 0x00009338 */ - u32 rx_desc_1_ack_fifo_15[1]; /* 0x0000933c */ - u32 rx_desc_1_ack_fifo_16[1]; /* 0x00009340 */ - u32 rx_desc_1_ack_fifo_17[1]; /* 0x00009344 */ - u32 rx_desc_1_ack_fifo_18[1]; /* 0x00009348 */ - u32 rx_desc_1_ack_fifo_19[1]; /* 0x0000934c */ - u32 rx_desc_1_ack_fifo_20[1]; /* 0x00009350 */ - u32 rx_desc_1_ack_fifo_21[1]; /* 0x00009354 */ - u32 rx_desc_1_ack_fifo_22[1]; /* 0x00009358 */ - u32 rx_desc_1_ack_fifo_23[1]; /* 0x0000935c */ - u32 rx_desc_1_ack_fifo_24[1]; /* 0x00009360 */ - u32 rx_desc_1_ack_fifo_25[1]; /* 0x00009364 */ - u32 rx_desc_1_ack_fifo_26[1]; /* 0x00009368 */ - u32 rx_desc_1_ack_fifo_27[1]; /* 0x0000936c */ - u32 rx_desc_1_ack_fifo_28[1]; /* 0x00009370 */ - u32 rx_desc_1_ack_fifo_29[1]; /* 0x00009374 */ - u32 rx_desc_1_ack_fifo_30[1]; /* 0x00009378 */ - u32 rx_desc_1_ack_fifo_31[1]; /* 0x0000937c */ - u32 rx_desc_1_ack_fifo_32[1]; /* 0x00009380 */ - u32 rx_desc_1_ack_fifo_33[1]; /* 0x00009384 */ - u32 rx_desc_1_ack_fifo_34[1]; /* 0x00009388 */ - u32 rx_desc_1_ack_fifo_35[1]; /* 0x0000938c */ - u32 rx_desc_1_ack_fifo_36[1]; /* 0x00009390 */ - u32 rx_desc_1_ack_fifo_37[1]; /* 0x00009394 */ - u32 rx_desc_1_ack_fifo_38[1]; /* 0x00009398 */ - u32 rx_desc_1_ack_fifo_39[1]; /* 0x0000939c */ - u32 rx_desc_1_ack_fifo_40[1]; /* 0x000093a0 */ - u32 rx_desc_1_ack_fifo_41[1]; /* 0x000093a4 */ - u32 rx_desc_1_ack_fifo_42[1]; /* 0x000093a8 */ - u32 rx_desc_1_ack_fifo_43[1]; /* 0x000093ac */ - u32 rx_desc_1_ack_fifo_44[1]; /* 0x000093b0 */ - u32 rx_desc_1_ack_fifo_45[1]; /* 0x000093b4 */ - u32 rx_desc_1_ack_fifo_46[1]; /* 0x000093b8 */ - u32 rx_desc_1_ack_fifo_47[1]; /* 0x000093bc */ - u32 rx_desc_1_ack_fifo_48[1]; /* 0x000093c0 */ - u32 rx_desc_1_ack_fifo_49[1]; /* 0x000093c4 */ - u32 rx_desc_1_ack_fifo_50[1]; /* 0x000093c8 */ - u32 rx_desc_1_ack_fifo_51[1]; /* 0x000093cc */ - u32 rx_desc_1_ack_fifo_52[1]; /* 0x000093d0 */ - u32 rx_desc_1_ack_fifo_53[1]; /* 0x000093d4 */ - u32 rx_desc_1_ack_fifo_54[1]; /* 0x000093d8 */ - u32 rx_desc_1_ack_fifo_55[1]; /* 0x000093dc */ - u32 rx_desc_1_ack_fifo_56[1]; /* 0x000093e0 */ - u32 rx_desc_1_ack_fifo_57[1]; /* 0x000093e4 */ - u32 rx_desc_1_ack_fifo_58[1]; /* 0x000093e8 */ - u32 rx_desc_1_ack_fifo_59[1]; /* 0x000093ec */ - u32 rx_desc_1_ack_fifo_60[1]; /* 0x000093f0 */ - u32 rx_desc_1_ack_fifo_61[1]; /* 0x000093f4 */ - u32 rx_desc_1_ack_fifo_62[1]; /* 0x000093f8 */ - u32 rx_desc_1_ack_fifo_63[1]; /* 0x000093fc */ - u32 tx_desc_ack_fifo_0[1]; /* 0x00009400 */ - u32 tx_desc_ack_fifo_1[1]; /* 0x00009404 */ - u32 tx_desc_ack_fifo_2[1]; /* 0x00009408 */ - u32 tx_desc_ack_fifo_3[1]; /* 0x0000940c */ - u32 tx_desc_ack_fifo_4[1]; /* 0x00009410 */ - u32 tx_desc_ack_fifo_5[1]; /* 0x00009414 */ - u32 tx_desc_ack_fifo_6[1]; /* 0x00009418 */ - u32 tx_desc_ack_fifo_7[1]; /* 0x0000941c */ - u32 tx_desc_ack_fifo_8[1]; /* 0x00009420 */ - u32 tx_desc_ack_fifo_9[1]; /* 0x00009424 */ - u32 tx_desc_ack_fifo_10[1]; /* 0x00009428 */ - u32 tx_desc_ack_fifo_11[1]; /* 0x0000942c */ - u32 tx_desc_ack_fifo_12[1]; /* 0x00009430 */ - u32 tx_desc_ack_fifo_13[1]; /* 0x00009434 */ - u32 tx_desc_ack_fifo_14[1]; /* 0x00009438 */ - u32 tx_desc_ack_fifo_15[1]; /* 0x0000943c */ - u32 tx_desc_ack_fifo_16[1]; /* 0x00009440 */ - u32 tx_desc_ack_fifo_17[1]; /* 0x00009444 */ - u32 tx_desc_ack_fifo_18[1]; /* 0x00009448 */ - u32 tx_desc_ack_fifo_19[1]; /* 0x0000944c */ - u32 tx_desc_ack_fifo_20[1]; /* 0x00009450 */ - u32 tx_desc_ack_fifo_21[1]; /* 0x00009454 */ - u32 tx_desc_ack_fifo_22[1]; /* 0x00009458 */ - u32 tx_desc_ack_fifo_23[1]; /* 0x0000945c */ - u32 tx_desc_ack_fifo_24[1]; /* 0x00009460 */ - u32 tx_desc_ack_fifo_25[1]; /* 0x00009464 */ - u32 tx_desc_ack_fifo_26[1]; /* 0x00009468 */ - u32 tx_desc_ack_fifo_27[1]; /* 0x0000946c */ - u32 tx_desc_ack_fifo_28[1]; /* 0x00009470 */ - u32 tx_desc_ack_fifo_29[1]; /* 0x00009474 */ - u32 tx_desc_ack_fifo_30[1]; /* 0x00009478 */ - u32 tx_desc_ack_fifo_31[1]; /* 0x0000947c */ - u32 tx_desc_ack_fifo_32[1]; /* 0x00009480 */ - u32 tx_desc_ack_fifo_33[1]; /* 0x00009484 */ - u32 tx_desc_ack_fifo_34[1]; /* 0x00009488 */ - u32 tx_desc_ack_fifo_35[1]; /* 0x0000948c */ - u32 tx_desc_ack_fifo_36[1]; /* 0x00009490 */ - u32 tx_desc_ack_fifo_37[1]; /* 0x00009494 */ - u32 tx_desc_ack_fifo_38[1]; /* 0x00009498 */ - u32 tx_desc_ack_fifo_39[1]; /* 0x0000949c */ - u32 tx_desc_ack_fifo_40[1]; /* 0x000094a0 */ - u32 tx_desc_ack_fifo_41[1]; /* 0x000094a4 */ - u32 tx_desc_ack_fifo_42[1]; /* 0x000094a8 */ - u32 tx_desc_ack_fifo_43[1]; /* 0x000094ac */ - u32 tx_desc_ack_fifo_44[1]; /* 0x000094b0 */ - u32 tx_desc_ack_fifo_45[1]; /* 0x000094b4 */ - u32 tx_desc_ack_fifo_46[1]; /* 0x000094b8 */ - u32 tx_desc_ack_fifo_47[1]; /* 0x000094bc */ - u32 tx_desc_ack_fifo_48[1]; /* 0x000094c0 */ - u32 tx_desc_ack_fifo_49[1]; /* 0x000094c4 */ - u32 tx_desc_ack_fifo_50[1]; /* 0x000094c8 */ - u32 tx_desc_ack_fifo_51[1]; /* 0x000094cc */ - u32 tx_desc_ack_fifo_52[1]; /* 0x000094d0 */ - u32 tx_desc_ack_fifo_53[1]; /* 0x000094d4 */ - u32 tx_desc_ack_fifo_54[1]; /* 0x000094d8 */ - u32 tx_desc_ack_fifo_55[1]; /* 0x000094dc */ - u32 tx_desc_ack_fifo_56[1]; /* 0x000094e0 */ - u32 tx_desc_ack_fifo_57[1]; /* 0x000094e4 */ - u32 tx_desc_ack_fifo_58[1]; /* 0x000094e8 */ - u32 tx_desc_ack_fifo_59[1]; /* 0x000094ec */ - u32 tx_desc_ack_fifo_60[1]; /* 0x000094f0 */ - u32 tx_desc_ack_fifo_61[1]; /* 0x000094f4 */ - u32 tx_desc_ack_fifo_62[1]; /* 0x000094f8 */ - u32 tx_desc_ack_fifo_63[1]; /* 0x000094fc */ - u32 cpu_mac_desc_intf_0[2]; /* 0x00009500 */ - u32 cpu_mac_desc_intf_1[2]; /* 0x00009508 */ - u32 cpu_mac_desc_intf_2[2]; /* 0x00009510 */ + u32 TxDescCfgFifo0[2]; /* 0x00008c00 */ + u32 TxDescCfgFifo1[2]; /* 0x00008c08 */ + u32 TxDescCfgFifo2[2]; /* 0x00008c10 */ + u32 TxDescCfgFifo3[2]; /* 0x00008c18 */ + u32 TxDescCfgFifo4[2]; /* 0x00008c20 */ + u32 TxDescCfgFifo5[2]; /* 0x00008c28 */ + u32 TxDescCfgFifo6[2]; /* 0x00008c30 */ + u32 TxDescCfgFifo7[2]; /* 0x00008c38 */ + u32 TxDescCfgFifo8[2]; /* 0x00008c40 */ + u32 TxDescCfgFifo9[2]; /* 0x00008c48 */ + u32 TxDescCfgFifo10[2]; /* 0x00008c50 */ + u32 TxDescCfgFifo11[2]; /* 0x00008c58 */ + u32 TxDescCfgFifo12[2]; /* 0x00008c60 */ + u32 TxDescCfgFifo13[2]; /* 0x00008c68 */ + u32 TxDescCfgFifo14[2]; /* 0x00008c70 */ + u32 TxDescCfgFifo15[2]; /* 0x00008c78 */ + u32 TxDescCfgFifo16[2]; /* 0x00008c80 */ + u32 TxDescCfgFifo17[2]; /* 0x00008c88 */ + u32 TxDescCfgFifo18[2]; /* 0x00008c90 */ + u32 TxDescCfgFifo19[2]; /* 0x00008c98 */ + u32 TxDescCfgFifo20[2]; /* 0x00008ca0 */ + u32 TxDescCfgFifo21[2]; /* 0x00008ca8 */ + u32 TxDescCfgFifo22[2]; /* 0x00008cb0 */ + u32 TxDescCfgFifo23[2]; /* 0x00008cb8 */ + u32 TxDescCfgFifo24[2]; /* 0x00008cc0 */ + u32 TxDescCfgFifo25[2]; /* 0x00008cc8 */ + u32 TxDescCfgFifo26[2]; /* 0x00008cd0 */ + u32 TxDescCfgFifo27[2]; /* 0x00008cd8 */ + u32 TxDescCfgFifo28[2]; /* 0x00008ce0 */ + u32 TxDescCfgFifo29[2]; /* 0x00008ce8 */ + u32 TxDescCfgFifo30[2]; /* 0x00008cf0 */ + u32 TxDescCfgFifo31[2]; /* 0x00008cf8 */ + u32 TxDescCfgFifo32[2]; /* 0x00008d00 */ + u32 TxDescCfgFifo33[2]; /* 0x00008d08 */ + u32 TxDescCfgFifo34[2]; /* 0x00008d10 */ + u32 TxDescCfgFifo35[2]; /* 0x00008d18 */ + u32 TxDescCfgFifo36[2]; /* 0x00008d20 */ + u32 TxDescCfgFifo37[2]; /* 0x00008d28 */ + u32 TxDescCfgFifo38[2]; /* 0x00008d30 */ + u32 TxDescCfgFifo39[2]; /* 0x00008d38 */ + u32 TxDescCfgFifo40[2]; /* 0x00008d40 */ + u32 TxDescCfgFifo41[2]; /* 0x00008d48 */ + u32 TxDescCfgFifo42[2]; /* 0x00008d50 */ + u32 TxDescCfgFifo43[2]; /* 0x00008d58 */ + u32 TxDescCfgFifo44[2]; /* 0x00008d60 */ + u32 TxDescCfgFifo45[2]; /* 0x00008d68 */ + u32 TxDescCfgFifo46[2]; /* 0x00008d70 */ + u32 TxDescCfgFifo47[2]; /* 0x00008d78 */ + u32 TxDescCfgFifo48[2]; /* 0x00008d80 */ + u32 TxDescCfgFifo49[2]; /* 0x00008d88 */ + u32 TxDescCfgFifo50[2]; /* 0x00008d90 */ + u32 TxDescCfgFifo51[2]; /* 0x00008d98 */ + u32 TxDescCfgFifo52[2]; /* 0x00008da0 */ + u32 TxDescCfgFifo53[2]; /* 0x00008da8 */ + u32 TxDescCfgFifo54[2]; /* 0x00008db0 */ + u32 TxDescCfgFifo55[2]; /* 0x00008db8 */ + u32 TxDescCfgFifo56[2]; /* 0x00008dc0 */ + u32 TxDescCfgFifo57[2]; /* 0x00008dc8 */ + u32 TxDescCfgFifo58[2]; /* 0x00008dd0 */ + u32 TxDescCfgFifo59[2]; /* 0x00008dd8 */ + u32 TxDescCfgFifo60[2]; /* 0x00008de0 */ + u32 TxDescCfgFifo61[2]; /* 0x00008de8 */ + u32 TxDescCfgFifo62[2]; /* 0x00008df0 */ + u32 TxDescCfgFifo63[2]; /* 0x00008df8 */ + u32 RxDesc0CfgFifo0[2]; /* 0x00008e00 */ + u32 RxDesc0CfgFifo1[2]; /* 0x00008e08 */ + u32 RxDesc0CfgFifo2[2]; /* 0x00008e10 */ + u32 RxDesc0CfgFifo3[2]; /* 0x00008e18 */ + u32 RxDesc0CfgFifo4[2]; /* 0x00008e20 */ + u32 RxDesc0CfgFifo5[2]; /* 0x00008e28 */ + u32 RxDesc0CfgFifo6[2]; /* 0x00008e30 */ + u32 RxDesc0CfgFifo7[2]; /* 0x00008e38 */ + u32 RxDesc0CfgFifo8[2]; /* 0x00008e40 */ + u32 RxDesc0CfgFifo9[2]; /* 0x00008e48 */ + u32 RxDesc0CfgFifo10[2]; /* 0x00008e50 */ + u32 RxDesc0CfgFifo11[2]; /* 0x00008e58 */ + u32 RxDesc0CfgFifo12[2]; /* 0x00008e60 */ + u32 RxDesc0CfgFifo13[2]; /* 0x00008e68 */ + u32 RxDesc0CfgFifo14[2]; /* 0x00008e70 */ + u32 RxDesc0CfgFifo15[2]; /* 0x00008e78 */ + u32 RxDesc0CfgFifo16[2]; /* 0x00008e80 */ + u32 RxDesc0CfgFifo17[2]; /* 0x00008e88 */ + u32 RxDesc0CfgFifo18[2]; /* 0x00008e90 */ + u32 RxDesc0CfgFifo19[2]; /* 0x00008e98 */ + u32 RxDesc0CfgFifo20[2]; /* 0x00008ea0 */ + u32 RxDesc0CfgFifo21[2]; /* 0x00008ea8 */ + u32 RxDesc0CfgFifo22[2]; /* 0x00008eb0 */ + u32 RxDesc0CfgFifo23[2]; /* 0x00008eb8 */ + u32 RxDesc0CfgFifo24[2]; /* 0x00008ec0 */ + u32 RxDesc0CfgFifo25[2]; /* 0x00008ec8 */ + u32 RxDesc0CfgFifo26[2]; /* 0x00008ed0 */ + u32 RxDesc0CfgFifo27[2]; /* 0x00008ed8 */ + u32 RxDesc0CfgFifo28[2]; /* 0x00008ee0 */ + u32 RxDesc0CfgFifo29[2]; /* 0x00008ee8 */ + u32 RxDesc0CfgFifo30[2]; /* 0x00008ef0 */ + u32 RxDesc0CfgFifo31[2]; /* 0x00008ef8 */ + u32 RxDesc0CfgFifo32[2]; /* 0x00008f00 */ + u32 RxDesc0CfgFifo33[2]; /* 0x00008f08 */ + u32 RxDesc0CfgFifo34[2]; /* 0x00008f10 */ + u32 RxDesc0CfgFifo35[2]; /* 0x00008f18 */ + u32 RxDesc0CfgFifo36[2]; /* 0x00008f20 */ + u32 RxDesc0CfgFifo37[2]; /* 0x00008f28 */ + u32 RxDesc0CfgFifo38[2]; /* 0x00008f30 */ + u32 RxDesc0CfgFifo39[2]; /* 0x00008f38 */ + u32 RxDesc0CfgFifo40[2]; /* 0x00008f40 */ + u32 RxDesc0CfgFifo41[2]; /* 0x00008f48 */ + u32 RxDesc0CfgFifo42[2]; /* 0x00008f50 */ + u32 RxDesc0CfgFifo43[2]; /* 0x00008f58 */ + u32 RxDesc0CfgFifo44[2]; /* 0x00008f60 */ + u32 RxDesc0CfgFifo45[2]; /* 0x00008f68 */ + u32 RxDesc0CfgFifo46[2]; /* 0x00008f70 */ + u32 RxDesc0CfgFifo47[2]; /* 0x00008f78 */ + u32 RxDesc0CfgFifo48[2]; /* 0x00008f80 */ + u32 RxDesc0CfgFifo49[2]; /* 0x00008f88 */ + u32 RxDesc0CfgFifo50[2]; /* 0x00008f90 */ + u32 RxDesc0CfgFifo51[2]; /* 0x00008f98 */ + u32 RxDesc0CfgFifo52[2]; /* 0x00008fa0 */ + u32 RxDesc0CfgFifo53[2]; /* 0x00008fa8 */ + u32 RxDesc0CfgFifo54[2]; /* 0x00008fb0 */ + u32 RxDesc0CfgFifo55[2]; /* 0x00008fb8 */ + u32 RxDesc0CfgFifo56[2]; /* 0x00008fc0 */ + u32 RxDesc0CfgFifo57[2]; /* 0x00008fc8 */ + u32 RxDesc0CfgFifo58[2]; /* 0x00008fd0 */ + u32 RxDesc0CfgFifo59[2]; /* 0x00008fd8 */ + u32 RxDesc0CfgFifo60[2]; /* 0x00008fe0 */ + u32 RxDesc0CfgFifo61[2]; /* 0x00008fe8 */ + u32 RxDesc0CfgFifo62[2]; /* 0x00008ff0 */ + u32 RxDesc0CfgFifo63[2]; /* 0x00008ff8 */ + u32 RxDesc1CfgFifo0[2]; /* 0x00009000 */ + u32 RxDesc1CfgFifo1[2]; /* 0x00009008 */ + u32 RxDesc1CfgFifo2[2]; /* 0x00009010 */ + u32 RxDesc1CfgFifo3[2]; /* 0x00009018 */ + u32 RxDesc1CfgFifo4[2]; /* 0x00009020 */ + u32 RxDesc1CfgFifo5[2]; /* 0x00009028 */ + u32 RxDesc1CfgFifo6[2]; /* 0x00009030 */ + u32 RxDesc1CfgFifo7[2]; /* 0x00009038 */ + u32 RxDesc1CfgFifo8[2]; /* 0x00009040 */ + u32 RxDesc1CfgFifo9[2]; /* 0x00009048 */ + u32 RxDesc1CfgFifo10[2]; /* 0x00009050 */ + u32 RxDesc1CfgFifo11[2]; /* 0x00009058 */ + u32 RxDesc1CfgFifo12[2]; /* 0x00009060 */ + u32 RxDesc1CfgFifo13[2]; /* 0x00009068 */ + u32 RxDesc1CfgFifo14[2]; /* 0x00009070 */ + u32 RxDesc1CfgFifo15[2]; /* 0x00009078 */ + u32 RxDesc1CfgFifo16[2]; /* 0x00009080 */ + u32 RxDesc1CfgFifo17[2]; /* 0x00009088 */ + u32 RxDesc1CfgFifo18[2]; /* 0x00009090 */ + u32 RxDesc1CfgFifo19[2]; /* 0x00009098 */ + u32 RxDesc1CfgFifo20[2]; /* 0x000090a0 */ + u32 RxDesc1CfgFifo21[2]; /* 0x000090a8 */ + u32 RxDesc1CfgFifo22[2]; /* 0x000090b0 */ + u32 RxDesc1CfgFifo23[2]; /* 0x000090b8 */ + u32 RxDesc1CfgFifo24[2]; /* 0x000090c0 */ + u32 RxDesc1CfgFifo25[2]; /* 0x000090c8 */ + u32 RxDesc1CfgFifo26[2]; /* 0x000090d0 */ + u32 RxDesc1CfgFifo27[2]; /* 0x000090d8 */ + u32 RxDesc1CfgFifo28[2]; /* 0x000090e0 */ + u32 RxDesc1CfgFifo29[2]; /* 0x000090e8 */ + u32 RxDesc1CfgFifo30[2]; /* 0x000090f0 */ + u32 RxDesc1CfgFifo31[2]; /* 0x000090f8 */ + u32 RxDesc1CfgFifo32[2]; /* 0x00009100 */ + u32 RxDesc1CfgFifo33[2]; /* 0x00009108 */ + u32 RxDesc1CfgFifo34[2]; /* 0x00009110 */ + u32 RxDesc1CfgFifo35[2]; /* 0x00009118 */ + u32 RxDesc1CfgFifo36[2]; /* 0x00009120 */ + u32 RxDesc1CfgFifo37[2]; /* 0x00009128 */ + u32 RxDesc1CfgFifo38[2]; /* 0x00009130 */ + u32 RxDesc1CfgFifo39[2]; /* 0x00009138 */ + u32 RxDesc1CfgFifo40[2]; /* 0x00009140 */ + u32 RxDesc1CfgFifo41[2]; /* 0x00009148 */ + u32 RxDesc1CfgFifo42[2]; /* 0x00009150 */ + u32 RxDesc1CfgFifo43[2]; /* 0x00009158 */ + u32 RxDesc1CfgFifo44[2]; /* 0x00009160 */ + u32 RxDesc1CfgFifo45[2]; /* 0x00009168 */ + u32 RxDesc1CfgFifo46[2]; /* 0x00009170 */ + u32 RxDesc1CfgFifo47[2]; /* 0x00009178 */ + u32 RxDesc1CfgFifo48[2]; /* 0x00009180 */ + u32 RxDesc1CfgFifo49[2]; /* 0x00009188 */ + u32 RxDesc1CfgFifo50[2]; /* 0x00009190 */ + u32 RxDesc1CfgFifo51[2]; /* 0x00009198 */ + u32 RxDesc1CfgFifo52[2]; /* 0x000091a0 */ + u32 RxDesc1CfgFifo53[2]; /* 0x000091a8 */ + u32 RxDesc1CfgFifo54[2]; /* 0x000091b0 */ + u32 RxDesc1CfgFifo55[2]; /* 0x000091b8 */ + u32 RxDesc1CfgFifo56[2]; /* 0x000091c0 */ + u32 RxDesc1CfgFifo57[2]; /* 0x000091c8 */ + u32 RxDesc1CfgFifo58[2]; /* 0x000091d0 */ + u32 RxDesc1CfgFifo59[2]; /* 0x000091d8 */ + u32 RxDesc1CfgFifo60[2]; /* 0x000091e0 */ + u32 RxDesc1CfgFifo61[2]; /* 0x000091e8 */ + u32 RxDesc1CfgFifo62[2]; /* 0x000091f0 */ + u32 RxDesc1CfgFifo63[2]; /* 0x000091f8 */ + u32 RxDesc0AckFifo0[1]; /* 0x00009200 */ + u32 RxDesc0AckFifo1[1]; /* 0x00009204 */ + u32 RxDesc0AckFifo2[1]; /* 0x00009208 */ + u32 RxDesc0AckFifo3[1]; /* 0x0000920c */ + u32 RxDesc0AckFifo4[1]; /* 0x00009210 */ + u32 RxDesc0AckFifo5[1]; /* 0x00009214 */ + u32 RxDesc0AckFifo6[1]; /* 0x00009218 */ + u32 RxDesc0AckFifo7[1]; /* 0x0000921c */ + u32 RxDesc0AckFifo8[1]; /* 0x00009220 */ + u32 RxDesc0AckFifo9[1]; /* 0x00009224 */ + u32 RxDesc0AckFifo10[1]; /* 0x00009228 */ + u32 RxDesc0AckFifo11[1]; /* 0x0000922c */ + u32 RxDesc0AckFifo12[1]; /* 0x00009230 */ + u32 RxDesc0AckFifo13[1]; /* 0x00009234 */ + u32 RxDesc0AckFifo14[1]; /* 0x00009238 */ + u32 RxDesc0AckFifo15[1]; /* 0x0000923c */ + u32 RxDesc0AckFifo16[1]; /* 0x00009240 */ + u32 RxDesc0AckFifo17[1]; /* 0x00009244 */ + u32 RxDesc0AckFifo18[1]; /* 0x00009248 */ + u32 RxDesc0AckFifo19[1]; /* 0x0000924c */ + u32 RxDesc0AckFifo20[1]; /* 0x00009250 */ + u32 RxDesc0AckFifo21[1]; /* 0x00009254 */ + u32 RxDesc0AckFifo22[1]; /* 0x00009258 */ + u32 RxDesc0AckFifo23[1]; /* 0x0000925c */ + u32 RxDesc0AckFifo24[1]; /* 0x00009260 */ + u32 RxDesc0AckFifo25[1]; /* 0x00009264 */ + u32 RxDesc0AckFifo26[1]; /* 0x00009268 */ + u32 RxDesc0AckFifo27[1]; /* 0x0000926c */ + u32 RxDesc0AckFifo28[1]; /* 0x00009270 */ + u32 RxDesc0AckFifo29[1]; /* 0x00009274 */ + u32 RxDesc0AckFifo30[1]; /* 0x00009278 */ + u32 RxDesc0AckFifo31[1]; /* 0x0000927c */ + u32 RxDesc0AckFifo32[1]; /* 0x00009280 */ + u32 RxDesc0AckFifo33[1]; /* 0x00009284 */ + u32 RxDesc0AckFifo34[1]; /* 0x00009288 */ + u32 RxDesc0AckFifo35[1]; /* 0x0000928c */ + u32 RxDesc0AckFifo36[1]; /* 0x00009290 */ + u32 RxDesc0AckFifo37[1]; /* 0x00009294 */ + u32 RxDesc0AckFifo38[1]; /* 0x00009298 */ + u32 RxDesc0AckFifo39[1]; /* 0x0000929c */ + u32 RxDesc0AckFifo40[1]; /* 0x000092a0 */ + u32 RxDesc0AckFifo41[1]; /* 0x000092a4 */ + u32 RxDesc0AckFifo42[1]; /* 0x000092a8 */ + u32 RxDesc0AckFifo43[1]; /* 0x000092ac */ + u32 RxDesc0AckFifo44[1]; /* 0x000092b0 */ + u32 RxDesc0AckFifo45[1]; /* 0x000092b4 */ + u32 RxDesc0AckFifo46[1]; /* 0x000092b8 */ + u32 RxDesc0AckFifo47[1]; /* 0x000092bc */ + u32 RxDesc0AckFifo48[1]; /* 0x000092c0 */ + u32 RxDesc0AckFifo49[1]; /* 0x000092c4 */ + u32 RxDesc0AckFifo50[1]; /* 0x000092c8 */ + u32 RxDesc0AckFifo51[1]; /* 0x000092cc */ + u32 RxDesc0AckFifo52[1]; /* 0x000092d0 */ + u32 RxDesc0AckFifo53[1]; /* 0x000092d4 */ + u32 RxDesc0AckFifo54[1]; /* 0x000092d8 */ + u32 RxDesc0AckFifo55[1]; /* 0x000092dc */ + u32 RxDesc0AckFifo56[1]; /* 0x000092e0 */ + u32 RxDesc0AckFifo57[1]; /* 0x000092e4 */ + u32 RxDesc0AckFifo58[1]; /* 0x000092e8 */ + u32 RxDesc0AckFifo59[1]; /* 0x000092ec */ + u32 RxDesc0AckFifo60[1]; /* 0x000092f0 */ + u32 RxDesc0AckFifo61[1]; /* 0x000092f4 */ + u32 RxDesc0AckFifo62[1]; /* 0x000092f8 */ + u32 RxDesc0AckFifo63[1]; /* 0x000092fc */ + u32 RxDesc1AckFifo0[1]; /* 0x00009300 */ + u32 RxDesc1AckFifo1[1]; /* 0x00009304 */ + u32 RxDesc1AckFifo2[1]; /* 0x00009308 */ + u32 RxDesc1AckFifo3[1]; /* 0x0000930c */ + u32 RxDesc1AckFifo4[1]; /* 0x00009310 */ + u32 RxDesc1AckFifo5[1]; /* 0x00009314 */ + u32 RxDesc1AckFifo6[1]; /* 0x00009318 */ + u32 RxDesc1AckFifo7[1]; /* 0x0000931c */ + u32 RxDesc1AckFifo8[1]; /* 0x00009320 */ + u32 RxDesc1AckFifo9[1]; /* 0x00009324 */ + u32 RxDesc1AckFifo10[1]; /* 0x00009328 */ + u32 RxDesc1AckFifo11[1]; /* 0x0000932c */ + u32 RxDesc1AckFifo12[1]; /* 0x00009330 */ + u32 RxDesc1AckFifo13[1]; /* 0x00009334 */ + u32 RxDesc1AckFifo14[1]; /* 0x00009338 */ + u32 RxDesc1AckFifo15[1]; /* 0x0000933c */ + u32 RxDesc1AckFifo16[1]; /* 0x00009340 */ + u32 RxDesc1AckFifo17[1]; /* 0x00009344 */ + u32 RxDesc1AckFifo18[1]; /* 0x00009348 */ + u32 RxDesc1AckFifo19[1]; /* 0x0000934c */ + u32 RxDesc1AckFifo20[1]; /* 0x00009350 */ + u32 RxDesc1AckFifo21[1]; /* 0x00009354 */ + u32 RxDesc1AckFifo22[1]; /* 0x00009358 */ + u32 RxDesc1AckFifo23[1]; /* 0x0000935c */ + u32 RxDesc1AckFifo24[1]; /* 0x00009360 */ + u32 RxDesc1AckFifo25[1]; /* 0x00009364 */ + u32 RxDesc1AckFifo26[1]; /* 0x00009368 */ + u32 RxDesc1AckFifo27[1]; /* 0x0000936c */ + u32 RxDesc1AckFifo28[1]; /* 0x00009370 */ + u32 RxDesc1AckFifo29[1]; /* 0x00009374 */ + u32 RxDesc1AckFifo30[1]; /* 0x00009378 */ + u32 RxDesc1AckFifo31[1]; /* 0x0000937c */ + u32 RxDesc1AckFifo32[1]; /* 0x00009380 */ + u32 RxDesc1AckFifo33[1]; /* 0x00009384 */ + u32 RxDesc1AckFifo34[1]; /* 0x00009388 */ + u32 RxDesc1AckFifo35[1]; /* 0x0000938c */ + u32 RxDesc1AckFifo36[1]; /* 0x00009390 */ + u32 RxDesc1AckFifo37[1]; /* 0x00009394 */ + u32 RxDesc1AckFifo38[1]; /* 0x00009398 */ + u32 RxDesc1AckFifo39[1]; /* 0x0000939c */ + u32 RxDesc1AckFifo40[1]; /* 0x000093a0 */ + u32 RxDesc1AckFifo41[1]; /* 0x000093a4 */ + u32 RxDesc1AckFifo42[1]; /* 0x000093a8 */ + u32 RxDesc1AckFifo43[1]; /* 0x000093ac */ + u32 RxDesc1AckFifo44[1]; /* 0x000093b0 */ + u32 RxDesc1AckFifo45[1]; /* 0x000093b4 */ + u32 RxDesc1AckFifo46[1]; /* 0x000093b8 */ + u32 RxDesc1AckFifo47[1]; /* 0x000093bc */ + u32 RxDesc1AckFifo48[1]; /* 0x000093c0 */ + u32 RxDesc1AckFifo49[1]; /* 0x000093c4 */ + u32 RxDesc1AckFifo50[1]; /* 0x000093c8 */ + u32 RxDesc1AckFifo51[1]; /* 0x000093cc */ + u32 RxDesc1AckFifo52[1]; /* 0x000093d0 */ + u32 RxDesc1AckFifo53[1]; /* 0x000093d4 */ + u32 RxDesc1AckFifo54[1]; /* 0x000093d8 */ + u32 RxDesc1AckFifo55[1]; /* 0x000093dc */ + u32 RxDesc1AckFifo56[1]; /* 0x000093e0 */ + u32 RxDesc1AckFifo57[1]; /* 0x000093e4 */ + u32 RxDesc1AckFifo58[1]; /* 0x000093e8 */ + u32 RxDesc1AckFifo59[1]; /* 0x000093ec */ + u32 RxDesc1AckFifo60[1]; /* 0x000093f0 */ + u32 RxDesc1AckFifo61[1]; /* 0x000093f4 */ + u32 RxDesc1AckFifo62[1]; /* 0x000093f8 */ + u32 RxDesc1AckFifo63[1]; /* 0x000093fc */ + u32 TxDescAckFifo0[1]; /* 0x00009400 */ + u32 TxDescAckFifo1[1]; /* 0x00009404 */ + u32 TxDescAckFifo2[1]; /* 0x00009408 */ + u32 TxDescAckFifo3[1]; /* 0x0000940c */ + u32 TxDescAckFifo4[1]; /* 0x00009410 */ + u32 TxDescAckFifo5[1]; /* 0x00009414 */ + u32 TxDescAckFifo6[1]; /* 0x00009418 */ + u32 TxDescAckFifo7[1]; /* 0x0000941c */ + u32 TxDescAckFifo8[1]; /* 0x00009420 */ + u32 TxDescAckFifo9[1]; /* 0x00009424 */ + u32 TxDescAckFifo10[1]; /* 0x00009428 */ + u32 TxDescAckFifo11[1]; /* 0x0000942c */ + u32 TxDescAckFifo12[1]; /* 0x00009430 */ + u32 TxDescAckFifo13[1]; /* 0x00009434 */ + u32 TxDescAckFifo14[1]; /* 0x00009438 */ + u32 TxDescAckFifo15[1]; /* 0x0000943c */ + u32 TxDescAckFifo16[1]; /* 0x00009440 */ + u32 TxDescAckFifo17[1]; /* 0x00009444 */ + u32 TxDescAckFifo18[1]; /* 0x00009448 */ + u32 TxDescAckFifo19[1]; /* 0x0000944c */ + u32 TxDescAckFifo20[1]; /* 0x00009450 */ + u32 TxDescAckFifo21[1]; /* 0x00009454 */ + u32 TxDescAckFifo22[1]; /* 0x00009458 */ + u32 TxDescAckFifo23[1]; /* 0x0000945c */ + u32 TxDescAckFifo24[1]; /* 0x00009460 */ + u32 TxDescAckFifo25[1]; /* 0x00009464 */ + u32 TxDescAckFifo26[1]; /* 0x00009468 */ + u32 TxDescAckFifo27[1]; /* 0x0000946c */ + u32 TxDescAckFifo28[1]; /* 0x00009470 */ + u32 TxDescAckFifo29[1]; /* 0x00009474 */ + u32 TxDescAckFifo30[1]; /* 0x00009478 */ + u32 TxDescAckFifo31[1]; /* 0x0000947c */ + u32 TxDescAckFifo32[1]; /* 0x00009480 */ + u32 TxDescAckFifo33[1]; /* 0x00009484 */ + u32 TxDescAckFifo34[1]; /* 0x00009488 */ + u32 TxDescAckFifo35[1]; /* 0x0000948c */ + u32 TxDescAckFifo36[1]; /* 0x00009490 */ + u32 TxDescAckFifo37[1]; /* 0x00009494 */ + u32 TxDescAckFifo38[1]; /* 0x00009498 */ + u32 TxDescAckFifo39[1]; /* 0x0000949c */ + u32 TxDescAckFifo40[1]; /* 0x000094a0 */ + u32 TxDescAckFifo41[1]; /* 0x000094a4 */ + u32 TxDescAckFifo42[1]; /* 0x000094a8 */ + u32 TxDescAckFifo43[1]; /* 0x000094ac */ + u32 TxDescAckFifo44[1]; /* 0x000094b0 */ + u32 TxDescAckFifo45[1]; /* 0x000094b4 */ + u32 TxDescAckFifo46[1]; /* 0x000094b8 */ + u32 TxDescAckFifo47[1]; /* 0x000094bc */ + u32 TxDescAckFifo48[1]; /* 0x000094c0 */ + u32 TxDescAckFifo49[1]; /* 0x000094c4 */ + u32 TxDescAckFifo50[1]; /* 0x000094c8 */ + u32 TxDescAckFifo51[1]; /* 0x000094cc */ + u32 TxDescAckFifo52[1]; /* 0x000094d0 */ + u32 TxDescAckFifo53[1]; /* 0x000094d4 */ + u32 TxDescAckFifo54[1]; /* 0x000094d8 */ + u32 TxDescAckFifo55[1]; /* 0x000094dc */ + u32 TxDescAckFifo56[1]; /* 0x000094e0 */ + u32 TxDescAckFifo57[1]; /* 0x000094e4 */ + u32 TxDescAckFifo58[1]; /* 0x000094e8 */ + u32 TxDescAckFifo59[1]; /* 0x000094ec */ + u32 TxDescAckFifo60[1]; /* 0x000094f0 */ + u32 TxDescAckFifo61[1]; /* 0x000094f4 */ + u32 TxDescAckFifo62[1]; /* 0x000094f8 */ + u32 TxDescAckFifo63[1]; /* 0x000094fc */ + u32 CpuMacDescIntf0[2]; /* 0x00009500 */ + u32 CpuMacDescIntf1[2]; /* 0x00009508 */ + u32 CpuMacDescIntf2[2]; /* 0x00009510 */ }; -/* tx_pkt_fifo Definition */ -#define TX_PKT_FIFO_W0_TX_PKT_FIFO_FIELD0 BIT(0) -#define TX_PKT_FIFO_W1_TX_PKT_FIFO_FIELD1 BIT(0) -#define TX_PKT_FIFO_W2_TX_PKT_FIFO_FIELD2 BIT(0) +/* ################################################################################ + * # TxPktFifo Definition */ +#define TX_PKT_FIFO_W0_TX_PKT_FIFO_FIELD0_BIT 0 +#define TX_PKT_FIFO_W1_TX_PKT_FIFO_FIELD1_BIT 0 +#define TX_PKT_FIFO_W2_TX_PKT_FIFO_FIELD2_BIT 0 #define TX_PKT_FIFO_W0_TX_PKT_FIFO_FIELD0_MASK 0xffffffff #define TX_PKT_FIFO_W1_TX_PKT_FIFO_FIELD1_MASK 0xffffffff #define TX_PKT_FIFO_W2_TX_PKT_FIFO_FIELD2_MASK 0x0000000f -/* rx_pkt_msg_fifo Definition */ -#define RX_PKT_MSG_FIFO_W0_RX_PKT_MSG_FIFO_FIELD BIT(0) +/* ################################################################################ + * # RxPktMsgFifo Definition */ +#define RX_PKT_MSG_FIFO_W0_RX_PKT_MSG_FIFO_FIELD_BIT 0 #define RX_PKT_MSG_FIFO_W0_RX_PKT_MSG_FIFO_FIELD_MASK 0x0000ffff -/* cpu_mac_stats_ram Definition */ -#define CPU_MAC_STATS_RAM_W0_BYTE_CNT_31_0 BIT(0) -#define CPU_MAC_STATS_RAM_W1_BYTE_CNT_39_32 BIT(0) -#define CPU_MAC_STATS_RAM_W2_FRAME_CNT_31_0 BIT(0) -#define CPU_MAC_STATS_RAM_W3_FRAME_CNT_33_32 BIT(0) +/* ################################################################################ + * # CpuMacStatsRam Definition */ +#define CPU_MAC_STATS_RAM_W0_BYTE_CNT_31_0_BIT 0 +#define CPU_MAC_STATS_RAM_W1_BYTE_CNT_39_32_BIT 0 +#define CPU_MAC_STATS_RAM_W2_FRAME_CNT_31_0_BIT 0 +#define CPU_MAC_STATS_RAM_W3_FRAME_CNT_33_32_BIT 0 #define CPU_MAC_STATS_RAM_W0_BYTE_CNT_31_0_MASK 0xffffffff #define CPU_MAC_STATS_RAM_W1_BYTE_CNT_39_32_MASK 0x000000ff #define CPU_MAC_STATS_RAM_W2_FRAME_CNT_31_0_MASK 0xffffffff #define CPU_MAC_STATS_RAM_W3_FRAME_CNT_33_32_MASK 0x00000003 -/* tx_desc_cfg_fifo Definition */ -#define TX_DESC_CFG_FIFO_W0_TX_DESC_CFG_FIFO_FIELD0 BIT(0) -#define TX_DESC_CFG_FIFO_W1_TX_DESC_CFG_FIFO_FIELD1 BIT(0) +/* ################################################################################ + * # TxDescCfgFifo Definition */ +#define TX_DESC_CFG_FIFO_W0_TX_DESC_CFG_FIFO_FIELD0_BIT 0 +#define TX_DESC_CFG_FIFO_W1_TX_DESC_CFG_FIFO_FIELD1_BIT 0 #define TX_DESC_CFG_FIFO_W0_TX_DESC_CFG_FIFO_FIELD0_MASK 0xffffffff #define TX_DESC_CFG_FIFO_W1_TX_DESC_CFG_FIFO_FIELD1_MASK 0x01ffffff -/* rx_desc_0_cfg_fifo Definition */ -#define RX_DESC0_CFG_FIFO_W0_RX_DESC0_CFG_FIFO_FIELD0 BIT(0) -#define RX_DESC0_CFG_FIFO_W1_RX_DESC0_CFG_FIFO_FIELD1 BIT(0) +/* ################################################################################ + * # RxDesc0CfgFifo Definition */ +#define RX_DESC0_CFG_FIFO_W0_RX_DESC0_CFG_FIFO_FIELD0_BIT 0 +#define RX_DESC0_CFG_FIFO_W1_RX_DESC0_CFG_FIFO_FIELD1_BIT 0 #define RX_DESC0_CFG_FIFO_W0_RX_DESC0_CFG_FIFO_FIELD0_MASK 0xffffffff #define RX_DESC0_CFG_FIFO_W1_RX_DESC0_CFG_FIFO_FIELD1_MASK 0x01ffffff -/* rx_desc_1_cfg_fifo Definition */ -#define RX_DESC1_CFG_FIFO_W0_RX_DESC1_CFG_FIFO_FIELD0 BIT(0) -#define RX_DESC1_CFG_FIFO_W1_RX_DESC1_CFG_FIFO_FIELD1 BIT(0) +/* ################################################################################ + * # RxDesc1CfgFifo Definition */ +#define RX_DESC1_CFG_FIFO_W0_RX_DESC1_CFG_FIFO_FIELD0_BIT 0 +#define RX_DESC1_CFG_FIFO_W1_RX_DESC1_CFG_FIFO_FIELD1_BIT 0 #define RX_DESC1_CFG_FIFO_W0_RX_DESC1_CFG_FIFO_FIELD0_MASK 0xffffffff #define RX_DESC1_CFG_FIFO_W1_RX_DESC1_CFG_FIFO_FIELD1_MASK 0x01ffffff -/* rx_desc_0_ack_fifo Definition */ -#define RX_DESC0_ACK_FIFO_W0_RX_DESC0_ACK_FIFO_FIELD BIT(0) +/* ################################################################################ + * # RxDesc0AckFifo Definition */ +#define RX_DESC0_ACK_FIFO_W0_RX_DESC0_ACK_FIFO_FIELD_BIT 0 #define RX_DESC0_ACK_FIFO_W0_RX_DESC0_ACK_FIFO_FIELD_MASK 0x0007ffff -/* rx_desc_1_ack_fifo Definition */ -#define RX_DESC1_ACK_FIFO_W0_RX_DESC1_ACK_FIFO_FIELD BIT(0) +/* ################################################################################ + * # RxDesc1AckFifo Definition */ +#define RX_DESC1_ACK_FIFO_W0_RX_DESC1_ACK_FIFO_FIELD_BIT 0 #define RX_DESC1_ACK_FIFO_W0_RX_DESC1_ACK_FIFO_FIELD_MASK 0x0007ffff -/* tx_desc_ack_fifo Definition */ -#define TX_DESC_ACK_FIFO_W0_TX_DESC_ACK_FIFO_FIELD BIT(0) +/* ################################################################################ + * # TxDescAckFifo Definition */ +#define TX_DESC_ACK_FIFO_W0_TX_DESC_ACK_FIFO_FIELD_BIT 0 #define TX_DESC_ACK_FIFO_W0_TX_DESC_ACK_FIFO_FIELD_MASK 0x00000001 -/* cpu_mac_desc_intf Definition */ -#define CPU_MAC_DESC_INTF_W0_DESC_ADDR_31_0 BIT(0) -#define CPU_MAC_DESC_INTF_W1_DESC_ADDR_39_32 BIT(0) -#define CPU_MAC_DESC_INTF_W1_DESC_SIZE BIT(8) -#define CPU_MAC_DESC_INTF_W1_DESC_SOP BIT(22) -#define CPU_MAC_DESC_INTF_W1_DESC_ERR_TYPE BIT(25) -#define CPU_MAC_DESC_INTF_W1_DESC_EOP BIT(23) -#define CPU_MAC_DESC_INTF_W1_DESC_ERR BIT(24) +/* ################################################################################ + * # CpuMacDescIntf Definition */ +#define CPU_MAC_DESC_INTF_W0_DESC_ADDR_31_0_BIT 0 +#define CPU_MAC_DESC_INTF_W1_DESC_ADDR_39_32_BIT 0 +#define CPU_MAC_DESC_INTF_W1_DESC_EOP_BIT 23 +#define CPU_MAC_DESC_INTF_W1_DESC_ERR_BIT 24 +#define CPU_MAC_DESC_INTF_W1_DESC_ERR_TYPE_BIT 25 +#define CPU_MAC_DESC_INTF_W1_DESC_SIZE_BIT 8 +#define CPU_MAC_DESC_INTF_W1_DESC_SOP_BIT 22 #define CPU_MAC_DESC_INTF_W0_DESC_ADDR_31_0_MASK 0xffffffff #define CPU_MAC_DESC_INTF_W1_DESC_ADDR_39_32_MASK 0x000000ff -#define CPU_MAC_DESC_INTF_W1_DESC_SIZE_MASK 0x003fff00 -#define CPU_MAC_DESC_INTF_W1_DESC_SOP_MASK 0x00400000 -#define CPU_MAC_DESC_INTF_W1_DESC_ERR_TYPE_MASK 0x0e000000 #define CPU_MAC_DESC_INTF_W1_DESC_EOP_MASK 0x00800000 #define CPU_MAC_DESC_INTF_W1_DESC_ERR_MASK 0x01000000 - -/* defing MDIOSOC_REG_BASE 0x00000000 */ - -struct mdio_soc_regs { - u32 mdio_soc_cmd_0[2]; /* 0x00000000 */ - u32 mdio_soc_cmd_1[2]; /* 0x00000008 */ - u32 mdio_soc_status_1; /* 0x00000010 */ - u32 mdio_soc_status_0; /* 0x00000014 */ - u32 mdio_soc_reserved; /* 0x00000018 */ - u32 mdio_soc_cfg_0; /* 0x0000001c */ - u32 mdio_soc_cfg_1; /* 0x00000020 */ -}; - -/* mdio_soc_cmd_0 Definition */ -#define MDIO_SOC_CMD0_W0_OP_CODE_CMD_LANE0 BIT(26) -#define MDIO_SOC_CMD0_W0_REG_ADD_CMD_LANE0 BIT(16) -#define MDIO_SOC_CMD0_W0_DATA_CMD_LANE0 BIT(0) -#define MDIO_SOC_CMD0_W0_PHY_ADD_CMD_LANE0 BIT(21) -#define MDIO_SOC_CMD0_W1_START_CMD_LANE0 BIT(0) - -#define MDIO_SOC_CMD0_W0_OP_CODE_CMD_LANE0_MASK 0x0c000000 -#define MDIO_SOC_CMD0_W0_REG_ADD_CMD_LANE0_MASK 0x001f0000 -#define MDIO_SOC_CMD0_W0_DATA_CMD_LANE0_MASK 0x0000ffff -#define MDIO_SOC_CMD0_W0_PHY_ADD_CMD_LANE0_MASK 0x03e00000 -#define MDIO_SOC_CMD0_W1_START_CMD_LANE0_MASK 0x00000003 - -/* mdio_soc_cmd_1 Definition */ -#define MDIO_SOC_CMD1_W0_PHY_ADD_CMD_LANE1 BIT(21) -#define MDIO_SOC_CMD1_W0_OP_CODE_CMD_LANE1 BIT(26) -#define MDIO_SOC_CMD1_W0_DATA_CMD_LANE1 BIT(0) -#define MDIO_SOC_CMD1_W0_REG_ADD_CMD_LANE1 BIT(16) -#define MDIO_SOC_CMD1_W1_START_CMD_LANE1 BIT(0) - -#define MDIO_SOC_CMD1_W0_PHY_ADD_CMD_LANE1_MASK 0x03e00000 -#define MDIO_SOC_CMD1_W0_OP_CODE_CMD_LANE1_MASK 0x0c000000 -#define MDIO_SOC_CMD1_W0_DATA_CMD_LANE1_MASK 0x0000ffff -#define MDIO_SOC_CMD1_W0_REG_ADD_CMD_LANE1_MASK 0x001f0000 -#define MDIO_SOC_CMD1_W1_START_CMD_LANE1_MASK 0x00000003 - -/* mdio_soc_status_1 Definition */ -#define MDIO_SOC_STATUS1_W0_MDIO_CMD_DONE_LANE1 BIT(16) -#define MDIO_SOC_STATUS1_W0_MDIO_READ_DATA_LANE1 BIT(0) - -#define MDIO_SOC_STATUS1_W0_MDIO_CMD_DONE_LANE1_MASK 0x00010000 -#define MDIO_SOC_STATUS1_W0_MDIO_READ_DATA_LANE1_MASK 0x0000ffff - -/* mdio_soc_status_0 Definition */ -#define MDIO_SOC_STATUS0_W0_MDIO_CMD_DONE_LANE0 BIT(16) -#define MDIO_SOC_STATUS0_W0_MDIO_READ_DATA_LANE0 BIT(0) - -#define MDIO_SOC_STATUS0_W0_MDIO_CMD_DONE_LANE0_MASK 0x00010000 -#define MDIO_SOC_STATUS0_W0_MDIO_READ_DATA_LANE0_MASK 0x0000ffff - -/* mdio_soc_reserved Definition */ -#define MDIO_SOC_RESERVED_W0_RESERVED BIT(0) - -#define MDIO_SOC_RESERVED_W0_RESERVED_MASK 0x0000ffff - -/* mdio_soc_cfg_0 Definition */ -#define MDIO_SOC_CFG0_W0_MDIO_MAC_PRE_LANE0 BIT(0) -#define MDIO_SOC_CFG0_W0_MDIO_IN_DLY_LANE0 BIT(8) - -#define MDIO_SOC_CFG0_W0_MDIO_MAC_PRE_LANE0_MASK 0x0000003f -#define MDIO_SOC_CFG0_W0_MDIO_IN_DLY_LANE0_MASK 0x00000f00 - -/* mdio_soc_cfg_1 Definition */ -#define MDIO_SOC_CFG1_W0_MDIO_IN_DLY_LANE1 BIT(8) -#define MDIO_SOC_CFG1_W0_MDIO_MAC_PRE_LANE1 BIT(0) - -#define MDIO_SOC_CFG1_W0_MDIO_IN_DLY_LANE1_MASK 0x00000f00 -#define MDIO_SOC_CFG1_W0_MDIO_MAC_PRE_LANE1_MASK 0x0000003f +#define CPU_MAC_DESC_INTF_W1_DESC_ERR_TYPE_MASK 0x0e000000 +#define CPU_MAC_DESC_INTF_W1_DESC_SIZE_MASK 0x003fff00 +#define CPU_MAC_DESC_INTF_W1_DESC_SOP_MASK 0x00400000 #define CPUMACUNIT_MEM_BASE 0x00000400 #define CPUMACUNIT_REG_BASE 0x00000040 -struct cpu_mac_unit_regs { - u32 cpu_mac_unit_hss_mon[7]; /* 0x00000040 */ +struct CpuMacUnit_regs { + u32 CpuMacUnitHssMon[7]; /* 0x00000040 */ u32 rsv23; - u32 cpu_mac_hss_reg_acc_timing_cfg[2]; /* 0x00000060 */ - u32 cpu_mac_unit_reset_ctl; /* 0x00000068 */ - u32 cpu_mac_unit_hss_reg_acc_ctl; /* 0x0000006c */ - u32 cpu_mac_unit_hss_reg_acc_result; /* 0x00000070 */ - u32 cpu_mac_unit_axi_cfg; /* 0x00000074 */ - u32 cpu_mac_unit_ts_cfg; /* 0x00000078 */ - u32 cpu_mac_unit_fifo_status; /* 0x0000007c */ - u32 cpu_mac_unit_ts_mon[3]; /* 0x00000080 */ + u32 CpuMacHssRegAccTimingCfg[2]; /* 0x00000060 */ + u32 CpuMacUnitResetCtl; /* 0x00000068 */ + u32 CpuMacUnitHssRegAccCtl; /* 0x0000006c */ + u32 CpuMacUnitHssRegAccResult; /* 0x00000070 */ + u32 CpuMacUnitAxiCfg; /* 0x00000074 */ + u32 CpuMacUnitTsCfg; /* 0x00000078 */ + u32 CpuMacUnitFifoStatus; /* 0x0000007c */ + u32 CpuMacUnitTsMon[3]; /* 0x00000080 */ u32 rsv35; - u32 cpu_mac_unit_ref_pulse_cfg[4]; /* 0x00000090 */ - u32 cpu_mac_unit_interrupt_func[4]; /* 0x000000a0 */ + u32 CpuMacUnitRefPulseCfg[4]; /* 0x00000090 */ + u32 CpuMacUnitInterruptFunc[4]; /* 0x000000a0 */ u32 rsv44; u32 rsv45; u32 rsv46; u32 rsv47; - u32 cpu_mac_unit_hss_cfg[12]; /* 0x000000c0 */ - u32 rsv60; - u32 rsv61; + u32 CpuMacUnitHssCfg[14]; /* 0x000000c0 */ u32 rsv62; u32 rsv63; - u32 cpu_mac_unit_ip_cam_cfg[32]; /* 0x00000100 */ - u32 cpu_mac_unit_mac_cam_cfg[32]; /* 0x00000180 */ - u32 cpu_mac_unit_filter_cfg[6]; /* 0x00000200 */ + u32 CpuMacUnitIpCamCfg[32]; /* 0x00000100 */ + u32 CpuMacUnitMacCamCfg[32]; /* 0x00000180 */ + u32 CpuMacUnitFilterCfg[6]; /* 0x00000200 */ + u32 rsv134; + u32 rsv135; + u32 CpuMacUnitFilterCfg1[4]; /* 0x00000220 */ }; -/* cpu_mac_unit_hss_mon Definition */ -#define CPU_MAC_UNIT_HSS_MON_W0_MON_HSS_CMU0_DBG_OBS BIT(0) -#define CPU_MAC_UNIT_HSS_MON_W0_MON_HSS_CMU0_LOL BIT(16) -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_PMA2_PCS_TX_DET_RX_N BIT(22) -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_PMA2_PCS_TX_DET_RX_P BIT(23) -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_LOL_UDL BIT(20) -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_RX_EI BIT(18) -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_DBG_OBS BIT(0) -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_PMA_RST_DONE BIT(17) -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_I_SCAN_DONE BIT(21) -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_RX_EI_FILTERED BIT(24) -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_LOL BIT(19) -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_DFE_RST_DONE BIT(16) -#define CPU_MAC_UNIT_HSS_MON_W2_MON_HSS_L0_I_SCAN_RESULTS_31_0 BIT(0) -#define CPU_MAC_UNIT_HSS_MON_W3_MON_HSS_L0_I_SCAN_RESULTS_63_32 BIT(0) -#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_PMA2_PCS_TX_DET_RX_P BIT(23) -#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_RX_EI_FILTERED BIT(24) -#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_I_SCAN_DONE BIT(21) -#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_PMA2_PCS_TX_DET_RX_N BIT(22) -#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_LOL BIT(19) -#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_DFE_RST_DONE BIT(16) -#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_LOL_UDL BIT(20) -#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_PMA_RST_DONE BIT(17) -#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_RX_EI BIT(18) -#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_DBG_OBS BIT(0) -#define CPU_MAC_UNIT_HSS_MON_W5_MON_HSS_L1_I_SCAN_RESULTS_31_0 BIT(0) -#define CPU_MAC_UNIT_HSS_MON_W6_MON_HSS_L1_I_SCAN_RESULTS_63_32 BIT(0) +/* ################################################################################ + * # CpuMacUnitHssMon Definition */ +#define CPU_MAC_UNIT_HSS_MON_W0_MON_HSS_CMU0_DBG_OBS_BIT 0 +#define CPU_MAC_UNIT_HSS_MON_W0_MON_HSS_CMU0_LOL_BIT 16 +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_DBG_OBS_BIT 0 +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_DFE_RST_DONE_BIT 16 +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_I_SCAN_DONE_BIT 21 +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_LOL_BIT 19 +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_LOL_UDL_BIT 20 +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_PMA2_PCS_TX_DET_RX_N_BIT 22 +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_PMA2_PCS_TX_DET_RX_P_BIT 23 +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_PMA_RST_DONE_BIT 17 +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_RX_EI_BIT 18 +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_RX_EI_FILTERED_BIT 24 +#define CPU_MAC_UNIT_HSS_MON_W2_MON_HSS_L0_I_SCAN_RESULTS_31_0_BIT 0 +#define CPU_MAC_UNIT_HSS_MON_W3_MON_HSS_L0_I_SCAN_RESULTS_63_32_BIT 0 +#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_DBG_OBS_BIT 0 +#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_DFE_RST_DONE_BIT 16 +#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_I_SCAN_DONE_BIT 21 +#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_LOL_BIT 19 +#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_LOL_UDL_BIT 20 +#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_PMA2_PCS_TX_DET_RX_N_BIT 22 +#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_PMA2_PCS_TX_DET_RX_P_BIT 23 +#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_PMA_RST_DONE_BIT 17 +#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_RX_EI_BIT 18 +#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_RX_EI_FILTERED_BIT 24 +#define CPU_MAC_UNIT_HSS_MON_W5_MON_HSS_L1_I_SCAN_RESULTS_31_0_BIT 0 +#define CPU_MAC_UNIT_HSS_MON_W6_MON_HSS_L1_I_SCAN_RESULTS_63_32_BIT 0 #define CPU_MAC_UNIT_HSS_MON_W0_MON_HSS_CMU0_DBG_OBS_MASK 0x0000ffff #define CPU_MAC_UNIT_HSS_MON_W0_MON_HSS_CMU0_LOL_MASK 0x00010000 +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_DBG_OBS_MASK 0x0000ffff +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_DFE_RST_DONE_MASK 0x00010000 +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_I_SCAN_DONE_MASK 0x00200000 +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_LOL_MASK 0x00080000 +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_LOL_UDL_MASK 0x00100000 #define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_PMA2_PCS_TX_DET_RX_N_MASK 0x00400000 #define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_PMA2_PCS_TX_DET_RX_P_MASK 0x00800000 -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_LOL_UDL_MASK 0x00100000 -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_RX_EI_MASK 0x00040000 -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_DBG_OBS_MASK 0x0000ffff #define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_PMA_RST_DONE_MASK 0x00020000 -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_I_SCAN_DONE_MASK 0x00200000 +#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_RX_EI_MASK 0x00040000 #define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_RX_EI_FILTERED_MASK 0x01000000 -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_LOL_MASK 0x00080000 -#define CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_DFE_RST_DONE_MASK 0x00010000 -#define CPU_MAC_UNIT_HSS_MON_W2_MON_HSS_L0_I_SCAN_RESULTS_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_HSS_MON_W3_MON_HSS_L0_I_SCAN_RESULTS_63_32_MASK 0x00000001 -#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_PMA2_PCS_TX_DET_RX_P_MASK 0x00800000 -#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_RX_EI_FILTERED_MASK 0x01000000 +#define CPU_MAC_UNIT_HSS_MON_W2_MON_HSS_L0_I_SCAN_RESULTS_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_HSS_MON_W3_MON_HSS_L0_I_SCAN_RESULTS_63_32_MASK 0xffffffff +#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_DBG_OBS_MASK 0x0000ffff +#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_DFE_RST_DONE_MASK 0x00010000 #define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_I_SCAN_DONE_MASK 0x00200000 -#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_PMA2_PCS_TX_DET_RX_N_MASK 0x00400000 #define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_LOL_MASK 0x00080000 -#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_DFE_RST_DONE_MASK 0x00010000 #define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_LOL_UDL_MASK 0x00100000 +#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_PMA2_PCS_TX_DET_RX_N_MASK 0x00400000 +#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_PMA2_PCS_TX_DET_RX_P_MASK 0x00800000 #define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_PMA_RST_DONE_MASK 0x00020000 #define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_RX_EI_MASK 0x00040000 -#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_DBG_OBS_MASK 0x0000ffff -#define CPU_MAC_UNIT_HSS_MON_W5_MON_HSS_L1_I_SCAN_RESULTS_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_HSS_MON_W6_MON_HSS_L1_I_SCAN_RESULTS_63_32_MASK 0x00000001 +#define CPU_MAC_UNIT_HSS_MON_W4_MON_HSS_L1_RX_EI_FILTERED_MASK 0x01000000 +#define CPU_MAC_UNIT_HSS_MON_W5_MON_HSS_L1_I_SCAN_RESULTS_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_HSS_MON_W6_MON_HSS_L1_I_SCAN_RESULTS_63_32_MASK 0xffffffff -/* cpu_mac_hss_reg_acc_timing_cfg Definition */ -#define CPU_MAC_HSS_REG_ACC_TIMING_CFG_W0_CFG_ACTIVE_CYCLES BIT(0) -#define CPU_MAC_HSS_REG_ACC_TIMING_CFG_W0_CFG_HOLD_CYCLES BIT(8) -#define CPU_MAC_HSS_REG_ACC_TIMING_CFG_W1_CFG_RD_OUT_VALID_CYCLES BIT(8) -#define CPU_MAC_HSS_REG_ACC_TIMING_CFG_W1_CFG_SETUP_CYCLES BIT(0) +/* ################################################################################ + * # CpuMacHssRegAccTimingCfg Definition */ +#define CPU_MAC_HSS_REG_ACC_TIMING_CFG_W0_CFG_ACTIVE_CYCLES_BIT 0 +#define CPU_MAC_HSS_REG_ACC_TIMING_CFG_W0_CFG_HOLD_CYCLES_BIT 8 +#define CPU_MAC_HSS_REG_ACC_TIMING_CFG_W1_CFG_RD_OUT_VALID_CYCLES_BIT 8 +#define CPU_MAC_HSS_REG_ACC_TIMING_CFG_W1_CFG_SETUP_CYCLES_BIT 0 #define CPU_MAC_HSS_REG_ACC_TIMING_CFG_W0_CFG_ACTIVE_CYCLES_MASK 0x000000ff #define CPU_MAC_HSS_REG_ACC_TIMING_CFG_W0_CFG_HOLD_CYCLES_MASK 0x0000ff00 #define CPU_MAC_HSS_REG_ACC_TIMING_CFG_W1_CFG_RD_OUT_VALID_CYCLES_MASK 0x0000ff00 #define CPU_MAC_HSS_REG_ACC_TIMING_CFG_W1_CFG_SETUP_CYCLES_MASK 0x000000ff -/* cpu_mac_unit_reset_ctl Definition */ -#define CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC1 BIT(1) -#define CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC0 BIT(2) -#define CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_BASE BIT(0) +/* ################################################################################ + * # CpuMacUnitResetCtl Definition */ +#define CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_BASE_BIT 0 +#define CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC0_BIT 2 +#define CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC1_BIT 1 -#define CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC1_MASK 0x00000002 -#define CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC0_MASK 0x00000004 #define CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_BASE_MASK 0x00000001 +#define CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC0_MASK 0x00000004 +#define CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC1_MASK 0x00000002 -/* cpu_mac_unit_hss_reg_acc_ctl Definition */ -#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_WDATA BIT(8) -#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_VALID BIT(31) -#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_ADDR BIT(0) -#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_IS_READ BIT(16) -#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_ID BIT(24) +/* ################################################################################ + * # CpuMacUnitHssRegAccCtl Definition */ +#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_ADDR_BIT 0 +#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_ID_BIT 24 +#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_IS_READ_BIT 16 +#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_VALID_BIT 31 +#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_WDATA_BIT 8 -#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_WDATA_MASK 0x0000ff00 -#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_VALID_MASK 0x80000000 #define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_ADDR_MASK 0x000000ff -#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_IS_READ_MASK 0x00010000 #define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_ID_MASK 0x0f000000 +#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_IS_READ_MASK 0x00010000 +#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_VALID_MASK 0x80000000 +#define CPU_MAC_UNIT_HSS_REG_ACC_CTL_W0_HSS_ACC_WDATA_MASK 0x0000ff00 -/* cpu_mac_unit_hss_reg_acc_result Definition */ -#define CPU_MAC_UNIT_HSS_REG_ACC_RESULT_W0_HSS_ACC_ACK BIT(31) -#define CPU_MAC_UNIT_HSS_REG_ACC_RESULT_W0_HSS_ACC_ACK_DATA BIT(0) +/* ################################################################################ + * # CpuMacUnitHssRegAccResult Definition */ +#define CPU_MAC_UNIT_HSS_REG_ACC_RESULT_W0_HSS_ACC_ACK_BIT 31 +#define CPU_MAC_UNIT_HSS_REG_ACC_RESULT_W0_HSS_ACC_ACK_DATA_BIT 0 #define CPU_MAC_UNIT_HSS_REG_ACC_RESULT_W0_HSS_ACC_ACK_MASK 0x80000000 #define CPU_MAC_UNIT_HSS_REG_ACC_RESULT_W0_HSS_ACC_ACK_DATA_MASK 0x000000ff -/* cpu_mac_unit_axi_cfg Definition */ -#define CPU_MAC_UNIT_AXI_CFG_W0_CFG_AXI0_ID BIT(0) -#define CPU_MAC_UNIT_AXI_CFG_W0_CFG_AXI1_ID BIT(4) +/* ################################################################################ + * # CpuMacUnitAxiCfg Definition */ +#define CPU_MAC_UNIT_AXI_CFG_W0_CFG_AXI0_ID_BIT 0 +#define CPU_MAC_UNIT_AXI_CFG_W0_CFG_AXI1_ID_BIT 4 #define CPU_MAC_UNIT_AXI_CFG_W0_CFG_AXI0_ID_MASK 0x0000000f #define CPU_MAC_UNIT_AXI_CFG_W0_CFG_AXI1_ID_MASK 0x000000f0 -/* cpu_mac_unit_ts_cfg Definition */ -#define CPU_MAC_UNIT_TS_CFG_W0_CFG_TX_CAPTURE_FIFO_INTR_THRD BIT(0) -#define CPU_MAC_UNIT_TS_CFG_W0_CFG_FORCE_S_AND_NS_EN BIT(31) +/* ################################################################################ + * # CpuMacUnitTsCfg Definition */ +#define CPU_MAC_UNIT_TS_CFG_W0_CFG_FORCE_S_AND_NS_EN_BIT 31 +#define CPU_MAC_UNIT_TS_CFG_W0_CFG_TX_CAPTURE_FIFO_INTR_THRD_BIT 0 -#define CPU_MAC_UNIT_TS_CFG_W0_CFG_TX_CAPTURE_FIFO_INTR_THRD_MASK 0x0000000f #define CPU_MAC_UNIT_TS_CFG_W0_CFG_FORCE_S_AND_NS_EN_MASK 0x80000000 +#define CPU_MAC_UNIT_TS_CFG_W0_CFG_TX_CAPTURE_FIFO_INTR_THRD_MASK 0x0000000f -/* cpu_mac_unit_fifo_status Definition */ -#define CPU_MAC_UNIT_FIFO_STATUS_W0_CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_FIFO_DEPTH BIT(0) +/* ################################################################################ + * # CpuMacUnitFifoStatus Definition */ +#define CPU_MAC_UNIT_FIFO_STATUS_W0_CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_FIFO_DEPTH_BIT 0 #define CPU_MAC_UNIT_FIFO_STATUS_W0_CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_FIFO_DEPTH_MASK 0x0000000f -/* cpu_mac_unit_ts_mon Definition */ -#define CPU_MAC_UNIT_TS_MON_W0_MON_ADJ_NS BIT(0) -#define CPU_MAC_UNIT_TS_MON_W1_MON_ADJ_SECOND BIT(0) -#define CPU_MAC_UNIT_TS_MON_W2_MON_TX_CAPTURE_FIFO_DROP_CNT BIT(0) +/* ################################################################################ + * # CpuMacUnitTsMon Definition */ +#define CPU_MAC_UNIT_TS_MON_W0_MON_ADJ_NS_BIT 0 +#define CPU_MAC_UNIT_TS_MON_W1_MON_ADJ_SECOND_BIT 0 +#define CPU_MAC_UNIT_TS_MON_W2_MON_TX_CAPTURE_FIFO_DROP_CNT_BIT 0 #define CPU_MAC_UNIT_TS_MON_W0_MON_ADJ_NS_MASK 0x3fffffff #define CPU_MAC_UNIT_TS_MON_W1_MON_ADJ_SECOND_MASK 0xffffffff #define CPU_MAC_UNIT_TS_MON_W2_MON_TX_CAPTURE_FIFO_DROP_CNT_MASK 0x0000000f -/* cpu_mac_unit_ref_pulse_cfg Definition */ -#define CPU_MAC_UNIT_REF_PULSE_CFG_W0_REF_PAUSE_TIMER_PULSE_DIV BIT(0) -#define CPU_MAC_UNIT_REF_PULSE_CFG_W0_REF_PAUSE_TIMER_PULSE_RST BIT(31) -#define CPU_MAC_UNIT_REF_PULSE_CFG_W1_REF_LINK_PULSE_DIV BIT(0) -#define CPU_MAC_UNIT_REF_PULSE_CFG_W1_REF_LINK_PULSE_RST BIT(31) -#define CPU_MAC_UNIT_REF_PULSE_CFG_W2_REF_LINK_FILTER_PULSE_RST BIT(31) -#define CPU_MAC_UNIT_REF_PULSE_CFG_W2_REF_LINK_FILTER_PULSE_DIV BIT(0) -#define CPU_MAC_UNIT_REF_PULSE_CFG_W3_REF_EEE_PULSE_DIV BIT(0) -#define CPU_MAC_UNIT_REF_PULSE_CFG_W3_REF_EEE_PULSE_RST BIT(31) +/* ################################################################################ + * # CpuMacUnitRefPulseCfg Definition */ +#define CPU_MAC_UNIT_REF_PULSE_CFG_W0_REF_PAUSE_TIMER_PULSE_DIV_BIT 0 +#define CPU_MAC_UNIT_REF_PULSE_CFG_W0_REF_PAUSE_TIMER_PULSE_RST_BIT 31 +#define CPU_MAC_UNIT_REF_PULSE_CFG_W1_REF_LINK_PULSE_DIV_BIT 0 +#define CPU_MAC_UNIT_REF_PULSE_CFG_W1_REF_LINK_PULSE_RST_BIT 31 +#define CPU_MAC_UNIT_REF_PULSE_CFG_W2_REF_LINK_FILTER_PULSE_DIV_BIT 0 +#define CPU_MAC_UNIT_REF_PULSE_CFG_W2_REF_LINK_FILTER_PULSE_RST_BIT 31 +#define CPU_MAC_UNIT_REF_PULSE_CFG_W3_REF_EEE_PULSE_DIV_BIT 0 +#define CPU_MAC_UNIT_REF_PULSE_CFG_W3_REF_EEE_PULSE_RST_BIT 31 #define CPU_MAC_UNIT_REF_PULSE_CFG_W0_REF_PAUSE_TIMER_PULSE_DIV_MASK 0x7fffffff #define CPU_MAC_UNIT_REF_PULSE_CFG_W0_REF_PAUSE_TIMER_PULSE_RST_MASK 0x80000000 #define CPU_MAC_UNIT_REF_PULSE_CFG_W1_REF_LINK_PULSE_DIV_MASK 0x7fffffff #define CPU_MAC_UNIT_REF_PULSE_CFG_W1_REF_LINK_PULSE_RST_MASK 0x80000000 -#define CPU_MAC_UNIT_REF_PULSE_CFG_W2_REF_LINK_FILTER_PULSE_RST_MASK 0x80000000 #define CPU_MAC_UNIT_REF_PULSE_CFG_W2_REF_LINK_FILTER_PULSE_DIV_MASK 0x7fffffff +#define CPU_MAC_UNIT_REF_PULSE_CFG_W2_REF_LINK_FILTER_PULSE_RST_MASK 0x80000000 #define CPU_MAC_UNIT_REF_PULSE_CFG_W3_REF_EEE_PULSE_DIV_MASK 0x7fffffff #define CPU_MAC_UNIT_REF_PULSE_CFG_W3_REF_EEE_PULSE_RST_MASK 0x80000000 -/* cpu_mac_unit_interrupt_func Definition */ -#define CPU_MAC_UNIT_INTERRUPT_FUNC_W0_VALUE_SET0_CPU_MAC_UNIT_INTERRUPT_FUNC BIT(0) -#define CPU_MAC_UNIT_INTERRUPT_FUNC_W1_VALUE_RESET0_CPU_MAC_UNIT_INTERRUPT_FUNC BIT(0) -#define CPU_MAC_UNIT_INTERRUPT_FUNC_W2_MASK_SET0_CPU_MAC_UNIT_INTERRUPT_FUNC BIT(0) -#define CPU_MAC_UNIT_INTERRUPT_FUNC_W3_MASK_RESET0_CPU_MAC_UNIT_INTERRUPT_FUNC BIT(0) +/* ################################################################################ + * # CpuMacUnitInterruptFunc Definition */ +#define CPU_MAC_UNIT_INTERRUPT_FUNC_W0_VALUE_SET0_CPU_MAC_UNIT_INTERRUPT_FUNC_BIT 0 +#define CPU_MAC_UNIT_INTERRUPT_FUNC_W1_VALUE_RESET0_CPU_MAC_UNIT_INTERRUPT_FUNC_BIT 0 +#define CPU_MAC_UNIT_INTERRUPT_FUNC_W2_MASK_SET0_CPU_MAC_UNIT_INTERRUPT_FUNC_BIT 0 +#define CPU_MAC_UNIT_INTERRUPT_FUNC_W3_MASK_RESET0_CPU_MAC_UNIT_INTERRUPT_FUNC_BIT 0 #define CPU_MAC_UNIT_INTERRUPT_FUNC_W0_VALUE_SET0_CPU_MAC_UNIT_INTERRUPT_FUNC_MASK 0x00000001 #define CPU_MAC_UNIT_INTERRUPT_FUNC_W1_VALUE_RESET0_CPU_MAC_UNIT_INTERRUPT_FUNC_MASK 0x00000001 #define CPU_MAC_UNIT_INTERRUPT_FUNC_W2_MASK_SET0_CPU_MAC_UNIT_INTERRUPT_FUNC_MASK 0x00000001 #define CPU_MAC_UNIT_INTERRUPT_FUNC_W3_MASK_RESET0_CPU_MAC_UNIT_INTERRUPT_FUNC_MASK 0x00000001 -/* cpu_mac_unit_hss_cfg Definition */ +/* ################################################################################ + * # CpuMacUnitHssCfg Definition */ #define CPU_MAC_UNIT_HSS_CFG_W0_CFG_HSS_BCLK_RST_N_BIT 1 #define CPU_MAC_UNIT_HSS_CFG_W0_CFG_HSS_CMU0_HWT_BIAS_DN_EN_BIT 13 #define CPU_MAC_UNIT_HSS_CFG_W0_CFG_HSS_CMU0_HWT_BIAS_UP_EN_BIT 14 @@ -5024,197 +5050,201 @@ struct cpu_mac_unit_regs { #define CPU_MAC_UNIT_HSS_CFG_W13_CFG_HSS_L1_PCS2_PMA_H4_MASK 0x00078000 #define CPU_MAC_UNIT_HSS_CFG_W13_CFG_HSS_L1_PCS2_PMA_H5_MASK 0x00780000 #define CPU_MAC_UNIT_HSS_CFG_W13_CFG_HSS_L1_PCS2_PMA_H_BYP_MASK 0x40000000 -/* cpu_mac_unit_ip_cam_cfg Definition */ -#define CPU_MAC_UNIT_IP_CAM_CFG_W0_CFG_IP_CAM_VALUE0_31_0 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W1_CFG_IP_CAM_VALUE0_63_32 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W2_CFG_IP_CAM_VALUE0_95_64 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W3_CFG_IP_CAM_VALUE0_127_96 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W4_CFG_IP_CAM_VALUE1_31_0 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W5_CFG_IP_CAM_VALUE1_63_32 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W6_CFG_IP_CAM_VALUE1_95_64 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W7_CFG_IP_CAM_VALUE1_127_96 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W8_CFG_IP_CAM_VALUE2_31_0 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W9_CFG_IP_CAM_VALUE2_63_32 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W10_CFG_IP_CAM_VALUE2_95_64 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W11_CFG_IP_CAM_VALUE2_127_96 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W12_CFG_IP_CAM_VALUE3_31_0 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W13_CFG_IP_CAM_VALUE3_63_32 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W14_CFG_IP_CAM_VALUE3_95_64 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W15_CFG_IP_CAM_VALUE3_127_96 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W16_CFG_IP_CAM_MASK0_31_0 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W17_CFG_IP_CAM_MASK0_63_32 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W18_CFG_IP_CAM_MASK0_95_64 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W19_CFG_IP_CAM_MASK0_127_96 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W20_CFG_IP_CAM_MASK1_31_0 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W21_CFG_IP_CAM_MASK1_63_32 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W22_CFG_IP_CAM_MASK1_95_64 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W23_CFG_IP_CAM_MASK1_127_96 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W24_CFG_IP_CAM_MASK2_31_0 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W25_CFG_IP_CAM_MASK2_63_32 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W26_CFG_IP_CAM_MASK2_95_64 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W27_CFG_IP_CAM_MASK2_127_96 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W28_CFG_IP_CAM_MASK3_31_0 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W29_CFG_IP_CAM_MASK3_63_32 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W30_CFG_IP_CAM_MASK3_95_64 BIT(0) -#define CPU_MAC_UNIT_IP_CAM_CFG_W31_CFG_IP_CAM_MASK3_127_96 BIT(0) - -#define CPU_MAC_UNIT_IP_CAM_CFG_W0_CFG_IP_CAM_VALUE0_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W1_CFG_IP_CAM_VALUE0_63_32_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W2_CFG_IP_CAM_VALUE0_95_64_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W3_CFG_IP_CAM_VALUE0_127_96_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W4_CFG_IP_CAM_VALUE1_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W5_CFG_IP_CAM_VALUE1_63_32_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W6_CFG_IP_CAM_VALUE1_95_64_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W7_CFG_IP_CAM_VALUE1_127_96_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W8_CFG_IP_CAM_VALUE2_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W9_CFG_IP_CAM_VALUE2_63_32_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W10_CFG_IP_CAM_VALUE2_95_64_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W11_CFG_IP_CAM_VALUE2_127_96_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W12_CFG_IP_CAM_VALUE3_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W13_CFG_IP_CAM_VALUE3_63_32_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W14_CFG_IP_CAM_VALUE3_95_64_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W15_CFG_IP_CAM_VALUE3_127_96_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W16_CFG_IP_CAM_MASK0_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W17_CFG_IP_CAM_MASK0_63_32_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W18_CFG_IP_CAM_MASK0_95_64_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W19_CFG_IP_CAM_MASK0_127_96_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W20_CFG_IP_CAM_MASK1_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W21_CFG_IP_CAM_MASK1_63_32_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W22_CFG_IP_CAM_MASK1_95_64_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W23_CFG_IP_CAM_MASK1_127_96_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W24_CFG_IP_CAM_MASK2_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W25_CFG_IP_CAM_MASK2_63_32_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W26_CFG_IP_CAM_MASK2_95_64_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W27_CFG_IP_CAM_MASK2_127_96_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W28_CFG_IP_CAM_MASK3_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W29_CFG_IP_CAM_MASK3_63_32_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W30_CFG_IP_CAM_MASK3_95_64_MASK 0x00000001 -#define CPU_MAC_UNIT_IP_CAM_CFG_W31_CFG_IP_CAM_MASK3_127_96_MASK 0x00000001 - -/* cpu_mac_unit_mac_cam_cfg Definition */ -#define CPU_MAC_UNIT_MAC_CAM_CFG_W0_CFG_MAC_CAM_VALUE0_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W1_CFG_MAC_CAM_VALUE0_47_32 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W2_CFG_MAC_CAM_VALUE1_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W3_CFG_MAC_CAM_VALUE1_47_32 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W4_CFG_MAC_CAM_VALUE2_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W5_CFG_MAC_CAM_VALUE2_47_32 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W6_CFG_MAC_CAM_VALUE3_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W7_CFG_MAC_CAM_VALUE3_47_32 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W8_CFG_MAC_CAM_VALUE4_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W9_CFG_MAC_CAM_VALUE4_47_32 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W10_CFG_MAC_CAM_VALUE5_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W11_CFG_MAC_CAM_VALUE5_47_32 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W12_CFG_MAC_CAM_VALUE6_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W13_CFG_MAC_CAM_VALUE6_47_32 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W14_CFG_MAC_CAM_VALUE7_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W15_CFG_MAC_CAM_VALUE7_47_32 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W16_CFG_MAC_CAM_MASK0_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W17_CFG_MAC_CAM_MASK0_47_32 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W18_CFG_MAC_CAM_MASK1_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W19_CFG_MAC_CAM_MASK1_47_32 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W20_CFG_MAC_CAM_MASK2_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W21_CFG_MAC_CAM_MASK2_47_32 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W22_CFG_MAC_CAM_MASK3_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W23_CFG_MAC_CAM_MASK3_47_32 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W24_CFG_MAC_CAM_MASK4_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W25_CFG_MAC_CAM_MASK4_47_32 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W26_CFG_MAC_CAM_MASK5_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W27_CFG_MAC_CAM_MASK5_47_32 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W28_CFG_MAC_CAM_MASK6_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W29_CFG_MAC_CAM_MASK6_47_32 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W30_CFG_MAC_CAM_MASK7_31_0 BIT(0) -#define CPU_MAC_UNIT_MAC_CAM_CFG_W31_CFG_MAC_CAM_MASK7_47_32 BIT(0) - -#define CPU_MAC_UNIT_MAC_CAM_CFG_W0_CFG_MAC_CAM_VALUE0_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W1_CFG_MAC_CAM_VALUE0_47_32_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W2_CFG_MAC_CAM_VALUE1_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W3_CFG_MAC_CAM_VALUE1_47_32_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W4_CFG_MAC_CAM_VALUE2_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W5_CFG_MAC_CAM_VALUE2_47_32_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W6_CFG_MAC_CAM_VALUE3_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W7_CFG_MAC_CAM_VALUE3_47_32_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W8_CFG_MAC_CAM_VALUE4_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W9_CFG_MAC_CAM_VALUE4_47_32_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W10_CFG_MAC_CAM_VALUE5_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W11_CFG_MAC_CAM_VALUE5_47_32_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W12_CFG_MAC_CAM_VALUE6_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W13_CFG_MAC_CAM_VALUE6_47_32_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W14_CFG_MAC_CAM_VALUE7_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W15_CFG_MAC_CAM_VALUE7_47_32_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W16_CFG_MAC_CAM_MASK0_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W17_CFG_MAC_CAM_MASK0_47_32_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W18_CFG_MAC_CAM_MASK1_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W19_CFG_MAC_CAM_MASK1_47_32_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W20_CFG_MAC_CAM_MASK2_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W21_CFG_MAC_CAM_MASK2_47_32_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W22_CFG_MAC_CAM_MASK3_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W23_CFG_MAC_CAM_MASK3_47_32_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W24_CFG_MAC_CAM_MASK4_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W25_CFG_MAC_CAM_MASK4_47_32_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W26_CFG_MAC_CAM_MASK5_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W27_CFG_MAC_CAM_MASK5_47_32_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W28_CFG_MAC_CAM_MASK6_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W29_CFG_MAC_CAM_MASK6_47_32_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W30_CFG_MAC_CAM_MASK7_31_0_MASK 0x00000001 -#define CPU_MAC_UNIT_MAC_CAM_CFG_W31_CFG_MAC_CAM_MASK7_47_32_MASK 0x00000001 - -/* cpu_mac_unit_filter_cfg Definition */ -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_IS_SA0 BIT(17) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA0 BIT(9) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_IS_SA3 BIT(20) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA6 BIT(15) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_IS_SA1 BIT(18) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_FILTER_IS_LOOSE BIT(5) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA7 BIT(16) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_FILTER_EN BIT(2) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_BLOCK_SUPPRESSION_TRAFFIC BIT(6) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_IS_SA2 BIT(19) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM3_IS_V6 BIT(24) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA5 BIT(14) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA2 BIT(11) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA4 BIT(13) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM_IS_BLACK_LIST BIT(4) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_CAM_IS_BLACK_LIST BIT(3) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_FILTER_EN BIT(0) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM2_IS_V6 BIT(23) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM1_IS_V6 BIT(22) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_ETHER_TYPE_FILTER_EN BIT(1) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA1 BIT(10) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA3 BIT(12) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM0_IS_V6 BIT(21) -#define CPU_MAC_UNIT_FILTER_CFG_W1_CFG_SUPPRESSION_ETHER_TYPE0 BIT(16) -#define CPU_MAC_UNIT_FILTER_CFG_W1_CFG_VLAN_TPID BIT(0) -#define CPU_MAC_UNIT_FILTER_CFG_W2_CFG_SUPPRESSION_ETHER_TYPE1 BIT(0) -#define CPU_MAC_UNIT_FILTER_CFG_W2_CFG_SUPPRESSION_ETHER_TYPE2 BIT(16) -#define CPU_MAC_UNIT_FILTER_CFG_W3_CFG_CONFIRM_ETHER_TYPE0 BIT(0) -#define CPU_MAC_UNIT_FILTER_CFG_W3_CFG_CONFIRM_ETHER_TYPE1 BIT(16) -#define CPU_MAC_UNIT_FILTER_CFG_W4_CFG_CONFIRM_ETHER_TYPE2 BIT(0) -#define CPU_MAC_UNIT_FILTER_CFG_W5_CFG_METER_TOKEN_UPD_INTERVAL BIT(0) -#define CPU_MAC_UNIT_FILTER_CFG_W5_CFG_METER_TOKEN_UPD_VALUE BIT(16) -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_IS_SA0_MASK 0x00020000 -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA0_MASK 0x00000200 -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_IS_SA3_MASK 0x00100000 -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA6_MASK 0x00008000 -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_IS_SA1_MASK 0x00040000 +/* ################################################################################ + * # CpuMacUnitIpCamCfg Definition */ +#define CPU_MAC_UNIT_IP_CAM_CFG_W0_CFG_IP_CAM_VALUE0_31_0_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W1_CFG_IP_CAM_VALUE0_63_32_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W2_CFG_IP_CAM_VALUE0_95_64_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W3_CFG_IP_CAM_VALUE0_127_96_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W4_CFG_IP_CAM_VALUE1_31_0_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W5_CFG_IP_CAM_VALUE1_63_32_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W6_CFG_IP_CAM_VALUE1_95_64_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W7_CFG_IP_CAM_VALUE1_127_96_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W8_CFG_IP_CAM_VALUE2_31_0_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W9_CFG_IP_CAM_VALUE2_63_32_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W10_CFG_IP_CAM_VALUE2_95_64_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W11_CFG_IP_CAM_VALUE2_127_96_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W12_CFG_IP_CAM_VALUE3_31_0_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W13_CFG_IP_CAM_VALUE3_63_32_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W14_CFG_IP_CAM_VALUE3_95_64_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W15_CFG_IP_CAM_VALUE3_127_96_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W16_CFG_IP_CAM_MASK0_31_0_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W17_CFG_IP_CAM_MASK0_63_32_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W18_CFG_IP_CAM_MASK0_95_64_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W19_CFG_IP_CAM_MASK0_127_96_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W20_CFG_IP_CAM_MASK1_31_0_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W21_CFG_IP_CAM_MASK1_63_32_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W22_CFG_IP_CAM_MASK1_95_64_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W23_CFG_IP_CAM_MASK1_127_96_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W24_CFG_IP_CAM_MASK2_31_0_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W25_CFG_IP_CAM_MASK2_63_32_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W26_CFG_IP_CAM_MASK2_95_64_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W27_CFG_IP_CAM_MASK2_127_96_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W28_CFG_IP_CAM_MASK3_31_0_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W29_CFG_IP_CAM_MASK3_63_32_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W30_CFG_IP_CAM_MASK3_95_64_BIT 0 +#define CPU_MAC_UNIT_IP_CAM_CFG_W31_CFG_IP_CAM_MASK3_127_96_BIT 0 + +#define CPU_MAC_UNIT_IP_CAM_CFG_W0_CFG_IP_CAM_VALUE0_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W1_CFG_IP_CAM_VALUE0_63_32_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W2_CFG_IP_CAM_VALUE0_95_64_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W3_CFG_IP_CAM_VALUE0_127_96_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W4_CFG_IP_CAM_VALUE1_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W5_CFG_IP_CAM_VALUE1_63_32_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W6_CFG_IP_CAM_VALUE1_95_64_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W7_CFG_IP_CAM_VALUE1_127_96_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W8_CFG_IP_CAM_VALUE2_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W9_CFG_IP_CAM_VALUE2_63_32_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W10_CFG_IP_CAM_VALUE2_95_64_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W11_CFG_IP_CAM_VALUE2_127_96_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W12_CFG_IP_CAM_VALUE3_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W13_CFG_IP_CAM_VALUE3_63_32_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W14_CFG_IP_CAM_VALUE3_95_64_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W15_CFG_IP_CAM_VALUE3_127_96_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W16_CFG_IP_CAM_MASK0_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W17_CFG_IP_CAM_MASK0_63_32_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W18_CFG_IP_CAM_MASK0_95_64_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W19_CFG_IP_CAM_MASK0_127_96_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W20_CFG_IP_CAM_MASK1_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W21_CFG_IP_CAM_MASK1_63_32_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W22_CFG_IP_CAM_MASK1_95_64_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W23_CFG_IP_CAM_MASK1_127_96_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W24_CFG_IP_CAM_MASK2_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W25_CFG_IP_CAM_MASK2_63_32_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W26_CFG_IP_CAM_MASK2_95_64_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W27_CFG_IP_CAM_MASK2_127_96_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W28_CFG_IP_CAM_MASK3_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W29_CFG_IP_CAM_MASK3_63_32_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W30_CFG_IP_CAM_MASK3_95_64_MASK 0xffffffff +#define CPU_MAC_UNIT_IP_CAM_CFG_W31_CFG_IP_CAM_MASK3_127_96_MASK 0xffffffff + +/* ################################################################################ + * # CpuMacUnitMacCamCfg Definition */ +#define CPU_MAC_UNIT_MAC_CAM_CFG_W0_CFG_MAC_CAM_VALUE0_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W1_CFG_MAC_CAM_VALUE0_47_32_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W2_CFG_MAC_CAM_VALUE1_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W3_CFG_MAC_CAM_VALUE1_47_32_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W4_CFG_MAC_CAM_VALUE2_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W5_CFG_MAC_CAM_VALUE2_47_32_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W6_CFG_MAC_CAM_VALUE3_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W7_CFG_MAC_CAM_VALUE3_47_32_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W8_CFG_MAC_CAM_VALUE4_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W9_CFG_MAC_CAM_VALUE4_47_32_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W10_CFG_MAC_CAM_VALUE5_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W11_CFG_MAC_CAM_VALUE5_47_32_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W12_CFG_MAC_CAM_VALUE6_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W13_CFG_MAC_CAM_VALUE6_47_32_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W14_CFG_MAC_CAM_VALUE7_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W15_CFG_MAC_CAM_VALUE7_47_32_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W16_CFG_MAC_CAM_MASK0_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W17_CFG_MAC_CAM_MASK0_47_32_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W18_CFG_MAC_CAM_MASK1_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W19_CFG_MAC_CAM_MASK1_47_32_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W20_CFG_MAC_CAM_MASK2_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W21_CFG_MAC_CAM_MASK2_47_32_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W22_CFG_MAC_CAM_MASK3_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W23_CFG_MAC_CAM_MASK3_47_32_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W24_CFG_MAC_CAM_MASK4_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W25_CFG_MAC_CAM_MASK4_47_32_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W26_CFG_MAC_CAM_MASK5_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W27_CFG_MAC_CAM_MASK5_47_32_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W28_CFG_MAC_CAM_MASK6_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W29_CFG_MAC_CAM_MASK6_47_32_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W30_CFG_MAC_CAM_MASK7_31_0_BIT 0 +#define CPU_MAC_UNIT_MAC_CAM_CFG_W31_CFG_MAC_CAM_MASK7_47_32_BIT 0 + +#define CPU_MAC_UNIT_MAC_CAM_CFG_W0_CFG_MAC_CAM_VALUE0_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W1_CFG_MAC_CAM_VALUE0_47_32_MASK 0x0000ffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W2_CFG_MAC_CAM_VALUE1_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W3_CFG_MAC_CAM_VALUE1_47_32_MASK 0x0000ffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W4_CFG_MAC_CAM_VALUE2_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W5_CFG_MAC_CAM_VALUE2_47_32_MASK 0x0000ffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W6_CFG_MAC_CAM_VALUE3_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W7_CFG_MAC_CAM_VALUE3_47_32_MASK 0x0000ffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W8_CFG_MAC_CAM_VALUE4_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W9_CFG_MAC_CAM_VALUE4_47_32_MASK 0x0000ffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W10_CFG_MAC_CAM_VALUE5_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W11_CFG_MAC_CAM_VALUE5_47_32_MASK 0x0000ffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W12_CFG_MAC_CAM_VALUE6_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W13_CFG_MAC_CAM_VALUE6_47_32_MASK 0x0000ffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W14_CFG_MAC_CAM_VALUE7_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W15_CFG_MAC_CAM_VALUE7_47_32_MASK 0x0000ffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W16_CFG_MAC_CAM_MASK0_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W17_CFG_MAC_CAM_MASK0_47_32_MASK 0x0000ffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W18_CFG_MAC_CAM_MASK1_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W19_CFG_MAC_CAM_MASK1_47_32_MASK 0x0000ffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W20_CFG_MAC_CAM_MASK2_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W21_CFG_MAC_CAM_MASK2_47_32_MASK 0x0000ffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W22_CFG_MAC_CAM_MASK3_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W23_CFG_MAC_CAM_MASK3_47_32_MASK 0x0000ffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W24_CFG_MAC_CAM_MASK4_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W25_CFG_MAC_CAM_MASK4_47_32_MASK 0x0000ffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W26_CFG_MAC_CAM_MASK5_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W27_CFG_MAC_CAM_MASK5_47_32_MASK 0x0000ffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W28_CFG_MAC_CAM_MASK6_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W29_CFG_MAC_CAM_MASK6_47_32_MASK 0x0000ffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W30_CFG_MAC_CAM_MASK7_31_0_MASK 0xffffffff +#define CPU_MAC_UNIT_MAC_CAM_CFG_W31_CFG_MAC_CAM_MASK7_47_32_MASK 0x0000ffff + +/* ################################################################################ + * # CpuMacUnitFilterCfg Definition */ +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_BLOCK_SUPPRESSION_TRAFFIC_BIT 6 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_ETHER_TYPE_FILTER_EN_BIT 1 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_FILTER_IS_LOOSE_BIT 5 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_FILTER_EN_BIT 2 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_IS_SA0_BIT 17 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_IS_SA1_BIT 18 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_IS_SA2_BIT 19 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_IS_SA3_BIT 20 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM0_IS_V6_BIT 21 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM1_IS_V6_BIT 22 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM2_IS_V6_BIT 23 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM3_IS_V6_BIT 24 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM_IS_BLACK_LIST_BIT 4 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA0_BIT 9 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA1_BIT 10 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA2_BIT 11 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA3_BIT 12 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA4_BIT 13 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA5_BIT 14 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA6_BIT 15 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA7_BIT 16 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_CAM_IS_BLACK_LIST_BIT 3 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_FILTER_EN_BIT 0 +#define CPU_MAC_UNIT_FILTER_CFG_W1_CFG_SUPPRESSION_ETHER_TYPE0_BIT 16 +#define CPU_MAC_UNIT_FILTER_CFG_W1_CFG_VLAN_TPID_BIT 0 +#define CPU_MAC_UNIT_FILTER_CFG_W2_CFG_SUPPRESSION_ETHER_TYPE1_BIT 0 +#define CPU_MAC_UNIT_FILTER_CFG_W2_CFG_SUPPRESSION_ETHER_TYPE2_BIT 16 +#define CPU_MAC_UNIT_FILTER_CFG_W3_CFG_CONFIRM_ETHER_TYPE0_BIT 0 +#define CPU_MAC_UNIT_FILTER_CFG_W3_CFG_CONFIRM_ETHER_TYPE1_BIT 16 +#define CPU_MAC_UNIT_FILTER_CFG_W4_CFG_CONFIRM_ETHER_TYPE2_BIT 0 +#define CPU_MAC_UNIT_FILTER_CFG_W5_CFG_METER_TOKEN_UPD_INTERVAL_BIT 0 +#define CPU_MAC_UNIT_FILTER_CFG_W5_CFG_METER_TOKEN_UPD_VALUE_BIT 16 + +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_BLOCK_SUPPRESSION_TRAFFIC_MASK 0x000001c0 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_ETHER_TYPE_FILTER_EN_MASK 0x00000002 #define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_FILTER_IS_LOOSE_MASK 0x00000020 -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA7_MASK 0x00010000 #define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_FILTER_EN_MASK 0x00000004 -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_BLOCK_SUPPRESSION_TRAFFIC_MASK 0x000001c0 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_IS_SA0_MASK 0x00020000 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_IS_SA1_MASK 0x00040000 #define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_IS_SA2_MASK 0x00080000 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_ADDR_IS_SA3_MASK 0x00100000 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM0_IS_V6_MASK 0x00200000 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM1_IS_V6_MASK 0x00400000 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM2_IS_V6_MASK 0x00800000 #define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM3_IS_V6_MASK 0x01000000 -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA5_MASK 0x00004000 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM_IS_BLACK_LIST_MASK 0x00000010 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA0_MASK 0x00000200 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA1_MASK 0x00000400 #define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA2_MASK 0x00000800 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA3_MASK 0x00001000 #define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA4_MASK 0x00002000 -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM_IS_BLACK_LIST_MASK 0x00000010 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA5_MASK 0x00004000 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA6_MASK 0x00008000 +#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA7_MASK 0x00010000 #define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_CAM_IS_BLACK_LIST_MASK 0x00000008 #define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_FILTER_EN_MASK 0x00000001 -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM2_IS_V6_MASK 0x00800000 -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM1_IS_V6_MASK 0x00400000 -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_ETHER_TYPE_FILTER_EN_MASK 0x00000002 -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA1_MASK 0x00000400 -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_MAC_ADDR_IS_SA3_MASK 0x00001000 -#define CPU_MAC_UNIT_FILTER_CFG_W0_CFG_IP_CAM0_IS_V6_MASK 0x00200000 #define CPU_MAC_UNIT_FILTER_CFG_W1_CFG_SUPPRESSION_ETHER_TYPE0_MASK 0xffff0000 #define CPU_MAC_UNIT_FILTER_CFG_W1_CFG_VLAN_TPID_MASK 0x0000ffff #define CPU_MAC_UNIT_FILTER_CFG_W2_CFG_SUPPRESSION_ETHER_TYPE1_MASK 0x0000ffff @@ -5225,64 +5255,182 @@ struct cpu_mac_unit_regs { #define CPU_MAC_UNIT_FILTER_CFG_W5_CFG_METER_TOKEN_UPD_INTERVAL_MASK 0x0000ffff #define CPU_MAC_UNIT_FILTER_CFG_W5_CFG_METER_TOKEN_UPD_VALUE_MASK 0xffff0000 -struct cpu_mac_unit_mems { - u32 cpu_mac_unit_tx_ts_capture_fifo_0[3]; /* 0x00000400 */ - u32 cpu_mac_unit_tx_ts_capture_fifo_0_rsv3; - u32 cpu_mac_unit_tx_ts_capture_fifo_1[3]; /* 0x00000410 */ - u32 cpu_mac_unit_tx_ts_capture_fifo_1_rsv3; - u32 cpu_mac_unit_tx_ts_capture_fifo_2[3]; /* 0x00000420 */ - u32 cpu_mac_unit_tx_ts_capture_fifo_2_rsv3; - u32 cpu_mac_unit_tx_ts_capture_fifo_3[3]; /* 0x00000430 */ - u32 cpu_mac_unit_tx_ts_capture_fifo_3_rsv3; - u32 cpu_mac_unit_tx_ts_capture_fifo_4[3]; /* 0x00000440 */ - u32 cpu_mac_unit_tx_ts_capture_fifo_4_rsv3; - u32 cpu_mac_unit_tx_ts_capture_fifo_5[3]; /* 0x00000450 */ - u32 cpu_mac_unit_tx_ts_capture_fifo_5_rsv3; - u32 cpu_mac_unit_tx_ts_capture_fifo_6[3]; /* 0x00000460 */ - u32 cpu_mac_unit_tx_ts_capture_fifo_6_rsv3; - u32 cpu_mac_unit_tx_ts_capture_fifo_7[3]; /* 0x00000470 */ - u32 cpu_mac_unit_tx_ts_capture_fifo_7_rsv3; - u32 cpu_mac_unit_tx_capture_ts_0[3]; /* 0x00000480 */ - u32 cpu_mac_unit_tx_capture_ts_0_rsv3; +/* ################################################################################ + * # CpuMacUnitFilterCfg1 Definition */ +#define CPU_MAC_UNIT_FILTER_CFG1_W0_CFG_MAC_CAM_ENABLE_BMP0_BIT 16 +#define CPU_MAC_UNIT_FILTER_CFG1_W0_CFG_MAC_CAM_ENABLE_BMP1_BIT 24 +#define CPU_MAC_UNIT_FILTER_CFG1_W0_CFG_METER_TOKEN_UPD_VALUE1_BIT 0 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_CHECK_NORMAL_PKT_ENABLE0_BIT 16 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_CHECK_NORMAL_PKT_ENABLE1_BIT 17 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_DROP_NORMAL_PKT0_BIT 18 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_DROP_NORMAL_PKT1_BIT 19 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_ETHER_TYPE_ENABLE_BMP0_BIT 8 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_ETHER_TYPE_ENABLE_BMP1_BIT 12 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_IP_CAM_ENABLE_BMP0_BIT 0 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_IP_CAM_ENABLE_BMP1_BIT 4 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_METER_TOKEN_UPD_VALUE_SEL0_BIT 22 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_METER_TOKEN_UPD_VALUE_SEL1_BIT 23 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_VLAN_FILTER_ENABLE0_BIT 21 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_VLAN_FILTER_ENABLE1_BIT 20 +#define CPU_MAC_UNIT_FILTER_CFG1_W2_CFG_METER_TOKEN_MAX_VALUE0_BIT 0 +#define CPU_MAC_UNIT_FILTER_CFG1_W3_CFG_METER_TOKEN_MAX_VALUE1_BIT 0 + +#define CPU_MAC_UNIT_FILTER_CFG1_W0_CFG_MAC_CAM_ENABLE_BMP0_MASK 0x00ff0000 +#define CPU_MAC_UNIT_FILTER_CFG1_W0_CFG_MAC_CAM_ENABLE_BMP1_MASK 0xff000000 +#define CPU_MAC_UNIT_FILTER_CFG1_W0_CFG_METER_TOKEN_UPD_VALUE1_MASK 0x0000ffff +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_CHECK_NORMAL_PKT_ENABLE0_MASK 0x00010000 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_CHECK_NORMAL_PKT_ENABLE1_MASK 0x00020000 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_DROP_NORMAL_PKT0_MASK 0x00040000 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_DROP_NORMAL_PKT1_MASK 0x00080000 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_ETHER_TYPE_ENABLE_BMP0_MASK 0x00000f00 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_ETHER_TYPE_ENABLE_BMP1_MASK 0x0000f000 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_IP_CAM_ENABLE_BMP0_MASK 0x0000000f +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_IP_CAM_ENABLE_BMP1_MASK 0x000000f0 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_METER_TOKEN_UPD_VALUE_SEL0_MASK 0x00400000 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_METER_TOKEN_UPD_VALUE_SEL1_MASK 0x00800000 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_VLAN_FILTER_ENABLE0_MASK 0x00200000 +#define CPU_MAC_UNIT_FILTER_CFG1_W1_CFG_VLAN_FILTER_ENABLE1_MASK 0x00100000 +#define CPU_MAC_UNIT_FILTER_CFG1_W2_CFG_METER_TOKEN_MAX_VALUE0_MASK 0x00ffffff +#define CPU_MAC_UNIT_FILTER_CFG1_W3_CFG_METER_TOKEN_MAX_VALUE1_MASK 0x00ffffff + +struct CpuMacUnit_mems { + u32 CpuMacUnitTxTsCaptureFifo0[3]; /* 0x00000400 */ + u32 CpuMacUnitTxTsCaptureFifo0_rsv3; + u32 CpuMacUnitTxTsCaptureFifo1[3]; /* 0x00000410 */ + u32 CpuMacUnitTxTsCaptureFifo1_rsv3; + u32 CpuMacUnitTxTsCaptureFifo2[3]; /* 0x00000420 */ + u32 CpuMacUnitTxTsCaptureFifo2_rsv3; + u32 CpuMacUnitTxTsCaptureFifo3[3]; /* 0x00000430 */ + u32 CpuMacUnitTxTsCaptureFifo3_rsv3; + u32 CpuMacUnitTxTsCaptureFifo4[3]; /* 0x00000440 */ + u32 CpuMacUnitTxTsCaptureFifo4_rsv3; + u32 CpuMacUnitTxTsCaptureFifo5[3]; /* 0x00000450 */ + u32 CpuMacUnitTxTsCaptureFifo5_rsv3; + u32 CpuMacUnitTxTsCaptureFifo6[3]; /* 0x00000460 */ + u32 CpuMacUnitTxTsCaptureFifo6_rsv3; + u32 CpuMacUnitTxTsCaptureFifo7[3]; /* 0x00000470 */ + u32 CpuMacUnitTxTsCaptureFifo7_rsv3; + u32 CpuMacUnitTxCaptureTs0[3]; /* 0x00000480 */ + u32 CpuMacUnitTxCaptureTs0_rsv3; }; -/* cpu_mac_unit_tx_ts_capture_fifo Definition */ -#define CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_W0_CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_FIELD0 BIT(0) -#define CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_W1_CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_FIELD1 BIT(0) -#define CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_W2_CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_FIELD2 BIT(0) +/* ################################################################################ + * # CpuMacUnitTxTsCaptureFifo Definition */ +#define CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_W0_CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_FIELD0_BIT 0 +#define CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_W1_CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_FIELD1_BIT 0 +#define CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_W2_CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_FIELD2_BIT 0 #define CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_W0_CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_FIELD0_MASK 0xffffffff #define CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_W1_CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_FIELD1_MASK 0xffffffff #define CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_W2_CPU_MAC_UNIT_TX_TS_CAPTURE_FIFO_FIELD2_MASK 0x0000000f -/* cpu_mac_unit_tx_capture_ts Definition */ -#define CPU_MAC_UNIT_TX_CAPTURE_TS_W0_CPU_MAC1_TX_SEQ_ID BIT(5) -#define CPU_MAC_UNIT_TX_CAPTURE_TS_W0_CPU_MAC1_TX_SFD BIT(4) -#define CPU_MAC_UNIT_TX_CAPTURE_TS_W0_CPU_MAC0_TX_SEQ_ID BIT(1) -#define CPU_MAC_UNIT_TX_CAPTURE_TS_W0_CPU_MAC0_TX_SFD BIT(0) -#define CPU_MAC_UNIT_TX_CAPTURE_TS_W1_ADJ_RC_SECOND BIT(0) -#define CPU_MAC_UNIT_TX_CAPTURE_TS_W2_ADJ_RC_NS BIT(0) +/* ################################################################################ + * # CpuMacUnitTxCaptureTs Definition */ +#define CPU_MAC_UNIT_TX_CAPTURE_TS_W0_CPU_MAC0_TX_SEQ_ID_BIT 1 +#define CPU_MAC_UNIT_TX_CAPTURE_TS_W0_CPU_MAC0_TX_SFD_BIT 0 +#define CPU_MAC_UNIT_TX_CAPTURE_TS_W0_CPU_MAC1_TX_SEQ_ID_BIT 5 +#define CPU_MAC_UNIT_TX_CAPTURE_TS_W0_CPU_MAC1_TX_SFD_BIT 4 +#define CPU_MAC_UNIT_TX_CAPTURE_TS_W1_ADJ_RC_SECOND_BIT 0 +#define CPU_MAC_UNIT_TX_CAPTURE_TS_W2_ADJ_RC_NS_BIT 0 -#define CPU_MAC_UNIT_TX_CAPTURE_TS_W0_CPU_MAC1_TX_SEQ_ID_MASK 0x00000060 -#define CPU_MAC_UNIT_TX_CAPTURE_TS_W0_CPU_MAC1_TX_SFD_MASK 0x00000010 #define CPU_MAC_UNIT_TX_CAPTURE_TS_W0_CPU_MAC0_TX_SEQ_ID_MASK 0x00000006 #define CPU_MAC_UNIT_TX_CAPTURE_TS_W0_CPU_MAC0_TX_SFD_MASK 0x00000001 +#define CPU_MAC_UNIT_TX_CAPTURE_TS_W0_CPU_MAC1_TX_SEQ_ID_MASK 0x00000060 +#define CPU_MAC_UNIT_TX_CAPTURE_TS_W0_CPU_MAC1_TX_SFD_MASK 0x00000010 #define CPU_MAC_UNIT_TX_CAPTURE_TS_W1_ADJ_RC_SECOND_MASK 0xffffffff #define CPU_MAC_UNIT_TX_CAPTURE_TS_W2_ADJ_RC_NS_MASK 0x3fffffff -#define CTCMAC_NUM 2 -#define TX_BUF_CNT 2 +/* defing MDIOSOC_REG_BASE 0x00000000 */ + +struct MdioSoc_regs { + u32 MdioSocCmd0[2]; /* 0x00000000 */ + u32 MdioSocCmd1[2]; /* 0x00000008 */ + u32 MdioSocStatus1; /* 0x00000010 */ + u32 MdioSocStatus0; /* 0x00000014 */ + u32 MdioSocReserved; /* 0x00000018 */ + u32 MdioSocCfg0; /* 0x0000001c */ + u32 MdioSocCfg1; /* 0x00000020 */ +}; + +/* ################################################################################ + * # MdioSocCmd0 Definition + */ +#define MDIO_SOC_CMD0_W0_DATA_CMD_LANE0 0 +#define MDIO_SOC_CMD0_W0_OP_CODE_CMD_LANE0 26 +#define MDIO_SOC_CMD0_W0_PHY_ADD_CMD_LANE0 21 +#define MDIO_SOC_CMD0_W0_REG_ADD_CMD_LANE0 16 +#define MDIO_SOC_CMD0_W1_START_CMD_LANE0 0 + +#define MDIO_SOC_CMD0_W0_DATA_CMD_LANE0_MASK 0x0000ffff +#define MDIO_SOC_CMD0_W0_OP_CODE_CMD_LANE0_MASK 0x0c000000 +#define MDIO_SOC_CMD0_W0_PHY_ADD_CMD_LANE0_MASK 0x03e00000 +#define MDIO_SOC_CMD0_W0_REG_ADD_CMD_LANE0_MASK 0x001f0000 +#define MDIO_SOC_CMD0_W1_START_CMD_LANE0_MASK 0x00000003 + +/* ################################################################################ + * # MdioSocCmd1 Definition + */ +#define MDIO_SOC_CMD1_W0_DATA_CMD_LANE1 0 +#define MDIO_SOC_CMD1_W0_OP_CODE_CMD_LANE1 26 +#define MDIO_SOC_CMD1_W0_PHY_ADD_CMD_LANE1 21 +#define MDIO_SOC_CMD1_W0_REG_ADD_CMD_LANE1 16 +#define MDIO_SOC_CMD1_W1_START_CMD_LANE1 0 + +#define MDIO_SOC_CMD1_W0_DATA_CMD_LANE1_MASK 0x0000ffff +#define MDIO_SOC_CMD1_W0_OP_CODE_CMD_LANE1_MASK 0x0c000000 +#define MDIO_SOC_CMD1_W0_PHY_ADD_CMD_LANE1_MASK 0x03e00000 +#define MDIO_SOC_CMD1_W0_REG_ADD_CMD_LANE1_MASK 0x001f0000 +#define MDIO_SOC_CMD1_W1_START_CMD_LANE1_MASK 0x00000003 -#define CTCMAC_MDIO_BASE 0x33620000 -#define CTCMAC_0_BASE 0x33410000 -#define CTCMAC_1_BASE 0x33420000 +/* ################################################################################ + * # MdioSocStatus1 Definition + */ +#define MDIO_SOC_STATUS1_W0_MDIO_CMD_DONE_LANE1 16 +#define MDIO_SOC_STATUS1_W0_MDIO_READ_DATA_LANE1 0 + +#define MDIO_SOC_STATUS1_W0_MDIO_CMD_DONE_LANE1_MASK 0x00010000 +#define MDIO_SOC_STATUS1_W0_MDIO_READ_DATA_LANE1_MASK 0x0000ffff + +/* ################################################################################ + * # MdioSocStatus0 Definition + */ +#define MDIO_SOC_STATUS0_W0_MDIO_CMD_DONE_LANE0 16 +#define MDIO_SOC_STATUS0_W0_MDIO_READ_DATA_LANE0 0 + +#define MDIO_SOC_STATUS0_W0_MDIO_CMD_DONE_LANE0_MASK 0x00010000 +#define MDIO_SOC_STATUS0_W0_MDIO_READ_DATA_LANE0_MASK 0x0000ffff + +/* ################################################################################ + * # MdioSocReserved Definition + */ +#define MDIO_SOC_RESERVED_W0_RESERVED 0 + +#define MDIO_SOC_RESERVED_W0_RESERVED_MASK 0x0000ffff + +/* ################################################################################ + * # MdioSocCfg0 Definition + */ +#define MDIO_SOC_CFG0_W0_MDIO_IN_DLY_LANE0 8 +#define MDIO_SOC_CFG0_W0_MDIO_MAC_PRE_LANE0 0 + +#define MDIO_SOC_CFG0_W0_MDIO_IN_DLY_LANE0_MASK 0x00000f00 +#define MDIO_SOC_CFG0_W0_MDIO_MAC_PRE_LANE0_MASK 0x0000003f + +/* ################################################################################ + * # MdioSocCfg1 Definition + */ +#define MDIO_SOC_CFG1_W0_MDIO_IN_DLY_LANE1 8 +#define MDIO_SOC_CFG1_W0_MDIO_MAC_PRE_LANE1 0 + +#define MDIO_SOC_CFG1_W0_MDIO_IN_DLY_LANE1_MASK 0x00000f00 +#define MDIO_SOC_CFG1_W0_MDIO_MAC_PRE_LANE1_MASK 0x0000003f -#define CTCMAC_MDIO_CMD_STCODE(V) (V << 0) -#define CTCMAC_MDIO_CMD_OPCODE(V) (V << 26) -#define CTCMAC_MDIO_CMD_PHYAD(V) (V << 21) -#define CTCMAC_MDIO_CMD_REGAD(V) (V << 16) -#define CTCMAC_MDIO_CMD_DATA(V) (V << 0) +#define CTCMAC_MDIO_CMD_STCODE(V) (V<<0) +#define CTCMAC_MDIO_CMD_OPCODE(V) (V<<26) +#define CTCMAC_MDIO_CMD_PHYAD(V) (V<<21) +#define CTCMAC_MDIO_CMD_REGAD(V) (V<<16) +#define CTCMAC_MDIO_CMD_DATA(V) (V<<0) -#define CTCMAC_MDIO_STAT(V) (V << 16) +#define CTCMAC_MDIO_STAT(V) (V<<16) #endif diff --git a/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac_test.c b/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac_test.c deleted file mode 100644 index 72bbf7599ebb..000000000000 --- a/platform/centec-arm64/tsingma-bsp/src/ctcmac/ctcmac_test.c +++ /dev/null @@ -1,2116 +0,0 @@ -/* - * Centec cpu_mac Ethernet Driver For Test -- cpu_mac controller implementation - * Provides Bus interface for MIIM regs - * - * Author: liuht - * - * Copyright 2002-2018, Centec Networks (Suzhou) Co., Ltd. - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include "../pinctrl-ctc/pinctrl-ctc.h" -#include "../include/sysctl.h" -#include -#include -#include - -#include "ctcmac.h" -#include "ctcmac_reg.h" - -enum ctcmac_test_field { - CTCMAC_RING_SIZE = 0, - CTCMAC_PAYLOAD_SIZE = 1, - CTCMAC_RXTS_EN = 2, - CTCMAC_RXTS_DUMP = 3, - CTCMAC_TXTS_EN = 4, - CTCMAC_TXTS_DUMP = 5, - CTCMAC_TXINFO_VAL1 = 6, - CTCMAC_TXINFO_VAL2 = 7, - CTCMAC_TXINFO_VAL3 = 8, - CTCMAC_TXINFO_VAL4 = 9, -}; - -struct ctcmac_ptp_info { - u32 val1; - u32 val2; - u32 val3; - u32 val4; -}; - -struct ctcmac_test_param { - u32 ring_size; - u32 payload_size; - u32 rxts_en; - u32 rxts_dump; - u32 txts_en; - u32 txts_dump; - struct ctcmac_ptp_info ptp_info; -}; - -static int ctcmac_alloc_skb_resources(struct net_device *ndev); -static int ctcmac_free_skb_resources(struct ctcmac_private *priv); -static void cpumac_start(struct ctcmac_private *priv); -static void cpumac_halt(struct ctcmac_private *priv); -static void ctcmac_hw_init(struct ctcmac_private *priv); -static spinlock_t global_reglock __aligned(SMP_CACHE_BYTES); -static int g_reglock_init_done; -static int g_mac_unit_init_done; -static struct ctcmac_test_param test_param[2]; -static struct ctcmac_pkt_stats pkt_stats[2]; -static int cpumac_unit_irq_installed; -static struct regmap *regmap_base; -struct cpu_mac_unit_regs *g_cpumacu_reg; -/* get cpumac register : just for test */ -static int ctcmac_ethtool_get_eeprom(struct net_device *netdev, - struct ethtool_eeprom *ee, u8 *data) -{ - u8 *iobase; - u32 val; - unsigned long flags; - struct ctcmac_private *priv = netdev_priv(netdev); - - if (ee->offset >= 0x00010000) { - iobase = (u8 *)priv->cpumacu_reg; - ee->offset -= (0x00010000 + CPUMACUNIT_REG_BASE); - } else if (ee->offset >= 0x00004000) { - iobase = (u8 *)priv->cpumac_mem; - ee->offset -= 0x00004000; - } else { - iobase = (u8 *)priv->cpumac_reg; - } - - spin_lock_irqsave(&priv->reglock, flags); - val = readl((unsigned __iomem *)(iobase + ee->offset)); - pr_err("0x%llx : 0x%x\n", (u64)(iobase + ee->offset), val); - memcpy(data, (u8 *)&val, 4); - - spin_unlock_irqrestore(&priv->reglock, flags); - - return 0; -} - -static int ctcmac_fill_test_param(u32 index, u32 field, u32 val) -{ - if (field == CTCMAC_RING_SIZE) - test_param[index].ring_size = val; - else if (field == CTCMAC_PAYLOAD_SIZE) - test_param[index].payload_size = val; - else if (field == CTCMAC_RXTS_EN) - test_param[index].rxts_en = val; - else if (field == CTCMAC_RXTS_DUMP) - test_param[index].rxts_dump = val; - else if (field == CTCMAC_TXTS_EN) - test_param[index].txts_en = val; - else if (field == CTCMAC_TXTS_DUMP) - test_param[index].txts_dump = val; - else if (field == CTCMAC_TXINFO_VAL1) - test_param[index].ptp_info.val1 = val; - else if (field == CTCMAC_TXINFO_VAL2) - test_param[index].ptp_info.val2 = val; - else if (field == CTCMAC_TXINFO_VAL3) - test_param[index].ptp_info.val3 = val; - else if (field == CTCMAC_TXINFO_VAL4) - test_param[index].ptp_info.val4 = val; - - pr_err("test param:\n"); - pr_err("ring size : %d\n", test_param[index].ring_size); - pr_err("payload size : %d\n", test_param[index].payload_size); - pr_err("rxts en : %d\n", test_param[index].rxts_en); - pr_err("rxts dump : %d\n", test_param[index].rxts_dump); - pr_err("txts en : %d\n", test_param[index].txts_en); - pr_err("txts dump : %d\n", test_param[index].txts_dump); - pr_err("ptp info : 0x%x 0x%x 0x%x 0x%x\n", - test_param[index].ptp_info.val1, - test_param[index].ptp_info.val2, - test_param[index].ptp_info.val3, - test_param[index].ptp_info.val4); - - return 0; -} - -/* set cpumac register : just for test */ -static int ctcmac_ethtool_set_eeprom(struct net_device *netdev, - struct ethtool_eeprom *ee, u8 *data) -{ - u8 *iobase; - u32 val = 0; - unsigned long flags; - struct ctcmac_private *priv = netdev_priv(netdev); - - if (ee->offset >= 0x00030000) { - memset(&pkt_stats[priv->index], 0, - sizeof(struct ctcmac_pkt_stats)); - return 0; - } else if (ee->offset >= 0x00020000) { - val = - data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << - 24); - ctcmac_fill_test_param(priv->index, ee->offset - 0x00020000, - val); - return 0; - } else if (ee->offset >= 0x00010000) { - iobase = (u8 *)priv->cpumacu_reg; - ee->offset -= (0x00010000 + CPUMACUNIT_REG_BASE); - } else if (ee->offset >= 0x00004000) { - iobase = (u8 *)priv->cpumac_mem; - ee->offset -= 0x00004000; - } else { - iobase = (u8 *)priv->cpumac_reg; - } - - val = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24); - pr_err("0x%llx : 0x%x\n", (u64)(iobase + ee->offset), val); - spin_lock_irqsave(&priv->reglock, flags); - writel(val, (unsigned __iomem *)(iobase + ee->offset)); - spin_unlock_irqrestore(&priv->reglock, flags); - - return 0; -} - -static void ctcmac_ethtool_get_stats(struct net_device *netdev, - struct ethtool_regs *regs, void *regbuf) -{ - u32 mtu; - unsigned long flags; - struct ctcmac_pkt_stats *stats; - struct ctcmac_private *priv = netdev_priv(netdev); - - spin_lock_irqsave(&priv->reglock, flags); - stats = &pkt_stats[priv->index]; - stats->rx_good_ucast_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_0[0]); - stats->rx_good_ucast_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_0[2]); - stats->rx_good_mcast_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_1[0]); - stats->rx_good_mcast_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_1[2]); - stats->rx_good_bcast_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_2[0]); - stats->rx_good_bcast_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_2[2]); - stats->rx_good_pause_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_3[0]); - stats->rx_good_pause_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_3[2]); - stats->rx_good_pfc_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_4[0]); - stats->rx_good_pfc_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_4[2]); - stats->rx_good_control_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_5[0]); - stats->rx_good_control_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_5[2]); - stats->rx_fcs_error_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_6[0]); - stats->rx_fcs_error_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_6[2]); - stats->rx_mac_overrun_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_7[0]); - stats->rx_mac_overrun_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_7[2]); - stats->rx_good_63B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_8[0]); - stats->rx_good_63B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_8[2]); - stats->rx_bad_63B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_9[0]); - stats->rx_bad_63B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_9[2]); - stats->rx_good_mtu2B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_10[0]); - stats->rx_good_mtu2B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_10[2]); - stats->rx_bad_mtu2B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_11[0]); - stats->rx_bad_mtu2B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_11[2]); - stats->rx_good_jumbo_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_12[0]); - stats->rx_good_jumbo_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_12[2]); - stats->rx_bad_jumbo_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_13[0]); - stats->rx_bad_jumbo_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_13[2]); - stats->rx_64B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_14[0]); - stats->rx_64B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_14[2]); - stats->rx_127B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_15[0]); - stats->rx_127B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_15[2]); - stats->rx_255B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_16[0]); - stats->rx_255B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_16[2]); - stats->rx_511B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_17[0]); - stats->rx_511B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_17[2]); - stats->rx_1023B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_18[0]); - stats->rx_1023B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_18[2]); - stats->rx_mtu1B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_19[0]); - stats->rx_mtu1B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_19[2]); - stats->tx_ucast_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_20[0]); - stats->tx_ucast_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_20[2]); - stats->tx_mcast_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_21[0]); - stats->tx_mcast_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_21[2]); - stats->tx_bcast_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_22[0]); - stats->tx_bcast_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_22[2]); - stats->tx_pause_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_23[0]); - stats->tx_pause_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_23[2]); - stats->tx_control_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_24[0]); - stats->tx_control_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_24[2]); - stats->tx_fcs_error_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_25[0]); - stats->tx_fcs_error_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_25[2]); - stats->tx_underrun_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_26[0]); - stats->tx_underrun_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_26[2]); - stats->tx_63B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_27[0]); - stats->tx_63B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_27[2]); - stats->tx_64B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_28[0]); - stats->tx_64B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_28[2]); - stats->tx_127B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_29[0]); - stats->tx_127B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_29[2]); - stats->tx_255B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_30[0]); - stats->tx_255B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_30[2]); - stats->tx_511B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_31[0]); - stats->tx_511B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_31[2]); - stats->tx_1023B_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_32[0]); - stats->tx_1023B_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_32[2]); - stats->tx_mtu1_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_33[0]); - stats->tx_mtu1_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_33[2]); - stats->tx_mtu2_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_34[0]); - stats->tx_mtu2_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_34[2]); - stats->tx_jumbo_bytes += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_35[0]); - stats->tx_jumbo_pkt += - readq(&priv->cpumac_mem->cpu_mac_stats_ram_35[2]); - mtu = readl(&priv->cpumac_reg->cpu_mac_stats_cfg[1]); - stats->mtu1 = mtu & 0x3fff; - stats->mtu2 = (mtu >> 16) & 0x3fff; - spin_unlock_irqrestore(&priv->reglock, flags); - - memcpy(regbuf, (void *)stats, sizeof(struct ctcmac_pkt_stats)); -} - -static int ctcmac_ethtool_get_eeprom_len(struct net_device *netdev) -{ - return 0x40000; -} - -static int ctcmac_ethtool_get_regs_len(struct net_device *netdev) -{ - return sizeof(struct ctcmac_pkt_stats); -} - -const struct ethtool_ops ctcmac_ethtool_test_ops = { - .get_eeprom = ctcmac_ethtool_get_eeprom, - .set_eeprom = ctcmac_ethtool_set_eeprom, - .get_eeprom_len = ctcmac_ethtool_get_eeprom_len, - .get_regs = ctcmac_ethtool_get_stats, - .get_regs_len = ctcmac_ethtool_get_regs_len, -}; - -static void clrsetbits(unsigned __iomem *addr, u32 clr, u32 set) -{ - writel((readl(addr) & ~(clr)) | (set), addr); -} - -static u32 ctcmac_regr(unsigned __iomem *addr) -{ - u32 val; - - val = readl(addr); - return val; -} - -static void ctcmac_regw(unsigned __iomem *addr, u32 val) -{ - writel(val, addr); -} - -static inline int ctcmac_rxbd_unused(struct ctcmac_priv_rx_q *rxq) -{ - if (rxq->next_to_clean > rxq->next_to_use) - return rxq->next_to_clean - rxq->next_to_use - 1; - - return rxq->rx_ring_size + rxq->next_to_clean - rxq->next_to_use - 1; -} - -static int ctcmac_alloc_tx_queues(struct ctcmac_private *priv) -{ - int i; - - for (i = 0; i < priv->num_tx_queues; i++) { - priv->tx_queue[i] = kzalloc(sizeof(*priv->tx_queue[i]), - GFP_KERNEL); - if (!priv->tx_queue[i]) - return -ENOMEM; - - priv->tx_queue[i]->tx_skbuff = NULL; - priv->tx_queue[i]->qindex = i; - priv->tx_queue[i]->dev = priv->ndev; - spin_lock_init(&priv->tx_queue[i]->txlock); - } - return 0; -} - -static int ctcmac_alloc_rx_queues(struct ctcmac_private *priv) -{ - int i; - - for (i = 0; i < priv->num_rx_queues; i++) { - priv->rx_queue[i] = kzalloc(sizeof(*priv->rx_queue[i]), - GFP_KERNEL); - if (!priv->rx_queue[i]) - return -ENOMEM; - - priv->rx_queue[i]->qindex = i; - priv->rx_queue[i]->ndev = priv->ndev; - } - return 0; -} - -static void ctcmac_unmap_io_space(struct ctcmac_private *priv) -{ - if (priv->iobase) - iounmap(priv->iobase); -} - -static void ctcmac_free_tx_queues(struct ctcmac_private *priv) -{ - int i; - - for (i = 0; i < priv->num_tx_queues; i++) - kfree(priv->tx_queue[i]); -} - -static void ctcmac_free_rx_queues(struct ctcmac_private *priv) -{ - int i; - - for (i = 0; i < priv->num_rx_queues; i++) - kfree(priv->rx_queue[i]); -} - -static void ctcmac_free_dev(struct ctcmac_private *priv) -{ - if (priv->ndev) - free_netdev(priv->ndev); -} - -static int ctcmac_of_init(struct platform_device *ofdev, - struct net_device **pdev) -{ - int err = 0, index; - const char *ctype; - struct net_device *dev = NULL; - struct ctcmac_private *priv = NULL; - unsigned int num_tx_qs, num_rx_qs; - struct device_node *np = ofdev->dev.of_node; - - num_tx_qs = CTCMAC_TX_QUEUE_MAX; - num_rx_qs = CTCMAC_RX_QUEUE_MAX; - - *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); - dev = *pdev; - if (!dev) - return -ENOMEM; - - priv = netdev_priv(dev); - priv->ndev = dev; - priv->ofdev = ofdev; - priv->dev = &ofdev->dev; - priv->dev->coherent_dma_mask = DMA_BIT_MASK(64); - priv->num_tx_queues = num_tx_qs; - netif_set_real_num_rx_queues(dev, num_rx_qs); - priv->num_rx_queues = num_rx_qs; - - priv->iobase = of_iomap(np, 0); - priv->cpumac_reg = priv->iobase + CPUMAC_REG_BASE; - priv->cpumac_mem = priv->iobase + CPUMAC_MEM_BASE; - priv->cpumacu_reg = of_iomap(np, 1) + CPUMACUNIT_REG_BASE; - g_cpumacu_reg = priv->cpumacu_reg; - - err = of_property_read_u32(np, "index", &index); - if (err == 0) - priv->index = index; - else - priv->index = 0; - - err = of_property_read_string(np, "phy-connection-type", &ctype); - if (err == 0 && !strncmp(ctype, "sgmii", 5)) - priv->interface = PHY_INTERFACE_MODE_SGMII; - else - priv->interface = PHY_INTERFACE_MODE_MII; - - priv->supported = SUPPORTED_10baseT_Full | SUPPORTED_10baseT_Half; - err = of_property_read_string(np, "capability-100M", &ctype); - if (err == 0 && !strncmp(ctype, "support", 7)) - priv->supported |= - SUPPORTED_100baseT_Full | SUPPORTED_100baseT_Half; - - err = of_property_read_string(np, "capability-1000M", &ctype); - if (err == 0 && !strncmp(ctype, "support", 7)) - priv->supported |= SUPPORTED_1000baseT_Full; - - priv->phy_node = of_parse_phandle(np, "phy-handle", 0); - - priv->irqinfo[CTCMAC_NORMAL].irq = irq_of_parse_and_map(np, 0); - priv->irqinfo[CTCMAC_FUNC].irq = irq_of_parse_and_map(np, 1); - priv->irqinfo[CTCMAC_UNIT].irq = irq_of_parse_and_map(np, 2); - - return 0; -} - -static int startup_ctcmac(struct net_device *ndev) -{ - int i; - int err; - struct ctcmac_private *priv = netdev_priv(ndev); - - if (ctcmac_alloc_tx_queues(priv)) - return -1; - - if (ctcmac_alloc_rx_queues(priv)) - return -1; - - /* Initializing some of the rx/tx queue level parameters */ - for (i = 0; i < priv->num_tx_queues; i++) { - priv->tx_queue[i]->tx_ring_size = - test_param[priv->index].ring_size; - priv->tx_queue[i]->num_txbdfree = - test_param[priv->index].ring_size; - } - - for (i = 0; i < priv->num_rx_queues; i++) { - priv->rx_queue[i]->rx_ring_size = - test_param[priv->index].ring_size; - } - - ctcmac_hw_init(priv); - - err = ctcmac_alloc_skb_resources(ndev); - if (err) - return err; - - /* barrier */ - smp_mb__before_atomic(); - clear_bit(CTCMAC_DOWN, &priv->state); - /* barrier */ - smp_mb__after_atomic(); - - cpumac_start(priv); - /* force link state update after mac reset */ - priv->oldlink = 0; - priv->oldspeed = 0; - priv->oldduplex = -1; - - phy_start(ndev->phydev); - - napi_enable(&priv->napi_rx); - napi_enable(&priv->napi_tx); - - netif_tx_wake_all_queues(ndev); - - return 0; -} - -static void stop_ctcmac(struct net_device *ndev) -{ - struct ctcmac_private *priv = netdev_priv(ndev); - - /* disable ints and gracefully shut down Rx/Tx DMA */ - cpumac_halt(priv); - - netif_tx_stop_all_queues(ndev); - - /* barrier */ - smp_mb__before_atomic(); - set_bit(CTCMAC_DOWN, &priv->state); - /* barrier */ - smp_mb__after_atomic(); - napi_disable(&priv->napi_rx); - napi_disable(&priv->napi_tx); - phy_stop(ndev->phydev); - ctcmac_free_skb_resources(priv); -} - -static void ctcmac_reset(struct net_device *ndev) -{ - struct ctcmac_private *priv = netdev_priv(ndev); - - while (test_and_set_bit_lock(CTCMAC_RESETTING, &priv->state)) - cpu_relax(); - - stop_ctcmac(ndev); - startup_ctcmac(ndev); - clear_bit_unlock(CTCMAC_RESETTING, &priv->state); -} - -/* ctcmac_reset_task gets scheduled when a packet has not been - * transmitted after a set amount of time. - * For now, assume that clearing out all the structures, and - * starting over will fix the problem. - */ -static void ctcmac_reset_task(struct work_struct *work) -{ - struct ctcmac_private *priv = container_of(work, struct ctcmac_private, - reset_task); - - ctcmac_reset(priv->ndev); -} - -static int ctcmac_rxbd_used_untreated(struct ctcmac_private *priv, int qidx) -{ - u32 count; - - if (qidx) { - count = readl(&priv->cpumac_reg->cpu_mac_desc_mon[2]); - return count & 0xffff; - } - - count = readl(&priv->cpumac_reg->cpu_mac_desc_mon[1]); - - return (count >> 16) & 0xffff; -} - -static int ctcmac_txbd_used_untreated(struct ctcmac_private *priv) -{ - u32 count; - - count = readl(&priv->cpumac_reg->cpu_mac_desc_mon[2]); - - return (count >> 16) & 0xffff; -} - -static bool ctcmac_add_rx_frag(struct ctcmac_rx_buff *rxb, u32 lstatus, - struct sk_buff *skb, bool first) -{ - struct page *page = rxb->page; - unsigned int size = - (lstatus & CPU_MAC_DESC_INTF_W1_DESC_SIZE_MASK) >> 8; - - if (likely(first)) { - skb_put(skb, size); - } else { - skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, - rxb->page_offset, size, CTCMAC_RXB_TRUESIZE); - } - - /* try reuse page */ - if (unlikely(page_count(page) != 1)) - return false; - - /* change offset to the other half */ - rxb->page_offset ^= CTCMAC_RXB_TRUESIZE; - - page_ref_inc(page); - - return true; -} - -static void ctcmac_reuse_rx_page(struct ctcmac_priv_rx_q *rxq, - struct ctcmac_rx_buff *old_rxb) -{ - struct ctcmac_rx_buff *new_rxb; - u16 nta = rxq->next_to_alloc; - - new_rxb = &rxq->rx_buff[nta]; - - /* find next buf that can reuse a page */ - nta++; - rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0; - - /* copy page reference */ - *new_rxb = *old_rxb; - - /* sync for use by the device */ - dma_sync_single_range_for_device(rxq->dev, old_rxb->dma, - old_rxb->page_offset, - CTCMAC_RXB_TRUESIZE, DMA_FROM_DEVICE); -} - -static struct sk_buff *ctcmac_get_next_rxbuff(struct ctcmac_priv_rx_q *rx_queue, - u32 lstatus, struct sk_buff *skb) -{ - struct ctcmac_rx_buff *rxb = - &rx_queue->rx_buff[rx_queue->next_to_clean]; - struct page *page = rxb->page; - bool first = false; - - if (likely(!skb)) { - void *buff_addr = page_address(page) + rxb->page_offset; - - skb = build_skb(buff_addr, CTCMAC_SKBFRAG_SIZE); - if (unlikely(!skb)) - return NULL; - first = true; - } - - dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset, - CTCMAC_RXB_TRUESIZE, DMA_FROM_DEVICE); - - if (ctcmac_add_rx_frag(rxb, lstatus, skb, first)) { - /* reuse the free half of the page */ - ctcmac_reuse_rx_page(rx_queue, rxb); - } else { - /* page cannot be reused, unmap it */ - dma_unmap_page(rx_queue->dev, rxb->dma, - PAGE_SIZE, DMA_FROM_DEVICE); - } - - /* clear rxb content */ - rxb->page = NULL; - - return skb; -} - -static void ctcmac_process_frame(struct net_device *ndev, struct sk_buff *skb) -{ - struct ctcmac_private *priv = netdev_priv(ndev); - - if (test_param[priv->index].rxts_en) { - struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); - u64 *ns = (u64 *)(skb->data + skb->len - 8); - - if (test_param[priv->index].rxts_dump) - pr_err("receive frame time stamp 0x%llx\n", *ns); - - memset(shhwtstamps, 0, sizeof(*shhwtstamps)); - shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns)); - skb_pull(skb, 8); - if (test_param[priv->index].rxts_dump) { - pr_err("receive frame time stamp %lld\n", - shhwtstamps->hwtstamp); - } - } - - skb->protocol = eth_type_trans(skb, ndev); -} - -static int ctc_mac_serdes_init(struct ctcmac_private *priv) -{ - int ret = 0; - u32 status; - int delay_ms = 10; - - /* reset serdes */ - writel(0x83806000, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[0]); - writel(0x28061800, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[2]); - writel(0x0026c03a, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[6]); - writel(0x28061810, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[8]); - writel(0x0026c03a, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[12]); - - /* offset0 bit1 BlkRstN */ - writel(0x83806002, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[0]); - mdelay(delay_ms); - - writel(0x80002309, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x80000842, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x8000ea45, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - - /* serdes 0 init */ - writel(0x83000a05, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x83002008, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x8300640f, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x83000214, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x83008015, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x83000116, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x83001817, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x83003018, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x83000e24, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x83008226, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x83001f27, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x83002028, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x83002829, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x8300302a, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x83002038, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x8300223a, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x8300523b, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x83002040, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x8300f141, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x8300014a, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x8300e693, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - - /* serdes 1 init */ - writel(0x84000a05, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x84002008, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x8400640f, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x84000214, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x84008015, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x84000116, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x84001817, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x84003018, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x84000e24, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x84008226, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x84001f27, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x84002028, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x84002829, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x8400302a, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x84002038, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x8400223a, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x8400523b, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x84002040, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x8400f141, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x8400014a, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - mdelay(delay_ms); - writel(0x8400e693, &priv->cpumacu_reg->cpu_mac_unit_hss_reg_acc_ctl); - - /* serdes post release */ - writel(0x83806003, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[0]); - writel(0x83826003, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[0]); - - writel(0x28061801, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[2]); - writel(0x28061c01, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[2]); - writel(0x28071c01, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[2]); - - writel(0x28061811, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[8]); - writel(0x28061c11, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[8]); - writel(0x28071c11, &priv->cpumacu_reg->cpu_mac_unit_hss_cfg[8]); - - ret = - readl_poll_timeout(&priv->cpumacu_reg->cpu_mac_unit_hss_mon[1], - status, - status & - CPU_MAC_UNIT_HSS_MON_W1_MON_HSS_L0_DFE_RST_DONE, - 1000, 2000000); - if (ret) { - netdev_dbg(priv->ndev, - "%s:wait for hss reset done fail with cpu_mac_unit_hss_mon[1]:0x%x\n", - priv->ndev->name, - readl(&priv->cpumacu_reg->cpu_mac_unit_hss_mon[1])); - } - mdelay(delay_ms); - - return 0; -} - -static void ctcmac_hw_init(struct ctcmac_private *priv) -{ - int i; - u32 val; - int use_extram = 0; - - /* two cpumac access the same cpumac unit register */ - spin_lock_irq(&global_reglock); - if (priv->index == 0) { - clrsetbits(&priv->cpumacu_reg->cpu_mac_unit_reset_ctl, - CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_BASE, - CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC0); - clrsetbits(&priv->cpumacu_reg->cpu_mac_unit_reset_ctl, - CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC0, 0); - } else { - clrsetbits(&priv->cpumacu_reg->cpu_mac_unit_reset_ctl, - CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_BASE, - CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC1); - clrsetbits(&priv->cpumacu_reg->cpu_mac_unit_reset_ctl, - CPU_MAC_UNIT_RESET_CTL_W0_RESET_CORE_CPU_MAC1, 0); - } - - clrsetbits(&priv->cpumacu_reg->cpu_mac_unit_ts_cfg, - 0, CPU_MAC_UNIT_TS_CFG_W0_CFG_FORCE_S_AND_NS_EN); - - spin_unlock_irq(&global_reglock); - mdelay(10); - - clrsetbits(&priv->cpumac_reg->cpu_mac_init, 0, - CPU_MAC_INIT_DONE_W0_INIT_DONE); - udelay(1); - - if (priv->interface == PHY_INTERFACE_MODE_SGMII) { - /* switch to sgmii and enable auto nego */ - val = readl(&priv->cpumac_reg->cpu_mac_sgmii_auto_neg_cfg); - val &= ~(CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_ENABLE_MASK - | CPU_MAC_SGMII_AUTO_NEG_CFG_W0_CFG_AN_MODE_MASK); - val |= (CSA_SGMII_MD_MASK | CSA_EN); - writel(val, &priv->cpumac_reg->cpu_mac_sgmii_auto_neg_cfg); - } - - clrsetbits(&priv->cpumac_reg->cpu_mac_sgmii_cfg[0], - CPU_MAC_SGMII_CFG_W0_CFG_MII_RX_LINK_FILTER_EN, 0); - clrsetbits(&priv->cpumac_reg->cpu_mac_sgmii_cfg[0], - 0, CPU_MAC_SGMII_CFG_W0_CFG_TX_EVEN_IGNORE); - - clrsetbits(&priv->cpumac_reg->cpu_mac_axi_cfg, - 0, CPU_MAC_AXI_CFG_W0_CFG_AXI_RD_D_WORD_SWAP_EN); - clrsetbits(&priv->cpumac_reg->cpu_mac_axi_cfg, - 0, CPU_MAC_AXI_CFG_W0_CFG_AXI_WR_D_WORD_SWAP_EN); - - clrsetbits(&priv->cpumac_reg->cpu_mac_gmac_cfg[0], - 0, CPU_MAC_GMAC_CFG_W0_CFG_RX_OVERRUN_DROP_EN - | CPU_MAC_GMAC_CFG_W0_CFG_RX_OVERSIZE_DROP_EN); - - clrsetbits(&priv->cpumac_reg->cpu_mac_gmac_cfg[2], - CPU_MAC_GMAC_CFG_W2_CFG_TX_STRIP_CRC_EN, 0); - - clrsetbits(&priv->cpumac_reg->cpu_mac_gmac_cfg[2], - 0, CPU_MAC_GMAC_CFG_W2_CFG_TX_CUT_THROUGH_EN); - - for (i = 0; i < priv->num_tx_queues; i++) { - if (priv->tx_queue[i]->tx_ring_size > - CTCMAC_INTERNAL_RING_SIZE) { - use_extram = 1; - break; - } - } - - for (i = 0; i < priv->num_rx_queues; i++) { - if (priv->rx_queue[i]->rx_ring_size > - CTCMAC_INTERNAL_RING_SIZE) { - use_extram = 1; - break; - } - } - - if (use_extram) { - spin_lock_irq(&global_reglock); - regmap_read(regmap_base, - offsetof(struct SysCtl_regs, SysMemCtl), &val); - val |= SYS_MEM_CTL_W0_CFG_RAM_MUX_EN; - regmap_write(regmap_base, - offsetof(struct SysCtl_regs, SysMemCtl), val); - spin_unlock_irq(&global_reglock); - if (priv->index == 0) { - ctcmac_regw(&priv->cpumac_reg->cpu_mac_ext_ram_cfg[1], - CTCMAC0_EXSRAM_BASE); - } else { - ctcmac_regw(&priv->cpumac_reg->cpu_mac_ext_ram_cfg[1], - CTCMAC1_EXSRAM_BASE); - } - ctcmac_regw(&priv->cpumac_reg->cpu_mac_ext_ram_cfg[0], - test_param[priv->index].ring_size); - clrsetbits(&priv->cpumac_reg->cpu_mac_ext_ram_cfg[0], 0, - CPU_MAC_EXT_RAM_CFG_W0_CFG_EXT_RAM_EN); - - } else { - clrsetbits(&priv->cpumac_reg->cpu_mac_ext_ram_cfg[0], - CPU_MAC_EXT_RAM_CFG_W0_CFG_EXT_RAM_EN, 0); - spin_lock_irq(&global_reglock); - regmap_read(regmap_base, - offsetof(struct SysCtl_regs, SysMemCtl), &val); - val &= ~SYS_MEM_CTL_W0_CFG_RAM_MUX_EN; - regmap_write(regmap_base, - offsetof(struct SysCtl_regs, SysMemCtl), val); - spin_unlock_irq(&global_reglock); - } - - if (test_param[priv->index].rxts_en) { - clrsetbits(&priv->cpumac_reg->cpu_mac_gmac_cfg[0], - 0, CPU_MAC_GMAC_CFG_W0_CFG_RX_TS_EN); - } - - if (test_param[priv->index].txts_en) { - clrsetbits(&priv->cpumac_reg->cpu_mac_gmac_cfg[2], - CPU_MAC_GMAC_CFG_W2_CFG_TX_WAIT_CAPTURE_TS, - CPU_MAC_GMAC_CFG_W2_CFG_TX_HDR_INFO_EN); - } - - /* clear all interrupt */ - ctcmac_regw(&priv->cpumac_reg->cpu_mac_interrupt_func[1], 0xffffffff); - ctcmac_regw(&priv->cpumac_reg->cpu_mac_interrupt_normal[1], 0xffffffff); - /* mask all interrupt */ - ctcmac_regw(&priv->cpumac_reg->cpu_mac_interrupt_func[2], 0xffffffff); - ctcmac_regw(&priv->cpumac_reg->cpu_mac_interrupt_normal[2], 0xffffffff); - - pr_err("%s ctcmac_hw_init 0x%x\n", __func__, priv->ndev->flags); -} - -/* update cpumac speed when phy linkup speed changed */ -static noinline void ctcmac_update_link_state(struct ctcmac_private *priv, - struct phy_device *phydev) -{ - int timeout = 2000; - u32 mon, cfg_rep, cfg_smp; - int speed = phydev->speed; - - if (priv->interface != PHY_INTERFACE_MODE_SGMII) - return; - - if (netif_msg_link(priv)) - netdev_dbg(priv->ndev, "link up speed is %d\n", speed); - - if (phydev->link) { - cfg_rep = readl(&priv->cpumac_reg->cpu_mac_sgmii_cfg[0]); - cfg_smp = readl(&priv->cpumac_reg->cpu_mac_sgmii_cfg[1]); - cfg_rep &= ~CSC_REP_MASK; - cfg_smp &= ~CSC_SMP_MASK; - if (speed == 1000) { - cfg_rep |= CSC_1000M; - cfg_smp |= CSC_1000M; - } else if (speed == 100) { - cfg_rep |= CSC_100M; - cfg_smp |= CSC_100M; - } else if (speed == 10) { - cfg_rep |= CSC_10M; - cfg_smp |= CSC_10M; - } else { - return; - } - writel(cfg_rep, &priv->cpumac_reg->cpu_mac_sgmii_cfg[0]); - writel(cfg_smp, &priv->cpumac_reg->cpu_mac_sgmii_cfg[1]); - - while (timeout--) { - mon = readl(&priv->cpumac_reg->cpu_mac_sgmii_mon[0]); - if ((mon & CSM_ANST_MASK) == 6) - break; - - mdelay(1); - } - - if ((mon & CSM_ANST_MASK) != 6) { - pr_err("Error! when phy link up, auto-neg status %d is not right.\n", - mon); - } - if (!priv->oldlink) - priv->oldlink = 1; - - } else { - priv->oldlink = 0; - priv->oldspeed = 0; - priv->oldduplex = -1; - } -} - -static void adjust_link(struct net_device *dev) -{ - struct ctcmac_private *priv = netdev_priv(dev); - struct phy_device *phydev = dev->phydev; - - if (unlikely(phydev->link != priv->oldlink || - (phydev->link && (phydev->duplex != priv->oldduplex || - phydev->speed != priv->oldspeed)))) - ctcmac_update_link_state(priv, phydev); -} - -/* Initializes driver's PHY state, and attaches to the PHY. - * Returns 0 on success. - */ -static int ctcmac_init_phy(struct net_device *dev) -{ - struct ctcmac_private *priv = netdev_priv(dev); - phy_interface_t interface; - struct phy_device *phydev; - - priv->oldlink = 0; - priv->oldspeed = 0; - priv->oldduplex = -1; - - interface = priv->interface; - - phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, - interface); - if (!phydev) { - dev_err(&dev->dev, "could not attach to PHY\n"); - return -ENODEV; - } - - /* Remove any features not supported by the controller */ - phydev->supported = priv->supported; - phydev->advertising = phydev->supported; - - return 0; -} - -static irqreturn_t ctcmac_receive(int irq, struct ctcmac_private *priv) -{ - unsigned long flags; - - if (likely(napi_schedule_prep(&priv->napi_rx))) { - /* disable interrupt */ - spin_lock_irqsave(&priv->reglock, flags); - writel(CTCMAC_NOR_RX0_D | CTCMAC_NOR_RX1_D, - &priv->cpumac_reg->cpu_mac_interrupt_func[2]); - spin_unlock_irqrestore(&priv->reglock, flags); - __napi_schedule(&priv->napi_rx); - } else { - /* clear interrupt */ - writel(CTCMAC_NOR_RX0_D | CTCMAC_NOR_RX1_D, - &priv->cpumac_reg->cpu_mac_interrupt_func[1]); - } - - return IRQ_HANDLED; -} - -static irqreturn_t ctcmac_transmit(int irq, struct ctcmac_private *priv) -{ - unsigned long flags; - - if (likely(napi_schedule_prep(&priv->napi_tx))) { - /* disable interrupt */ - spin_lock_irqsave(&priv->reglock, flags); - writel(CTCMAC_NOR_TX_D, - &priv->cpumac_reg->cpu_mac_interrupt_func[2]); - spin_unlock_irqrestore(&priv->reglock, flags); - __napi_schedule(&priv->napi_tx); - - } else { - /* clear interrupt */ - writel(CTCMAC_NOR_TX_D, - &priv->cpumac_reg->cpu_mac_interrupt_func[1]); - } - - return IRQ_HANDLED; -} - -static irqreturn_t ctcmac_func(int irq, void *data) -{ - u32 event, stat, mask; - struct ctcmac_private *priv = (struct ctcmac_private *)data; - - stat = ctcmac_regr(&priv->cpumac_reg->cpu_mac_interrupt_func[0]); - mask = ctcmac_regr(&priv->cpumac_reg->cpu_mac_interrupt_func[2]); - event = stat & ~mask; - - if ((event & CTCMAC_NOR_RX0_D) || (event & CTCMAC_NOR_RX1_D)) - ctcmac_receive(irq, priv); - - if (event & CTCMAC_NOR_TX_D) - ctcmac_transmit(irq, priv); - - return IRQ_HANDLED; -} - -static irqreturn_t ctcmac_unit(int irq, void *data) -{ - struct cpu_mac_unit_mems *mems = - (struct cpu_mac_unit_mems *)(g_cpumacu_reg + 0x400 - - CPUMACUNIT_REG_BASE); - - ctcmac_regw(&g_cpumacu_reg->cpu_mac_unit_interrupt_func[2], 1); - ctcmac_regw(&g_cpumacu_reg->cpu_mac_unit_interrupt_func[1], 1); - - while (ctcmac_regr(&g_cpumacu_reg->cpu_mac_unit_fifo_status)) { - pr_err("Tx Capture time stamp in fifo 0x%x 0x%x 0x%x\n", - ctcmac_regr(&mems->cpu_mac_unit_tx_capture_ts_0[0]), - ctcmac_regr(&mems->cpu_mac_unit_tx_capture_ts_0[1]), - ctcmac_regr(&mems->cpu_mac_unit_tx_capture_ts_0[2])); - } - ctcmac_regw(&g_cpumacu_reg->cpu_mac_unit_interrupt_func[3], 1); - - return IRQ_HANDLED; -} - -static irqreturn_t ctcmac_normal(int irq, void *grp_id) //TODO by liuht -{ - return IRQ_HANDLED; -} - -static int ctcmac_request_irq(struct ctcmac_private *priv) -{ - int err = 0; - - err = request_irq(priv->irqinfo[CTCMAC_NORMAL].irq, ctcmac_normal, 0, - priv->irqinfo[CTCMAC_NORMAL].name, priv); - if (err < 0) - free_irq(priv->irqinfo[CTCMAC_NORMAL].irq, priv); - enable_irq_wake(priv->irqinfo[CTCMAC_NORMAL].irq); - - err = request_irq(priv->irqinfo[CTCMAC_FUNC].irq, ctcmac_func, 0, - priv->irqinfo[CTCMAC_FUNC].name, priv); - if (err < 0) - free_irq(priv->irqinfo[CTCMAC_FUNC].irq, priv); - enable_irq_wake(priv->irqinfo[CTCMAC_FUNC].irq); - - spin_lock_irq(&global_reglock); - if (priv->irqinfo[CTCMAC_UNIT].irq && !cpumac_unit_irq_installed) { - err = - request_irq(priv->irqinfo[CTCMAC_UNIT].irq, ctcmac_unit, 0, - "cpumac_unit", NULL); - if (err < 0) { - free_irq(priv->irqinfo[CTCMAC_UNIT].irq, NULL); - return err; - } - enable_irq_wake(priv->irqinfo[CTCMAC_UNIT].irq); - cpumac_unit_irq_installed = 1; - } - spin_unlock_irq(&global_reglock); - - return err; -} - -static void ctcmac_free_irq(struct ctcmac_private *priv) -{ - free_irq(priv->irqinfo[CTCMAC_NORMAL].irq, priv); - free_irq(priv->irqinfo[CTCMAC_FUNC].irq, priv); - - spin_lock_irq(&global_reglock); - if (cpumac_unit_irq_installed == 1) { - free_irq(priv->irqinfo[CTCMAC_UNIT].irq, NULL); - cpumac_unit_irq_installed = 0; - } - spin_unlock_irq(&global_reglock); -} - -static bool ctcmac_new_page(struct ctcmac_priv_rx_q *rxq, - struct ctcmac_rx_buff *rxb) -{ - struct page *page; - dma_addr_t addr; - - page = dev_alloc_page(); - if (unlikely(!page)) - return false; - - addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); - if (unlikely(dma_mapping_error(rxq->dev, addr))) { - __free_page(page); - - return false; - } - - rxb->dma = addr; - rxb->page = page; - rxb->page_offset = 0; - - return true; -} - -static void ctcmac_fill_rxbd(struct ctcmac_private *priv, - struct ctcmac_rx_buff *rxb, int qidx) -{ - u32 desc_cfg_low, desc_cfg_high; - dma_addr_t bufaddr = rxb->dma + rxb->page_offset; - - desc_cfg_low = - (bufaddr - CTC_DDR_BASE) & CPU_MAC_DESC_INTF_W0_DESC_ADDR_31_0_MASK; - /* CPU_MAC_DESC_INTF_W1_DESC_SIZE:bit(8) */ - desc_cfg_high = (test_param[priv->index].payload_size << 8) | - (((bufaddr - - CTC_DDR_BASE) >> 32) & - CPU_MAC_DESC_INTF_W1_DESC_ADDR_39_32_MASK); - - spin_lock_irq(&priv->reglock); - if (qidx) { - ctcmac_regw(&priv->cpumac_mem->cpu_mac_desc_intf_1[0], - desc_cfg_low); - /* barrier */ - smp_mb__before_atomic(); - ctcmac_regw(&priv->cpumac_mem->cpu_mac_desc_intf_1[1], - desc_cfg_high); - - } else { - ctcmac_regw(&priv->cpumac_mem->cpu_mac_desc_intf_0[0], - desc_cfg_low); - /* barrier */ - smp_mb__before_atomic(); - ctcmac_regw(&priv->cpumac_mem->cpu_mac_desc_intf_0[1], - desc_cfg_high); - } - - spin_unlock_irq(&priv->reglock); -} - -static void ctcmac_fill_txbd(struct ctcmac_private *priv, - struct ctcmac_desc_cfg *txdesc) -{ - u32 desc_cfg_low, desc_cfg_high; - - desc_cfg_low = txdesc->addr_low; - /* CPU_MAC_DESC_INTF_W1_DESC_SIZE:bit(8) */ - /* CPU_MAC_DESC_INTF_W1_DESC_SOP:bit(22) */ - /* CPU_MAC_DESC_INTF_W1_DESC_EOP:bit(23) */ - desc_cfg_high = txdesc->addr_high | - (txdesc->size << 8) | (txdesc->sop << 22) | (txdesc->eop << 23); - - spin_lock_irq(&priv->reglock); - ctcmac_regw(&priv->cpumac_mem->cpu_mac_desc_intf_2[0], desc_cfg_low); - /* barrier */ - smp_mb__before_atomic(); - ctcmac_regw(&priv->cpumac_mem->cpu_mac_desc_intf_2[1], desc_cfg_high); - spin_unlock_irq(&priv->reglock); -} - -static void ctcmac_get_txbd(struct ctcmac_private *priv) -{ - u32 lstatus; - - spin_lock_irq(&priv->reglock); - lstatus = ctcmac_regr(&priv->cpumac_mem->cpu_mac_desc_intf_2[0]); - /* barrier */ - smp_mb__before_atomic(); - lstatus = ctcmac_regr(&priv->cpumac_mem->cpu_mac_desc_intf_2[1]); - - spin_unlock_irq(&priv->reglock); -} - -static void ctcmac_get_rxbd(struct ctcmac_private *priv, u32 *lstatus, - int qidx) -{ - spin_lock_irq(&priv->reglock); - if (qidx) { - ctcmac_regr(&priv->cpumac_mem->cpu_mac_desc_intf_1[0]); - *lstatus = - ctcmac_regr(&priv->cpumac_mem->cpu_mac_desc_intf_1[1]); - } else { - ctcmac_regr(&priv->cpumac_mem->cpu_mac_desc_intf_0[0]); - *lstatus = - ctcmac_regr(&priv->cpumac_mem->cpu_mac_desc_intf_0[1]); - } - /* barrier */ - smp_mb__before_atomic(); - - spin_unlock_irq(&priv->reglock); -} - -static void ctcmac_alloc_rx_buffs(struct ctcmac_priv_rx_q *rx_queue, - int alloc_cnt) -{ - int i; - int qidx = rx_queue->qindex; - struct ctcmac_rx_buff *rxb; - struct net_device *ndev = rx_queue->ndev; - struct ctcmac_private *priv = netdev_priv(ndev); - - i = rx_queue->next_to_use; - rxb = &rx_queue->rx_buff[i]; - - while (alloc_cnt--) { - /* try reuse page */ - if (unlikely(!rxb->page)) { - if (unlikely(!ctcmac_new_page(rx_queue, rxb))) - break; - } - - ctcmac_fill_rxbd(priv, rxb, qidx); - rxb++; - - if (unlikely(++i == rx_queue->rx_ring_size)) { - i = 0; - rxb = rx_queue->rx_buff; - } - } - - rx_queue->next_to_use = i; - rx_queue->next_to_alloc = i; -} - -static int ctcmac_clean_rx_ring(struct ctcmac_priv_rx_q *rx_queue, - int rx_work_limit) -{ - struct net_device *ndev = rx_queue->ndev; - struct ctcmac_private *priv = netdev_priv(ndev); - int i, howmany = 0; - struct sk_buff *skb = rx_queue->skb; - int cleaned_cnt = ctcmac_rxbd_unused(rx_queue); - unsigned int total_bytes = 0, total_pkts = 0; - int qidx = rx_queue->qindex; - - /* Get the first full descriptor */ - i = rx_queue->next_to_clean; - - while (rx_work_limit--) { - u32 lstatus; - - if (cleaned_cnt >= test_param[priv->index].ring_size / 2) { - ctcmac_alloc_rx_buffs(rx_queue, cleaned_cnt); - cleaned_cnt = 0; - } - - if (ctcmac_rxbd_used_untreated(priv, qidx) <= 0) - break; - - if (qidx != 0) - pr_err("rx queue %d rx packet!\n", qidx); - ctcmac_get_rxbd(priv, &lstatus, qidx); - - /* fetch next to clean buffer from the ring */ - skb = ctcmac_get_next_rxbuff(rx_queue, lstatus, skb); - if (unlikely(!skb)) - break; - - cleaned_cnt++; - howmany++; - - if (unlikely(++i == rx_queue->rx_ring_size)) - i = 0; - - rx_queue->next_to_clean = i; - - /* fetch next buffer if not the last in frame */ - if (!(lstatus & CPU_MAC_DESC_INTF_W1_DESC_EOP)) - continue; - - if (unlikely(lstatus & CPU_MAC_DESC_INTF_W1_DESC_ERR)) { - if (!test_param[priv->index].rxts_en) { - /* discard faulty buffer */ - dev_kfree_skb(skb); - skb = NULL; - rx_queue->stats.rx_dropped++; - pr_err("%s: Error with rx desc status 0x%x\n", - ndev->name, lstatus); - continue; - } else { - pr_err("%s: Error with rx desc status 0x%x\n", - ndev->name, lstatus); - } - } - - /* Increment the number of packets */ - total_pkts++; - total_bytes += skb->len; - - skb_record_rx_queue(skb, rx_queue->qindex); - ctcmac_process_frame(ndev, skb); - /* Send the packet up the stack */ - napi_gro_receive(&priv->napi_rx, skb); - - skb = NULL; - } - - /* Store incomplete frames for completion */ - rx_queue->skb = skb; - - rx_queue->stats.rx_packets += total_pkts; - rx_queue->stats.rx_bytes += total_bytes; - - if (cleaned_cnt) - ctcmac_alloc_rx_buffs(rx_queue, cleaned_cnt); - - return howmany; -} - -static void ctcmac_clean_tx_ring(struct ctcmac_priv_tx_q *tx_queue) -{ - u16 next_to_clean; - int tqi = tx_queue->qindex; - struct sk_buff *skb; - struct netdev_queue *txq; - struct ctcmac_tx_buff *tx_buff; - struct net_device *dev = tx_queue->dev; - struct ctcmac_private *priv = netdev_priv(dev); - - txq = netdev_get_tx_queue(dev, tqi); - next_to_clean = tx_queue->next_to_clean; - while (ctcmac_txbd_used_untreated(priv)) { - ctcmac_get_txbd(priv); - - tx_buff = &tx_queue->tx_buff[next_to_clean]; - skb = tx_queue->tx_skbuff[next_to_clean]; - dev_kfree_skb_any(skb); - tx_queue->tx_skbuff[next_to_clean] = NULL; - - dma_unmap_single(priv->dev, tx_buff->dma, - tx_buff->len, DMA_TO_DEVICE); - if (tx_buff->alloc) - kfree(tx_buff->vaddr); - - if ((next_to_clean + 1) >= tx_queue->tx_ring_size) - next_to_clean = 0; - else - next_to_clean++; - - spin_lock(&tx_queue->txlock); - tx_queue->num_txbdfree++; - spin_unlock(&tx_queue->txlock); - } - - /* If we freed a buffer, we can restart transmission, if necessary */ - if (tx_queue->num_txbdfree && - netif_tx_queue_stopped(txq) && - !(test_bit(CTCMAC_DOWN, &priv->state))) { - netif_wake_subqueue(priv->ndev, tqi); - } - - tx_queue->next_to_clean = next_to_clean; -} - -static int ctcmac_poll_rx_sq(struct napi_struct *napi, int budget) -{ - int qidx; - int work_done = 0; - int rx_work_limit; - struct ctcmac_private *priv = - container_of(napi, struct ctcmac_private, napi_rx); - struct ctcmac_priv_rx_q *rx_queue = NULL; - - /* clear interrupt */ - writel(CTCMAC_NOR_RX0_D | CTCMAC_NOR_RX1_D, - &priv->cpumac_reg->cpu_mac_interrupt_func[1]); - - rx_work_limit = budget; - for (qidx = priv->num_rx_queues - 1; qidx >= 0; qidx--) { - rx_queue = priv->rx_queue[qidx]; - work_done += ctcmac_clean_rx_ring(rx_queue, rx_work_limit); - rx_work_limit -= work_done; - } - - if (work_done < budget) { - napi_complete(napi); - /* enable interrupt */ - spin_lock_irq(&priv->reglock); - writel(CTCMAC_NOR_RX0_D | CTCMAC_NOR_RX1_D, - &priv->cpumac_reg->cpu_mac_interrupt_func[3]); - spin_unlock_irq(&priv->reglock); - } - - return work_done; -} - -static int ctcmac_poll_tx_sq(struct napi_struct *napi, int budget) -{ - struct ctcmac_private *priv = - container_of(napi, struct ctcmac_private, napi_tx); - struct ctcmac_priv_tx_q *tx_queue = priv->tx_queue[0]; - - /* clear interrupt */ - writel(CTCMAC_NOR_TX_D, &priv->cpumac_reg->cpu_mac_interrupt_func[1]); - - ctcmac_clean_tx_ring(tx_queue); - - napi_complete(napi); - /* enable interrupt */ - spin_lock_irq(&priv->reglock); - writel(CTCMAC_NOR_TX_D, &priv->cpumac_reg->cpu_mac_interrupt_func[3]); - spin_unlock_irq(&priv->reglock); - - return 0; -} - -static void ctcmac_free_rx_resources(struct ctcmac_private *priv) -{ - int i, j; - struct ctcmac_priv_rx_q *rx_queue = NULL; - - for (i = 0; i < priv->num_rx_queues; i++) { - rx_queue = priv->rx_queue[i]; - if (rx_queue->skb) - dev_kfree_skb(rx_queue->skb); - - for (j = 0; j < rx_queue->rx_ring_size; j++) { - struct ctcmac_rx_buff *rxb = &rx_queue->rx_buff[j]; - - if (!rxb->page) - continue; - dma_unmap_single(rx_queue->dev, rxb->dma, - PAGE_SIZE, DMA_TO_DEVICE); - __free_page(rxb->page); - } - kfree(rx_queue->rx_buff); - rx_queue->rx_buff = NULL; - } -} - -static int ctcmac_init_rx_resources(struct net_device *ndev) -{ - int i; - struct ctcmac_private *priv = netdev_priv(ndev); - struct device *dev = priv->dev; - struct ctcmac_priv_rx_q *rx_queue = NULL; - - for (i = 0; i < priv->num_rx_queues; i++) { - rx_queue = priv->rx_queue[i]; - rx_queue->ndev = ndev; - rx_queue->dev = dev; - rx_queue->next_to_clean = 0; - rx_queue->next_to_use = 0; - rx_queue->next_to_alloc = 0; - rx_queue->skb = NULL; - rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size, - sizeof(*rx_queue->rx_buff), - GFP_KERNEL); - if (!rx_queue->rx_buff) - goto cleanup; - - ctcmac_alloc_rx_buffs(rx_queue, ctcmac_rxbd_unused(rx_queue)); - } - - return 0; - -cleanup: - ctcmac_free_rx_resources(priv); - - return -1; -} - -static void ctcmac_free_tx_resources(struct ctcmac_private *priv) -{ - int i; - struct ctcmac_priv_tx_q *tx_queue = NULL; - - for (i = 0; i < priv->num_tx_queues; i++) { - struct netdev_queue *txq; - - tx_queue = priv->tx_queue[i]; - txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); - - kfree(tx_queue->tx_skbuff); - tx_queue->tx_skbuff = NULL; - } -} - -static int ctcmac_init_tx_resources(struct net_device *ndev) -{ - int i; - struct ctcmac_private *priv = netdev_priv(ndev); - struct ctcmac_priv_tx_q *tx_queue = NULL; - - for (i = 0; i < priv->num_tx_queues; i++) { - tx_queue = priv->tx_queue[i]; - tx_queue->num_txbdfree = tx_queue->tx_ring_size; - tx_queue->next_to_clean = 0; - tx_queue->next_to_alloc = 0; - tx_queue->dev = ndev; - tx_queue->tx_skbuff = - kmalloc_array(tx_queue->tx_ring_size, - sizeof(*tx_queue->tx_skbuff), GFP_KERNEL); - - if (!tx_queue->tx_skbuff) - goto cleanup; - } - - return 0; - -cleanup: - ctcmac_free_tx_resources(priv); - - return -1; -} - -static int ctcmac_alloc_skb_resources(struct net_device *ndev) -{ - if (ctcmac_init_rx_resources(ndev)) - return -1; - if (ctcmac_init_tx_resources(ndev)) - return -1; - - return 0; -} - -static int ctcmac_free_skb_resources(struct ctcmac_private *priv) -{ - ctcmac_free_rx_resources(priv); - ctcmac_free_tx_resources(priv); - ctcmac_free_tx_queues(priv); - ctcmac_free_rx_queues(priv); - - return 0; -} - -static void cpumac_start(struct ctcmac_private *priv) -{ - /* 1. enable rx/tx interrupt */ - writel(CTCMAC_NOR_TX_D | CTCMAC_NOR_RX0_D | CTCMAC_NOR_RX1_D, - &priv->cpumac_reg->cpu_mac_interrupt_func[3]); - /* 2. enable rx/tx */ - clrsetbits(&priv->cpumac_reg->cpu_mac_reset, - CPU_MAC_RESET_W0_SOFT_RST_TX, - 0); - clrsetbits(&priv->cpumac_reg->cpu_mac_reset, - CPU_MAC_RESET_W0_SOFT_RST_RX, - 0); - - netif_trans_update(priv->ndev); /* prevent tx timeout */ -} - -static void cpumac_halt(struct ctcmac_private *priv) -{ - /* 1. disable rx/tx interrupt */ - ctcmac_regw(&priv->cpumac_reg->cpu_mac_interrupt_func[2], 0xffffffff); - ctcmac_regw(&priv->cpumac_reg->cpu_mac_interrupt_normal[2], 0xffffffff); - /* 2. disable rx/tx */ - clrsetbits(&priv->cpumac_reg->cpu_mac_reset, 0, - CPU_MAC_RESET_W0_SOFT_RST_TX); - clrsetbits(&priv->cpumac_reg->cpu_mac_reset, 0, - CPU_MAC_RESET_W0_SOFT_RST_RX); -} - -static int ctcmac_enet_open(struct net_device *dev) -{ - struct ctcmac_private *priv = netdev_priv(dev); - int err; - - err = ctcmac_init_phy(dev); - if (err) - return err; - err = ctcmac_request_irq(priv); - if (err) - return err; - err = startup_ctcmac(dev); - if (err) - return err; - return 0; -} - -static struct ctcmac_tx_buff *skb_to_txbuff(struct ctcmac_private *priv, - struct sk_buff *skb) -{ - u64 addr, offset; - int frag_index, nr_frags, rq; - skb_frag_t *frag; - struct ctcmac_tx_buff *tx_buff; - struct ctcmac_priv_tx_q *tx_queue = NULL; - - nr_frags = skb_shinfo(skb)->nr_frags; - rq = skb->queue_mapping; - tx_queue = priv->tx_queue[rq]; - - tx_buff = &tx_queue->tx_buff[tx_queue->next_to_alloc]; - addr = (u64)skb->data; - if (!test_param[priv->index].txts_en && !nr_frags && - ((addr & PAGE_MASK) == ((addr + skb_headlen(skb)) & PAGE_MASK))) { - tx_buff->alloc = 0; - tx_buff->vaddr = skb->data; - tx_buff->len = skb_headlen(skb); - tx_buff->dma = - dma_map_single(priv->dev, skb->data, skb_headlen(skb), - DMA_TO_DEVICE); - tx_buff->offset = 0; - - } else { - int alloc_size; - - if (test_param[priv->index].txts_en) { - alloc_size = ALIGN(skb->len + 16, BUF_ALIGNMENT); - tx_buff->len = skb->len + 16; - } else { - alloc_size = ALIGN(skb->len, BUF_ALIGNMENT); - tx_buff->len = skb->len; - } - tx_buff->alloc = 1; - tx_buff->vaddr = kmalloc(alloc_size, GFP_KERNEL); - offset = - (BUF_ALIGNMENT - - (((u64)tx_buff->vaddr) & (BUF_ALIGNMENT - 1))); - if (offset == BUF_ALIGNMENT) - offset = 0; - - tx_buff->offset = offset; - if (test_param[priv->index].txts_en) { - memcpy(tx_buff->vaddr + offset, - &test_param[priv->index].ptp_info, 16); - } - - offset += 16; - memcpy(tx_buff->vaddr + offset, skb->data, skb_headlen(skb)); - offset += skb_headlen(skb); - for (frag_index = 0; frag_index < nr_frags; frag_index++) { - frag = &skb_shinfo(skb)->frags[frag_index]; - memcpy(tx_buff->vaddr + offset, frag, - skb_frag_size(frag)); - offset += skb_frag_size(frag); - } - - tx_buff->dma = - dma_map_single(priv->dev, tx_buff->vaddr, tx_buff->len, - DMA_TO_DEVICE); - } - return tx_buff; -} - -static int ctcmac_start_xmit(struct sk_buff *skb, struct net_device *dev) -{ - int rq = 0; - unsigned int bytes_sent; - struct netdev_queue *txq; - struct ctcmac_desc_cfg tx_desc; - struct ctcmac_tx_buff *tx_buff; - struct ctcmac_priv_tx_q *tx_queue = NULL; - struct ctcmac_private *priv = netdev_priv(dev); - - rq = skb->queue_mapping; - tx_queue = priv->tx_queue[rq]; - txq = netdev_get_tx_queue(dev, rq); - - /* check if there is space to queue this packet */ - if (tx_queue->num_txbdfree <= 0) { - pr_err("%s: no space left before send pkt!\n", - priv->ndev->name); - /* no space, stop the queue */ - netif_tx_stop_queue(txq); - dev->stats.tx_fifo_errors++; - return NETDEV_TX_BUSY; - } - - /* Update transmit stats */ - bytes_sent = skb->len; - tx_queue->stats.tx_bytes += bytes_sent; - tx_queue->stats.tx_packets++; - - tx_buff = skb_to_txbuff(priv, skb); - tx_desc.sop = 1; - tx_desc.eop = 1; - tx_desc.size = tx_buff->len; - tx_desc.addr_low = (tx_buff->dma + tx_buff->offset - CTC_DDR_BASE) - & CPU_MAC_DESC_INTF_W0_DESC_ADDR_31_0_MASK; - tx_desc.addr_high = - ((tx_buff->dma + tx_buff->offset - CTC_DDR_BASE) >> 32) - & CPU_MAC_DESC_INTF_W1_DESC_ADDR_39_32_MASK; - ctcmac_fill_txbd(priv, &tx_desc); - tx_queue->tx_skbuff[tx_queue->next_to_alloc] = skb; - - if (tx_queue->next_to_alloc >= tx_queue->tx_ring_size - 1) - tx_queue->next_to_alloc = 0; - else - tx_queue->next_to_alloc++; - - /* We can work in parallel with 872(), except - * when modifying num_txbdfree. Note that we didn't grab the lock - * when we were reading the num_txbdfree and checking for available - * space, that's because outside of this function it can only grow. - */ - spin_lock_bh(&tx_queue->txlock); - /* reduce TxBD free count */ - tx_queue->num_txbdfree--; - spin_unlock_bh(&tx_queue->txlock); - - /* If the next BD still needs to be cleaned up, then the bds - * are full. We need to tell the kernel to stop sending us stuff. - */ - if (!tx_queue->num_txbdfree) { - netif_tx_stop_queue(txq); - pr_err("%s: no space left after send pkt!\n", priv->ndev->name); - dev->stats.tx_fifo_errors++; - } - - return NETDEV_TX_OK; -} - -static int ctcmac_change_mtu(struct net_device *dev, int new_mtu) -{ - struct ctcmac_private *priv = netdev_priv(dev); - int frame_size = new_mtu + ETH_HLEN; - - if (frame_size < 64 || frame_size > CTCMAC_JUMBO_FRAME_SIZE) - return -EINVAL; - - while (test_and_set_bit_lock(CTCMAC_RESETTING, &priv->state)) - cpu_relax(); - - if (dev->flags & IFF_UP) - stop_ctcmac(dev); - - dev->mtu = new_mtu; - - if (dev->flags & IFF_UP) - startup_ctcmac(dev); - - clear_bit_unlock(CTCMAC_RESETTING, &priv->state); - - return 0; -} - -static int ctcmac_set_features(struct net_device *dev, - netdev_features_t features) -{ - return 0; -} - -/* Stops the kernel queue, and halts the controller */ -static int ctcmac_close(struct net_device *dev) -{ - struct ctcmac_private *priv = netdev_priv(dev); - - cancel_work_sync(&priv->reset_task); - stop_ctcmac(dev); - - /* Disconnect from the PHY */ - phy_disconnect(dev->phydev); - ctcmac_free_irq(priv); - return 0; -} - -static void ctcmac_set_multi(struct net_device *dev) -{ -} - -static void ctcmac_timeout(struct net_device *dev) -{ - struct ctcmac_private *priv = netdev_priv(dev); - - dev->stats.tx_errors++; - schedule_work(&priv->reset_task); -} - -static int ctcmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) -{ - struct phy_device *phydev = dev->phydev; - - if (!netif_running(dev)) - return -EINVAL; - - if (!phydev) - return -ENODEV; - - return phy_mii_ioctl(phydev, rq, cmd); -} - -static struct net_device_stats *ctcmac_get_stats(struct net_device *dev) -{ - int qidx; - unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; - unsigned long tx_packets = 0, tx_bytes = 0; - struct ctcmac_private *priv = netdev_priv(dev); - - for (qidx = 0; qidx < priv->num_rx_queues; qidx++) { - if (!priv->rx_queue[qidx]) - return &dev->stats; - rx_packets += priv->rx_queue[qidx]->stats.rx_packets; - rx_bytes += priv->rx_queue[qidx]->stats.rx_bytes; - rx_dropped += priv->rx_queue[qidx]->stats.rx_dropped; - } - - if (!priv->tx_queue[0]) - return &dev->stats; - - tx_packets = priv->tx_queue[0]->stats.tx_packets; - tx_bytes = priv->tx_queue[0]->stats.tx_bytes; - - dev->stats.rx_packets = rx_packets; - dev->stats.rx_bytes = rx_bytes; - dev->stats.rx_dropped = rx_dropped; - dev->stats.tx_bytes = tx_bytes; - dev->stats.tx_packets = tx_packets; - - return &dev->stats; -} - -static int ctcmac_set_mac_addr(struct net_device *dev, void *p) -{ - eth_mac_addr(dev, p); - - return 0; -} - -static const struct net_device_ops ctcmac_netdev_ops = { - .ndo_open = ctcmac_enet_open, - .ndo_start_xmit = ctcmac_start_xmit, - .ndo_stop = ctcmac_close, - .ndo_change_mtu = ctcmac_change_mtu, - .ndo_set_features = ctcmac_set_features, - .ndo_set_rx_mode = ctcmac_set_multi, - .ndo_tx_timeout = ctcmac_timeout, - .ndo_do_ioctl = ctcmac_ioctl, - .ndo_get_stats = ctcmac_get_stats, - .ndo_set_mac_address = ctcmac_set_mac_addr, - .ndo_validate_addr = eth_validate_addr, -}; - -static int ctcmac_probe(struct platform_device *ofdev) -{ - struct net_device *dev = NULL; - struct ctcmac_private *priv = NULL; - int err = 0; - - regmap_base = - syscon_regmap_lookup_by_phandle(ofdev->dev.of_node, "ctc,sysctrl"); - if (IS_ERR(regmap_base)) - return PTR_ERR(regmap_base); - - err = ctcmac_of_init(ofdev, &dev); - if (err) - return err; - - priv = netdev_priv(dev); - SET_NETDEV_DEV(dev, &ofdev->dev); - INIT_WORK(&priv->reset_task, ctcmac_reset_task); - platform_set_drvdata(ofdev, priv); - - dev->base_addr = (unsigned long)priv->iobase; - dev->watchdog_timeo = TX_TIMEOUT; - dev->mtu = CTCMAC_DEFAULT_MTU; - dev->netdev_ops = &ctcmac_netdev_ops; - dev->ethtool_ops = &ctcmac_ethtool_test_ops; - - netif_napi_add(dev, &priv->napi_rx, ctcmac_poll_rx_sq, - CTCMAC_NAIP_RX_WEIGHT); - netif_napi_add(dev, &priv->napi_tx, ctcmac_poll_tx_sq, - CTCMAC_NAIP_TX_WEIGHT); - - set_bit(CTCMAC_DOWN, &priv->state); - - if (!g_reglock_init_done) - spin_lock_init(&global_reglock); - - g_reglock_init_done = 1; - - spin_lock_init(&priv->reglock); - /* Carrier starts down, phylib will bring it up */ - netif_carrier_off(dev); - err = register_netdev(dev); - if (err) - goto register_fail; - - if (!g_mac_unit_init_done) { - writel(0x07, &priv->cpumacu_reg->cpu_mac_unit_reset_ctl); - writel(0x00, &priv->cpumacu_reg->cpu_mac_unit_reset_ctl); - - clrsetbits(&priv->cpumacu_reg->cpu_mac_unit_ts_cfg, - 0, CPU_MAC_UNIT_TS_CFG_W0_CFG_FORCE_S_AND_NS_EN); - if (priv->interface == PHY_INTERFACE_MODE_SGMII) { - clrsetbits(&priv->cpumacu_reg->cpu_mac_unit_ref_pulse_cfg[1], - CPU_MAC_UNIT_REF_PULSE_CFG_W1_REF_LINK_PULSE_RST, - 0); - - ctc_mac_serdes_init(priv); - } - g_mac_unit_init_done = 1; - } - - mdelay(10); - - sprintf(priv->irqinfo[CTCMAC_NORMAL].name, "%s%s", - dev->name, "_normal"); - sprintf(priv->irqinfo[CTCMAC_FUNC].name, "%s%s", dev->name, "_func"); - sprintf(priv->irqinfo[CTCMAC_UNIT].name, "%s%s", dev->name, "_unit"); - test_param[priv->index].ring_size = 64; - test_param[priv->index].payload_size = 256; - - return 0; - -register_fail: - ctcmac_unmap_io_space(priv); - ctcmac_free_rx_queues(priv); - ctcmac_free_tx_queues(priv); - of_node_put(priv->phy_node); - ctcmac_free_dev(priv); - - return err; -} - -static int ctcmac_remove(struct platform_device *ofdev) -{ - struct ctcmac_private *priv = platform_get_drvdata(ofdev); - - of_node_put(priv->phy_node); - - unregister_netdev(priv->ndev); - - ctcmac_unmap_io_space(priv); - ctcmac_free_rx_queues(priv); - ctcmac_free_tx_queues(priv); - ctcmac_free_dev(priv); - - return 0; -} - -static const struct of_device_id ctcmac_match[] = { - { - .type = "network", - .compatible = "ctc,mac-test", - }, - {}, -}; - -MODULE_DEVICE_TABLE(of, ctcmac_match); - -/* Structure for a device driver */ -static struct platform_driver ctcmac_driver = { - .driver = { - .name = "ctc-cpumac-test", - .of_match_table = ctcmac_match, - }, - .probe = ctcmac_probe, - .remove = ctcmac_remove, -}; - -module_platform_driver(ctcmac_driver); -MODULE_LICENSE("GPL"); diff --git a/platform/centec-arm64/tsingma-bsp/src/ehci-ctc/ehci-ctc.c b/platform/centec-arm64/tsingma-bsp/src/ehci-ctc/ehci-ctc.c old mode 100644 new mode 100755 index 458ef18dc3ff..f66f1a39a489 --- a/platform/centec-arm64/tsingma-bsp/src/ehci-ctc/ehci-ctc.c +++ b/platform/centec-arm64/tsingma-bsp/src/ehci-ctc/ehci-ctc.c @@ -14,13 +14,18 @@ #include #include #include -#include #include #include +#include +#include #include #include #include +#include +#include "../include/sysctl.h" +#include +#include #include "ehci.h" #define DRIVER_DESC "Centec EHCI platform driver" @@ -28,12 +33,15 @@ #define EHCI_MAX_RSTS 4 #define hcd_to_ehci_priv(h) ((struct ehci_ctc_priv *)hcd_to_ehci(h)->priv) +static struct regmap *regmap_base; + struct ehci_ctc_priv { struct clk *clks[EHCI_MAX_CLKS]; - struct reset_control *rsts[EHCI_MAX_RSTS]; - struct phy **phys; - int num_phys; + struct reset_control *rsts; bool reset_on_resume; + bool quirk_poll; + struct timer_list poll_timer; + struct delayed_work poll_work; }; static const char hcd_name[] = "ehci-ctc"; @@ -67,7 +75,7 @@ static int ehci_ctc_power_on(struct platform_device *dev) { struct usb_hcd *hcd = platform_get_drvdata(dev); struct ehci_ctc_priv *priv = hcd_to_ehci_priv(hcd); - int clk, ret, phy_num; + int clk, ret; for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++) { ret = clk_prepare_enable(priv->clks[clk]); @@ -75,24 +83,8 @@ static int ehci_ctc_power_on(struct platform_device *dev) goto err_disable_clks; } - for (phy_num = 0; phy_num < priv->num_phys; phy_num++) { - ret = phy_init(priv->phys[phy_num]); - if (ret) - goto err_exit_phy; - ret = phy_power_on(priv->phys[phy_num]); - if (ret) { - phy_exit(priv->phys[phy_num]); - goto err_exit_phy; - } - } - return 0; -err_exit_phy: - while (--phy_num >= 0) { - phy_power_off(priv->phys[phy_num]); - phy_exit(priv->phys[phy_num]); - } err_disable_clks: while (--clk >= 0) clk_disable_unprepare(priv->clks[clk]); @@ -104,12 +96,7 @@ static void ehci_ctc_power_off(struct platform_device *dev) { struct usb_hcd *hcd = platform_get_drvdata(dev); struct ehci_ctc_priv *priv = hcd_to_ehci_priv(hcd); - int clk, phy_num; - - for (phy_num = 0; phy_num < priv->num_phys; phy_num++) { - phy_power_off(priv->phys[phy_num]); - phy_exit(priv->phys[phy_num]); - } + int clk; for (clk = EHCI_MAX_CLKS - 1; clk >= 0; clk--) if (priv->clks[clk]) @@ -124,22 +111,146 @@ static const struct ehci_driver_overrides platform_overrides __initconst = { }; static struct usb_ehci_pdata ehci_ctc_defaults = { - .caps_offset = 0x100, - .dma_mask_64 = 1, .power_on = ehci_ctc_power_on, .power_suspend = ehci_ctc_power_off, .power_off = ehci_ctc_power_off, }; #define KERN_CTC KERN_ERR +static bool quirk_poll_check_port_status(struct ehci_hcd *ehci) +{ + u32 port_status = ehci_readl(ehci, &ehci->regs->port_status[0]); + + if (!(port_status & PORT_OWNER) && + (port_status & PORT_POWER) && + !(port_status & PORT_CONNECT) && (port_status & PORT_LS_MASK)) + return true; + + return false; +} + +/** + * quirk_poll_rebind_companion - rebind comanion device to recover + * @ehci: the ehci hcd pointer + * + * Since EHCI/OHCI controllers on R-Car Gen3 SoCs are possible to be getting + * stuck very rarely after a full/low usb device was disconnected. To + * recover from such a situation, the controllers require changing the OHCI + * functional state. + */ +static void quirk_poll_rebind_companion(struct ehci_hcd *ehci) +{ + struct device *companion_dev; + struct usb_hcd *hcd = ehci_to_hcd(ehci); + + companion_dev = usb_of_get_companion_dev(hcd->self.controller); + if (!companion_dev) + return; + + device_release_driver(companion_dev); + if (device_attach(companion_dev) < 0) + ehci_err(ehci, "%s: failed\n", __func__); + + put_device(companion_dev); +} + +static void quirk_poll_work(struct work_struct *work) +{ + struct ehci_ctc_priv *priv = + container_of(to_delayed_work(work), struct ehci_ctc_priv, + poll_work); + struct ehci_hcd *ehci = container_of((void *)priv, struct ehci_hcd, + priv); + + /* check the status twice to reduce misdetection rate */ + if (!quirk_poll_check_port_status(ehci)) + return; + udelay(10); + if (!quirk_poll_check_port_status(ehci)) + return; + + ehci_dbg(ehci, "%s: detected getting stuck. rebind now!\n", __func__); + quirk_poll_rebind_companion(ehci); +} + +static void quirk_poll_timer(struct timer_list *t) +{ + struct ehci_ctc_priv *priv = from_timer(priv, t, poll_timer); + struct ehci_hcd *ehci = container_of((void *)priv, struct ehci_hcd, + priv); + + if (quirk_poll_check_port_status(ehci)) { + /* + * Now scheduling the work for testing the port more. Note that + * updating the status is possible to be delayed when + * reconnection. So, this uses delayed work with 5 ms delay + * to avoid misdetection. + */ + schedule_delayed_work(&priv->poll_work, msecs_to_jiffies(5)); + } + + mod_timer(&priv->poll_timer, jiffies + HZ); +} + +static void quirk_poll_init(struct ehci_ctc_priv *priv) +{ + INIT_DELAYED_WORK(&priv->poll_work, quirk_poll_work); + timer_setup(&priv->poll_timer, quirk_poll_timer, 0); + mod_timer(&priv->poll_timer, jiffies + HZ); +} + +static void quirk_poll_end(struct ehci_ctc_priv *priv) +{ + del_timer_sync(&priv->poll_timer); + cancel_delayed_work(&priv->poll_work); +} + +static const struct soc_device_attribute quirk_poll_match[] = { + {.family = "R-Car Gen3"}, + { /* sentinel */ } +}; + static int ehci_ctc_probe(struct platform_device *dev) { + u32 val; struct usb_hcd *hcd; struct resource *res_mem; struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev); struct ehci_ctc_priv *priv; struct ehci_hcd *ehci; - int err, irq, phy_num, clk = 0, rst; + int err, irq, clk = 0; + + regmap_base = + syscon_regmap_lookup_by_phandle(dev->dev.of_node, "ctc,sysctrl"); + if (IS_ERR(regmap_base)) + return PTR_ERR(regmap_base); + + /* USB interface reset config */ + val = 0x7f; + regmap_write(regmap_base, offsetof(struct SysCtl_regs, SysUsbResetCtl), + val); + udelay(1); + val &= ~SYS_USB_RESET_CTL_W0_CFG_USB_PHY_PWR_ON_RESET; + regmap_write(regmap_base, offsetof(struct SysCtl_regs, SysUsbResetCtl), + val); + udelay(1); + val &= + ~(SYS_USB_RESET_CTL_W0_CFG_USB_PHY_RESET | + SYS_USB_RESET_CTL_W0_CFG_USB_PHY_PORT_RESET | + SYS_USB_RESET_CTL_W0_CFG_USB_UTMI_RESET); + regmap_write(regmap_base, offsetof(struct SysCtl_regs, SysUsbResetCtl), + val); + udelay(1); + val &= + ~(SYS_USB_RESET_CTL_W0_CFG_USB_INTF_RESET | + SYS_USB_RESET_CTL_W0_CFG_USB_AUX_RESET); + regmap_write(regmap_base, offsetof(struct SysCtl_regs, SysUsbResetCtl), + val); + udelay(1); + val &= ~SYS_USB_RESET_CTL_W0_CFG_USB_PHY_ATE_RESET; + regmap_write(regmap_base, offsetof(struct SysCtl_regs, SysUsbResetCtl), + val); + mdelay(500); if (usb_disabled()) return -ENODEV; @@ -152,18 +263,17 @@ static int ehci_ctc_probe(struct platform_device *dev) pdata = &ehci_ctc_defaults; err = dma_coerce_mask_and_coherent(&dev->dev, - pdata->dma_mask_64 ? - DMA_BIT_MASK(64) : DMA_BIT_MASK(32)); + pdata-> + dma_mask_64 ? DMA_BIT_MASK(64) : + DMA_BIT_MASK(32)); if (err) { dev_err(&dev->dev, "Error: DMA mask configuration failed\n"); return err; } irq = platform_get_irq(dev, 0); - if (irq < 0) { - dev_err(&dev->dev, "no irq provided"); + if (irq < 0) return irq; - } hcd = usb_create_hcd(&ehci_ctc_hc_driver, &dev->dev, dev_name(&dev->dev)); @@ -174,6 +284,7 @@ static int ehci_ctc_probe(struct platform_device *dev) dev->dev.platform_data = pdata; priv = hcd_to_ehci_priv(hcd); ehci = hcd_to_ehci(hcd); + if (pdata == &ehci_ctc_defaults && dev->dev.of_node) { if (of_property_read_bool(dev->dev.of_node, "big-endian-regs")) ehci->big_endian_mmio = 1; @@ -192,28 +303,8 @@ static int ehci_ctc_probe(struct platform_device *dev) "has-transaction-translator")) hcd->has_tt = 1; - priv->num_phys = of_count_phandle_with_args(dev->dev.of_node, - "phys", - "#phy-cells"); - - if (priv->num_phys > 0) { - priv->phys = devm_kcalloc(&dev->dev, priv->num_phys, - sizeof(struct phy *), - GFP_KERNEL); - if (!priv->phys) - return -ENOMEM; - } else - priv->num_phys = 0; - - for (phy_num = 0; phy_num < priv->num_phys; phy_num++) { - priv->phys[phy_num] = - devm_of_phy_get_by_index(&dev->dev, - dev->dev.of_node, phy_num); - if (IS_ERR(priv->phys[phy_num])) { - err = PTR_ERR(priv->phys[phy_num]); - goto err_put_hcd; - } - } + if (soc_device_match(quirk_poll_match)) + priv->quirk_poll = true; for (clk = 0; clk < EHCI_MAX_CLKS; clk++) { priv->clks[clk] = of_clk_get(dev->dev.of_node, clk); @@ -226,21 +317,17 @@ static int ehci_ctc_probe(struct platform_device *dev) } } } - for (rst = 0; rst < EHCI_MAX_RSTS; rst++) { - priv->rsts[rst] = - devm_reset_control_get_shared_by_index(&dev->dev, rst); - if (IS_ERR(priv->rsts[rst])) { - err = PTR_ERR(priv->rsts[rst]); - if (err == -EPROBE_DEFER) - goto err_reset; - priv->rsts[rst] = NULL; - break; - } - err = reset_control_deassert(priv->rsts[rst]); - if (err) - goto err_reset; + priv->rsts = devm_reset_control_array_get_optional_shared(&dev->dev); + if (IS_ERR(priv->rsts)) { + err = PTR_ERR(priv->rsts); + goto err_put_clks; } + + err = reset_control_deassert(priv->rsts); + if (err) + goto err_put_clks; + if (pdata->big_endian_desc) ehci->big_endian_desc = 1; if (pdata->big_endian_mmio) @@ -272,6 +359,7 @@ static int ehci_ctc_probe(struct platform_device *dev) if (err < 0) goto err_reset; } + res_mem = platform_get_resource(dev, IORESOURCE_MEM, 0); hcd->regs = devm_ioremap_resource(&dev->dev, res_mem); if (IS_ERR(hcd->regs)) { @@ -280,23 +368,29 @@ static int ehci_ctc_probe(struct platform_device *dev) } hcd->rsrc_start = res_mem->start; hcd->rsrc_len = resource_size(res_mem); + err = usb_add_hcd(hcd, irq, IRQF_SHARED); if (err) goto err_power; + device_wakeup_enable(hcd->self.controller); + device_enable_async_suspend(hcd->self.controller); platform_set_drvdata(dev, hcd); + + if (priv->quirk_poll) + quirk_poll_init(priv); + return err; err_power: if (pdata->power_off) pdata->power_off(dev); err_reset: - while (--rst >= 0) - reset_control_assert(priv->rsts[rst]); + reset_control_assert(priv->rsts); err_put_clks: while (--clk >= 0) clk_put(priv->clks[clk]); -err_put_hcd: + if (pdata == &ehci_ctc_defaults) dev->dev.platform_data = NULL; @@ -310,15 +404,17 @@ static int ehci_ctc_remove(struct platform_device *dev) struct usb_hcd *hcd = platform_get_drvdata(dev); struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev); struct ehci_ctc_priv *priv = hcd_to_ehci_priv(hcd); - int clk, rst; + int clk; + + if (priv->quirk_poll) + quirk_poll_end(priv); usb_remove_hcd(hcd); if (pdata->power_off) pdata->power_off(dev); - for (rst = 0; rst < EHCI_MAX_RSTS && priv->rsts[rst]; rst++) - reset_control_assert(priv->rsts[rst]); + reset_control_assert(priv->rsts); for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++) clk_put(priv->clks[clk]); @@ -337,9 +433,13 @@ static int ehci_ctc_suspend(struct device *dev) struct usb_hcd *hcd = dev_get_drvdata(dev); struct usb_ehci_pdata *pdata = dev_get_platdata(dev); struct platform_device *pdev = to_platform_device(dev); + struct ehci_ctc_priv *priv = hcd_to_ehci_priv(hcd); bool do_wakeup = device_may_wakeup(dev); int ret; + if (priv->quirk_poll) + quirk_poll_end(priv); + ret = ehci_suspend(hcd, do_wakeup); if (ret) return ret; @@ -356,15 +456,25 @@ static int ehci_ctc_resume(struct device *dev) struct usb_ehci_pdata *pdata = dev_get_platdata(dev); struct platform_device *pdev = to_platform_device(dev); struct ehci_ctc_priv *priv = hcd_to_ehci_priv(hcd); + struct device *companion_dev; if (pdata->power_on) { int err = pdata->power_on(pdev); - if (err < 0) return err; } + companion_dev = usb_of_get_companion_dev(hcd->self.controller); + if (companion_dev) { + device_pm_wait_for_dev(hcd->self.controller, companion_dev); + put_device(companion_dev); + } + ehci_resume(hcd, priv->reset_on_resume); + + if (priv->quirk_poll) + quirk_poll_init(priv); + return 0; } #endif /* CONFIG_PM_SLEEP */ @@ -394,7 +504,7 @@ static struct platform_driver ehci_ctc_driver = { .name = "ehci-ctc", .pm = &ehci_ctc_pm_ops, .of_match_table = ctc_ehci_ids, - } + } }; static int __init ehci_ctc_init(void) diff --git a/platform/centec-arm64/tsingma-bsp/src/ehci-ctc/ehci.h b/platform/centec-arm64/tsingma-bsp/src/ehci-ctc/ehci.h index c8e9a48e1d51..accc08b4ab81 100644 --- a/platform/centec-arm64/tsingma-bsp/src/ehci-ctc/ehci.h +++ b/platform/centec-arm64/tsingma-bsp/src/ehci-ctc/ehci.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (c) 2001-2002 by David Brownell */ @@ -31,14 +31,14 @@ typedef __u16 __bitwise __hc16; struct ehci_stats { /* irq usage */ - unsigned long normal; - unsigned long error; - unsigned long iaa; - unsigned long lost_iaa; + unsigned long normal; + unsigned long error; + unsigned long iaa; + unsigned long lost_iaa; /* termination of urbs from core */ - unsigned long complete; - unsigned long unlink; + unsigned long complete; + unsigned long unlink; }; /* @@ -46,22 +46,22 @@ struct ehci_stats { * high-speed devices and full/low-speed devices lying behind a TT. */ struct ehci_per_sched { - struct usb_device *udev; /* access to the TT */ + struct usb_device *udev; /* access to the TT */ struct usb_host_endpoint *ep; - struct list_head ps_list; /* node on ehci_tt's ps_list */ - u16 tt_usecs; /* time on the FS/LS bus */ - u16 cs_mask; /* C-mask and S-mask bytes */ - u16 period; /* actual period in frames */ - u16 phase; /* actual phase, frame part */ - u8 bw_phase; /* same, for bandwidth - reservation */ - u8 phase_uf; /* uframe part of the phase */ - u8 usecs, c_usecs; /* times on the HS bus */ - u8 bw_uperiod; /* period in microframes, for - bandwidth reservation */ - u8 bw_period; /* same, in frames */ + struct list_head ps_list; /* node on ehci_tt's ps_list */ + u16 tt_usecs; /* time on the FS/LS bus */ + u16 cs_mask; /* C-mask and S-mask bytes */ + u16 period; /* actual period in frames */ + u16 phase; /* actual phase, frame part */ + u8 bw_phase; /* same, for bandwidth + reservation */ + u8 phase_uf; /* uframe part of the phase */ + u8 usecs, c_usecs; /* times on the HS bus */ + u8 bw_uperiod; /* period in microframes, for + bandwidth reservation */ + u8 bw_period; /* same, in frames */ }; -#define NO_FRAME 29999 /* frame not assigned yet */ +#define NO_FRAME 29999 /* frame not assigned yet */ /* ehci_hcd->lock guards shared data against other CPUs: * ehci_hcd: async, unlink, periodic (and shadow), ... @@ -73,7 +73,7 @@ struct ehci_per_sched { * when updating hw_* fields in shared qh/qtd/... structures. */ -#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ +#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ /* * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the @@ -92,180 +92,180 @@ enum ehci_rh_state { * ehci-timer.c) in parallel with this list. */ enum ehci_hrtimer_event { - EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */ - EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ - EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */ + EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */ + EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ + EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */ EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */ - EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */ + EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */ EHCI_HRTIMER_ACTIVE_UNLINK, /* Wait while unlinking an active QH */ - EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */ + EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */ EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */ EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */ EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */ EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */ EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */ - EHCI_HRTIMER_NUM_EVENTS /* Must come last */ + EHCI_HRTIMER_NUM_EVENTS /* Must come last */ }; #define EHCI_HRTIMER_NO_EVENT 99 -struct ehci_hcd { /* one per controller */ +struct ehci_hcd { /* one per controller */ /* timing support */ - enum ehci_hrtimer_event next_hrtimer_event; - unsigned enabled_hrtimer_events; - ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS]; - struct hrtimer hrtimer; + enum ehci_hrtimer_event next_hrtimer_event; + unsigned enabled_hrtimer_events; + ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS]; + struct hrtimer hrtimer; - int PSS_poll_count; - int ASS_poll_count; - int died_poll_count; + int PSS_poll_count; + int ASS_poll_count; + int died_poll_count; /* glue to PCI and HCD framework */ struct ehci_caps __iomem *caps; struct ehci_regs __iomem *regs; struct ehci_dbg_port __iomem *debug; - __u32 hcs_params; /* cached register copy */ - spinlock_t lock; - enum ehci_rh_state rh_state; + __u32 hcs_params; /* cached register copy */ + spinlock_t lock; + enum ehci_rh_state rh_state; /* general schedule support */ - bool scanning:1; - bool need_rescan:1; - bool intr_unlinking:1; - bool iaa_in_progress:1; - bool async_unlinking:1; - bool shutdown:1; - struct ehci_qh *qh_scan_next; + bool scanning:1; + bool need_rescan:1; + bool intr_unlinking:1; + bool iaa_in_progress:1; + bool async_unlinking:1; + bool shutdown:1; + struct ehci_qh *qh_scan_next; /* async schedule support */ - struct ehci_qh *async; - struct ehci_qh *dummy; /* For AMD quirk use */ - struct list_head async_unlink; - struct list_head async_idle; - unsigned async_unlink_cycle; - unsigned async_count; /* async activity count */ - __hc32 old_current; /* Test for QH becoming */ - __hc32 old_token; /* inactive during unlink */ + struct ehci_qh *async; + struct ehci_qh *dummy; /* For AMD quirk use */ + struct list_head async_unlink; + struct list_head async_idle; + unsigned async_unlink_cycle; + unsigned async_count; /* async activity count */ + __hc32 old_current; /* Test for QH becoming */ + __hc32 old_token; /* inactive during unlink */ /* periodic schedule support */ -#define DEFAULT_I_TDPS 1024 /* some HCs can do less */ - unsigned periodic_size; - __hc32 *periodic; /* hw periodic table */ - dma_addr_t periodic_dma; - struct list_head intr_qh_list; - unsigned i_thresh; /* uframes HC might cache */ - - union ehci_shadow *pshadow; /* mirror hw periodic table */ - struct list_head intr_unlink_wait; - struct list_head intr_unlink; - unsigned intr_unlink_wait_cycle; - unsigned intr_unlink_cycle; - unsigned now_frame; /* frame from HC hardware */ - unsigned last_iso_frame; /* last frame scanned for iso */ - unsigned intr_count; /* intr activity count */ - unsigned isoc_count; /* isoc activity count */ - unsigned periodic_count; /* periodic activity count */ - unsigned uframe_periodic_max; /* max periodic time per uframe */ - +#define DEFAULT_I_TDPS 1024 /* some HCs can do less */ + unsigned periodic_size; + __hc32 *periodic; /* hw periodic table */ + dma_addr_t periodic_dma; + struct list_head intr_qh_list; + unsigned i_thresh; /* uframes HC might cache */ + + union ehci_shadow *pshadow; /* mirror hw periodic table */ + struct list_head intr_unlink_wait; + struct list_head intr_unlink; + unsigned intr_unlink_wait_cycle; + unsigned intr_unlink_cycle; + unsigned now_frame; /* frame from HC hardware */ + unsigned last_iso_frame; /* last frame scanned for iso */ + unsigned intr_count; /* intr activity count */ + unsigned isoc_count; /* isoc activity count */ + unsigned periodic_count; /* periodic activity count */ + unsigned uframe_periodic_max; /* max periodic time per uframe */ /* list of itds & sitds completed while now_frame was still active */ - struct list_head cached_itd_list; - struct ehci_itd *last_itd_to_free; - struct list_head cached_sitd_list; - struct ehci_sitd *last_sitd_to_free; + struct list_head cached_itd_list; + struct ehci_itd *last_itd_to_free; + struct list_head cached_sitd_list; + struct ehci_sitd *last_sitd_to_free; /* per root hub port */ - unsigned long reset_done[EHCI_MAX_ROOT_PORTS]; + unsigned long reset_done[EHCI_MAX_ROOT_PORTS]; /* bit vectors (one bit per port) */ - unsigned long bus_suspended; /* which ports were - already suspended at the start of a bus suspend */ - unsigned long companion_ports; /* which ports are - dedicated to the companion controller */ - unsigned long owned_ports; /* which ports are - owned by the companion during a bus suspend */ - unsigned long port_c_suspend; /* which ports have - the change-suspend feature turned on */ - unsigned long suspended_ports; /* which ports are - suspended */ - unsigned long resuming_ports; /* which ports have - started to resume */ + unsigned long bus_suspended; /* which ports were + already suspended at the start of a bus suspend */ + unsigned long companion_ports; /* which ports are + dedicated to the companion controller */ + unsigned long owned_ports; /* which ports are + owned by the companion during a bus suspend */ + unsigned long port_c_suspend; /* which ports have + the change-suspend feature turned on */ + unsigned long suspended_ports; /* which ports are + suspended */ + unsigned long resuming_ports; /* which ports have + started to resume */ /* per-HC memory pools (could be per-bus, but ...) */ - struct dma_pool *qh_pool; /* qh per active urb */ - struct dma_pool *qtd_pool; /* one or more per qh */ - struct dma_pool *itd_pool; /* itd per iso urb */ - struct dma_pool *sitd_pool; /* sitd per split iso urb */ + struct dma_pool *qh_pool; /* qh per active urb */ + struct dma_pool *qtd_pool; /* one or more per qh */ + struct dma_pool *itd_pool; /* itd per iso urb */ + struct dma_pool *sitd_pool; /* sitd per split iso urb */ - unsigned random_frame; - unsigned long next_statechange; - ktime_t last_periodic_enable; - u32 command; + unsigned random_frame; + unsigned long next_statechange; + ktime_t last_periodic_enable; + u32 command; /* SILICON QUIRKS */ - unsigned no_selective_suspend:1; - unsigned has_fsl_port_bug:1; /* FreeScale */ - unsigned has_fsl_hs_errata:1; /* Freescale HS quirk */ - unsigned has_fsl_susp_errata:1; /* NXP SUSP quirk */ - unsigned big_endian_mmio:1; - unsigned big_endian_desc:1; - unsigned big_endian_capbase:1; - unsigned has_amcc_usb23:1; - unsigned need_io_watchdog:1; - unsigned amd_pll_fix:1; - unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ - unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ - unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ - unsigned need_oc_pp_cycle:1; /* MPC834X port power */ - unsigned imx28_write_fix:1; /* For Freescale i.MX28 */ + unsigned no_selective_suspend:1; + unsigned has_fsl_port_bug:1; /* FreeScale */ + unsigned has_fsl_hs_errata:1; /* Freescale HS quirk */ + unsigned has_fsl_susp_errata:1; /* NXP SUSP quirk */ + unsigned big_endian_mmio:1; + unsigned big_endian_desc:1; + unsigned big_endian_capbase:1; + unsigned has_amcc_usb23:1; + unsigned need_io_watchdog:1; + unsigned amd_pll_fix:1; + unsigned use_dummy_qh:1; /* AMD Frame List table quirk */ + unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ + unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ + unsigned need_oc_pp_cycle:1; /* MPC834X port power */ + unsigned imx28_write_fix:1; /* For Freescale i.MX28 */ /* required for usb32 quirk */ - #define OHCI_CTRL_HCFS (3 << 6) - #define OHCI_USB_OPER (2 << 6) - #define OHCI_USB_SUSPEND (3 << 6) - - #define OHCI_HCCTRL_OFFSET 0x4 - #define OHCI_HCCTRL_LEN 0x4 - __hc32 *ohci_hcctrl_reg; - unsigned has_hostpc:1; - unsigned has_tdi_phy_lpm:1; - unsigned has_ppcd:1; /* support per-port change bits */ - u8 sbrn; /* packed release number */ +#define OHCI_CTRL_HCFS (3 << 6) +#define OHCI_USB_OPER (2 << 6) +#define OHCI_USB_SUSPEND (3 << 6) + +#define OHCI_HCCTRL_OFFSET 0x4 +#define OHCI_HCCTRL_LEN 0x4 + __hc32 *ohci_hcctrl_reg; + unsigned has_hostpc:1; + unsigned has_tdi_phy_lpm:1; + unsigned has_ppcd:1; /* support per-port change bits */ + u8 sbrn; /* packed release number */ /* irq statistics */ #ifdef EHCI_STATS - struct ehci_stats stats; -# define COUNT(x) ((x)++) + struct ehci_stats stats; +# define INCR(x) ((x)++) #else -# define COUNT(x) +# define INCR(x) do {} while (0) #endif /* debug files */ #ifdef CONFIG_DYNAMIC_DEBUG - struct dentry *debug_dir; + struct dentry *debug_dir; #endif /* bandwidth usage */ #define EHCI_BANDWIDTH_SIZE 64 #define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3) - u8 bandwidth[EHCI_BANDWIDTH_SIZE]; - /* us allocated per uframe */ - u8 tt_budget[EHCI_BANDWIDTH_SIZE]; - /* us budgeted per uframe */ - struct list_head tt_list; + u8 bandwidth[EHCI_BANDWIDTH_SIZE]; + /* us allocated per uframe */ + u8 tt_budget[EHCI_BANDWIDTH_SIZE]; + /* us budgeted per uframe */ + struct list_head tt_list; /* platform-specific data -- must come last */ - unsigned long priv[0] __aligned(sizeof(s64)); + unsigned long priv[] __aligned(sizeof(s64)); }; /* convert between an HCD pointer and the corresponding EHCI_HCD */ static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd) { - return (struct ehci_hcd *) (hcd->hcd_priv); + return (struct ehci_hcd *)(hcd->hcd_priv); } + static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci) { - return container_of((void *) ehci, struct usb_hcd, hcd_priv); + return container_of((void *)ehci, struct usb_hcd, hcd_priv); } /*-------------------------------------------------------------------------*/ @@ -286,9 +286,9 @@ static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci) */ struct ehci_qtd { /* first part defined by EHCI spec */ - __hc32 hw_next; /* see EHCI 3.5.1 */ - __hc32 hw_alt_next; /* see EHCI 3.5.2 */ - __hc32 hw_token; /* see EHCI 3.5.3 */ + __hc32 hw_next; /* see EHCI 3.5.1 */ + __hc32 hw_alt_next; /* see EHCI 3.5.2 */ + __hc32 hw_token; /* see EHCI 3.5.3 */ #define QTD_TOGGLE (1 << 31) /* data toggle */ #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) #define QTD_IOC (1 << 15) /* interrupt on complete */ @@ -307,14 +307,14 @@ struct ehci_qtd { #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) - __hc32 hw_buf[5]; /* see EHCI 3.5.4 */ - __hc32 hw_buf_hi[5]; /* Appendix B */ + __hc32 hw_buf[5]; /* see EHCI 3.5.4 */ + __hc32 hw_buf_hi[5]; /* Appendix B */ /* the rest is HCD-private */ - dma_addr_t qtd_dma; /* qtd address */ - struct list_head qtd_list; /* sw qtd list */ - struct urb *urb; /* qtd's urb */ - size_t length; /* length of buffer */ + dma_addr_t qtd_dma; /* qtd address */ + struct list_head qtd_list; /* sw qtd list */ + struct urb *urb; /* qtd's urb */ + size_t length; /* length of buffer */ } __aligned(32); /* mask NakCnt+T in qh->hw_alt_next */ @@ -345,7 +345,7 @@ struct ehci_qtd { (cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH)) /* for periodic/async schedules and qtd lists, mark end of list */ -#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ +#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ /* * Entries in periodic shadow table are pointers to one of four kinds @@ -356,12 +356,12 @@ struct ehci_qtd { * For entries in the async schedule, the type tag always says "qh". */ union ehci_shadow { - struct ehci_qh *qh; /* Q_TYPE_QH */ - struct ehci_itd *itd; /* Q_TYPE_ITD */ - struct ehci_sitd *sitd; /* Q_TYPE_SITD */ - struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ - __hc32 *hw_next; /* (all types) */ - void *ptr; + struct ehci_qh *qh; /* Q_TYPE_QH */ + struct ehci_itd *itd; /* Q_TYPE_ITD */ + struct ehci_sitd *sitd; /* Q_TYPE_SITD */ + struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ + __hc32 *hw_next; /* (all types) */ + void *ptr; }; /*-------------------------------------------------------------------------*/ @@ -376,8 +376,8 @@ union ehci_shadow { /* first part defined by EHCI spec */ struct ehci_qh_hw { - __hc32 hw_next; /* see EHCI 3.6.1 */ - __hc32 hw_info1; /* see EHCI 3.6.2 */ + __hc32 hw_next; /* see EHCI 3.6.1 */ + __hc32 hw_info1; /* see EHCI 3.6.2 */ #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ #define QH_HEAD (1 << 15) /* Head of async reclamation list */ #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ @@ -385,59 +385,59 @@ struct ehci_qh_hw { #define QH_LOW_SPEED (1 << 12) #define QH_FULL_SPEED (0 << 12) #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */ - __hc32 hw_info2; /* see EHCI 3.6.2 */ + __hc32 hw_info2; /* see EHCI 3.6.2 */ #define QH_SMASK 0x000000ff #define QH_CMASK 0x0000ff00 #define QH_HUBADDR 0x007f0000 #define QH_HUBPORT 0x3f800000 #define QH_MULT 0xc0000000 - __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ + __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ /* qtd overlay (hardware parts of a struct ehci_qtd) */ - __hc32 hw_qtd_next; - __hc32 hw_alt_next; - __hc32 hw_token; - __hc32 hw_buf[5]; - __hc32 hw_buf_hi[5]; + __hc32 hw_qtd_next; + __hc32 hw_alt_next; + __hc32 hw_token; + __hc32 hw_buf[5]; + __hc32 hw_buf_hi[5]; } __aligned(32); struct ehci_qh { - struct ehci_qh_hw *hw; /* Must come first */ + struct ehci_qh_hw *hw; /* Must come first */ /* the rest is HCD-private */ - dma_addr_t qh_dma; /* address of qh */ - union ehci_shadow qh_next; /* ptr to qh; or periodic */ - struct list_head qtd_list; /* sw qtd list */ - struct list_head intr_node; /* list of intr QHs */ - struct ehci_qtd *dummy; - struct list_head unlink_node; - struct ehci_per_sched ps; /* scheduling info */ - - unsigned unlink_cycle; - - u8 qh_state; -#define QH_STATE_LINKED 1 /* HC sees this */ -#define QH_STATE_UNLINK 2 /* HC may still see this */ -#define QH_STATE_IDLE 3 /* HC doesn't see this */ -#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ -#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ - - u8 xacterrs; /* XactErr retry counter */ -#define QH_XACTERR_MAX 32 /* XactErr retry limit */ - - u8 unlink_reason; -#define QH_UNLINK_HALTED 0x01 /* Halt flag is set */ -#define QH_UNLINK_SHORT_READ 0x02 /* Recover from a short read */ -#define QH_UNLINK_DUMMY_OVERLAY 0x04 /* QH overlayed the dummy TD */ -#define QH_UNLINK_SHUTDOWN 0x08 /* The HC isn't running */ -#define QH_UNLINK_QUEUE_EMPTY 0x10 /* Reached end of the queue */ -#define QH_UNLINK_REQUESTED 0x20 /* Disable, reset, or dequeue */ - - u8 gap_uf; /* uframes split/csplit gap */ - - unsigned is_out:1; /* bulk or intr OUT */ - unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ - unsigned dequeue_during_giveback:1; - unsigned should_be_inactive:1; + dma_addr_t qh_dma; /* address of qh */ + union ehci_shadow qh_next; /* ptr to qh; or periodic */ + struct list_head qtd_list; /* sw qtd list */ + struct list_head intr_node; /* list of intr QHs */ + struct ehci_qtd *dummy; + struct list_head unlink_node; + struct ehci_per_sched ps; /* scheduling info */ + + unsigned unlink_cycle; + + u8 qh_state; +#define QH_STATE_LINKED 1 /* HC sees this */ +#define QH_STATE_UNLINK 2 /* HC may still see this */ +#define QH_STATE_IDLE 3 /* HC doesn't see this */ +#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ +#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ + + u8 xacterrs; /* XactErr retry counter */ +#define QH_XACTERR_MAX 32 /* XactErr retry limit */ + + u8 unlink_reason; +#define QH_UNLINK_HALTED 0x01 /* Halt flag is set */ +#define QH_UNLINK_SHORT_READ 0x02 /* Recover from a short read */ +#define QH_UNLINK_DUMMY_OVERLAY 0x04 /* QH overlayed the dummy TD */ +#define QH_UNLINK_SHUTDOWN 0x08 /* The HC isn't running */ +#define QH_UNLINK_QUEUE_EMPTY 0x10 /* Reached end of the queue */ +#define QH_UNLINK_REQUESTED 0x20 /* Disable, reset, or dequeue */ + + u8 gap_uf; /* uframes split/csplit gap */ + + unsigned is_out:1; /* bulk or intr OUT */ + unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ + unsigned dequeue_during_giveback:1; + unsigned should_be_inactive:1; }; /*-------------------------------------------------------------------------*/ @@ -445,11 +445,11 @@ struct ehci_qh { /* description of one iso transaction (up to 3 KB data if highspeed) */ struct ehci_iso_packet { /* These will be copied to iTD when scheduling */ - u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ - __hc32 transaction; /* itd->hw_transaction[i] |= */ - u8 cross; /* buf crosses pages */ + u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ + __hc32 transaction; /* itd->hw_transaction[i] |= */ + u8 cross; /* buf crosses pages */ /* for full speed OUT splits */ - u32 buf1; + u32 buf1; }; /* temporary schedule data for packets from iso urbs (both speeds) @@ -457,10 +457,10 @@ struct ehci_iso_packet { * beginning at stream->next_uframe */ struct ehci_iso_sched { - struct list_head td_list; - unsigned span; - unsigned first_packet; - struct ehci_iso_packet packet[0]; + struct list_head td_list; + unsigned span; + unsigned first_packet; + struct ehci_iso_packet packet[]; }; /* @@ -469,32 +469,32 @@ struct ehci_iso_sched { */ struct ehci_iso_stream { /* first field matches ehci_hq, but is NULL */ - struct ehci_qh_hw *hw; + struct ehci_qh_hw *hw; - u8 bEndpointAddress; - u8 highspeed; - struct list_head td_list; /* queued itds/sitds */ - struct list_head free_list; /* list of unused itds/sitds */ + u8 bEndpointAddress; + u8 highspeed; + struct list_head td_list; /* queued itds/sitds */ + struct list_head free_list; /* list of unused itds/sitds */ /* output of (re)scheduling */ - struct ehci_per_sched ps; /* scheduling info */ - unsigned next_uframe; - __hc32 splits; + struct ehci_per_sched ps; /* scheduling info */ + unsigned next_uframe; + __hc32 splits; /* the rest is derived from the endpoint descriptor, * including the extra info for hw_bufp[0..2] */ - u16 uperiod; /* period in uframes */ - u16 maxp; - unsigned bandwidth; + u16 uperiod; /* period in uframes */ + u16 maxp; + unsigned bandwidth; /* This is used to initialize iTD's hw_bufp fields */ - __hc32 buf0; - __hc32 buf1; - __hc32 buf2; + __hc32 buf0; + __hc32 buf1; + __hc32 buf2; /* this is used to initialize sITD's tt info */ - __hc32 address; + __hc32 address; }; /*-------------------------------------------------------------------------*/ @@ -507,32 +507,32 @@ struct ehci_iso_stream { */ struct ehci_itd { /* first part defined by EHCI spec */ - __hc32 hw_next; /* see EHCI 3.3.1 */ - __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */ -#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ -#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ -#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ -#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ + __hc32 hw_next; /* see EHCI 3.3.1 */ + __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */ +#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ +#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ +#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ +#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) - __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */ - __hc32 hw_bufp_hi[7]; /* Appendix B */ + __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */ + __hc32 hw_bufp_hi[7]; /* Appendix B */ /* the rest is HCD-private */ - dma_addr_t itd_dma; /* for this itd */ - union ehci_shadow itd_next; /* ptr to periodic q entry */ + dma_addr_t itd_dma; /* for this itd */ + union ehci_shadow itd_next; /* ptr to periodic q entry */ - struct urb *urb; - struct ehci_iso_stream *stream; /* endpoint's queue */ - struct list_head itd_list; /* list of stream's itds */ + struct urb *urb; + struct ehci_iso_stream *stream; /* endpoint's queue */ + struct list_head itd_list; /* list of stream's itds */ /* any/all hw_transactions here may be used by that urb */ - unsigned frame; /* where scheduled */ - unsigned pg; - unsigned index[8]; /* in urb->iso_frame_desc */ + unsigned frame; /* where scheduled */ + unsigned pg; + unsigned index[8]; /* in urb->iso_frame_desc */ } __aligned(32); /*-------------------------------------------------------------------------*/ @@ -545,11 +545,11 @@ struct ehci_itd { */ struct ehci_sitd { /* first part defined by EHCI spec */ - __hc32 hw_next; + __hc32 hw_next; /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ - __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ - __hc32 hw_uframe; /* EHCI table 3-10 */ - __hc32 hw_results; /* EHCI table 3-11 */ + __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ + __hc32 hw_uframe; /* EHCI table 3-10 */ + __hc32 hw_results; /* EHCI table 3-11 */ #define SITD_IOC (1 << 31) /* interrupt on completion */ #define SITD_PAGE (1 << 30) /* buffer 0/1 */ #define SITD_LENGTH(x) (((x) >> 16) & 0x3ff) @@ -563,19 +563,19 @@ struct ehci_sitd { #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) - __hc32 hw_buf[2]; /* EHCI table 3-12 */ - __hc32 hw_backpointer; /* EHCI table 3-13 */ - __hc32 hw_buf_hi[2]; /* Appendix B */ + __hc32 hw_buf[2]; /* EHCI table 3-12 */ + __hc32 hw_backpointer; /* EHCI table 3-13 */ + __hc32 hw_buf_hi[2]; /* Appendix B */ /* the rest is HCD-private */ - dma_addr_t sitd_dma; - union ehci_shadow sitd_next; /* ptr to periodic q entry */ - - struct urb *urb; - struct ehci_iso_stream *stream; /* endpoint's queue */ - struct list_head sitd_list; /* list of stream's sitds */ - unsigned frame; - unsigned index; + dma_addr_t sitd_dma; + union ehci_shadow sitd_next; /* ptr to periodic q entry */ + + struct urb *urb; + struct ehci_iso_stream *stream; /* endpoint's queue */ + struct list_head sitd_list; /* list of stream's sitds */ + unsigned frame; + unsigned index; } __aligned(32); /*-------------------------------------------------------------------------*/ @@ -590,12 +590,12 @@ struct ehci_sitd { * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. */ struct ehci_fstn { - __hc32 hw_next; /* any periodic q entry */ - __hc32 hw_prev; /* qh or EHCI_LIST_END */ + __hc32 hw_next; /* any periodic q entry */ + __hc32 hw_prev; /* qh or EHCI_LIST_END */ /* the rest is HCD-private */ - dma_addr_t fstn_dma; - union ehci_shadow fstn_next; /* ptr to periodic q entry */ + dma_addr_t fstn_dma; + union ehci_shadow fstn_next; /* ptr to periodic q entry */ } __aligned(32); /*-------------------------------------------------------------------------*/ @@ -619,12 +619,12 @@ struct ehci_fstn { */ struct ehci_tt { - u16 bandwidth[EHCI_BANDWIDTH_FRAMES]; + u16 bandwidth[EHCI_BANDWIDTH_FRAMES]; - struct list_head tt_list; /* List of all ehci_tt's */ - struct list_head ps_list; /* Items using this TT */ - struct usb_tt *usb_tt; - int tt_port; /* TT port number */ + struct list_head tt_list; /* List of all ehci_tt's */ + struct list_head ps_list; /* Items using this TT */ + struct usb_tt *usb_tt; + int tt_port; /* TT port number */ }; /*-------------------------------------------------------------------------*/ @@ -736,12 +736,10 @@ ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) #endif static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, - __u32 __iomem *regs) + __u32 __iomem * regs) { #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO - return ehci_big_endian_mmio(ehci) ? - readl_be(regs) : - readl(regs); + return ehci_big_endian_mmio(ehci) ? readl_be(regs) : readl(regs); #else return readl(regs); #endif @@ -749,23 +747,21 @@ static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, #ifdef CONFIG_SOC_IMX28 static inline void imx28_ehci_writel(const unsigned int val, - volatile __u32 __iomem *addr) + volatile __u32 __iomem * addr) { - __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr)); +__asm__("swp %0, %0, [%1]": :"r"(val), "r"(addr)); } #else static inline void imx28_ehci_writel(const unsigned int val, - volatile __u32 __iomem *addr) + volatile __u32 __iomem * addr) { } #endif static inline void ehci_writel(const struct ehci_hcd *ehci, - const unsigned int val, __u32 __iomem *regs) + const unsigned int val, __u32 __iomem * regs) { #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO - ehci_big_endian_mmio(ehci) ? - writel_be(val, regs) : - writel(val, regs); + ehci_big_endian_mmio(ehci) ? writel_be(val, regs) : writel(val, regs); #else if (ehci->imx28_write_fix) imx28_ehci_writel(val, regs); @@ -791,11 +787,12 @@ static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) hc_control |= OHCI_USB_SUSPEND; writel_be(hc_control, ehci->ohci_hcctrl_reg); - (void) readl_be(ehci->ohci_hcctrl_reg); + (void)readl_be(ehci->ohci_hcctrl_reg); } #else static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) -{ } +{ +} #endif /*-------------------------------------------------------------------------*/ @@ -814,23 +811,23 @@ static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x) { return ehci_big_endian_desc(ehci) - ? (__force __hc32)cpu_to_be32(x) - : (__force __hc32)cpu_to_le32(x); + ? (__force __hc32) cpu_to_be32(x) + : (__force __hc32) cpu_to_le32(x); } /* ehci to cpu */ static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x) { return ehci_big_endian_desc(ehci) - ? be32_to_cpu((__force __be32)x) - : le32_to_cpu((__force __le32)x); + ? be32_to_cpu((__force __be32) x) + : le32_to_cpu((__force __le32) x); } -static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x) +static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 * x) { return ehci_big_endian_desc(ehci) - ? be32_to_cpup((__force __be32 *)x) - : le32_to_cpup((__force __le32 *)x); + ? be32_to_cpup((__force __be32 *) x) + : le32_to_cpup((__force __le32 *) x); } #else @@ -847,7 +844,7 @@ static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x) return le32_to_cpu(x); } -static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x) +static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 * x) { return le32_to_cpup(x); } @@ -870,25 +867,24 @@ static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x) /* Declarations of things exported for use by ehci platform drivers */ struct ehci_driver_overrides { - size_t extra_priv_size; - int (*reset)(struct usb_hcd *hcd); - int (*port_power)(struct usb_hcd *hcd, - int portnum, bool enable); + size_t extra_priv_size; + int (*reset) (struct usb_hcd * hcd); + int (*port_power) (struct usb_hcd * hcd, int portnum, bool enable); }; -extern void ehci_init_driver(struct hc_driver *drv, - const struct ehci_driver_overrides *over); -extern int ehci_setup(struct usb_hcd *hcd); -extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr, - u32 mask, u32 done, int usec); -extern int ehci_reset(struct ehci_hcd *ehci); +extern void ehci_init_driver(struct hc_driver *drv, + const struct ehci_driver_overrides *over); +extern int ehci_setup(struct usb_hcd *hcd); +extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem * ptr, + u32 mask, u32 done, int usec); +extern int ehci_reset(struct ehci_hcd *ehci); -extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup); -extern int ehci_resume(struct usb_hcd *hcd, bool force_reset); -extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci, - bool suspending, bool do_wakeup); +extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup); +extern int ehci_resume(struct usb_hcd *hcd, bool force_reset); +extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci, + bool suspending, bool do_wakeup); -extern int ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, - u16 wIndex, char *buf, u16 wLength); +extern int ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + u16 wIndex, char *buf, u16 wLength); #endif /* __LINUX_EHCI_HCD_H */ diff --git a/platform/centec-arm64/tsingma-bsp/src/gpio-ctc/gpio-ctc.c b/platform/centec-arm64/tsingma-bsp/src/gpio-ctc/gpio-ctc.c old mode 100644 new mode 100755 index de310e02d210..776f7da001bc --- a/platform/centec-arm64/tsingma-bsp/src/gpio-ctc/gpio-ctc.c +++ b/platform/centec-arm64/tsingma-bsp/src/gpio-ctc/gpio-ctc.c @@ -25,12 +25,19 @@ #include #include "gpio-ctcapb.h" #include +#include #include "gpiolib.h" +#include "../include/sysctl.h" +#include +#include +#include "gpiolib-acpi.h" #define DWAPB_MAX_PORTS 2 struct ctcapb_gpio; +static u32 soc_v; + struct ctcapb_gpio_port { bool is_registered; unsigned int idx; @@ -45,14 +52,15 @@ struct ctcapb_gpio { unsigned int nr_ports; struct GpioSoc_regs *regs; struct ctcapb_gpio_port *ports; + struct regmap *regmap_base; }; -static void clrsetbits(unsigned __iomem *addr, u32 clr, u32 set) +static void clrsetbits(unsigned __iomem * addr, u32 clr, u32 set) { writel((readl(addr) & ~(clr)) | (set), addr); } -static int ctcapb_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) +static int ctcapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) { struct ctcapb_gpio_port *port = gpiochip_get_data(gc); @@ -123,6 +131,20 @@ static void ctcapb_irq_unmask(struct irq_data *d) ctcapb_irq_enable(d); } +#if 0 +static void ctcapb_irq_disable(struct irq_data *d) +{ + struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); + struct ctcapb_gpio_port *port = igc->private; + struct gpio_chip *gc = &port->gc; + unsigned long flags; + + spin_lock_irqsave(&gc->bgpio_lock, flags); + clrsetbits(&port->regs->GpioIntrEn, ~BIT(d->hwirq), 0); + spin_unlock_irqrestore(&gc->bgpio_lock, flags); +} +#endif + static int ctcapb_irq_reqres(struct irq_data *d) { struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); @@ -152,7 +174,7 @@ static int ctcapb_irq_set_type(struct irq_data *d, u32 type) struct ctcapb_gpio_port *port = igc->private; struct gpio_chip *gc = &port->gc; int bit = d->hwirq; - unsigned long level, polarity, flags; + unsigned long level, polarity, flags, datactl, outctl; if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) @@ -162,6 +184,21 @@ static int ctcapb_irq_set_type(struct irq_data *d, u32 type) level = readl(&port->regs->GpioIntrLevel); polarity = readl(&port->regs->GpioIntrPolarity); + if (!soc_v) { + datactl = readl(&port->regs->GpioDataCtl); + outctl = readl(&port->regs->GpioOutCtl); + + datactl &= ~BIT(bit); + outctl |= BIT(bit); + + writel(datactl, &port->regs->GpioDataCtl); + writel(outctl, &port->regs->GpioOutCtl); + + udelay(10); + + outctl &= ~BIT(bit); + writel(outctl, &port->regs->GpioOutCtl); + } switch (type) { case IRQ_TYPE_EDGE_BOTH: level &= ~BIT(bit); @@ -195,7 +232,7 @@ static int ctcapb_irq_set_type(struct irq_data *d, u32 type) } static int ctcapb_gpio_set_debounce(struct gpio_chip *gc, - unsigned int offset, unsigned int debounce) + unsigned offset, unsigned debounce) { struct ctcapb_gpio_port *port = gpiochip_get_data(gc); unsigned long flags, val_deb; @@ -445,7 +482,8 @@ static struct ctcapb_platform_data *ctcapb_gpio_get_pdata(struct device *dev) } if (dev->of_node && fwnode_property_read_bool(fwnode, - "interrupt-controller")) { + "interrupt-controller")) + { pp->irq = irq_of_parse_and_map(to_of_node(fwnode), 0); if (!pp->irq) dev_warn(dev, "no irq for port%d\n", pp->idx); @@ -461,12 +499,42 @@ static struct ctcapb_platform_data *ctcapb_gpio_get_pdata(struct device *dev) return pdata; } +int ctc_bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) +{ + unsigned long mask; + + if (gc->be_bits) + mask = BIT(gc->bgpio_bits - 1 - gpio); + else + mask = BIT(gpio); + + if (soc_v) { + return 0; + } else { + if (val) + gc->bgpio_data |= mask; + else + gc->bgpio_data &= ~mask; + + gc->write_reg(gc->reg_set, gc->bgpio_data); + + if (gc->be_bits) + gc->bgpio_dir |= BIT(gc->bgpio_bits - 1 - gpio); + else + gc->bgpio_dir |= BIT(gpio); + + gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); + + return 0; + } +} + static int ctcapb_gpio_probe(struct platform_device *pdev) { unsigned int i; struct resource *res; struct ctcapb_gpio *gpio; - int err; + int err, val; struct device *dev = &pdev->dev; struct ctcapb_platform_data *pdata = dev_get_platdata(dev); @@ -491,6 +559,18 @@ static int ctcapb_gpio_probe(struct platform_device *pdev) if (!gpio->ports) return -ENOMEM; + gpio->regmap_base = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "ctc,sysctrl"); + if (IS_ERR(gpio->regmap_base)) + return PTR_ERR(gpio->regmap_base); + + regmap_read(gpio->regmap_base, + offsetof(struct SysCtl_regs, SysCtlSysRev), &val); + + soc_v = val; + + printk("soc version = 0x%x\n", soc_v); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); gpio->regs = (struct GpioSoc_regs *)devm_ioremap_resource(&pdev->dev, res); @@ -508,8 +588,9 @@ static int ctcapb_gpio_probe(struct platform_device *pdev) out_unregister: ctcapb_gpio_unregister(gpio); - for (i = 0; i < gpio->nr_ports; i++) + for (i = 0; i < gpio->nr_ports; i++) { ctcapb_irq_teardown(&gpio->ports[i]); + } return err; } @@ -520,8 +601,9 @@ static int ctcapb_gpio_remove(struct platform_device *pdev) struct ctcapb_gpio *gpio = platform_get_drvdata(pdev); ctcapb_gpio_unregister(gpio); - for (i = 0; i < gpio->nr_ports; i++) + for (i = 0; i < gpio->nr_ports; i++) { ctcapb_irq_teardown(&gpio->ports[i]); + } return 0; } diff --git a/platform/centec-arm64/tsingma-bsp/src/gpio-ctc/gpiolib.h b/platform/centec-arm64/tsingma-bsp/src/gpio-ctc/gpiolib.h index a7e49fef73d4..c7ec14a3c481 100644 --- a/platform/centec-arm64/tsingma-bsp/src/gpio-ctc/gpiolib.h +++ b/platform/centec-arm64/tsingma-bsp/src/gpio-ctc/gpiolib.h @@ -1,27 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Internal GPIO functions. * * Copyright (C) 2013, Intel Corporation * Author: Mika Westerberg - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef GPIOLIB_H #define GPIOLIB_H #include -#include /* for enum gpiod_flags */ +#include /* for enum gpiod_flags */ #include #include #include #include -enum of_gpio_flags; -enum gpio_lookup_flags; -struct acpi_device; +#define GPIOCHIP_NAME "gpiochip" /** * struct gpio_device - internal state container for GPIO devices @@ -49,18 +44,19 @@ struct acpi_device; * userspace. */ struct gpio_device { - int id; - struct device dev; - struct cdev chrdev; - struct device *mockdev; - struct module *owner; - struct gpio_chip *chip; - struct gpio_desc *descs; - int base; - u16 ngpio; - const char *label; - void *data; - struct list_head list; + int id; + struct device dev; + struct cdev chrdev; + struct device *mockdev; + struct module *owner; + struct gpio_chip *chip; + struct gpio_desc *descs; + int base; + u16 ngpio; + const char *label; + void *data; + struct list_head list; + struct blocking_notifier_head notifier; #ifdef CONFIG_PINCTRL /* @@ -73,138 +69,36 @@ struct gpio_device { #endif }; -/** - * struct acpi_gpio_info - ACPI GPIO specific information - * @adev: reference to ACPI device which consumes GPIO resource - * @flags: GPIO initialization flags - * @gpioint: if %true this GPIO is of type GpioInt otherwise type is GpioIo - * @polarity: interrupt polarity as provided by ACPI - * @triggering: triggering type as provided by ACPI - * @quirks: Linux specific quirks as provided by struct acpi_gpio_mapping - */ -struct acpi_gpio_info { - struct acpi_device *adev; - enum gpiod_flags flags; - bool gpioint; - int polarity; - int triggering; - unsigned int quirks; -}; - /* gpio suffixes used for ACPI and device tree lookup */ -static __maybe_unused const char * const gpio_suffixes[] = { "gpios", "gpio" }; - -#ifdef CONFIG_OF_GPIO -struct gpio_desc *of_find_gpio(struct device *dev, - const char *con_id, - unsigned int idx, - enum gpio_lookup_flags *flags); -struct gpio_desc *of_get_named_gpiod_flags(struct device_node *np, - const char *list_name, int index, enum of_gpio_flags *flags); -int of_gpiochip_add(struct gpio_chip *gc); -void of_gpiochip_remove(struct gpio_chip *gc); -#else -static inline struct gpio_desc *of_find_gpio(struct device *dev, - const char *con_id, - unsigned int idx, - enum gpio_lookup_flags *flags) -{ - return ERR_PTR(-ENOENT); -} -static inline struct gpio_desc *of_get_named_gpiod_flags(struct device_node *np, - const char *list_name, int index, enum of_gpio_flags *flags) -{ - return ERR_PTR(-ENOENT); -} -static inline int of_gpiochip_add(struct gpio_chip *gc) { return 0; } -static inline void of_gpiochip_remove(struct gpio_chip *gc) { } -#endif /* CONFIG_OF_GPIO */ - -#ifdef CONFIG_ACPI -void acpi_gpiochip_add(struct gpio_chip *chip); -void acpi_gpiochip_remove(struct gpio_chip *chip); - -void acpi_gpiochip_request_interrupts(struct gpio_chip *chip); -void acpi_gpiochip_free_interrupts(struct gpio_chip *chip); - -int acpi_gpio_update_gpiod_flags(enum gpiod_flags *flags, - struct acpi_gpio_info *info); - -struct gpio_desc *acpi_find_gpio(struct device *dev, - const char *con_id, - unsigned int idx, - enum gpiod_flags *dflags, - enum gpio_lookup_flags *lookupflags); -struct gpio_desc *acpi_node_get_gpiod(struct fwnode_handle *fwnode, - const char *propname, int index, - struct acpi_gpio_info *info); - -int acpi_gpio_count(struct device *dev, const char *con_id); - -bool acpi_can_fallback_to_crs(struct acpi_device *adev, const char *con_id); -#else -static inline void acpi_gpiochip_add(struct gpio_chip *chip) { } -static inline void acpi_gpiochip_remove(struct gpio_chip *chip) { } - -static inline void -acpi_gpiochip_request_interrupts(struct gpio_chip *chip) { } - -static inline void -acpi_gpiochip_free_interrupts(struct gpio_chip *chip) { } - -static inline int -acpi_gpio_update_gpiod_flags(enum gpiod_flags *flags, struct acpi_gpio_info *info) -{ - return 0; -} - -static inline struct gpio_desc * -acpi_find_gpio(struct device *dev, const char *con_id, - unsigned int idx, enum gpiod_flags *dflags, - enum gpio_lookup_flags *lookupflags) -{ - return ERR_PTR(-ENOENT); -} -static inline struct gpio_desc * -acpi_node_get_gpiod(struct fwnode_handle *fwnode, const char *propname, - int index, struct acpi_gpio_info *info) -{ - return ERR_PTR(-ENXIO); -} -static inline int acpi_gpio_count(struct device *dev, const char *con_id) -{ - return -ENODEV; -} - -static inline bool acpi_can_fallback_to_crs(struct acpi_device *adev, - const char *con_id) -{ - return false; -} -#endif +static __maybe_unused const char *const gpio_suffixes[] = { "gpios", "gpio" }; + +struct gpio_array { + struct gpio_desc **desc; + unsigned int size; + struct gpio_chip *chip; + unsigned long *get_mask; + unsigned long *set_mask; + unsigned long invert_mask[]; +}; -struct gpio_desc *gpiochip_get_desc(struct gpio_chip *chip, u16 hwnum); +struct gpio_desc *gpiochip_get_desc(struct gpio_chip *gc, unsigned int hwnum); int gpiod_get_array_value_complex(bool raw, bool can_sleep, unsigned int array_size, struct gpio_desc **desc_array, - int *value_array); + struct gpio_array *array_info, + unsigned long *value_bitmap); int gpiod_set_array_value_complex(bool raw, bool can_sleep, - unsigned int array_size, - struct gpio_desc **desc_array, - int *value_array); - -/* This is just passed between gpiolib and devres */ -struct gpio_desc *gpiod_get_from_of_node(struct device_node *node, - const char *propname, int index, - enum gpiod_flags dflags, - const char *label); + unsigned int array_size, + struct gpio_desc **desc_array, + struct gpio_array *array_info, + unsigned long *value_bitmap); -extern struct spinlock gpio_lock; +extern spinlock_t gpio_lock; extern struct list_head gpio_devices; struct gpio_desc { - struct gpio_device *gdev; - unsigned long flags; + struct gpio_device *gdev; + unsigned long flags; /* flag symbols are bit numbers */ #define FLAG_REQUESTED 0 #define FLAG_IS_OUT 1 @@ -214,21 +108,34 @@ struct gpio_desc { #define FLAG_OPEN_DRAIN 7 /* Gpio is open drain type */ #define FLAG_OPEN_SOURCE 8 /* Gpio is open source type */ #define FLAG_USED_AS_IRQ 9 /* GPIO is connected to an IRQ */ +#define FLAG_IRQ_IS_ENABLED 10 /* GPIO is connected to an enabled IRQ */ #define FLAG_IS_HOGGED 11 /* GPIO is hogged */ #define FLAG_TRANSITORY 12 /* GPIO may lose value in sleep or reset */ +#define FLAG_PULL_UP 13 /* GPIO has pull up enabled */ +#define FLAG_PULL_DOWN 14 /* GPIO has pull down enabled */ +#define FLAG_BIAS_DISABLE 15 /* GPIO has pull disabled */ +#define FLAG_EDGE_RISING 16 /* GPIO CDEV detects rising edge events */ +#define FLAG_EDGE_FALLING 17 /* GPIO CDEV detects falling edge events */ /* Connection label */ - const char *label; + const char *label; /* Name of the GPIO */ - const char *name; + const char *name; +#ifdef CONFIG_OF_DYNAMIC + struct device_node *hog; +#endif +#ifdef CONFIG_GPIO_CDEV + /* debounce period in microseconds */ + unsigned int debounce_period_us; +#endif }; int gpiod_request(struct gpio_desc *desc, const char *label); void gpiod_free(struct gpio_desc *desc); int gpiod_configure_flags(struct gpio_desc *desc, const char *con_id, - unsigned long lflags, enum gpiod_flags dflags); + unsigned long lflags, enum gpiod_flags dflags); int gpiod_hog(struct gpio_desc *desc, const char *name, - unsigned long lflags, enum gpiod_flags dflags); + unsigned long lflags, enum gpiod_flags dflags); /* * Return the GPIO number of the passed descriptor relative to its chip @@ -238,9 +145,6 @@ static inline int gpio_chip_hwgpio(const struct gpio_desc *desc) return desc - &desc->gdev->descs[0]; } -void devprop_gpiochip_set_names(struct gpio_chip *chip, - const struct fwnode_handle *fwnode); - /* With descriptor prefix */ #define gpiod_emerg(desc, fmt, ...) \ @@ -264,35 +168,17 @@ void devprop_gpiochip_set_names(struct gpio_chip *chip, /* With chip prefix */ -#define chip_emerg(chip, fmt, ...) \ - dev_emerg(&chip->gpiodev->dev, "(%s): " fmt, chip->label, ##__VA_ARGS__) -#define chip_crit(chip, fmt, ...) \ - dev_crit(&chip->gpiodev->dev, "(%s): " fmt, chip->label, ##__VA_ARGS__) -#define chip_err(chip, fmt, ...) \ - dev_err(&chip->gpiodev->dev, "(%s): " fmt, chip->label, ##__VA_ARGS__) -#define chip_warn(chip, fmt, ...) \ - dev_warn(&chip->gpiodev->dev, "(%s): " fmt, chip->label, ##__VA_ARGS__) -#define chip_info(chip, fmt, ...) \ - dev_info(&chip->gpiodev->dev, "(%s): " fmt, chip->label, ##__VA_ARGS__) -#define chip_dbg(chip, fmt, ...) \ - dev_dbg(&chip->gpiodev->dev, "(%s): " fmt, chip->label, ##__VA_ARGS__) - -#ifdef CONFIG_GPIO_SYSFS - -int gpiochip_sysfs_register(struct gpio_device *gdev); -void gpiochip_sysfs_unregister(struct gpio_device *gdev); - -#else - -static inline int gpiochip_sysfs_register(struct gpio_device *gdev) -{ - return 0; -} - -static inline void gpiochip_sysfs_unregister(struct gpio_device *gdev) -{ -} - -#endif /* CONFIG_GPIO_SYSFS */ +#define chip_emerg(gc, fmt, ...) \ + dev_emerg(&gc->gpiodev->dev, "(%s): " fmt, gc->label, ##__VA_ARGS__) +#define chip_crit(gc, fmt, ...) \ + dev_crit(&gc->gpiodev->dev, "(%s): " fmt, gc->label, ##__VA_ARGS__) +#define chip_err(gc, fmt, ...) \ + dev_err(&gc->gpiodev->dev, "(%s): " fmt, gc->label, ##__VA_ARGS__) +#define chip_warn(gc, fmt, ...) \ + dev_warn(&gc->gpiodev->dev, "(%s): " fmt, gc->label, ##__VA_ARGS__) +#define chip_info(gc, fmt, ...) \ + dev_info(&gc->gpiodev->dev, "(%s): " fmt, gc->label, ##__VA_ARGS__) +#define chip_dbg(gc, fmt, ...) \ + dev_dbg(&gc->gpiodev->dev, "(%s): " fmt, gc->label, ##__VA_ARGS__) #endif /* GPIOLIB_H */ diff --git a/platform/centec-arm64/tsingma-bsp/src/i2c-ctc/i2c-ctc.c b/platform/centec-arm64/tsingma-bsp/src/i2c-ctc/i2c-ctc.c old mode 100644 new mode 100755 index bcae26040d06..0d6b97f2b378 --- a/platform/centec-arm64/tsingma-bsp/src/i2c-ctc/i2c-ctc.c +++ b/platform/centec-arm64/tsingma-bsp/src/i2c-ctc/i2c-ctc.c @@ -1,4 +1,5 @@ -/* Centec I2C controller driver +/* + * Centec I2C controller driver * * Author: Wangyb * @@ -20,6 +21,10 @@ #include #include #include "i2c-ctc.h" +#include "../pinctrl-ctc/pinctrl-ctc.h" +#include "../include/sysctl.h" +#include +#include #define IC_ICK_NS(f) (1000000000 / f) @@ -30,7 +35,7 @@ static char *abort_sources[] = { [ABRT_10ADDR2_NOACK] = "second address byte not acknowledged (10bit mode)", [ABRT_TXDATA_NOACK] = "data not acknowledged", - [ABRT_GCALL_NOACK] = "no acknowledgment for a general call", + [ABRT_GCALL_NOACK] = "no acknowledgement for a general call", [ABRT_GCALL_READ] = "read after general call", [ABRT_SBYTE_ACKDET] = "start byte acknowledged", [ABRT_SBYTE_NORSTRT] = @@ -99,8 +104,7 @@ int i2c_ctc_init(struct ctc_i2c_dev *dev) __i2c_ctc_enable(dev, false); /* Set SCL timing parameters */ - if ((dev->master_cfg & CTC_IC_CON_SPEED_MASK) - == CTC_IC_CON_SPEED_FAST) { + if ((dev->master_cfg & CTC_IC_CON_SPEED_MASK) == CTC_IC_CON_SPEED_FAST) { hcnt = __ctc_calc_fs_cnt(dev->clk_freq) - 14 - 4; lcnt = __ctc_calc_fs_cnt(dev->clk_freq) - 1 - 2; @@ -122,8 +126,9 @@ int i2c_ctc_init(struct ctc_i2c_dev *dev) } /* Configure SDA Hold Time if required */ - if (dev->sda_hold_time) + if (dev->sda_hold_time) { ctc_writel(dev, dev->sda_hold_time, CTC_IC_SDA_HOLD); + } /* Configure Tx/Rx FIFO threshold levels */ comp_param1 = ctc_readl(dev, CTC_IC_COMP_PARAM_1); @@ -139,6 +144,33 @@ int i2c_ctc_init(struct ctc_i2c_dev *dev) return 0; } +int i2c_ctc_recover_bus(struct i2c_adapter *adap) +{ + struct ctc_i2c_dev *dev = i2c_get_adapdata(adap); + u32 val = 0; + + dev_info(dev->dev, "Trying i2c bus recovery\n"); + + if (dev->i2c_num == 0) + val = 0x1; + if (dev->i2c_num == 1) + val = 0x2; + + regmap_write(dev->regmap_base, + offsetof(struct SysCtl_regs, SysI2CResetCtl), val); + val = 0x0; + regmap_write(dev->regmap_base, + offsetof(struct SysCtl_regs, SysI2CResetCtl), val); + + if (dev->soc_ver == CTC_REV_TM_1_1) { + ctc_writel(dev, 0x1, CTC_IC_BUS_CLEAR_EN); + } + + i2c_ctc_init(dev); + + return 0; +} + static int i2c_ctc_wait_bus_not_busy(struct ctc_i2c_dev *dev) { int timeout = 20; @@ -146,7 +178,15 @@ static int i2c_ctc_wait_bus_not_busy(struct ctc_i2c_dev *dev) while (ctc_readl(dev, CTC_IC_STATUS) & CTC_IC_STATUS_ACTIVITY) { if (timeout <= 0) { dev_warn(dev->dev, "timeout waiting for bus ready\n"); - return -ETIMEDOUT; + i2c_recover_bus(&dev->adapter); + + if (ctc_readl(dev, CTC_IC_STATUS) & + CTC_IC_STATUS_ACTIVITY) { + dev_warn(dev->dev, + "timeout waiting for bus ready again\n"); + return -ETIMEDOUT; + } + return 0; } timeout--; usleep_range(1000, 1100); @@ -154,6 +194,16 @@ static int i2c_ctc_wait_bus_not_busy(struct ctc_i2c_dev *dev) return 0; } +void i2c_ctc_disable(struct ctc_i2c_dev *dev) +{ + /* Disable controller */ + __i2c_ctc_enable(dev, false); + + /* Disable all interupts */ + ctc_writel(dev, 0, CTC_IC_INTR_MASK); + ctc_readl(dev, CTC_IC_CLR_INTR); +} + void i2c_ctc_disable_intr(struct ctc_i2c_dev *dev) { ctc_writel(dev, 0, CTC_IC_INTR_MASK); @@ -189,7 +239,7 @@ static void i2c_ctc_xfer_init(struct ctc_i2c_dev *dev) /* Clear and enable interrupts */ ctc_readl(dev, CTC_IC_CLR_INTR); - ctc_writel(dev, CTC_IC_INTR_DEFAULT_MASK, CTC_IC_INTR_MASK); + ctc_writel(dev, CTC_IC_INTR_MASTER_MASK, CTC_IC_INTR_MASK); } static int i2c_ctc_handle_tx_abort(struct ctc_i2c_dev *dev) @@ -199,13 +249,12 @@ static int i2c_ctc_handle_tx_abort(struct ctc_i2c_dev *dev) if (abort_source & CTC_IC_TX_ABRT_NOACK) { for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) - dev_dbg(dev->dev, "%s: %s\n", __func__, - abort_sources[i]); + dev_dbg(dev->dev, "%s: %s\n", __func__, abort_sources[i]); return -EREMOTEIO; } for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) - dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); + dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); if (abort_source & CTC_IC_TX_ARB_LOST) return -EAGAIN; @@ -241,7 +290,7 @@ static int i2c_ctc_interrupt_transfer(struct ctc_i2c_dev *dev) /* wait for tx to complete */ if (!wait_for_completion_timeout(&dev->cmd_complete, HZ)) { dev_err(dev->dev, "controller timed out\n"); - i2c_ctc_init(dev); + i2c_recover_bus(&dev->adapter); ret = -ETIMEDOUT; goto done; } @@ -287,8 +336,7 @@ static int ctc_i2c_xfer_finish(struct ctc_i2c_dev *dev) CTC_IC_INTR_STOP_DET)) { ctc_readl(dev, CTC_IC_CLR_STOP_DET); break; - } else if (time_after(jiffies, start_stop_det + - I2C_STOPDET_TO)) { + } else if (time_after(jiffies, start_stop_det + I2C_STOPDET_TO)) { break; } } @@ -302,8 +350,8 @@ static int ctc_i2c_xfer_finish(struct ctc_i2c_dev *dev) return 0; } -static int __ctc_i2c_read(struct ctc_i2c_dev *dev, __u16 chip_addr, u8 *offset, - __u16 olen, u8 *data, __u16 dlen) +static int __ctc_i2c_read(struct ctc_i2c_dev *dev, __u16 chip_addr, u8 * offset, + __u16 olen, u8 * data, __u16 dlen) { unsigned int active = 0; unsigned int flag = 0; @@ -371,7 +419,7 @@ static int __ctc_i2c_read(struct ctc_i2c_dev *dev, __u16 chip_addr, u8 *offset, } static int __ctc_i2c_write(struct ctc_i2c_dev *dev, __u16 chip_addr, - u8 *offset, __u16 olen, u8 *data, __u16 dlen) + u8 * offset, __u16 olen, u8 * data, __u16 dlen) { int ret; unsigned long start_time_tx; @@ -401,8 +449,9 @@ static int __ctc_i2c_write(struct ctc_i2c_dev *dev, __u16 chip_addr, } data++; start_time_tx = jiffies; - } else if (time_after(jiffies, start_time_tx + - (nb * I2C_BYTE_TO))) { + } else + if (time_after(jiffies, start_time_tx + (nb * I2C_BYTE_TO))) + { dev_err(dev->dev, "Timed out. i2c write Failed\n"); return -ETIMEDOUT; } @@ -418,8 +467,7 @@ static int i2c_ctc_polling_transfer(struct ctc_i2c_dev *dev) memset(&dummy, 0, sizeof(struct i2c_msg)); /* We expect either two messages (one with an offset and one with the - * actucal data) or one message (just data) - */ + * actucal data) or one message (just data) */ if (dev->msgs_num > 2 || dev->msgs_num == 0) { dev_err(dev->dev, "%s: Only one or two messages are supported.", __func__); @@ -469,7 +517,7 @@ static void i2c_ctc_xfer_msg(struct ctc_i2c_dev *dev) u8 *buf = dev->tx_buf; bool need_restart = false; - intr_mask = CTC_IC_INTR_DEFAULT_MASK; + intr_mask = CTC_IC_INTR_MASTER_MASK; /* msg_write_idx */ for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { @@ -519,14 +567,11 @@ static void i2c_ctc_xfer_msg(struct ctc_i2c_dev *dev) if (rx_limit - dev->rx_outstanding <= 0) break; - /* 1 = Read */ - ctc_writel(dev, cmd | CTC_CMD_READ, - CTC_IC_DATA_CMD); + ctc_writel(dev, cmd | CTC_CMD_READ, CTC_IC_DATA_CMD); /* 1 = Read */ rx_limit--; dev->rx_outstanding++; } else - /* 0 = Write */ - ctc_writel(dev, cmd | *buf++, CTC_IC_DATA_CMD); + ctc_writel(dev, cmd | *buf++, CTC_IC_DATA_CMD); /* 0 = Write */ tx_limit--; buf_len--; } @@ -538,8 +583,8 @@ static void i2c_ctc_xfer_msg(struct ctc_i2c_dev *dev) /* more bytes to be written */ dev->status |= STATUS_WRITE_IN_PROGRESS; break; - } - dev->status &= ~STATUS_WRITE_IN_PROGRESS; + } else + dev->status &= ~STATUS_WRITE_IN_PROGRESS; } if (dev->msg_write_idx == dev->msgs_num) @@ -584,8 +629,8 @@ static void i2c_ctc_read(struct ctc_i2c_dev *dev) dev->rx_buf_len = len; dev->rx_buf = buf; return; - } - dev->status &= ~STATUS_READ_IN_PROGRESS; + } else + dev->status &= ~STATUS_READ_IN_PROGRESS; } } @@ -627,6 +672,7 @@ static irqreturn_t i2c_ctc_isr(int this_irq, void *dev_id) enabled = ctc_readl(dev, CTC_IC_ENABLE); stat = ctc_readl(dev, CTC_IC_RAW_INTR_STAT); + dev_dbg(dev->dev, "%s: enabled=%#x stat=%#x\n", __func__, enabled, stat); if (!enabled || !(stat & ~CTC_IC_INTR_ACTIVITY)) @@ -658,7 +704,6 @@ static irqreturn_t i2c_ctc_isr(int this_irq, void *dev_id) static u32 i2c_ctc_func(struct i2c_adapter *adap) { struct ctc_i2c_dev *dev = i2c_get_adapdata(adap); - return dev->functionality; } @@ -667,6 +712,10 @@ static struct i2c_algorithm i2c_ctc_algo = { .functionality = i2c_ctc_func, }; +static struct i2c_bus_recovery_info i2c_ctc_recovery_info = { + .recover_bus = i2c_ctc_recover_bus, +}; + int i2c_ctc_probe(struct ctc_i2c_dev *dev) { struct i2c_adapter *adap = &dev->adapter; @@ -680,6 +729,7 @@ int i2c_ctc_probe(struct ctc_i2c_dev *dev) snprintf(adap->name, sizeof(adap->name), "Centec TsingMa SoC's I2C adapter"); adap->algo = &i2c_ctc_algo; + adap->bus_recovery_info = &i2c_ctc_recovery_info; adap->dev.parent = dev->dev; i2c_set_adapdata(adap, dev); @@ -708,6 +758,7 @@ static int ctc_i2c_plat_probe(struct platform_device *pdev) struct resource *mem; int irq, ret; u32 clk_freq, ht; + u32 val, i2c_num; irq = platform_get_irq(pdev, 0); if (irq < 0) @@ -722,6 +773,15 @@ static int ctc_i2c_plat_probe(struct platform_device *pdev) if (IS_ERR(dev->base)) return PTR_ERR(dev->base); + dev->regmap_base = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "ctc,sysctrl"); + if (IS_ERR(dev->regmap_base)) + return PTR_ERR(dev->regmap_base); + + regmap_read(dev->regmap_base, + offsetof(struct SysCtl_regs, SysCtlSysRev), &val); + dev->soc_ver = ((val == 0x1) ? CTC_REV_TM_1_1 : CTC_REV_TM_1_0); + dev->dev = &pdev->dev; dev->irq = irq; platform_set_drvdata(pdev, dev); @@ -738,17 +798,6 @@ static int ctc_i2c_plat_probe(struct platform_device *pdev) return -EINVAL; } - dev->master_cfg |= - CTC_IC_CON_MASTER | CTC_IC_CON_SLAVE_DISABLE | - CTC_IC_CON_RESTART_EN; - - dev->functionality = - I2C_FUNC_I2C | - I2C_FUNC_10BIT_ADDR | - I2C_FUNC_SMBUS_BYTE | - I2C_FUNC_SMBUS_BYTE_DATA | - I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_I2C_BLOCK; - dev->clk = devm_clk_get(&pdev->dev, NULL); clk_prepare_enable(dev->clk); @@ -757,10 +806,8 @@ static int ctc_i2c_plat_probe(struct platform_device *pdev) dev->sda_hold_time = ht / IC_ICK_NS(clk_get_rate(dev->clk)); } - if (of_property_read_bool(pdev->dev.of_node, "i2c-polling-xfer")) - dev->xfer_type = CTC_IC_POLLING_TRANSFER; - else - dev->xfer_type = CTC_IC_INTERRUPT_TRANSFER; + of_property_read_u32(pdev->dev.of_node, "i2c-num", &i2c_num); + dev->i2c_num = i2c_num; dev->adapter.nr = pdev->id; adap = &dev->adapter; @@ -769,6 +816,7 @@ static int ctc_i2c_plat_probe(struct platform_device *pdev) adap->dev.of_node = pdev->dev.of_node; ret = i2c_ctc_probe(dev); + return ret; } @@ -778,12 +826,7 @@ static int ctc_i2c_plat_remove(struct platform_device *pdev) i2c_del_adapter(&dev->adapter); - /* Disable controller */ - __i2c_ctc_enable(dev, false); - - /* Disable all interupts */ - ctc_writel(dev, 0, CTC_IC_INTR_MASK); - ctc_readl(dev, CTC_IC_CLR_INTR); + i2c_ctc_disable(dev); return 0; } diff --git a/platform/centec-arm64/tsingma-bsp/src/i2c-ctc/i2c-ctc.h b/platform/centec-arm64/tsingma-bsp/src/i2c-ctc/i2c-ctc.h index c27079646a30..407a719ebe91 100644 --- a/platform/centec-arm64/tsingma-bsp/src/i2c-ctc/i2c-ctc.h +++ b/platform/centec-arm64/tsingma-bsp/src/i2c-ctc/i2c-ctc.h @@ -1,4 +1,5 @@ -/* Author: Wangyb +/* + * Author: Wangyb * * Copyright 2005-2018, Centec Networks (Suzhou) Co., Ltd. * @@ -71,7 +72,6 @@ #define CTC_IC_INTR_GEN_CALL 0x800 #define CTC_IC_INTR_DEFAULT_MASK (CTC_IC_INTR_RX_FULL | \ - CTC_IC_INTR_TX_EMPTY | \ CTC_IC_INTR_TX_ABRT | \ CTC_IC_INTR_STOP_DET) @@ -112,7 +112,7 @@ CTC_IC_TX_ABRT_TXDATA_NOACK | \ CTC_IC_TX_ABRT_GCALL_NOACK) -#define CTC_CMD_READ 0x0100 +#define CTC_CMD_READ 0x0100 #define CTC_STOP 0x0200 #define CTC_RESTART 0x0400 @@ -125,6 +125,38 @@ #define CTC_IC_STATUS_MA 0x0020 #define CTC_IC_STATUS_TFE 0x0004 +#define CTC_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \ + I2C_FUNC_SMBUS_BYTE | \ + I2C_FUNC_SMBUS_BYTE_DATA | \ + I2C_FUNC_SMBUS_WORD_DATA | \ + I2C_FUNC_SMBUS_BLOCK_DATA | \ + I2C_FUNC_SMBUS_I2C_BLOCK) + +#define CTC_IC_INTR_MASTER_MASK (CTC_IC_INTR_DEFAULT_MASK | \ + CTC_IC_INTR_TX_EMPTY) + +#define CTC_IC_INTR_SLAVE_MASK (CTC_IC_INTR_DEFAULT_MASK | \ + CTC_IC_INTR_RX_DONE | \ + CTC_IC_INTR_RX_UNDER | \ + CTC_IC_INTR_RD_REQ) + +#define CTC_IC_CON_STOP_DET_IFADDRESSED 0x80 +#define CTC_IC_CON_TX_EMPTY_CTRL 0x100 +#define CTC_IC_CON_RX_FIFO_FULL_HLD_CTRL 0x200 + +#define CTC_IC_SAR 0x8 + +#define CTC_IC_STATUS_SLAVE_ACTIVITY BIT(6) + +#define CTC_IC_BUS_CLEAR_EN 0xb0 +#define CTC_IC_BUS_CLEAR_THRD 0xb4 + +/* + * operation modes + */ +#define CTC_IC_MASTER 0 +#define CTC_IC_SLAVE 1 + enum xfer_type_e { CTC_IC_INTERRUPT_TRANSFER, CTC_IC_POLLING_TRANSFER @@ -159,4 +191,15 @@ struct ctc_i2c_dev { u32 clk_freq; u32 sda_hold_time; u32 xfer_type; + u32 mode; + u32 slave_cfg; + void (*disable) (struct ctc_i2c_dev * dev); + void (*disable_int) (struct ctc_i2c_dev * dev); + int (*init) (struct ctc_i2c_dev * dev); + struct i2c_client *slave; + struct regmap *regmap_base; + u32 soc_ver; +#define CTC_REV_TM_1_0 0x0 +#define CTC_REV_TM_1_1 0x1 + u32 i2c_num; }; diff --git a/platform/centec-arm64/tsingma-bsp/src/include/ctc5236_switch.h b/platform/centec-arm64/tsingma-bsp/src/include/ctc5236_switch.h index aba77b10be32..87a400169d1f 100644 --- a/platform/centec-arm64/tsingma-bsp/src/include/ctc5236_switch.h +++ b/platform/centec-arm64/tsingma-bsp/src/include/ctc5236_switch.h @@ -6,7 +6,7 @@ #define SYS_TSINGMA_TEMP_TABLE_NUM 166 #define SYS_TSINGMA_SENSOR_TIMEOUT 1000 -struct ctc_switch_cmd_status_t { +typedef struct ctc_switch_cmd_status_s { u32 cmdReadType:1; u32 pcieReqCmdChk:3; u32 cmdEntryWords:4; @@ -24,20 +24,20 @@ struct ctc_switch_cmd_status_t { u32 pciePoisoned:1; u32 regProcState:3; u32 pcieReqOverlap:1; -}; +} ctc_switch_cmd_status_t; -union ctc_switch_cmd_status_u_t { - struct ctc_switch_cmd_status_t cmd_status; +typedef union drv_pci_cmd_status_u_e { + ctc_switch_cmd_status_t cmd_status; u32 val; -}; +} ctc_switch_cmd_status_u_t; -struct ctc_access_t { +typedef struct ctc_access_s { u32 cmd_status; u32 addr; u32 data[16]; -}; +} ctc_access_t; -extern int ctc5236_switch_read(u32 offset, u32 len, u32 *p_value); -extern int ctc5236_switch_write(u32 offset, u32 len, u32 *p_value); +extern int ctc5236_switch_read(u32 offset, u32 len, u32 * p_value); +extern int ctc5236_switch_write(u32 offset, u32 len, u32 * p_value); extern int get_switch_temperature(void); #endif diff --git a/platform/centec-arm64/tsingma-bsp/src/include/sysctl.h b/platform/centec-arm64/tsingma-bsp/src/include/sysctl.h index 2201db88558f..58ea49988c38 100644 --- a/platform/centec-arm64/tsingma-bsp/src/include/sysctl.h +++ b/platform/centec-arm64/tsingma-bsp/src/include/sysctl.h @@ -39,7 +39,7 @@ struct SysCtl_regs { u32 SysWarm1ResetEnCtl; /* 0x0000005c */ u32 SysWdt0ResetEnCtl; /* 0x00000060 */ u32 SysWdt1ResetEnCtl; /* 0x00000064 */ - u32 SysCtlReserved; /* 0x00000068 */ + u32 SysCtlSysRev; /* 0x00000068 */ u32 SysEnClkCfg; /* 0x0000006c */ u32 SysPllSocCfg0; /* 0x00000070 */ u32 SysPllSocCfg1; /* 0x00000074 */ @@ -114,7 +114,7 @@ struct SysCtl_regs { u32 SysGpioMultiCtl; /* 0x000001a0 */ u32 rsv105; u32 SysGpioHsMultiCtl[2]; /* 0x000001a8 */ - u32 rsv108; + u32 SysPcieMemCtl; /* 0x000001b0 */ u32 rsv109; u32 SysPcieStatus[2]; /* 0x000001b8 */ u32 SysMsixStatus[8]; /* 0x000001c0 */ @@ -223,15 +223,12 @@ struct SysCtl_regs { u32 DebugAhbRespCnt; /* 0x000006a0 */ u32 DebugGicRespCnt; /* 0x000006a4 */ u32 DebugMemPtrCfg; /* 0x000006a8 */ - u32 rsv427; - u32 rsv428; - u32 rsv429; - u32 rsv430; - u32 rsv431; - u32 rsv432; - u32 rsv433; - u32 rsv434; - u32 rsv435; + u32 SysDdrEccCtl; /* 0x000006ac */ + u32 SysDdrInitStartAddr[2]; /* 0x000006b0 */ + u32 SysDdrInitLastAddr[2]; /* 0x000006b8 */ + u32 SysDdrInitData[2]; /* 0x000006c0 */ + u32 SysDdrInitMode; /* 0x000006c8 */ + u32 SysDdrInitCtl; /* 0x000006cc */ u32 rsv436; u32 rsv437; u32 rsv438; @@ -288,9 +285,14 @@ struct SysCtl_regs { u32 SupMiscInfo1; /* 0x000007b4 */ u32 SupMiscInfo2; /* 0x000007b8 */ u32 SupMiscInfo3; /* 0x000007bc */ + u32 SysBusDbgEn[2]; /* 0x000007c0 */ + u32 SysApbErrLog; /* 0x000007c8 */ + u32 MshClkPadSchmitEn; /* 0x000007cc */ + u32 SysI2C0DebugStatus; /* 0x000007d0 */ + u32 SysI2C1DebugStatus; /* 0x000007d4 */ }; -/* ############################################################################ +/* ################################################################################ * # SysResetCtl Definition */ #define SYS_RESET_CTL_W0_CFG_NIC_RESET BIT(9) @@ -347,7 +349,7 @@ struct SysCtl_regs { #define SYS_RESET_CTL_W0_CFG_CPU_MEM_RESET_MASK 0x00000100 #define SYS_RESET_CTL_W0_LOG_CPU_MEM_RESET_MASK 0x01000000 -/* ############################################################################ +/* ################################################################################ * # SysResetAutoEn Definition */ #define SYS_RESET_AUTO_EN_W0_CFG_CPU1_CORE_RESET_AUTO_EN BIT(3) @@ -382,14 +384,14 @@ struct SysCtl_regs { #define SYS_RESET_AUTO_EN_W0_CFG_CPU1_COLD_RESET_AUTO_EN_MASK 0x00000002 #define SYS_RESET_AUTO_EN_W0_CFG_CPU0_CORE_RESET_AUTO_EN_MASK 0x00000004 -/* ############################################################################ +/* ################################################################################ * # SysGicResetCtl Definition */ #define SYS_GIC_RESET_CTL_W0_CFG_GIC_RESET BIT(0) #define SYS_GIC_RESET_CTL_W0_CFG_GIC_RESET_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysWdtResetCtl Definition */ #define SYS_WDT_RESET_CTL_W0_LOG_WDT1_RESET BIT(5) @@ -402,14 +404,14 @@ struct SysCtl_regs { #define SYS_WDT_RESET_CTL_W0_LOG_WDT0_RESET_MASK 0x00000010 #define SYS_WDT_RESET_CTL_W0_CFG_WDT1_RESET_MASK 0x00000002 -/* ############################################################################ +/* ################################################################################ * # SysDmaResetCtl Definition */ #define SYS_DMA_RESET_CTL_W0_CFG_CPU_DMA_RESET BIT(0) #define SYS_DMA_RESET_CTL_W0_CFG_CPU_DMA_RESET_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysDdrResetCtl Definition */ #define SYS_DDR_RESET_CTL_W0_CFG_DDR_MC_RESET BIT(2) @@ -420,27 +422,29 @@ struct SysCtl_regs { #define SYS_DDR_RESET_CTL_W0_CFG_DDR_CFG_RESET_MASK 0x00000001 #define SYS_DDR_RESET_CTL_W0_CFG_DDR_AXI_RESET_MASK 0x00000002 -/* ############################################################################ +/* ################################################################################ * # SysPcieResetCtl Definition */ #define SYS_PCIE_RESET_CTL_W0_CFG_PIPE_RESET BIT(1) #define SYS_PCIE_RESET_CTL_W0_CFG_PHY_REG_RESET BIT(3) #define SYS_PCIE_RESET_CTL_W0_CFG_PCIE_RESET BIT(0) #define SYS_PCIE_RESET_CTL_W0_CFG_PCIE_POR BIT(2) +#define SYS_PCIE_RESET_CTL_W0_CFG_PCIE_SUP_RESET BIT(4) #define SYS_PCIE_RESET_CTL_W0_CFG_PIPE_RESET_MASK 0x00000002 #define SYS_PCIE_RESET_CTL_W0_CFG_PHY_REG_RESET_MASK 0x00000008 #define SYS_PCIE_RESET_CTL_W0_CFG_PCIE_RESET_MASK 0x00000001 #define SYS_PCIE_RESET_CTL_W0_CFG_PCIE_POR_MASK 0x00000004 +#define SYS_PCIE_RESET_CTL_W0_CFG_PCIE_SUP_RESET_MASK 0x00000010 -/* ############################################################################ +/* ################################################################################ * # SysMacResetCtl Definition */ #define SYS_MAC_RESET_CTL_W0_CFG_CPU_MAC_RESET BIT(0) #define SYS_MAC_RESET_CTL_W0_CFG_CPU_MAC_RESET_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysMshResetCtl Definition */ #define SYS_MSH_RESET_CTL_W0_CFG_MSH_C_TX_RESET BIT(3) @@ -459,7 +463,7 @@ struct SysCtl_regs { #define SYS_MSH_RESET_CTL_W0_CFG_MSH_AXI_RESET_MASK 0x00000001 #define SYS_MSH_RESET_CTL_W0_CFG_MSH_TM_RESET_MASK 0x00000020 -/* ############################################################################ +/* ################################################################################ * # SysUsbResetCtl Definition */ #define SYS_USB_RESET_CTL_W0_CFG_USB_INTF_RESET BIT(0) @@ -478,21 +482,21 @@ struct SysCtl_regs { #define SYS_USB_RESET_CTL_W0_CFG_USB_AUX_RESET_MASK 0x00000002 #define SYS_USB_RESET_CTL_W0_CFG_USB_PHY_PWR_ON_RESET_MASK 0x00000010 -/* ############################################################################ +/* ################################################################################ * # SysSpiResetCtl Definition */ #define SYS_SPI_RESET_CTL_W0_CFG_SPI_RESET BIT(0) #define SYS_SPI_RESET_CTL_W0_CFG_SPI_RESET_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysQspiResetCtl Definition */ #define SYS_QSPI_RESET_CTL_W0_CFG_QSPI_RESET BIT(0) #define SYS_QSPI_RESET_CTL_W0_CFG_QSPI_RESET_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysAxiSupResetCtl Definition */ #define SYS_AXI_SUP_RESET_CTL_W0_CFG_SWITCH_CORE_RESET BIT(1) @@ -503,14 +507,14 @@ struct SysCtl_regs { #define SYS_AXI_SUP_RESET_CTL_W0_CFG_SWITCH_SUP_RESET_MASK 0x00000004 #define SYS_AXI_SUP_RESET_CTL_W0_CFG_AXI_SUP_RESET_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysGpioResetCtl Definition */ #define SYS_GPIO_RESET_CTL_W0_CFG_GPIO_RESET BIT(0) #define SYS_GPIO_RESET_CTL_W0_CFG_GPIO_RESET_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysI2CResetCtl Definition */ #define SYS_I2_C_RESET_CTL_W0_CFG_I2_C0_RESET BIT(0) @@ -519,21 +523,21 @@ struct SysCtl_regs { #define SYS_I2_C_RESET_CTL_W0_CFG_I2_C0_RESET_MASK 0x00000001 #define SYS_I2_C_RESET_CTL_W0_CFG_I2_C1_RESET_MASK 0x00000002 -/* ############################################################################ +/* ################################################################################ * # SysMdioSocResetCtl Definition */ #define SYS_MDIO_SOC_RESET_CTL_W0_CFG_MDIO_SOC_RESET BIT(0) #define SYS_MDIO_SOC_RESET_CTL_W0_CFG_MDIO_SOC_RESET_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysTimerResetCtl Definition */ #define SYS_TIMER_RESET_CTL_W0_CFG_TIMER_RESET BIT(0) #define SYS_TIMER_RESET_CTL_W0_CFG_TIMER_RESET_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysUartResetCtl Definition */ #define SYS_UART_RESET_CTL_W0_CFG_UART1_RESET BIT(1) @@ -544,14 +548,14 @@ struct SysCtl_regs { #define SYS_UART_RESET_CTL_W0_CFG_UART2_RESET_MASK 0x00000004 #define SYS_UART_RESET_CTL_W0_CFG_UART0_RESET_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysTraceResetCtl Definition */ #define SYS_TRACE_RESET_CTL_W0_CFG_TRACE_RESET BIT(0) #define SYS_TRACE_RESET_CTL_W0_CFG_TRACE_RESET_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysDbg0ResetEnCtl Definition */ #define SYS_DBG0_RESET_EN_CTL_W0_DBG0_RST_EN_CPU_L2 BIT(4) @@ -580,7 +584,7 @@ struct SysCtl_regs { #define SYS_DBG0_RESET_EN_CTL_W0_DBG0_RST_EN_JTAG_POT_MASK 0x00000040 #define SYS_DBG0_RESET_EN_CTL_W0_DBG0_RST_EN_CPU_APB_MASK 0x00000020 -/* ############################################################################ +/* ################################################################################ * # SysDbg1ResetEnCtl Definition */ #define SYS_DBG1_RESET_EN_CTL_W0_DBG1_RST_EN_CPU1_CORE BIT(3) @@ -609,7 +613,7 @@ struct SysCtl_regs { #define SYS_DBG1_RESET_EN_CTL_W0_DBG1_RST_EN_WDT1_MASK 0x00000400 #define SYS_DBG1_RESET_EN_CTL_W0_DBG1_RST_EN_NIC_MASK 0x00000800 -/* ############################################################################ +/* ################################################################################ * # SysWarm0ResetEnCtl Definition */ #define SYS_WARM0_RESET_EN_CTL_W0_WARM0_RST_EN_CPU1_COLD BIT(1) @@ -638,7 +642,7 @@ struct SysCtl_regs { #define SYS_WARM0_RESET_EN_CTL_W0_WARM0_RST_EN_NIC_MASK 0x00000800 #define SYS_WARM0_RESET_EN_CTL_W0_WARM0_RST_EN_CPU1_CORE_MASK 0x00000008 -/* ############################################################################ +/* ################################################################################ * # SysWarm1ResetEnCtl Definition */ #define SYS_WARM1_RESET_EN_CTL_W0_WARM1_RST_EN_CPU_MEM BIT(8) @@ -667,7 +671,7 @@ struct SysCtl_regs { #define SYS_WARM1_RESET_EN_CTL_W0_WARM1_RST_EN_JTAG_POT_MASK 0x00000040 #define SYS_WARM1_RESET_EN_CTL_W0_WARM1_RST_EN_CPU0_CORE_MASK 0x00000004 -/* ############################################################################ +/* ################################################################################ * # SysWdt0ResetEnCtl Definition */ #define SYS_WDT0_RESET_EN_CTL_W0_WDT0_RST_EN_CPU_L2 BIT(4) @@ -696,7 +700,7 @@ struct SysCtl_regs { #define SYS_WDT0_RESET_EN_CTL_W0_WDT0_RST_EN_CPU0_COLD_MASK 0x00000001 #define SYS_WDT0_RESET_EN_CTL_W0_WDT0_RST_EN_NIC_MASK 0x00000800 -/* ############################################################################ +/* ################################################################################ * # SysWdt1ResetEnCtl Definition */ #define SYS_WDT1_RESET_EN_CTL_W0_WDT1_RST_EN_CPU_L2 BIT(4) @@ -725,14 +729,16 @@ struct SysCtl_regs { #define SYS_WDT1_RESET_EN_CTL_W0_WDT1_RST_EN_CPU0_CORE_MASK 0x00000004 #define SYS_WDT1_RESET_EN_CTL_W0_WDT1_RST_EN_NIC_MASK 0x00000800 -/* ############################################################################ - * # SysCtlReserved Definition +/* ################################################################################ + * # SysCtlSysRev Definition */ -#define SYS_CTL_RESERVED_W0_RESERVED BIT(0) +#define SYS_CTL_RESERVED_W0_RESERVED BIT(4) +#define SYS_CTL_RESERVED_W0_SYS_REV BIT(0) -#define SYS_CTL_RESERVED_W0_RESERVED_MASK 0xffffffff +#define SYS_CTL_RESERVED_W0_RESERVED_MASK 0xfffffff0 +#define SYS_CTL_RESERVED_W0_SYS_REV_MASK 0x0000000f -/* ############################################################################ +/* ################################################################################ * # SysEnClkCfg Definition */ #define SYS_EN_CLK_CFG_W0_CFG_EN_CLK_MSH BIT(2) @@ -763,7 +769,7 @@ struct SysCtl_regs { #define SYS_EN_CLK_CFG_W0_CFG_EN_CLK_AXI_SUP_MASK 0x00000200 #define SYS_EN_CLK_CFG_W0_CFG_EN_CLK_QSPI_MASK 0x00000800 -/* ############################################################################ +/* ################################################################################ * # SysPllSocCfg0 Definition */ #define SYS_PLL_SOC_CFG0_W0_PLL_SOC_POST_DIV BIT(12) @@ -782,7 +788,7 @@ struct SysCtl_regs { #define SYS_PLL_SOC_CFG0_W0_PLL_SOC_RESET_MASK 0x00000001 #define SYS_PLL_SOC_CFG0_W0_PLL_SOC_PLL_PWD_MASK 0x00000008 -/* ############################################################################ +/* ################################################################################ * # SysPllSocCfg1 Definition */ #define SYS_PLL_SOC_CFG1_W0_PLL_SOC_BYPASS BIT(24) @@ -799,7 +805,7 @@ struct SysCtl_regs { #define SYS_PLL_SOC_CFG1_W0_MON_PLL_SOC_LOCK_MASK 0x10000000 #define SYS_PLL_SOC_CFG1_W0_PLL_SOC_SIC_MASK 0x00001f00 -/* ############################################################################ +/* ################################################################################ * # SysPllDdrCfg0 Definition */ #define SYS_PLL_DDR_CFG0_W0_PLL_DDR_DCO_BYPASS BIT(1) @@ -818,7 +824,7 @@ struct SysCtl_regs { #define SYS_PLL_DDR_CFG0_W0_PLL_DDR_MULT_INT_MASK 0x0ff00000 #define SYS_PLL_DDR_CFG0_W0_PLL_DDR_POST_DIV_MASK 0x0003f000 -/* ############################################################################ +/* ################################################################################ * # SysPllDdrCfg1 Definition */ #define SYS_PLL_DDR_CFG1_W0_PLL_DDR_SLOCK BIT(16) @@ -835,7 +841,7 @@ struct SysCtl_regs { #define SYS_PLL_DDR_CFG1_W0_PLL_DDR_SIP_MASK 0x0000001f #define SYS_PLL_DDR_CFG1_W0_PLL_DDR_SGAIN_MASK 0x00700000 -/* ############################################################################ +/* ################################################################################ * # SysClkSelCfg Definition */ #define SYS_CLK_SEL_CFG_W0_RELEASE_DIV_CLK BIT(1) @@ -844,7 +850,7 @@ struct SysCtl_regs { #define SYS_CLK_SEL_CFG_W0_RELEASE_DIV_CLK_MASK 0x00000002 #define SYS_CLK_SEL_CFG_W0_SUP_CLOCK_SEL_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysClkDivCfg Definition */ #define SYS_CLK_DIV_CFG_W0_CFG_DIV_AHB_CNT BIT(8) @@ -857,7 +863,7 @@ struct SysCtl_regs { #define SYS_CLK_DIV_CFG_W0_CFG_DIV_CST_CNT_MASK 0x000000ff #define SYS_CLK_DIV_CFG_W0_CFG_DIV_MSH_CNT_MASK 0xff000000 -/* ############################################################################ +/* ################################################################################ * # SysClkPeriCfg Definition */ #define SYS_CLK_PERI_CFG_W0_CFG_DIV_USB_PHY_CNT BIT(16) @@ -876,7 +882,7 @@ struct SysCtl_regs { #define SYS_CLK_PERI_CFG_W1_CFG_DIV_MSH_TM_CNT_MASK 0x000007ff #define SYS_CLK_PERI_CFG_W1_CFG_DIV_MDIO_SOC_CNT_MASK 0x07ff0000 -/* ############################################################################ +/* ################################################################################ * # SysDbgCreditCtl Definition */ #define SYS_DBG_CREDIT_CTL_W0_DBG_CREDIT_CNT BIT(8) @@ -889,14 +895,14 @@ struct SysCtl_regs { #define SYS_DBG_CREDIT_CTL_W0_DBG_CREDIT_OK_MASK 0x00001000 #define SYS_DBG_CREDIT_CTL_W0_CFG_DBG_CREDIT_THRD_MASK 0x00000070 -/* ############################################################################ +/* ################################################################################ * # SysI2CMultiCtl Definition */ #define SYS_I2_C_MULTI_CTL_W0_CFG_I2_C_SLAVE_EN BIT(0) #define SYS_I2_C_MULTI_CTL_W0_CFG_I2_C_SLAVE_EN_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # BootStrapPin Definition */ #define BOOT_STRAP_PIN_W0_BOOT_STRAP_LOG BIT(0) @@ -905,7 +911,7 @@ struct SysCtl_regs { #define BOOT_STRAP_PIN_W0_BOOT_STRAP_LOG_MASK 0x00000007 #define BOOT_STRAP_PIN_W0_CPU_SPEED_LOG_MASK 0x00000010 -/* ############################################################################ +/* ################################################################################ * # SysCntValue Definition */ #define SYS_CNT_VALUE_W0_SYS_CNT_VALUE_READ_31_0 BIT(0) @@ -914,7 +920,7 @@ struct SysCtl_regs { #define SYS_CNT_VALUE_W0_SYS_CNT_VALUE_READ_31_0_MASK 0x00000001 #define SYS_CNT_VALUE_W1_SYS_CNT_VALUE_READ_63_32_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysCntLog Definition */ #define SYS_CNT_LOG_W0_SYS_CNT_HALT_READ BIT(1) @@ -927,14 +933,14 @@ struct SysCtl_regs { #define SYS_CNT_LOG_W0_SYS_CNT_DIV_READ_MASK 0x03ff0000 #define SYS_CNT_LOG_W0_SYS_CNT_EN_READ_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysCoreGicAddrBase Definition */ #define SYS_CORE_GIC_ADDR_BASE_W0_CFG_GIC_REG_BASE BIT(0) #define SYS_CORE_GIC_ADDR_BASE_W0_CFG_GIC_REG_BASE_MASK 0x00ffffff -/* ############################################################################ +/* ################################################################################ * # SysCorePmCfg Definition */ #define SYS_CORE_PM_CFG_W0_LOG_L2_Q_ACCEPTN BIT(1) @@ -949,7 +955,7 @@ struct SysCtl_regs { #define SYS_CORE_PM_CFG_W0_CFG_L2_Q_REQN_MASK 0x00000100 #define SYS_CORE_PM_CFG_W0_LOG_L2_Q_ACTIVE_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysCoreStatus Definition */ #define SYS_CORE_STATUS_W0_CORE_STANDBY_WFI_L2 BIT(7) @@ -976,39 +982,39 @@ struct SysCtl_regs { #define SYS_CORE_STATUS_W0_CFG_CORE0_EVENT_RAW_MASK 0x00040000 #define SYS_CORE_STATUS_W0_CFG_CORE1_EVENT_RAW_MASK 0x00080000 -/* ############################################################################ +/* ################################################################################ * # SysCorePmuEvent0 Definition */ #define SYS_CORE_PMU_EVENT0_W0_CORE0_PMU_EVENT BIT(0) #define SYS_CORE_PMU_EVENT0_W0_CORE0_PMU_EVENT_MASK 0x3fffffff -/* ############################################################################ +/* ################################################################################ * # SysCorePmuEvent1 Definition */ #define SYS_CORE_PMU_EVENT1_W0_CORE1_PMU_EVENT BIT(0) #define SYS_CORE_PMU_EVENT1_W0_CORE1_PMU_EVENT_MASK 0x3fffffff -/* ############################################################################ +/* ################################################################################ * # SysRstVecBar0 Definition */ #define SYS_RST_VEC_BAR0_W0_CFG_RV_BAR_ADDR0_31_0 BIT(0) #define SYS_RST_VEC_BAR0_W1_CFG_RV_BAR_ADDR0_39_32 BIT(0) -#define SYS_RST_VEC_BAR0_W0_CFG_RV_BAR_ADDR0_31_0_MASK 0x00000001 -#define SYS_RST_VEC_BAR0_W1_CFG_RV_BAR_ADDR0_39_32_MASK 0x00000001 +#define SYS_RST_VEC_BAR0_W0_CFG_RV_BAR_ADDR0_31_0_MASK 0xffffffff +#define SYS_RST_VEC_BAR0_W1_CFG_RV_BAR_ADDR0_39_32_MASK 0x000000ff -/* ############################################################################ +/* ################################################################################ * # SysRstVecBar1 Definition */ #define SYS_RST_VEC_BAR1_W0_CFG_RV_BAR_ADDR1_31_0 BIT(0) #define SYS_RST_VEC_BAR1_W1_CFG_RV_BAR_ADDR1_39_32 BIT(0) -#define SYS_RST_VEC_BAR1_W0_CFG_RV_BAR_ADDR1_31_0_MASK 0x00000001 -#define SYS_RST_VEC_BAR1_W1_CFG_RV_BAR_ADDR1_39_32_MASK 0x00000001 +#define SYS_RST_VEC_BAR1_W0_CFG_RV_BAR_ADDR1_31_0_MASK 0xffffffff +#define SYS_RST_VEC_BAR1_W1_CFG_RV_BAR_ADDR1_39_32_MASK 0x000000ff -/* ############################################################################ +/* ################################################################################ * # SysGicCfg Definition */ #define SYS_GIC_CFG_W0_CFG_GIC_LEGACY_IRQ_BAR BIT(4) @@ -1021,7 +1027,7 @@ struct SysCtl_regs { #define SYS_GIC_CFG_W0_CFG_GIC_LEGACY_FIQ_BAR_MASK 0x00000003 #define SYS_GIC_CFG_W0_CFG_GIC_RA_USER_MASK 0x00000100 -/* ############################################################################ +/* ################################################################################ * # SysGicStatus Definition */ #define SYS_GIC_STATUS_W0_GIC_FIQ_OUT_LOG BIT(0) @@ -1030,7 +1036,7 @@ struct SysCtl_regs { #define SYS_GIC_STATUS_W0_GIC_FIQ_OUT_LOG_MASK 0x00000003 #define SYS_GIC_STATUS_W0_GIC_IRQ_OUT_LOG_MASK 0x0000000c -/* ############################################################################ +/* ################################################################################ * # SysMemCtl Definition */ #define SYS_MEM_CTL_W0_CFG_RAM_MUX_EN BIT(0) @@ -1043,7 +1049,7 @@ struct SysCtl_regs { #define SYS_MEM_CTL_W0_CFG_SYS_DBG_EN_MASK 0x00000010 #define SYS_MEM_CTL_W0_CFG_RAM_REMAP_MASK 0x00000002 -/* ############################################################################ +/* ################################################################################ * # SysDmaMapCfg Definition */ #define SYS_DMA_MAP_CFG_W0_CFG_CPU_DMA_WR_MAP_LOW BIT(0) @@ -1056,7 +1062,7 @@ struct SysCtl_regs { #define SYS_DMA_MAP_CFG_W0_CFG_CPU_DMA_RD_MAP_HIGH_MASK 0x0f000000 #define SYS_DMA_MAP_CFG_W0_CFG_CPU_DMA_RD_MAP_LOW_MASK 0x00000f00 -/* ############################################################################ +/* ################################################################################ * # SysDmaAbortCfg Definition */ #define SYS_DMA_ABORT_CFG_W0_DMA_ABORT_LEVEL_EN BIT(4) @@ -1065,7 +1071,7 @@ struct SysCtl_regs { #define SYS_DMA_ABORT_CFG_W0_DMA_ABORT_LEVEL_EN_MASK 0x00000010 #define SYS_DMA_ABORT_CFG_W0_DMA_ABORT_STATUS_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysCstCfg Definition */ #define SYS_CST_CFG_W0_CFG_CST_PIU_TP_CTL BIT(4) @@ -1078,21 +1084,21 @@ struct SysCtl_regs { #define SYS_CST_CFG_W0_CFG_CST_INSTANCE_ID_MASK 0x0000000f #define SYS_CST_CFG_W0_CFG_CST_DEVICE_EN_MASK 0x00000020 -/* ############################################################################ +/* ################################################################################ * # SysCstTargetIdCfg Definition */ #define SYS_CST_TARGET_ID_CFG_W0_CFG_CST_TARGET_ID BIT(0) #define SYS_CST_TARGET_ID_CFG_W0_CFG_CST_TARGET_ID_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SysCstMemMapIdCfg Definition */ #define SYS_CST_MEM_MAP_ID_CFG_W0_CFG_CST_MEM_MAP_TARGET_ID BIT(0) #define SYS_CST_MEM_MAP_ID_CFG_W0_CFG_CST_MEM_MAP_TARGET_ID_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SysQspiBootCfg0 Definition */ #define SYS_QSPI_BOOT_CFG0_W0_QSPI_BOOT_EN_CPHA BIT(4) @@ -1115,7 +1121,7 @@ struct SysCtl_regs { #define SYS_QSPI_BOOT_CFG0_W0_QSPI_BOOT_EN_CPOL_MASK 0x00000020 #define SYS_QSPI_BOOT_CFG0_W0_QSPI_BOOT_CLK_DIV_MASK 0x00ff0000 -/* ############################################################################ +/* ################################################################################ * # SysQspiBootCfg1 Definition */ #define SYS_QSPI_BOOT_CFG1_W0_QSPI_BOOT_CMD_CODE BIT(24) @@ -1130,7 +1136,7 @@ struct SysCtl_regs { #define SYS_QSPI_BOOT_CFG1_W0_QSPI_BOOT_ADDR_MODE_MASK 0x00000700 #define SYS_QSPI_BOOT_CFG1_W0_QSPI_BOOT_ADDR_CYCLE_MASK 0x0000003f -/* ############################################################################ +/* ################################################################################ * # SysQspiBootCfg2 Definition */ #define SYS_QSPI_BOOT_CFG2_W0_QSPI_BOOT_DUMMY_MODE BIT(8) @@ -1139,14 +1145,14 @@ struct SysCtl_regs { #define SYS_QSPI_BOOT_CFG2_W0_QSPI_BOOT_DUMMY_MODE_MASK 0x00000700 #define SYS_QSPI_BOOT_CFG2_W0_QSPI_BOOT_DUMMY_CYCLE_MASK 0x0000003f -/* ############################################################################ +/* ################################################################################ * # SysQspiBootCfg3 Definition */ #define SYS_QSPI_BOOT_CFG3_W0_QSPI_BOOT_DUMMY_CODE BIT(0) #define SYS_QSPI_BOOT_CFG3_W0_QSPI_BOOT_DUMMY_CODE_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SysDdrCfg Definition */ #define SYS_DDR_CFG_W0_DDR_RESET_CK_E_LATCH_BAR BIT(0) @@ -1154,14 +1160,18 @@ struct SysCtl_regs { #define SYS_DDR_CFG_W0_DDR_PHY_IDDQ BIT(4) #define SYS_DDR_CFG_W0_DDR_VDD_ON BIT(2) #define SYS_DDR_CFG_W0_DDR_PWR_OFF_PHY BIT(1) +#define SYS_DDR_CFG_W0_DDR_INTF2_ADDR_TRANS_EN BIT(5) +#define SYS_DDR_CFG_W0_DDR_INTF3_ADDR_TRANS_EN BIT(6) #define SYS_DDR_CFG_W0_DDR_RESET_CK_E_LATCH_BAR_MASK 0x00000001 #define SYS_DDR_CFG_W0_DDR_FORCE_STA_CK_STP1_MASK 0x00000008 #define SYS_DDR_CFG_W0_DDR_PHY_IDDQ_MASK 0x00000010 #define SYS_DDR_CFG_W0_DDR_VDD_ON_MASK 0x00000004 #define SYS_DDR_CFG_W0_DDR_PWR_OFF_PHY_MASK 0x00000002 +#define SYS_DDR_CFG_W0_DDR_INTF2_ADDR_TRANS_EN_MASK 0x00000020 +#define SYS_DDR_CFG_W0_DDR_INTF3_ADDR_TRANS_EN_MASK 0x00000040 -/* ############################################################################ +/* ################################################################################ * # SysSpiSelCfg Definition */ #define SYS_SPI_SEL_CFG_W0_SSP_SLAVE_SEL BIT(0) @@ -1170,7 +1180,7 @@ struct SysCtl_regs { #define SYS_SPI_SEL_CFG_W0_SSP_SLAVE_SEL_MASK 0x00000003 #define SYS_SPI_SEL_CFG_W0_SSP_CS_CFG_CTL_MASK 0x000000f0 -/* ############################################################################ +/* ################################################################################ * # SysMdioSocCfg Definition */ #define SYS_MDIO_SOC_CFG_W0_CFG_EN_CLK_MDIO_SOC BIT(4) @@ -1181,35 +1191,35 @@ struct SysCtl_regs { #define SYS_MDIO_SOC_CFG_W0_CFG_INV_MDIO_SOC_MASK 0x00000001 #define SYS_MDIO_SOC_CFG_W0_CFG_EN_CLK_MDIO_SOC_REG_MASK 0x00000020 -/* ############################################################################ +/* ################################################################################ * # SysWdt0Cnt Definition */ #define SYS_WDT0_CNT_W0_CFG_WDT0_DIV_CNT BIT(0) #define SYS_WDT0_CNT_W0_CFG_WDT0_DIV_CNT_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SysWdt0Rev Definition */ #define SYS_WDT0_REV_W0_CFG_WDT0_ECO_REV BIT(0) #define SYS_WDT0_REV_W0_CFG_WDT0_ECO_REV_MASK 0x0000000f -/* ############################################################################ +/* ################################################################################ * # SysWdt1Cnt Definition */ #define SYS_WDT1_CNT_W0_CFG_WDT1_DIV_CNT BIT(0) #define SYS_WDT1_CNT_W0_CFG_WDT1_DIV_CNT_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SysWdt1Rev Definition */ #define SYS_WDT1_REV_W0_CFG_WDT1_ECO_REV BIT(0) #define SYS_WDT1_REV_W0_CFG_WDT1_ECO_REV_MASK 0x0000000f -/* ############################################################################ +/* ################################################################################ * # SysMshCfg Definition */ #define SYS_MSH_CFG_W0_CFG_MSH_CARD_DETECT_IN_EN BIT(4) @@ -1236,7 +1246,7 @@ struct SysCtl_regs { #define SYS_MSH_CFG_W0_MSH_INTF_AT_DLL_MASTER_BYPASS_MASK 0x00000001 #define SYS_MSH_CFG_W0_CFG_MSH_CARD_WRITE_PROT_IN_EN_MASK 0x00000040 -/* ############################################################################ +/* ################################################################################ * # SysMshStatus Definition */ #define SYS_MSH_STATUS_W0_MON_MSH_C_RESET_DONE BIT(2) @@ -1251,7 +1261,7 @@ struct SysCtl_regs { #define SYS_MSH_STATUS_W0_MON_MSH_AT_DLL_LOCK_MASK 0x00000010 #define SYS_MSH_STATUS_W0_MON_MSH_RX_DLL_LOCK_MASK 0x00000020 -/* ############################################################################ +/* ################################################################################ * # SysUsbCfg0 Definition */ #define SYS_USB_CFG0_W0_USB_PHY_TX_PRE_EMP_AMP_TUNE BIT(2) @@ -1284,7 +1294,7 @@ struct SysCtl_regs { #define SYS_USB_CFG0_W0_USB_PHY_TX_PRE_EMP_PULSE_TUNE_MASK 0x00000080 #define SYS_USB_CFG0_W0_USB_PHY_SQ_RX_TUNE_MASK 0x00007000 -/* ############################################################################ +/* ################################################################################ * # SysUsbCfg1 Definition */ #define SYS_USB_CFG1_W0_USB_INTF_AUTOPPD_ON_OVERCUR_EN BIT(1) @@ -1309,7 +1319,7 @@ struct SysCtl_regs { #define SYS_USB_CFG1_W0_USB_INTF_SIM_MODE_MASK 0x00008000 #define SYS_USB_CFG1_W0_USB_INTF_HUBSETUP_MIN_MASK 0x00000004 -/* ############################################################################ +/* ################################################################################ * # SysUsbCfg2 Definition */ #define SYS_USB_CFG2_W0_USB_PHY_PLL_P_TUNE BIT(8) @@ -1326,7 +1336,7 @@ struct SysCtl_regs { #define SYS_USB_CFG2_W0_USB_PHY_OTG_TUNE_MASK 0x00000007 #define SYS_USB_CFG2_W0_USB_PHY_VDAT_REF_TUNE_MASK 0x00003000 -/* ############################################################################ +/* ################################################################################ * # SysUsbStatus Definition */ #define SYS_USB_STATUS_W0_USB_INTF_EHCI_LPSMC_STATE BIT(0) @@ -1345,14 +1355,14 @@ struct SysCtl_regs { #define SYS_USB_STATUS_W0_USB_INTF_OHCI_GLOBALSUSPEND_MASK 0x00020000 #define SYS_USB_STATUS_W0_USB_INTF_OHCI_RMTWKP_MASK 0x00080000 -/* ############################################################################ +/* ################################################################################ * # SysPcieBaseCfg Definition */ #define SYS_PCIE_BASE_CFG_W0_PCIE_BASE_CFG BIT(0) #define SYS_PCIE_BASE_CFG_W0_PCIE_BASE_CFG_MASK 0x000fffff -/* ############################################################################ +/* ################################################################################ * # SysRegCfg Definition */ #define SYS_REG_CFG_W0_EN_CLK_GLOBAL_SYS BIT(0) @@ -1361,7 +1371,7 @@ struct SysCtl_regs { #define SYS_REG_CFG_W0_EN_CLK_GLOBAL_SYS_MASK 0x00000001 #define SYS_REG_CFG_W0_CFG_SOC_ACC_DIR_EN_MASK 0x00000002 -/* ############################################################################ +/* ################################################################################ * # SysInitCtl Definition */ #define SYS_INIT_CTL_W0_CPU_MEM_INIT_DONE BIT(1) @@ -1374,7 +1384,7 @@ struct SysCtl_regs { #define SYS_INIT_CTL_W1_CFG_INIT_START_PTR_MASK 0x00007fff #define SYS_INIT_CTL_W1_CFG_INIT_END_PTR_MASK 0x7fff0000 -/* ############################################################################ +/* ################################################################################ * # SysPllSupCfg0 Definition */ #define SYS_PLL_SUP_CFG0_W0_PLL_SUP_PLL_PWD BIT(3) @@ -1393,7 +1403,7 @@ struct SysCtl_regs { #define SYS_PLL_SUP_CFG0_W0_PLL_SUP_DCO_BYPASS_MASK 0x00000002 #define SYS_PLL_SUP_CFG0_W0_PLL_SUP_POST_DIV_MASK 0x0003f000 -/* ############################################################################ +/* ################################################################################ * # SysPllSupCfg1 Definition */ #define SYS_PLL_SUP_CFG1_W0_MON_PLL_SUP_LOCK BIT(28) @@ -1410,14 +1420,14 @@ struct SysCtl_regs { #define SYS_PLL_SUP_CFG1_W0_PLL_SUP_SLOCK_MASK 0x00010000 #define SYS_PLL_SUP_CFG1_W0_PLL_SUP_BYPASS_MASK 0x01000000 -/* ############################################################################ +/* ################################################################################ * # SysApbProcTimer Definition */ #define SYS_APB_PROC_TIMER_W0_CFG_APB_PROC_TIMER BIT(0) #define SYS_APB_PROC_TIMER_W0_CFG_APB_PROC_TIMER_MASK 0x0000ffff -/* ############################################################################ +/* ################################################################################ * # SysUsbTest Definition */ #define SYS_USB_TEST_W0_USB_PHY_TEST_DATA_IN BIT(8) @@ -1432,7 +1442,7 @@ struct SysCtl_regs { #define SYS_USB_TEST_W1_USB_PHY_TEST_CLK_MASK 0x00010000 #define SYS_USB_TEST_W1_USB_PHY_TEST_DATA_OUT_MASK 0x0000000f -/* ############################################################################ +/* ################################################################################ * # SysGpioMultiCtl Definition */ #define SYS_GPIO_MULTI_CTL_W0_CFG_GPIO14_SEL BIT(28) @@ -1469,7 +1479,7 @@ struct SysCtl_regs { #define SYS_GPIO_MULTI_CTL_W0_CFG_GPIO12_SEL_MASK 0x03000000 #define SYS_GPIO_MULTI_CTL_W0_CFG_GPIO4_SEL_MASK 0x00000300 -/* ############################################################################ +/* ################################################################################ * # SysGpioHsMultiCtl Definition */ #define SYS_GPIO_HS_MULTI_CTL_W0_CFG_GPIO_HS13_SEL BIT(26) @@ -1510,7 +1520,22 @@ struct SysCtl_regs { #define SYS_GPIO_HS_MULTI_CTL_W1_CFG_GPIO_HS17_SEL_MASK 0x0000000c #define SYS_GPIO_HS_MULTI_CTL_W1_CFG_GPIO_HS16_SEL_MASK 0x00000003 -/* ############################################################################ +/* ################################################################################ + * # SysPcieMemCtl Definition + */ +#define SYS_PCIE_MEM_CTL_W0_CFG_AXI4_LITE_BYTE BIT(4) +#define SYS_PCIE_MEM_CTL_W0_CFG_AXI4_LITE_MASK BIT(0) +#define SYS_PCIE_MEM_CTL_W0_CFG_AXI4_LITE_PROT BIT(8) +#define SYS_PCIE_MEM_CTL_W0_LOG_AXI4_LITE_RD_RESP BIT(16) +#define SYS_PCIE_MEM_CTL_W0_LOG_AXI4_LITE_WR_RESP BIT(20) + +#define SYS_PCIE_MEM_CTL_W0_CFG_AXI4_LITE_BYTE_MASK 0x00000030 +#define SYS_PCIE_MEM_CTL_W0_CFG_AXI4_LITE_MASK_MASK 0x0000000f +#define SYS_PCIE_MEM_CTL_W0_CFG_AXI4_LITE_PROT_MASK 0x00000700 +#define SYS_PCIE_MEM_CTL_W0_LOG_AXI4_LITE_RD_RESP_MASK 0x00030000 +#define SYS_PCIE_MEM_CTL_W0_LOG_AXI4_LITE_WR_RESP_MASK 0x00300000 + +/* ################################################################################ * # SysPcieStatus Definition */ #define SYS_PCIE_STATUS_W0_PCIE_LTSSM_LOG_31_0 BIT(0) @@ -1519,7 +1544,7 @@ struct SysCtl_regs { #define SYS_PCIE_STATUS_W0_PCIE_LTSSM_LOG_31_0_MASK 0x00000001 #define SYS_PCIE_STATUS_W1_PCIE_LTSSM_LOG_63_32_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysMsixStatus Definition */ #define SYS_MSIX_STATUS_W0_MSIX_STATUS0 BIT(0) @@ -1540,7 +1565,7 @@ struct SysCtl_regs { #define SYS_MSIX_STATUS_W6_MSIX_STATUS6_MASK 0xffffffff #define SYS_MSIX_STATUS_W7_MSIX_STATUS7_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SysMsixMask Definition */ #define SYS_MSIX_MASK_W0_MSIX_MASK0 BIT(0) @@ -1561,35 +1586,35 @@ struct SysCtl_regs { #define SYS_MSIX_MASK_W6_MSIX_MASK6_MASK 0xffffffff #define SYS_MSIX_MASK_W7_MSIX_MASK7_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SysMsixAddr Definition */ #define SYS_MSIX_ADDR_W0_MSIX_ADDR BIT(0) #define SYS_MSIX_ADDR_W0_MSIX_ADDR_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SysMsixVecCtl Definition */ #define SYS_MSIX_VEC_CTL_W0_MSIX_VEC_EN BIT(0) #define SYS_MSIX_VEC_CTL_W0_MSIX_VEC_EN_MASK 0x000000ff -/* ############################################################################ +/* ################################################################################ * # SysMsixAddrEn Definition */ #define SYS_MSIX_ADDR_EN_W0_MSIX_ADDR_EN BIT(0) #define SYS_MSIX_ADDR_EN_W0_MSIX_ADDR_EN_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysMsixIntrLog Definition */ #define SYS_MSIX_INTR_LOG_W0_MSIX_INTR_LOG BIT(0) #define SYS_MSIX_INTR_LOG_W0_MSIX_INTR_LOG_MASK 0x000000ff -/* ############################################################################ +/* ################################################################################ * # SysDebugCtl Definition */ #define SYS_DEBUG_CTL_W0_DEBUG_INIT_PCIE BIT(4) @@ -1622,7 +1647,7 @@ struct SysCtl_regs { #define SYS_DEBUG_CTL_W0_DEBUG_INIT_SUP_MASK 0x00000040 #define SYS_DEBUG_CTL_W0_DEBUG_INIT_QSPI_MASK 0x00000020 -/* ############################################################################ +/* ################################################################################ * # SysMsixPending Definition */ #define SYS_MSIX_PENDING_W0_MSIX_PENDING0 BIT(0) @@ -1643,7 +1668,7 @@ struct SysCtl_regs { #define SYS_MSIX_PENDING_W6_MSIX_PENDING6_MASK 0xffffffff #define SYS_MSIX_PENDING_W7_MSIX_PENDING7_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SysPwmCtl Definition */ #define SYS_PWM_CTL_W0_CFG_PWM0_EN BIT(31) @@ -1672,7 +1697,7 @@ struct SysCtl_regs { #define SYS_PWM_CTL_W6_CFG_PWM3_PERIOD_CYCLE_MASK 0x00ffffff #define SYS_PWM_CTL_W7_CFG_PWM3_DUTY_CYCLE_MASK 0x00ffffff -/* ############################################################################ +/* ################################################################################ * # SysTachLog Definition */ #define SYS_TACH_LOG_W0_TACH0_PERIOD_CYCLE BIT(0) @@ -1693,7 +1718,7 @@ struct SysCtl_regs { #define SYS_TACH_LOG_W6_TACH3_PERIOD_CYCLE_MASK 0x00ffffff #define SYS_TACH_LOG_W7_TACH3_DUTY_CYCLE_MASK 0x00ffffff -/* ############################################################################ +/* ################################################################################ * # MonAxiCpuCurInfo Definition */ #define MON_AXI_CPU_CUR_INFO_W0_MON_AXI_CPU_CUR_INFO_31_0 BIT(0) @@ -1726,7 +1751,7 @@ struct SysCtl_regs { #define MON_AXI_CPU_CUR_INFO_W12_MON_AXI_CPU_CUR_INFO_415_384_MASK 0x00000001 #define MON_AXI_CPU_CUR_INFO_W13_MON_AXI_CPU_CUR_INFO_427_416_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # MonAxiCpuLogInfo Definition */ #define MON_AXI_CPU_LOG_INFO_W0_MON_AXI_CPU_LOG_INFO_31_0 BIT(0) @@ -1759,7 +1784,7 @@ struct SysCtl_regs { #define MON_AXI_CPU_LOG_INFO_W12_MON_AXI_CPU_LOG_INFO_415_384_MASK 0x00000001 #define MON_AXI_CPU_LOG_INFO_W13_MON_AXI_CPU_LOG_INFO_427_416_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # MonAxiDdr0CurInfo Definition */ #define MON_AXI_DDR0_CUR_INFO_W0_MON_AXI_DDR0_CUR_INFO_31_0 BIT(0) @@ -1792,7 +1817,7 @@ struct SysCtl_regs { #define MON_AXI_DDR0_CUR_INFO_W12_MON_AXI_DDR0_CUR_INFO_415_384_MASK 0x00000001 #define MON_AXI_DDR0_CUR_INFO_W13_MON_AXI_DDR0_CUR_INFO_427_416_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # MonAxiDdr0LogInfo Definition */ #define MON_AXI_DDR0_LOG_INFO_W0_MON_AXI_DDR0_LOG_INFO_31_0 BIT(0) @@ -1825,7 +1850,7 @@ struct SysCtl_regs { #define MON_AXI_DDR0_LOG_INFO_W12_MON_AXI_DDR0_LOG_INFO_415_384_MASK 0x00000001 #define MON_AXI_DDR0_LOG_INFO_W13_MON_AXI_DDR0_LOG_INFO_427_416_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # MonAxiDdr1CurInfo Definition */ #define MON_AXI_DDR1_CUR_INFO_W0_MON_AXI_DDR1_CUR_INFO_31_0 BIT(0) @@ -1850,7 +1875,7 @@ struct SysCtl_regs { #define MON_AXI_DDR1_CUR_INFO_W8_MON_AXI_DDR1_CUR_INFO_287_256_MASK 0x00000001 #define MON_AXI_DDR1_CUR_INFO_W9_MON_AXI_DDR1_CUR_INFO_299_288_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # MonAxiDdr1LogInfo Definition */ #define MON_AXI_DDR1_LOG_INFO_W0_MON_AXI_DDR1_LOG_INFO_31_0 BIT(0) @@ -1875,7 +1900,7 @@ struct SysCtl_regs { #define MON_AXI_DDR1_LOG_INFO_W8_MON_AXI_DDR1_LOG_INFO_287_256_MASK 0x00000001 #define MON_AXI_DDR1_LOG_INFO_W9_MON_AXI_DDR1_LOG_INFO_299_288_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # MonAxiMemCurInfo Definition */ #define MON_AXI_MEM_CUR_INFO_W0_MON_AXI_MEM_CUR_INFO_31_0 BIT(0) @@ -1900,7 +1925,7 @@ struct SysCtl_regs { #define MON_AXI_MEM_CUR_INFO_W8_MON_AXI_MEM_CUR_INFO_287_256_MASK 0x00000001 #define MON_AXI_MEM_CUR_INFO_W9_MON_AXI_MEM_CUR_INFO_303_288_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # MonAxiMemLogInfo Definition */ #define MON_AXI_MEM_LOG_INFO_W0_MON_AXI_MEM_LOG_INFO_31_0 BIT(0) @@ -1925,7 +1950,7 @@ struct SysCtl_regs { #define MON_AXI_MEM_LOG_INFO_W8_MON_AXI_MEM_LOG_INFO_287_256_MASK 0x00000001 #define MON_AXI_MEM_LOG_INFO_W9_MON_AXI_MEM_LOG_INFO_303_288_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # MonAxiMshCurInfo Definition */ #define MON_AXI_MSH_CUR_INFO_W0_MON_AXI_MSH_CUR_INFO_31_0 BIT(0) @@ -1948,7 +1973,7 @@ struct SysCtl_regs { #define MON_AXI_MSH_CUR_INFO_W7_MON_AXI_MSH_CUR_INFO_255_224_MASK 0x00000001 #define MON_AXI_MSH_CUR_INFO_W8_MON_AXI_MSH_CUR_INFO_275_256_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # MonAxiMshLogInfo Definition */ #define MON_AXI_MSH_LOG_INFO_W0_MON_AXI_MSH_LOG_INFO_31_0 BIT(0) @@ -1973,7 +1998,7 @@ struct SysCtl_regs { #define MON_AXI_MSH_LOG_INFO_W8_MON_AXI_MSH_LOG_INFO_275_256_MASK 0x00000001 #define MON_AXI_MSH_LOG_INFO_W8_MON_AXI_MSH_LOG_WD_ID_MASK 0x0f000000 -/* ############################################################################ +/* ################################################################################ * # MonAxiPcieCurInfo Definition */ #define MON_AXI_PCIE_CUR_INFO_W0_MON_AXI_PCIE_CUR_INFO_31_0 BIT(0) @@ -1998,7 +2023,7 @@ struct SysCtl_regs { #define MON_AXI_PCIE_CUR_INFO_W8_MON_AXI_PCIE_CUR_INFO_287_256_MASK 0x00000001 #define MON_AXI_PCIE_CUR_INFO_W9_MON_AXI_PCIE_CUR_INFO_291_288_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # MonAxiPcieLogInfo Definition */ #define MON_AXI_PCIE_LOG_INFO_W0_MON_AXI_PCIE_LOG_INFO_31_0 BIT(0) @@ -2023,7 +2048,7 @@ struct SysCtl_regs { #define MON_AXI_PCIE_LOG_INFO_W8_MON_AXI_PCIE_LOG_INFO_287_256_MASK 0x00000001 #define MON_AXI_PCIE_LOG_INFO_W9_MON_AXI_PCIE_LOG_INFO_291_288_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # MonAxiQspiCurInfo Definition */ #define MON_AXI_QSPI_CUR_INFO_W0_MON_AXI_QSPI_CUR_INFO_31_0 BIT(0) @@ -2042,7 +2067,7 @@ struct SysCtl_regs { #define MON_AXI_QSPI_CUR_INFO_W5_MON_AXI_QSPI_CUR_INFO_191_160_MASK 0x00000001 #define MON_AXI_QSPI_CUR_INFO_W6_MON_AXI_QSPI_CUR_INFO_223_192_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # MonAxiQspiLogInfo Definition */ #define MON_AXI_QSPI_LOG_INFO_W0_MON_AXI_QSPI_LOG_INFO_31_0 BIT(0) @@ -2063,7 +2088,7 @@ struct SysCtl_regs { #define MON_AXI_QSPI_LOG_INFO_W6_MON_AXI_QSPI_LOG_INFO_223_192_MASK 0x00000001 #define MON_AXI_QSPI_LOG_INFO_W7_MON_AXI_QSPI_LOG_WD_ID_MASK 0x000003ff -/* ############################################################################ +/* ################################################################################ * # MonAxiSupCurInfo Definition */ #define MON_AXI_SUP_CUR_INFO_W0_MON_AXI_SUP_CUR_INFO_31_0 BIT(0) @@ -2084,7 +2109,7 @@ struct SysCtl_regs { #define MON_AXI_SUP_CUR_INFO_W6_MON_AXI_SUP_CUR_INFO_223_192_MASK 0x00000001 #define MON_AXI_SUP_CUR_INFO_W7_MON_AXI_SUP_CUR_INFO_231_224_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # MonAxiSupLogInfo Definition */ #define MON_AXI_SUP_LOG_INFO_W0_MON_AXI_SUP_LOG_INFO_31_0 BIT(0) @@ -2105,7 +2130,7 @@ struct SysCtl_regs { #define MON_AXI_SUP_LOG_INFO_W6_MON_AXI_SUP_LOG_INFO_223_192_MASK 0x00000001 #define MON_AXI_SUP_LOG_INFO_W7_MON_AXI_SUP_LOG_INFO_231_224_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # MonSysApbCurInfo Definition */ #define MON_SYS_APB_CUR_INFO_W0_MON_SYS_APB_CUR_ADDR BIT(0) @@ -2126,7 +2151,7 @@ struct SysCtl_regs { #define MON_SYS_APB_CUR_INFO_W3_MON_SYS_APB_CUR_SEL_MASK 0x00000010 #define MON_SYS_APB_CUR_INFO_W3_MON_SYS_APB_CUR_SLV_ERR_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # MonSysApbLogInfo Definition */ #define MON_SYS_APB_LOG_INFO_W0_MON_SYS_APB_LOG_ADDR BIT(0) @@ -2149,7 +2174,7 @@ struct SysCtl_regs { #define MON_SYS_APB_LOG_INFO_W3_MON_SYS_APB_LOG_SLV_ERR_MASK 0x00000001 #define MON_SYS_APB_LOG_INFO_W3_MON_SYS_APB_LOG_WRITE_MASK 0x00000004 -/* ############################################################################ +/* ################################################################################ * # MonSecApbCurInfo Definition */ #define MON_SEC_APB_CUR_INFO_W0_MON_SEC_APB_CUR_ADDR BIT(0) @@ -2170,7 +2195,7 @@ struct SysCtl_regs { #define MON_SEC_APB_CUR_INFO_W3_MON_SEC_APB_CUR_ENABLE_MASK 0x00000008 #define MON_SEC_APB_CUR_INFO_W3_MON_SEC_APB_CUR_SEL_MASK 0x00000010 -/* ############################################################################ +/* ################################################################################ * # MonSecApbLogInfo Definition */ #define MON_SEC_APB_LOG_INFO_W0_MON_SEC_APB_LOG_ADDR BIT(0) @@ -2193,7 +2218,7 @@ struct SysCtl_regs { #define MON_SEC_APB_LOG_INFO_W3_MON_SEC_APB_LOG_SEL_MASK 0x00000010 #define MON_SEC_APB_LOG_INFO_W3_MON_SEC_APB_ERR_CNT_MASK 0x0000ff00 -/* ############################################################################ +/* ################################################################################ * # DebugCpuCnt Definition */ #define DEBUG_CPU_CNT_W0_MON_CPU_WA_LOG_CNT BIT(8) @@ -2212,7 +2237,7 @@ struct SysCtl_regs { #define DEBUG_CPU_CNT_W1_MON_CPU_WR_RESP_ERROR_CNT_MASK 0xff000000 #define DEBUG_CPU_CNT_W1_MON_CPU_RD_RESP_ERROR_CNT_MASK 0x00ff0000 -/* ############################################################################ +/* ################################################################################ * # DebugMemCnt Definition */ #define DEBUG_MEM_CNT_W0_MON_MEM_WA_LOG_CNT BIT(8) @@ -2227,7 +2252,7 @@ struct SysCtl_regs { #define DEBUG_MEM_CNT_W1_MON_MEM_WR_OUT_CNT_MASK 0x00001f00 #define DEBUG_MEM_CNT_W1_MON_MEM_RD_OUT_CNT_MASK 0x0000001f -/* ############################################################################ +/* ################################################################################ * # DebugDdrCnt Definition */ #define DEBUG_DDR_CNT_W0_MON_DDR0_WA_LOG_CNT BIT(8) @@ -2260,7 +2285,7 @@ struct SysCtl_regs { #define DEBUG_DDR_CNT_W3_MON_DDR1_RD_OUT_CNT_MASK 0x0000001f #define DEBUG_DDR_CNT_W3_MON_DDR1_WR_RESP_ERROR_CNT_MASK 0xff000000 -/* ############################################################################ +/* ################################################################################ * # DebugMshCnt Definition */ #define DEBUG_MSH_CNT_W0_MON_MSH_WD_LOG_CNT BIT(16) @@ -2275,7 +2300,7 @@ struct SysCtl_regs { #define DEBUG_MSH_CNT_W1_MON_MSH_RD_OUT_CNT_MASK 0x0000001f #define DEBUG_MSH_CNT_W1_MON_MSH_WR_OUT_CNT_MASK 0x00001f00 -/* ############################################################################ +/* ################################################################################ * # DebugPcieCnt Definition */ #define DEBUG_PCIE_CNT_W0_MON_PCIE_WD_LOG_CNT BIT(16) @@ -2294,7 +2319,7 @@ struct SysCtl_regs { #define DEBUG_PCIE_CNT_W1_MON_PCIE_WR_RESP_ERROR_CNT_MASK 0xff000000 #define DEBUG_PCIE_CNT_W1_MON_PCIE_RD_RESP_ERROR_CNT_MASK 0x00ff0000 -/* ############################################################################ +/* ################################################################################ * # DebugQspiCnt Definition */ #define DEBUG_QSPI_CNT_W0_MON_QSPI_WD_LOG_CNT BIT(16) @@ -2309,7 +2334,7 @@ struct SysCtl_regs { #define DEBUG_QSPI_CNT_W1_MON_QSPI_RD_OUT_CNT_MASK 0x0000001f #define DEBUG_QSPI_CNT_W1_MON_QSPI_WR_OUT_CNT_MASK 0x00001f00 -/* ############################################################################ +/* ################################################################################ * # DebugSupCnt Definition */ #define DEBUG_SUP_CNT_W0_MON_SUP_WD_LOG_CNT BIT(16) @@ -2328,7 +2353,7 @@ struct SysCtl_regs { #define DEBUG_SUP_CNT_W1_MON_SUP_WR_RESP_ERROR_CNT_MASK 0xff000000 #define DEBUG_SUP_CNT_W1_MON_SUP_RD_OUT_CNT_MASK 0x0000001f -/* ############################################################################ +/* ################################################################################ * # SysSpiVecLog Definition */ #define SYS_SPI_VEC_LOG_W0_SPI_VEC_LOG_31_0 BIT(0) @@ -2343,7 +2368,7 @@ struct SysCtl_regs { #define SYS_SPI_VEC_LOG_W3_SPI_VEC_LOG_127_96_MASK 0x00000001 #define SYS_SPI_VEC_LOG_W4_SPI_VEC_LOG_159_128_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # DebugAhbRespCnt Definition */ #define DEBUG_AHB_RESP_CNT_W0_MON_MSH_CFG_RESP_ERROR_CNT BIT(8) @@ -2354,7 +2379,7 @@ struct SysCtl_regs { #define DEBUG_AHB_RESP_CNT_W0_MON_DDR_CFG_RESP_ERROR_CNT_MASK 0x000000ff #define DEBUG_AHB_RESP_CNT_W0_MON_USB_CFG_RESP_ERROR_CNT_MASK 0x00ff0000 -/* ############################################################################ +/* ################################################################################ * # DebugGicRespCnt Definition */ #define DEBUG_GIC_RESP_CNT_W0_MON_GIC_RD_RESP_ERROR_CNT BIT(0) @@ -2363,7 +2388,70 @@ struct SysCtl_regs { #define DEBUG_GIC_RESP_CNT_W0_MON_GIC_RD_RESP_ERROR_CNT_MASK 0x000000ff #define DEBUG_GIC_RESP_CNT_W0_MON_GIC_WR_RESP_ERROR_CNT_MASK 0x0000ff00 -/* ############################################################################ +/* ################################################################################ + * # SysDdrEccCtl Definition + */ +#define SYS_DDR_ECC_CTL_W0_DDR_ECC_CLEAR_EN BIT(0) +#define SYS_DDR_ECC_CTL_W0_DDR_ECC_ONE_BIT_ERR_CNT BIT(8) +#define SYS_DDR_ECC_CTL_W0_DDR_ECC_TWO_BIT_ERR_CNT BIT(12) + +#define SYS_DDR_ECC_CTL_W0_DDR_ECC_CLEAR_EN_MASK 0x00000001 +#define SYS_DDR_ECC_CTL_W0_DDR_ECC_ONE_BIT_ERR_CNT_MASK 0x00000f00 +#define SYS_DDR_ECC_CTL_W0_DDR_ECC_TWO_BIT_ERR_CNT_MASK 0x0000f000 + +/* ################################################################################ + * # SysDdrInitStartAddr Definition + */ +#define SYS_DDR_INIT_START_ADDR_W0_CFG_INIT_START_ADDR0 BIT(0) +#define SYS_DDR_INIT_START_ADDR_W1_CFG_INIT_START_ADDR1 BIT(0) + +#define SYS_DDR_INIT_START_ADDR_W0_CFG_INIT_START_ADDR0_MASK 0xffffffff +#define SYS_DDR_INIT_START_ADDR_W1_CFG_INIT_START_ADDR1_MASK 0x0000000f + +/* ################################################################################ + * # SysDdrInitLastAddr Definition + */ +#define SYS_DDR_INIT_LAST_ADDR_W0_CFG_INIT_LAST_ADDR0 BIT(0) +#define SYS_DDR_INIT_LAST_ADDR_W1_CFG_INIT_LAST_ADDR1 BIT(0) + +#define SYS_DDR_INIT_LAST_ADDR_W0_CFG_INIT_LAST_ADDR0_MASK 0xffffffff +#define SYS_DDR_INIT_LAST_ADDR_W1_CFG_INIT_LAST_ADDR1_MASK 0x0000000f + +/* ################################################################################ + * # SysDdrInitData Definition + */ +#define SYS_DDR_INIT_DATA_W0_CFG_INIT_WR_DATA0 BIT(0) +#define SYS_DDR_INIT_DATA_W1_CFG_INIT_WR_DATA1 BIT(0) + +#define SYS_DDR_INIT_DATA_W0_CFG_INIT_WR_DATA0_MASK 0xffffffff +#define SYS_DDR_INIT_DATA_W1_CFG_INIT_WR_DATA1_MASK 0xffffffff + +/* ################################################################################ + * # SysDdrInitMode Definition */ +#define SYS_DDR_INIT_MODE_W0_CFG_INIT_AXI_CRITICAL BIT(0) +#define SYS_DDR_INIT_MODE_W0_CFG_INIT_AXI_LEN BIT(8) +#define SYS_DDR_INIT_MODE_W0_CFG_INIT_AXI_QOS BIT(4) +#define SYS_DDR_INIT_MODE_W0_CFG_INIT_AXI_STRB BIT(16) +#define SYS_DDR_INIT_MODE_W0_CFG_INIT_AXI_THRD BIT(24) + +#define SYS_DDR_INIT_MODE_W0_CFG_INIT_AXI_CRITICAL_MASK 0x00000001 +#define SYS_DDR_INIT_MODE_W0_CFG_INIT_AXI_LEN_MASK 0x0000ff00 +#define SYS_DDR_INIT_MODE_W0_CFG_INIT_AXI_QOS_MASK 0x000000f0 +#define SYS_DDR_INIT_MODE_W0_CFG_INIT_AXI_STRB_MASK 0x00ff0000 +#define SYS_DDR_INIT_MODE_W0_CFG_INIT_AXI_THRD_MASK 0x0f000000 + +/* ################################################################################ + * # SysDdrInitCtl Definition + */ +#define SYS_DDR_INIT_CTL_W0_CFG_DDR_INIT_EN BIT(0) +#define SYS_DDR_INIT_CTL_W0_LOG_DDR_INIT_DONE BIT(4) +#define SYS_DDR_INIT_CTL_W0_LOG_DDR_INIT_RESP BIT(8) + +#define SYS_DDR_INIT_CTL_W0_CFG_DDR_INIT_EN_MASK 0x00000001 +#define SYS_DDR_INIT_CTL_W0_LOG_DDR_INIT_DONE_MASK 0x00000010 +#define SYS_DDR_INIT_CTL_W0_LOG_DDR_INIT_RESP_MASK 0x00000300 + +/* ################################################################################ * # DebugMemPtrCfg Definition */ #define DEBUG_MEM_PTR_CFG_W0_CFG_DBG_START_PTR BIT(0) @@ -2372,63 +2460,63 @@ struct SysCtl_regs { #define DEBUG_MEM_PTR_CFG_W0_CFG_DBG_START_PTR_MASK 0x00003fff #define DEBUG_MEM_PTR_CFG_W0_CFG_DBG_END_PTR_MASK 0x3fff0000 -/* ############################################################################ +/* ################################################################################ * # Grant0IntMask Definition */ #define GRANT0_INT_MASK_W0_GRANT0_INT_MASK BIT(0) #define GRANT0_INT_MASK_W0_GRANT0_INT_MASK_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # Grant0IntCtl Definition */ #define GRANT0_INT_CTL_W0_GRANT0_INT_CTL BIT(0) #define GRANT0_INT_CTL_W0_GRANT0_INT_CTL_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # Grant1IntMask Definition */ #define GRANT1_INT_MASK_W0_GRANT1_INT_MASK BIT(0) #define GRANT1_INT_MASK_W0_GRANT1_INT_MASK_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # Grant1IntCtl Definition */ #define GRANT1_INT_CTL_W0_GRANT1_INT_CTL BIT(0) #define GRANT1_INT_CTL_W0_GRANT1_INT_CTL_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # Grant2IntMask Definition */ #define GRANT2_INT_MASK_W0_GRANT2_INT_MASK BIT(0) #define GRANT2_INT_MASK_W0_GRANT2_INT_MASK_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # Grant2IntCtl Definition */ #define GRANT2_INT_CTL_W0_GRANT2_INT_CTL BIT(0) #define GRANT2_INT_CTL_W0_GRANT2_INT_CTL_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # Grant3IntMask Definition */ #define GRANT3_INT_MASK_W0_GRANT3_INT_MASK BIT(0) #define GRANT3_INT_MASK_W0_GRANT3_INT_MASK_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # Grant3IntCtl Definition */ #define GRANT3_INT_CTL_W0_GRANT3_INT_CTL BIT(0) #define GRANT3_INT_CTL_W0_GRANT3_INT_CTL_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SysIntrIntCtl Definition */ #define SYS_INTR_INT_CTL_W0_SYS_INTR_INT_CTL_31_0 BIT(0) @@ -2437,7 +2525,7 @@ struct SysCtl_regs { #define SYS_INTR_INT_CTL_W0_SYS_INTR_INT_CTL_31_0_MASK 0x00000001 #define SYS_INTR_INT_CTL_W1_SYS_INTR_INT_CTL_63_32_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SupIntrIntCtl Definition */ #define SUP_INTR_INT_CTL_W0_SUP_INTR_INT_CTL_31_0 BIT(0) @@ -2446,119 +2534,119 @@ struct SysCtl_regs { #define SUP_INTR_INT_CTL_W0_SUP_INTR_INT_CTL_31_0_MASK 0x00000001 #define SUP_INTR_INT_CTL_W1_SUP_INTR_INT_CTL_63_32_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SysMiscInfo0 Definition */ #define SYS_MISC_INFO0_W0_SYS_MISC_INFO0 BIT(0) #define SYS_MISC_INFO0_W0_SYS_MISC_INFO0_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SysMiscInfo1 Definition */ #define SYS_MISC_INFO1_W0_SYS_MISC_INFO1 BIT(0) #define SYS_MISC_INFO1_W0_SYS_MISC_INFO1_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SysMiscInfo2 Definition */ #define SYS_MISC_INFO2_W0_SYS_MISC_INFO2 BIT(0) #define SYS_MISC_INFO2_W0_SYS_MISC_INFO2_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SysMiscInfo3 Definition */ #define SYS_MISC_INFO3_W0_SYS_MISC_INFO3 BIT(0) #define SYS_MISC_INFO3_W0_SYS_MISC_INFO3_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # CommonInfo0 Definition */ #define COMMON_INFO0_W0_COMMON_INFO0 BIT(0) #define COMMON_INFO0_W0_COMMON_INFO0_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # CommonInfo1 Definition */ #define COMMON_INFO1_W0_COMMON_INFO1 BIT(0) #define COMMON_INFO1_W0_COMMON_INFO1_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # CommonInfo2 Definition */ #define COMMON_INFO2_W0_COMMON_INFO2 BIT(0) #define COMMON_INFO2_W0_COMMON_INFO2_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # CommonInfo3 Definition */ #define COMMON_INFO3_W0_COMMON_INFO3 BIT(0) #define COMMON_INFO3_W0_COMMON_INFO3_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # Grant0ExtMask Definition */ #define GRANT0_EXT_MASK_W0_GRANT0_EXT_MASK BIT(0) #define GRANT0_EXT_MASK_W0_GRANT0_EXT_MASK_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # Grant0ExtCtl Definition */ #define GRANT0_EXT_CTL_W0_GRANT0_EXT_CTL BIT(0) #define GRANT0_EXT_CTL_W0_GRANT0_EXT_CTL_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # Grant1ExtMask Definition */ #define GRANT1_EXT_MASK_W0_GRANT1_EXT_MASK BIT(0) #define GRANT1_EXT_MASK_W0_GRANT1_EXT_MASK_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # Grant1ExtCtl Definition */ #define GRANT1_EXT_CTL_W0_GRANT1_EXT_CTL BIT(0) #define GRANT1_EXT_CTL_W0_GRANT1_EXT_CTL_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # Grant2ExtMask Definition */ #define GRANT2_EXT_MASK_W0_GRANT2_EXT_MASK BIT(0) #define GRANT2_EXT_MASK_W0_GRANT2_EXT_MASK_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # Grant2ExtCtl Definition */ #define GRANT2_EXT_CTL_W0_GRANT2_EXT_CTL BIT(0) #define GRANT2_EXT_CTL_W0_GRANT2_EXT_CTL_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # Grant3ExtMask Definition */ #define GRANT3_EXT_MASK_W0_GRANT3_EXT_MASK BIT(0) #define GRANT3_EXT_MASK_W0_GRANT3_EXT_MASK_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # Grant3ExtCtl Definition */ #define GRANT3_EXT_CTL_W0_GRANT3_EXT_CTL BIT(0) #define GRANT3_EXT_CTL_W0_GRANT3_EXT_CTL_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SysIntrExtCtl Definition */ #define SYS_INTR_EXT_CTL_W0_SYS_INTR_EXT_CTL_31_0 BIT(0) @@ -2567,7 +2655,7 @@ struct SysCtl_regs { #define SYS_INTR_EXT_CTL_W0_SYS_INTR_EXT_CTL_31_0_MASK 0x00000001 #define SYS_INTR_EXT_CTL_W1_SYS_INTR_EXT_CTL_63_32_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SupIntrExtCtl Definition */ #define SUP_INTR_EXT_CTL_W0_SUP_INTR_EXT_CTL_31_0 BIT(0) @@ -2576,34 +2664,111 @@ struct SysCtl_regs { #define SUP_INTR_EXT_CTL_W0_SUP_INTR_EXT_CTL_31_0_MASK 0x00000001 #define SUP_INTR_EXT_CTL_W1_SUP_INTR_EXT_CTL_63_32_MASK 0x00000001 -/* ############################################################################ +/* ################################################################################ * # SupMiscInfo0 Definition */ #define SUP_MISC_INFO0_W0_SUP_MISC_INFO0 BIT(0) #define SUP_MISC_INFO0_W0_SUP_MISC_INFO0_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SupMiscInfo1 Definition */ #define SUP_MISC_INFO1_W0_SUP_MISC_INFO1 BIT(0) #define SUP_MISC_INFO1_W0_SUP_MISC_INFO1_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SupMiscInfo2 Definition */ #define SUP_MISC_INFO2_W0_SUP_MISC_INFO2 BIT(0) #define SUP_MISC_INFO2_W0_SUP_MISC_INFO2_MASK 0xffffffff -/* ############################################################################ +/* ################################################################################ * # SupMiscInfo3 Definition */ #define SUP_MISC_INFO3_W0_SUP_MISC_INFO3 BIT(0) #define SUP_MISC_INFO3_W0_SUP_MISC_INFO3_MASK 0xffffffff +/* ################################################################################ + * # SysBusDbgEn Definition + */ +#define SYS_BUS_DBG_EN_W0_CFG_DBG_EN_VEC0 BIT(0) +#define SYS_BUS_DBG_EN_W1_CFG_DBG_EN_VEC1 BIT(0) + +#define SYS_BUS_DBG_EN_W0_CFG_DBG_EN_VEC0_MASK 0xffffffff +#define SYS_BUS_DBG_EN_W1_CFG_DBG_EN_VEC1_MASK 0x001fffff + +/* ################################################################################ + * # SysApbErrLog Definition + */ +#define SYS_APB_ERR_LOG_W0_APB_SYS_ERR_LOG BIT(0) + +#define SYS_APB_ERR_LOG_W0_APB_SYS_ERR_LOG_MASK 0x00000fff + +/* ################################################################################ + * # MshClkPadSchmitEn Definition + */ +#define MSH_CLK_PAD_SCHMIT_EN_W0_MSH_CLK_PAD_SCHMIT_EN BIT(0) + +#define MSH_CLK_PAD_SCHMIT_EN_W0_MSH_CLK_PAD_SCHMIT_EN_MASK 0x00000001 + +/* ################################################################################ + * # SysI2C0DebugStatus Definition + */ +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_ADDR10_BIT BIT(6) +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_ADDR_PROC BIT(0) +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_DATA_PROC BIT(1) +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_MASTER_ACT BIT(7) +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_MASTER_STATE BIT(8) +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_RD_PROC BIT(2) +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_SLAVE_ACT BIT(20) +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_SLAVE_STATE BIT(16) +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_START_GEN BIT(4) +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_STOP_GEN BIT(5) +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_WR_PROC BIT(3) + +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_ADDR10_BIT_MASK 0x00000040 +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_ADDR_PROC_MASK 0x00000001 +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_DATA_PROC_MASK 0x00000002 +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_MASTER_ACT_MASK 0x00000080 +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_MASTER_STATE_MASK 0x00001f00 +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_RD_PROC_MASK 0x00000004 +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_SLAVE_ACT_MASK 0x00100000 +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_SLAVE_STATE_MASK 0x000f0000 +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_START_GEN_MASK 0x00000010 +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_STOP_GEN_MASK 0x00000020 +#define SYS_I2_C0_DEBUG_STATUS_W0_DBG_I2_C0_WR_PROC_MASK 0x00000008 + +/* ################################################################################ + * # SysI2C1DebugStatus Definition + */ +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_ADDR10_BIT BIT(6) +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_ADDR_PROC BIT(0) +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_DATA_PROC BIT(1) +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_MASTER_ACT BIT(7) +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_MASTER_STATE BIT(8) +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_RD_PROC BIT(2) +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_SLAVE_ACT BIT(20) +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_SLAVE_STATE BIT(16) +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_START_GEN BIT(4) +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_STOP_GEN BIT(5) +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_WR_PROC BIT(3) + +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_ADDR10_BIT_MASK 0x00000040 +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_ADDR_PROC_MASK 0x00000001 +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_DATA_PROC_MASK 0x00000002 +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_MASTER_ACT_MASK 0x00000080 +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_MASTER_STATE_MASK 0x00001f00 +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_RD_PROC_MASK 0x00000004 +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_SLAVE_ACT_MASK 0x00100000 +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_SLAVE_STATE_MASK 0x000f0000 +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_START_GEN_MASK 0x00000010 +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_STOP_GEN_MASK 0x00000020 +#define SYS_I2_C1_DEBUG_STATUS_W0_DBG_I2_C1_WR_PROC_MASK 0x00000008 + struct SysCtl_mems { u32 SysApbMem0[3]; /* 0x0000fe00 */ u32 SysApbMem0_rsv3; @@ -2671,7 +2836,7 @@ struct SysCtl_mems { u32 SecApbMem15_rsv3; }; -/* ############################################################################ +/* ################################################################################ * # SysApbMem Definition */ #define SYS_APB_MEM_W0_ADDR BIT(0) @@ -2684,7 +2849,7 @@ struct SysCtl_mems { #define SYS_APB_MEM_W2_WR_EN_MASK 0x00000001 #define SYS_APB_MEM_W2_SLV_ERR_MASK 0x00000002 -/* ############################################################################ +/* ################################################################################ * # SecApbMem Definition */ #define SEC_APB_MEM_W0_ADDR BIT(0) @@ -2697,6 +2862,13 @@ struct SysCtl_mems { #define SEC_APB_MEM_W2_WR_EN_MASK 0x00000001 #define SEC_APB_MEM_W2_SLV_ERR_MASK 0x00000002 +/* ################################################################################ + * # SysPcieMem Definition + */ +#define SYS_PCIE_MEM_W0_DATA_BIT BIT(0) + +#define SYS_PCIE_MEM_W0_DATA_MASK 0xffffffff + /* Bootmode setting values */ #define ROM_QSPI_MODE 0x00000000 #define ROM_EMMC_MODE 0x00000001 diff --git a/platform/centec-arm64/tsingma-bsp/src/pinctrl-ctc/core.h b/platform/centec-arm64/tsingma-bsp/src/pinctrl-ctc/core.h index 4a0526e567df..7110f259cd78 100644 --- a/platform/centec-arm64/tsingma-bsp/src/pinctrl-ctc/core.h +++ b/platform/centec-arm64/tsingma-bsp/src/pinctrl-ctc/core.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Core private header for the pin control subsystem * @@ -5,8 +6,6 @@ * Written on behalf of Linaro for ST-Ericsson * * Author: Linus Walleij - * - * License terms: GNU General Public License (GPL) version 2 */ #include @@ -218,7 +217,7 @@ int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name, int pinctrl_generic_remove_group(struct pinctrl_dev *pctldev, unsigned int group_selector); -#endif /* CONFIG_GENERIC_PINCTRL_GROUPS */ +#endif /* CONFIG_GENERIC_PINCTRL_GROUPS */ struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name); struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np); @@ -233,13 +232,12 @@ static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev, return radix_tree_lookup(&pctldev->pin_desc_tree, pin); } -extern struct pinctrl_gpio_range * -pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev, - unsigned int pin); - -int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps, - bool dup); -void pinctrl_unregister_map(const struct pinctrl_map *map); +extern struct pinctrl_gpio_range *pinctrl_find_gpio_range_from_pin_nolock(struct + pinctrl_dev + *pctldev, + unsigned + int + pin); extern int pinctrl_force_sleep(struct pinctrl_dev *pctldev); extern int pinctrl_force_default(struct pinctrl_dev *pctldev); diff --git a/platform/centec-arm64/tsingma-bsp/src/pinctrl-ctc/pinconf.h b/platform/centec-arm64/tsingma-bsp/src/pinctrl-ctc/pinconf.h index 6c722505f893..11f858eaa3c6 100644 --- a/platform/centec-arm64/tsingma-bsp/src/pinctrl-ctc/pinconf.h +++ b/platform/centec-arm64/tsingma-bsp/src/pinctrl-ctc/pinconf.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Internal interface between the core pin control system and the * pin config portions @@ -7,8 +8,6 @@ * Based on bits of regulator core, gpio core and clk core * * Author: Linus Walleij - * - * License terms: GNU General Public License (GPL) version 2 */ #ifdef CONFIG_PINCONF @@ -16,7 +15,7 @@ int pinconf_check_ops(struct pinctrl_dev *pctldev); int pinconf_validate_map(const struct pinctrl_map *map, int i); int pinconf_map_to_setting(const struct pinctrl_map *map, - struct pinctrl_setting *setting); + struct pinctrl_setting *setting); void pinconf_free_setting(const struct pinctrl_setting *setting); int pinconf_apply_setting(const struct pinctrl_setting *setting); @@ -45,7 +44,7 @@ static inline int pinconf_validate_map(const struct pinctrl_map *map, int i) } static inline int pinconf_map_to_setting(const struct pinctrl_map *map, - struct pinctrl_setting *setting) + struct pinctrl_setting *setting) { return 0; } diff --git a/platform/centec-arm64/tsingma-bsp/src/pinctrl-ctc/pinctrl-ctc.c b/platform/centec-arm64/tsingma-bsp/src/pinctrl-ctc/pinctrl-ctc.c old mode 100644 new mode 100755 index 50c65dbfd786..9d5f830eb28e --- a/platform/centec-arm64/tsingma-bsp/src/pinctrl-ctc/pinctrl-ctc.c +++ b/platform/centec-arm64/tsingma-bsp/src/pinctrl-ctc/pinctrl-ctc.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include @@ -24,6 +23,7 @@ #include #include #include +#include #include "../include/sysctl.h" #include "pinctrl-ctc.h" #include "core.h" @@ -87,12 +87,13 @@ static void ctc_pinctrl_child_count(struct ctc_pinctrl *info, } static struct ctc_pin_bank *ctc_bank_num_to_bank(struct ctc_pinctrl *info, - unsigned int num) + unsigned num) { struct ctc_pin_bank *b = info->ctrl->pin_banks; - if (num < info->ctrl->nr_banks) + if (num < info->ctrl->nr_banks) { return &b[num]; + } return ERR_PTR(-EINVAL); } @@ -195,8 +196,10 @@ static int ctc_pinctrl_parse_dt(struct platform_device *pdev, struct device_node *child; info->ctrl = devm_kzalloc(dev, sizeof(struct ctc_pin_ctrl), GFP_KERNEL); - if (!info->ctrl) + if (!info->ctrl) { + dev_err(dev, "failed to allocate memory for pin\n"); return -EINVAL; + } ret = of_property_read_u32(np, "ctc,pinctrl-bank0", &bank0_pins); if (ret < 0) { @@ -229,13 +232,17 @@ static int ctc_pinctrl_parse_dt(struct platform_device *pdev, info->functions = devm_kzalloc(dev, info->nfunctions * sizeof(struct ctc_pmx_func), GFP_KERNEL); - if (!info->functions) + if (!info->functions) { + dev_err(dev, "failed to allocate memory for function list\n"); return -EINVAL; + } info->groups = devm_kzalloc(dev, info->ngroups * sizeof(struct ctc_pin_group), GFP_KERNEL); - if (!info->groups) + if (!info->groups) { + dev_err(dev, "failed allocate memory for ping group list\n"); return -EINVAL; + } i = 0; for_each_child_of_node(np, child) { @@ -258,7 +265,7 @@ static int ctc_get_groups_count(struct pinctrl_dev *pctldev) } static const char *ctc_get_group_name(struct pinctrl_dev *pctldev, - unsigned int selector) + unsigned selector) { struct ctc_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); @@ -266,8 +273,8 @@ static const char *ctc_get_group_name(struct pinctrl_dev *pctldev, } static int ctc_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int selector, const unsigned int **pins, - unsigned int *npins) + unsigned selector, const unsigned **pins, + unsigned *npins) { struct ctc_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); @@ -298,7 +305,7 @@ static inline const struct ctc_pin_group *ctc_pinctrl_name_to_group(const struct static int ctc_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np, - struct pinctrl_map **map, unsigned int *num_maps) + struct pinctrl_map **map, unsigned *num_maps) { struct ctc_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); const struct ctc_pin_group *grp; @@ -348,7 +355,7 @@ static int ctc_pmx_get_funcs_count(struct pinctrl_dev *pctldev) } static const char *ctc_pmx_get_func_name(struct pinctrl_dev *pctldev, - unsigned int selector) + unsigned selector) { struct ctc_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); @@ -356,8 +363,8 @@ static const char *ctc_pmx_get_func_name(struct pinctrl_dev *pctldev, } static int ctc_pmx_get_groups(struct pinctrl_dev *pctldev, - unsigned int selector, const char *const **groups, - unsigned int *const num_groups) + unsigned selector, const char *const **groups, + unsigned *const num_groups) { struct ctc_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); @@ -368,7 +375,7 @@ static int ctc_pmx_get_groups(struct pinctrl_dev *pctldev, } static struct ctc_pin_bank *ctc_pin_to_bank(struct ctc_pinctrl *info, - unsigned int pin) + unsigned pin) { struct ctc_pin_bank *b = info->ctrl->pin_banks; @@ -396,8 +403,8 @@ static int ctc_set_pin_mux(struct ctc_pinctrl *info, struct ctc_pin_bank *bank, return 0; } -static int ctc_pmx_set(struct pinctrl_dev *pctldev, unsigned int selector, - unsigned int group) +static int ctc_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) { struct ctc_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); const unsigned int *pins = info->groups[group].pins; @@ -408,7 +415,8 @@ static int ctc_pmx_set(struct pinctrl_dev *pctldev, unsigned int selector, dev_dbg(info->dev, "enable function %s group %s\n", info->functions[selector].name, info->groups[group].name); - /* for each pin in the pin group selected, program the corresponding pin + /* + * for each pin in the pin group selected, program the correspoding pin * pin function number in the config register. */ for (cnt = 0; cnt < info->groups[group].npins; cnt++) { @@ -423,7 +431,7 @@ static int ctc_pmx_set(struct pinctrl_dev *pctldev, unsigned int selector, } static void ctc_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned int num_maps) + struct pinctrl_map *map, unsigned num_maps) { } @@ -528,7 +536,7 @@ static struct platform_driver ctc_pinctrl_driver = { //static int __init ctc_pinctrl_drv_register(void) //{ -// return platform_driver_register(&ctc_pinctrl_driver); +// return platform_driver_register(&ctc_pinctrl_driver); //} // //postcore_initcall(ctc_pinctrl_drv_register); diff --git a/platform/centec-arm64/tsingma-bsp/src/pwm-ctc/pwm-ctc.c b/platform/centec-arm64/tsingma-bsp/src/pwm-ctc/pwm-ctc.c old mode 100644 new mode 100755 index 8b2a031a46fa..a2e1f997766e --- a/platform/centec-arm64/tsingma-bsp/src/pwm-ctc/pwm-ctc.c +++ b/platform/centec-arm64/tsingma-bsp/src/pwm-ctc/pwm-ctc.c @@ -1,4 +1,5 @@ -/* Centec PWM driver +/* + * Centec PWM driver * * Author: wangyb * @@ -25,14 +26,14 @@ #include #include -#define CTC_NUM_PWM 4 -#define CTC_CR_PWM 0x0 -#define CTC_DUTY_PWM 0x4 +#define CTC_NUM_PWM 4 +#define CTC_CR_PWM 0x0 +#define CTC_DUTY_PWM 0x4 #define CTC_MAX_PERIOD_PWM 0xFFFFFF -#define CTC_MAX_DUTY_PWM 0xFFFFFF +#define CTC_MAX_DUTY_PWM 0xFFFFFF -#define CTC_PWM_ENABLE 0x80000000 +#define CTC_PWM_ENABLE 0x80000000 #define CTC_PERIOD_TACH 0x0 #define CTC_DUTY_TACH 0x4 @@ -60,7 +61,6 @@ static inline u32 ctc_pwm_readl(struct ctc_pwm_chip *chip, unsigned int num, unsigned long offset) { u32 val; - regmap_read(chip->regmap_base, offsetof(struct SysCtl_regs, SysPwmCtl) + offset + num * 0x8, &val); @@ -71,7 +71,6 @@ static inline u32 ctc_tach_readl(struct ctc_pwm_chip *chip, unsigned int num, unsigned long offset) { u32 val; - regmap_read(chip->regmap_base, offsetof(struct SysCtl_regs, SysTachLog) + offset + num * 0x8, &val); @@ -83,19 +82,30 @@ static int ctc_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, { struct ctc_pwm_chip *pc = to_ctc_pwm_chip(chip); u32 cur_value; + u32 duty_cycle = 0; + u32 period_cycle = 0; - duty_ns = duty_ns / 1000; - period_ns = period_ns / 1000; + duty_cycle = duty_ns / 1000; + period_cycle = period_ns / 1000; + + if (duty_cycle < 0 || period_cycle < 1) + return -1; + + if (duty_cycle == 0) { + duty_cycle = 1; + } else if (duty_cycle == period_cycle) { + duty_cycle = duty_cycle - 1; + } /* duty cycle */ - duty_ns = duty_ns & CTC_MAX_DUTY_PWM; - ctc_pwm_writel(pc, pwm->hwpwm, CTC_DUTY_PWM, duty_ns); + duty_cycle = duty_cycle & CTC_MAX_DUTY_PWM; + ctc_pwm_writel(pc, pwm->hwpwm, CTC_DUTY_PWM, duty_cycle); /* period cycle */ - period_ns = period_ns & CTC_MAX_PERIOD_PWM; + period_cycle = period_cycle & CTC_MAX_PERIOD_PWM; cur_value = ctc_pwm_readl(pc, pwm->hwpwm, CTC_CR_PWM); cur_value &= ~(CTC_MAX_PERIOD_PWM); - cur_value |= period_ns << 0; + cur_value |= period_cycle << 0; ctc_pwm_writel(pc, pwm->hwpwm, CTC_CR_PWM, cur_value); return 0; @@ -139,11 +149,11 @@ static void ctc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, state->polarity = PWM_POLARITY_NORMAL; - state->period = (cur_value & (~CTC_PWM_ENABLE)) * 1000; + state->period = (cur_value & (~CTC_PWM_ENABLE)) * 1000; // in nanoseconds cur_value_2 = ctc_pwm_readl(pc, pwm->hwpwm, CTC_DUTY_PWM); - state->duty_cycle = cur_value_2 * 1000; + state->duty_cycle = cur_value_2 * 1000; // in nanoseconds } static int ctc_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, @@ -154,10 +164,10 @@ static int ctc_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, u32 duty_tach; period_tach = ctc_tach_readl(pc, pwm->hwpwm, CTC_PERIOD_TACH) / 4; - result->period = period_tach * 1000; + result->period = period_tach * 1000; // in nanoseconds duty_tach = ctc_tach_readl(pc, pwm->hwpwm, CTC_DUTY_TACH) / 4; - result->duty_cycle = duty_tach * 1000; + result->duty_cycle = duty_tach * 1000; // in nanoseconds return 0; } @@ -188,12 +198,13 @@ static int ctc_pwm_probe(struct platform_device *pdev) pc->regmap_base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "ctc,sysctrl"); pctldev = devm_kzalloc(&pdev->dev, sizeof(*pctldev), GFP_KERNEL); - if (!pctldev) + if (!pctldev) { return -1; + } pctldev->p = pinctrl_get(&pdev->dev); state = pinctrl_lookup_state(pctldev->p, PINCTRL_STATE_DEFAULT); pinctrl_select_state(pctldev->p, state); - pr_info("Select PWM Function\n"); + printk("Select PWM Function\n"); for (i = 0; i < CTC_NUM_PWM; i++) { cur_value = ctc_pwm_readl(pc, i, CTC_CR_PWM); diff --git a/platform/centec-arm64/tsingma-bsp/src/rtc-sd2405/rtc-sd2405.c b/platform/centec-arm64/tsingma-bsp/src/rtc-sd2405/rtc-sd2405.c index 77c76353cd60..671784f11433 100644 --- a/platform/centec-arm64/tsingma-bsp/src/rtc-sd2405/rtc-sd2405.c +++ b/platform/centec-arm64/tsingma-bsp/src/rtc-sd2405/rtc-sd2405.c @@ -1,4 +1,5 @@ -/* rtc class driver for the SD2405 chip +/* + * rtc class driver for the SD2405 chip * * Author: Dale Farnsworth * @@ -45,7 +46,7 @@ static struct i2c_driver sd2405_driver; -static int sd2405_i2c_read_regs(struct i2c_client *client, u8 *buf) +static int sd2405_i2c_read_regs(struct i2c_client *client, u8 * buf) { struct i2c_msg msgs[1] = { { @@ -67,7 +68,9 @@ static int sd2405_i2c_read_regs(struct i2c_client *client, u8 *buf) static int sd2405_i2c_write_regs(struct i2c_client *client, u8 const *buf) { int rc; + u8 temp_reg[SD2405_REG_LEN + 1] = { 0 }; + memcpy(&temp_reg[1], buf, SD2405_REG_LEN); struct i2c_msg msgs[1] = { { @@ -77,8 +80,6 @@ static int sd2405_i2c_write_regs(struct i2c_client *client, u8 const *buf) .buf = temp_reg} }; - memcpy(&temp_reg[1], buf, SD2405_REG_LEN); - rc = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); if (rc != ARRAY_SIZE(msgs)) goto write_failed; @@ -114,7 +115,6 @@ static int sd2405_i2c_read_time(struct i2c_client *client, struct rtc_time *tm) static int sd2405_i2c_set_write_protect(struct i2c_client *client) { int rc; - rc = i2c_smbus_write_byte_data(client, SD2405_REG_CTRL1, 0); rc += i2c_smbus_write_byte_data(client, SD2405_REG_CTRL2, 0); if (rc < 0) { @@ -128,7 +128,6 @@ static int sd2405_i2c_set_write_protect(struct i2c_client *client) static int sd2405_i2c_clear_write_protect(struct i2c_client *client) { int rc; - rc = i2c_smbus_write_byte_data(client, SD2405_REG_CTRL2, SD2405_REG_CONTROL1_WRITE); rc += @@ -183,11 +182,12 @@ static int sd2405_rtc_set_time(struct device *dev, struct rtc_time *tm) static int sd2405_remove(struct i2c_client *client) { +#if 0 struct rtc_device *rtc = i2c_get_clientdata(client); if (rtc) rtc_device_unregister(rtc); - +#endif return 0; } @@ -199,17 +199,20 @@ static const struct rtc_class_ops sd2405_rtc_ops = { static int sd2405_probe(struct i2c_client *client, const struct i2c_device_id *id) { + int ret = 0; struct rtc_device *rtc; if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) return -ENODEV; dev_info(&client->dev, "chip found, driver version " DRV_VERSION "\n"); - - rtc = rtc_device_register(sd2405_driver.driver.name, - &client->dev, &sd2405_rtc_ops, THIS_MODULE); + rtc = devm_rtc_allocate_device(&client->dev); if (IS_ERR(rtc)) return PTR_ERR(rtc); + rtc->ops = &sd2405_rtc_ops; + ret = rtc_register_device(rtc); + if (ret) + return ret; i2c_set_clientdata(client, rtc); diff --git a/platform/centec-arm64/tsingma-bsp/src/sdhci-ctc5236/sdhci-ctc5236.c b/platform/centec-arm64/tsingma-bsp/src/sdhci-ctc5236/sdhci-ctc5236.c old mode 100644 new mode 100755 index b9981e8b0c54..5641ba6cd59d --- a/platform/centec-arm64/tsingma-bsp/src/sdhci-ctc5236/sdhci-ctc5236.c +++ b/platform/centec-arm64/tsingma-bsp/src/sdhci-ctc5236/sdhci-ctc5236.c @@ -1,17 +1,9 @@ -/* sdhci-ctc5236.c Support for SDHCI on Centec TsingMa SoC's +/* + * sdhci-ctc5236.c Support for SDHCI on Centec TsingMa SoC's * - * Copyright (C) 2004-2017 Centec Networks (suzhou) Co., LTD. + * Author: Wangyb * - * Author: Jay Cao - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright 2005-2020, Centec Networks (Suzhou) Co., Ltd. * */ @@ -27,38 +19,43 @@ #include #include #include +#include +#include #define REG_OFFSET_ADDR 0x500 #define MSHC_CTRL_R 0x8 #define AT_CTRL_R 0x40 #define SW_TUNE_EN 0x10 -#define SD_CLK_EN_MASK 0x00000001 +#define SD_CLK_EN_MASK 0x00000001 #define AT_STAT_R 0x44 #define MAX_TUNING_LOOP 0x80 -#define MIN_TUNING_LOOP 0x0 +#define MIN_TUNING_LOOP 0x0 #define TUNE_CTRL_STEP 1 +#define EMMC_CTRL_R 0x2c -struct regmap *regmap_base; #define SDHCI_REFCLK_150M 150000000 +static struct regmap *regmap_base; +static u32 version; +#define CTC_REV_TM_1_0 0x0 +#define CTC_REV_TM_1_1 0x1 + +#define BOUNDARY_OK(addr, len) \ + ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1))) + static u16 sdhci_ctc5236_readw(struct sdhci_host *host, int reg) { - if (unlikely(reg == SDHCI_HOST_VERSION)) + if (unlikely(reg == SDHCI_HOST_VERSION)) { return SDHCI_SPEC_300; + } return readw(host->ioaddr + reg); } static u32 sdhci_ctc5236_readl(struct sdhci_host *host, int reg) { - u32 ret = readl(host->ioaddr + reg); - - if (reg == SDHCI_CAPABILITIES_1) - ret &= - ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | - SDHCI_SUPPORT_DDR50); - if (reg == SDHCI_CAPABILITIES) - ret &= ~(SDHCI_CAN_64BIT); + u32 ret; + ret = readl(host->ioaddr + reg); return ret; } @@ -112,24 +109,74 @@ void sdhci_ctc5236_reset(struct sdhci_host *host, u8 mask) } +static void ctc5236_select_90degree_phase(struct sdhci_host *host) +{ + u32 val = 0; + + regmap_read(regmap_base, offsetof(struct SysCtl_regs, SysMshCfg), &val); + if (val & SYS_MSH_CFG_W0_MSH_INTF_C_CLK_TX_PHASE_SEL_MASK) { + val &= (~SYS_MSH_CFG_W0_MSH_INTF_C_CLK_TX_PHASE_SEL_MASK); + regmap_write(regmap_base, + offsetof(struct SysCtl_regs, SysMshCfg), val); + printk("select ctc 90 degree phase\n"); + } +} + void ctc_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) { int val = 0; if (clock == SDHCI_REFCLK_150M) { - /* SDHCI reference clock change 150M */ regmap_read(regmap_base, offsetof(struct SysCtl_regs, SysClkPeriCfg), &val); - val = val & (~SYS_CLK_PERI_CFG_W0_CFG_DIV_MSH_REF_CNT_MASK); - val |= - ((0x8 & SYS_CLK_PERI_CFG_W0_CFG_DIV_MSH_REF_CNT_MASK)) << 0; - regmap_write(regmap_base, - offsetof(struct SysCtl_regs, SysClkPeriCfg), val); + if ((val & 0xc) == 0xc) { + val = + val & + (~SYS_CLK_PERI_CFG_W0_CFG_DIV_MSH_REF_CNT_MASK); + val |= + ((0x8 & + SYS_CLK_PERI_CFG_W0_CFG_DIV_MSH_REF_CNT_MASK)) << + 0; + regmap_write(regmap_base, + offsetof(struct SysCtl_regs, + SysClkPeriCfg), val); + printk("SDHCI reference clock change 150M\n"); + } + } + + if (version == CTC_REV_TM_1_1) { + if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) { + ctc5236_select_90degree_phase(host); + } } sdhci_set_clock(host, clock); } +/* + * If DMA addr spans 128MB boundary, we split the DMA transfer into two + * so that each DMA transfer doesn't exceed the boundary. + */ +static void sdhci_ctc5236_adma_write_desc(struct sdhci_host *host, void **desc, + dma_addr_t addr, int len, + unsigned int cmd) +{ + int tmplen, offset; + + if (likely(!len || BOUNDARY_OK(addr, len))) { + sdhci_adma_write_desc(host, desc, addr, len, cmd); + return; + } + + offset = addr & (SZ_128M - 1); + tmplen = SZ_128M - offset; + sdhci_adma_write_desc(host, desc, addr, tmplen, cmd); + + addr += tmplen; + len -= tmplen; + sdhci_adma_write_desc(host, desc, addr, len, cmd); +} + static int sdhci_ctc5236_prepare_tuning(struct sdhci_host *host, int CENTER_PH_CODE) { @@ -180,51 +227,54 @@ static int sdhci_ctc5236_execute_tuning(struct sdhci_host *host, u32 opcode) val &= (~SYS_MSH_CFG_W0_MSH_INTF_RX_DLL_MASTER_BYPASS_MASK); regmap_write(regmap_base, offsetof(struct SysCtl_regs, SysMshCfg), val); + sdhci_ctc5236_prepare_tuning(host, 0); + /* find the mininum delay first which can pass tuning */ min = MIN_TUNING_LOOP; - sdhci_ctc5236_prepare_tuning(host, min); + sdhci_writel(host, min, REG_OFFSET_ADDR + AT_STAT_R); while (min < MAX_TUNING_LOOP) { - dev_dbg(mmc_dev(host->mmc), "#1# AT_STAT_R is %x\n", - sdhci_readl(host, REG_OFFSET_ADDR + AT_STAT_R)); if (!mmc_send_tuning(host->mmc, opcode, NULL)) break; - host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); - min += TUNE_CTRL_STEP; sdhci_writel(host, min, REG_OFFSET_ADDR + AT_STAT_R); } /* find the maxinum delay which can not pass tuning */ max = min + TUNE_CTRL_STEP; - sdhci_ctc5236_prepare_tuning(host, max); + sdhci_writel(host, max, REG_OFFSET_ADDR + AT_STAT_R); while (max < MAX_TUNING_LOOP) { - dev_dbg(mmc_dev(host->mmc), "#2# AT_STAT_R is %x\n", - sdhci_readl(host, REG_OFFSET_ADDR + AT_STAT_R)); if (mmc_send_tuning(host->mmc, opcode, NULL)) { max -= TUNE_CTRL_STEP; break; } - host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); - max += TUNE_CTRL_STEP; sdhci_writel(host, max, REG_OFFSET_ADDR + AT_STAT_R); } /* use average delay to get the best timing */ avg = (min + max) / 2; - sdhci_ctc5236_prepare_tuning(host, avg); + sdhci_writel(host, avg, REG_OFFSET_ADDR + AT_STAT_R); ret = mmc_send_tuning(host->mmc, opcode, NULL); host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); - sdhci_writel(host, avg, REG_OFFSET_ADDR + AT_STAT_R); - dev_info(mmc_dev(host->mmc), "Tuning %s at 0x%x ret %d\n", - ret ? "failed" : "passed", avg, ret); + dev_info(mmc_dev(host->mmc), + "Tuning %s at 0x%x ret %d, min is 0x%x, max is 0x%x\n", + ret ? "failed" : "passed", avg, ret, min, max); return ret; } +static void sdhci_ctc5236_hw_reset(struct sdhci_host *host) +{ + sdhci_writel(host, 0x0, REG_OFFSET_ADDR + EMMC_CTRL_R); + udelay(10); + sdhci_writel(host, 0xc, REG_OFFSET_ADDR + EMMC_CTRL_R); + udelay(300); + dev_info(mmc_dev(host->mmc), "Hardware reset\n"); +} + static const struct sdhci_ops sdhci_ctc5236_ops = { .read_w = sdhci_ctc5236_readw, .read_l = sdhci_ctc5236_readl, @@ -234,12 +284,14 @@ static const struct sdhci_ops sdhci_ctc5236_ops = { .set_uhs_signaling = sdhci_set_uhs_signaling, .get_max_clock = sdhci_pltfm_clk_get_max_clock, .platform_execute_tuning = sdhci_ctc5236_execute_tuning, + .adma_write_desc = sdhci_ctc5236_adma_write_desc, + .hw_reset = sdhci_ctc5236_hw_reset, }; static struct sdhci_pltfm_data sdhci_ctc5236_pdata = { .ops = &sdhci_ctc5236_ops, .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | SDHCI_QUIRK2_BROKEN_HS200, - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_BROKEN_ADMA, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, }; static int sdhci_ctc5236_probe(struct platform_device *pdev) @@ -247,32 +299,61 @@ static int sdhci_ctc5236_probe(struct platform_device *pdev) struct sdhci_host *host; struct sdhci_pltfm_host *pltfm_host; struct clk *clk; - int ret; + int ret, val; + u32 extra; host = sdhci_pltfm_init(pdev, &sdhci_ctc5236_pdata, 0); if (IS_ERR(host)) return PTR_ERR(host); - clk = devm_clk_get(&pdev->dev, "mmc_clk"); - if (IS_ERR(clk)) { - dev_err(&pdev->dev, "Peripheral clk not found\n"); - return PTR_ERR(clk); - } - pltfm_host = sdhci_priv(host); - pltfm_host->clk = clk; - clk_prepare_enable(clk); + /* + * extra adma table cnt for cross 128M boundary handling. + */ + extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M); + if (extra > SDHCI_MAX_SEGS) + extra = SDHCI_MAX_SEGS; + host->adma_table_cnt += extra; regmap_base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "ctc,sysctrl"); if (IS_ERR(regmap_base)) return PTR_ERR(regmap_base); + val = 0x3400027; + regmap_write(regmap_base, offsetof(struct SysCtl_regs, SysMshCfg), val); + + regmap_read(regmap_base, offsetof(struct SysCtl_regs, SysCtlSysRev), + &val); + + version = (val == 0x1) ? CTC_REV_TM_1_1 : CTC_REV_TM_1_0; + mmc_of_parse_voltage(pdev->dev.of_node, &host->ocr_mask); ret = mmc_of_parse(host->mmc); if (ret) goto err_sdhci_add; + clk = devm_clk_get(&pdev->dev, "mmc_clk"); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Peripheral clk not found\n"); + return PTR_ERR(clk); + } + pltfm_host = sdhci_priv(host); + pltfm_host->clk = clk; + clk_prepare_enable(clk); + + if (version == CTC_REV_TM_1_0) { + if (host->mmc->caps & MMC_CAP_1_8V_DDR) { + host->mmc->caps &= ~MMC_CAP_1_8V_DDR; + printk("%s, not support DDR Mode\n", __func__); + } + } + + if (host->mmc->caps2 & MMC_CAP2_HS200_1_8V_SDR) { + host->mmc->caps2 &= ~MMC_CAP2_HS200_1_8V_SDR; + printk("%s, not support Hs200 Mode\n", __func__); + } + ret = sdhci_add_host(host); if (ret) goto err_sdhci_add; @@ -303,5 +384,5 @@ static struct platform_driver sdhci_ctc5236_driver = { module_platform_driver(sdhci_ctc5236_driver); MODULE_DESCRIPTION("SDHCI driver for Centec TsingMa SoCs"); -MODULE_AUTHOR("Jay Cao "); +MODULE_AUTHOR("Wangyb "); MODULE_LICENSE("GPL v2"); diff --git a/platform/centec-arm64/tsingma-bsp/src/sdhci-ctc5236/sdhci-pltfm.h b/platform/centec-arm64/tsingma-bsp/src/sdhci-ctc5236/sdhci-pltfm.h index 1e91fb1c020e..ab508dd6314c 100644 --- a/platform/centec-arm64/tsingma-bsp/src/sdhci-ctc5236/sdhci-pltfm.h +++ b/platform/centec-arm64/tsingma-bsp/src/sdhci-ctc5236/sdhci-pltfm.h @@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright 2010 MontaVista Software, LLC. * * Author: Anton Vorontsov - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef _DRIVERS_MMC_SDHCI_PLTFM_H @@ -28,7 +25,7 @@ struct sdhci_pltfm_host { unsigned int clock; u16 xfer_mode_shadow; - unsigned long private[0] ____cacheline_aligned; + unsigned long private[] ____cacheline_aligned; }; #ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER @@ -86,15 +83,20 @@ static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg) int base = reg & ~0x3; int shift = (reg & 0x3) * 8; - clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift); + clrsetbits_be32(host->ioaddr + base, 0xff << shift, val << shift); } #endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */ -extern void sdhci_get_of_property(struct platform_device *pdev); +void sdhci_get_property(struct platform_device *pdev); + +static inline void sdhci_get_of_property(struct platform_device *pdev) +{ + return sdhci_get_property(pdev); +} extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev, - const struct sdhci_pltfm_data *pdata, - size_t priv_size); + const struct sdhci_pltfm_data *pdata, + size_t priv_size); extern void sdhci_pltfm_free(struct platform_device *pdev); extern int sdhci_pltfm_register(struct platform_device *pdev, @@ -109,8 +111,20 @@ static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host) return host->private; } +extern const struct dev_pm_ops sdhci_pltfm_pmops; +#ifdef CONFIG_PM_SLEEP int sdhci_pltfm_suspend(struct device *dev); int sdhci_pltfm_resume(struct device *dev); -extern const struct dev_pm_ops sdhci_pltfm_pmops; +#else +static inline int sdhci_pltfm_suspend(struct device *dev) +{ + return 0; +} + +static inline int sdhci_pltfm_resume(struct device *dev) +{ + return 0; +} +#endif #endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */ diff --git a/platform/centec-arm64/tsingma-bsp/src/sdhci-ctc5236/sdhci.h b/platform/centec-arm64/tsingma-bsp/src/sdhci-ctc5236/sdhci.h index 0f8c4f3ccafc..5644560aad19 100644 --- a/platform/centec-arm64/tsingma-bsp/src/sdhci-ctc5236/sdhci.h +++ b/platform/centec-arm64/tsingma-bsp/src/sdhci-ctc5236/sdhci.h @@ -1,18 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver * * Header file for Host Controller registers and I/O accessors. * * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or (at - * your option) any later version. */ #ifndef __SDHCI_HW_H #define __SDHCI_HW_H +#include #include #include #include @@ -28,6 +25,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) @@ -41,6 +39,7 @@ #define SDHCI_TRNS_BLK_CNT_EN 0x02 #define SDHCI_TRNS_AUTO_CMD12 0x04 #define SDHCI_TRNS_AUTO_CMD23 0x08 +#define SDHCI_TRNS_AUTO_SEL 0x0C #define SDHCI_TRNS_READ 0x10 #define SDHCI_TRNS_MULTI 0x20 @@ -71,6 +70,10 @@ #define SDHCI_SPACE_AVAILABLE 0x00000400 #define SDHCI_DATA_AVAILABLE 0x00000800 #define SDHCI_CARD_PRESENT 0x00010000 +#define SDHCI_CARD_PRES_SHIFT 16 +#define SDHCI_CD_STABLE 0x00020000 +#define SDHCI_CD_LVL 0x00040000 +#define SDHCI_CD_LVL_SHIFT 18 #define SDHCI_WRITE_PROTECT 0x00080000 #define SDHCI_DATA_LVL_MASK 0x00F00000 #define SDHCI_DATA_LVL_SHIFT 20 @@ -86,7 +89,8 @@ #define SDHCI_CTRL_ADMA1 0x08 #define SDHCI_CTRL_ADMA32 0x10 #define SDHCI_CTRL_ADMA64 0x18 -#define SDHCI_CTRL_8BITBUS 0x20 +#define SDHCI_CTRL_ADMA3 0x18 +#define SDHCI_CTRL_8BITBUS 0x20 #define SDHCI_CTRL_CDTEST_INS 0x40 #define SDHCI_CTRL_CDTEST_EN 0x80 @@ -111,6 +115,7 @@ #define SDHCI_DIV_HI_MASK 0x300 #define SDHCI_PROG_CLOCK_MODE 0x0020 #define SDHCI_CLOCK_CARD_EN 0x0004 +#define SDHCI_CLOCK_PLL_EN 0x0008 #define SDHCI_CLOCK_INT_STABLE 0x0002 #define SDHCI_CLOCK_INT_EN 0x0001 @@ -180,7 +185,7 @@ #define SDHCI_CTRL_UHS_SDR50 0x0002 #define SDHCI_CTRL_UHS_SDR104 0x0003 #define SDHCI_CTRL_UHS_DDR50 0x0004 -#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ +#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ #define SDHCI_CTRL_VDD_180 0x0008 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 @@ -189,15 +194,16 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CMD23_ENABLE 0x0800 +#define SDHCI_CTRL_V4_MODE 0x1000 +#define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 -#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F -#define SDHCI_TIMEOUT_CLK_SHIFT 0 +#define SDHCI_TIMEOUT_CLK_MASK GENMASK(5, 0) #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 -#define SDHCI_CLOCK_BASE_MASK 0x00003F00 -#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 -#define SDHCI_CLOCK_BASE_SHIFT 8 +#define SDHCI_CLOCK_BASE_MASK GENMASK(13, 8) +#define SDHCI_CLOCK_V3_BASE_MASK GENMASK(15, 8) #define SDHCI_MAX_BLOCK_MASK 0x00030000 #define SDHCI_MAX_BLOCK_SHIFT 16 #define SDHCI_CAN_DO_8BIT 0x00040000 @@ -209,33 +215,28 @@ #define SDHCI_CAN_VDD_330 0x01000000 #define SDHCI_CAN_VDD_300 0x02000000 #define SDHCI_CAN_VDD_180 0x04000000 +#define SDHCI_CAN_64BIT_V4 0x08000000 #define SDHCI_CAN_64BIT 0x10000000 +#define SDHCI_CAPABILITIES_1 0x44 #define SDHCI_SUPPORT_SDR50 0x00000001 #define SDHCI_SUPPORT_SDR104 0x00000002 #define SDHCI_SUPPORT_DDR50 0x00000004 #define SDHCI_DRIVER_TYPE_A 0x00000010 #define SDHCI_DRIVER_TYPE_C 0x00000020 #define SDHCI_DRIVER_TYPE_D 0x00000040 -#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 -#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 +#define SDHCI_RETUNING_TIMER_COUNT_MASK GENMASK(11, 8) #define SDHCI_USE_SDR50_TUNING 0x00002000 -#define SDHCI_RETUNING_MODE_MASK 0x0000C000 -#define SDHCI_RETUNING_MODE_SHIFT 14 -#define SDHCI_CLOCK_MUL_MASK 0x00FF0000 -#define SDHCI_CLOCK_MUL_SHIFT 16 -#define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ - -#define SDHCI_CAPABILITIES_1 0x44 +#define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14) +#define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16) +#define SDHCI_CAN_DO_ADMA3 0x08000000 +#define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ #define SDHCI_MAX_CURRENT 0x48 -#define SDHCI_MAX_CURRENT_LIMIT 0xFF -#define SDHCI_MAX_CURRENT_330_MASK 0x0000FF -#define SDHCI_MAX_CURRENT_330_SHIFT 0 -#define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 -#define SDHCI_MAX_CURRENT_300_SHIFT 8 -#define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 -#define SDHCI_MAX_CURRENT_180_SHIFT 16 +#define SDHCI_MAX_CURRENT_LIMIT GENMASK(7, 0) +#define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0) +#define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8) +#define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16) #define SDHCI_MAX_CURRENT_MULTIPLIER 4 /* 4C-4F reserved for more max current */ @@ -252,18 +253,16 @@ /* 60-FB reserved */ +#define SDHCI_PRESET_FOR_HIGH_SPEED 0x64 #define SDHCI_PRESET_FOR_SDR12 0x66 #define SDHCI_PRESET_FOR_SDR25 0x68 #define SDHCI_PRESET_FOR_SDR50 0x6A #define SDHCI_PRESET_FOR_SDR104 0x6C #define SDHCI_PRESET_FOR_DDR50 0x6E -#define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ -#define SDHCI_PRESET_DRV_MASK 0xC000 -#define SDHCI_PRESET_DRV_SHIFT 14 -#define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 -#define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 -#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF -#define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 +#define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ +#define SDHCI_PRESET_DRV_MASK GENMASK(15, 14) +#define SDHCI_PRESET_CLKGEN_SEL BIT(10) +#define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0) #define SDHCI_SLOT_INT_STATUS 0xFC @@ -275,6 +274,9 @@ #define SDHCI_SPEC_100 0 #define SDHCI_SPEC_200 1 #define SDHCI_SPEC_300 2 +#define SDHCI_SPEC_400 3 +#define SDHCI_SPEC_410 4 +#define SDHCI_SPEC_420 5 /* * End of controller registers. @@ -294,10 +296,10 @@ /* ADMA2 32-bit descriptor */ struct sdhci_adma2_32_desc { - __le16 cmd; - __le16 len; - __le32 addr; -} __packed __aligned(4); + __le16 cmd; + __le16 len; + __le32 addr; +} __packed __aligned(4); /* ADMA2 data alignment */ #define SDHCI_ADMA2_ALIGN 4 @@ -310,19 +312,25 @@ struct sdhci_adma2_32_desc { */ #define SDHCI_ADMA2_DESC_ALIGN 8 -/* ADMA2 64-bit DMA descriptor size */ -#define SDHCI_ADMA2_64_DESC_SZ 12 +/* + * ADMA2 64-bit DMA descriptor size + * According to SD Host Controller spec v4.10, there are two kinds of + * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit + * Descriptor, if Host Version 4 Enable is set in the Host Control 2 + * register, 128-bit Descriptor will be selected. + */ +#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) /* * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte * aligned. */ struct sdhci_adma2_64_desc { - __le16 cmd; - __le16 len; - __le32 addr_lo; - __le32 addr_hi; -} __packed __aligned(4); + __le16 cmd; + __le16 len; + __le32 addr_lo; + __le32 addr_hi; +} __packed __aligned(4); #define ADMA2_TRAN_VALID 0x21 #define ADMA2_NOP_END_VALID 0x3 @@ -343,7 +351,7 @@ struct sdhci_adma2_64_desc { * command and response, and the time between response and start of data is * not known, set the command transfer time to 10ms. */ -#define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */ +#define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */ enum sdhci_cookie { COOKIE_UNMAPPED, @@ -391,8 +399,12 @@ struct sdhci_host { #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) /* Controller reports inverted write-protect state */ #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) +/* Controller has unusable command queue engine */ +#define SDHCI_QUIRK_BROKEN_CQE (1<<17) /* Controller does not like fast PIO transfers */ #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) +/* Controller does not have a LED */ +#define SDHCI_QUIRK_NO_LED (1<<19) /* Controller has to be forced to use block size of 2048 bytes */ #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) /* Controller cannot do multi-block transfers */ @@ -455,9 +467,17 @@ struct sdhci_host { * obtainable timeout. */ #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) +/* + * 32-bit block count may not support eMMC where upper bits of CMD23 are used + * for other purposes. Consequently we support 16-bit block count by default. + * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit + * block count. + */ +#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ + phys_addr_t mapbase; /* physical address base */ char *bounce_buffer; /* For packing SDMA reads/writes */ dma_addr_t bounce_addr; unsigned int bounce_buffer_size; @@ -485,7 +505,6 @@ struct sdhci_host { #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ -#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ @@ -506,10 +525,14 @@ struct sdhci_host { bool preset_enabled; /* Preset is enabled */ bool pending_reset; /* Cmd/data reset is pending */ bool irq_wake_enabled; /* IRQ wakeup is enabled */ + bool v4_mode; /* Host Version 4 Enable */ + bool use_external_dma; /* Host selects to use external DMA */ + bool always_defer_done; /* Always defer to complete requests */ struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ struct mmc_command *cmd; /* Current command */ struct mmc_command *data_cmd; /* Current data command */ + struct mmc_command *deferred_cmd; /* Deferred command */ struct mmc_data *data; /* Current data request */ unsigned int data_early:1; /* Data finished before cmd */ @@ -527,87 +550,109 @@ struct sdhci_host { dma_addr_t adma_addr; /* Mapped ADMA descr. table */ dma_addr_t align_addr; /* Mapped bounce buffer */ - unsigned int desc_sz; /* ADMA descriptor size */ + unsigned int desc_sz; /* ADMA current descriptor size */ + unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */ - struct tasklet_struct finish_tasklet; /* Tasklet structures */ + struct workqueue_struct *complete_wq; /* Request completion wq */ + struct work_struct complete_work; /* Request completion work */ struct timer_list timer; /* Timer for timeouts */ struct timer_list data_timer; /* Timer for data timeouts */ +#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA) + struct dma_chan *rx_chan; + struct dma_chan *tx_chan; +#endif + u32 caps; /* CAPABILITY_0 */ u32 caps1; /* CAPABILITY_1 */ bool read_caps; /* Capability flags have been read */ - unsigned int ocr_avail_sdio; /* OCR bit masks */ - unsigned int ocr_avail_sd; - unsigned int ocr_avail_mmc; + bool sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */ + unsigned int ocr_avail_sdio; /* OCR bit masks */ + unsigned int ocr_avail_sd; + unsigned int ocr_avail_mmc; u32 ocr_mask; /* available voltages */ - unsigned timing; /* Current timing */ + unsigned timing; /* Current timing */ - u32 thread_isr; + u32 thread_isr; /* cached registers */ - u32 ier; + u32 ier; - bool cqe_on; /* CQE is operating */ - u32 cqe_ier; /* CQE interrupt mask */ - u32 cqe_err_ier; /* CQE error interrupt mask */ + bool cqe_on; /* CQE is operating */ + u32 cqe_ier; /* CQE interrupt mask */ + u32 cqe_err_ier; /* CQE error interrupt mask */ - wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ - unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ + wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ + unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ - unsigned int tuning_count; /* Timer count for re-tuning */ - unsigned int tuning_mode; /* Re-tuning mode supported by host */ + unsigned int tuning_count; /* Timer count for re-tuning */ + unsigned int tuning_mode; /* Re-tuning mode supported by host */ + unsigned int tuning_err; /* Error code for re-tuning */ #define SDHCI_TUNING_MODE_1 0 #define SDHCI_TUNING_MODE_2 1 #define SDHCI_TUNING_MODE_3 2 /* Delay (ms) between tuning commands */ - int tuning_delay; + int tuning_delay; + int tuning_loop_count; /* Host SDMA buffer boundary. */ - u32 sdma_boundary; + u32 sdma_boundary; - u64 data_timeout; + /* Host ADMA table count */ + u32 adma_table_cnt; - unsigned long private[0] ____cacheline_aligned; + u64 data_timeout; + + unsigned long private[] ____cacheline_aligned; }; struct sdhci_ops { #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS - u32 (*read_l)(struct sdhci_host *host, int reg); - u16 (*read_w)(struct sdhci_host *host, int reg); - u8 (*read_b)(struct sdhci_host *host, int reg); - void (*write_l)(struct sdhci_host *host, u32 val, int reg); - void (*write_w)(struct sdhci_host *host, u16 val, int reg); - void (*write_b)(struct sdhci_host *host, u8 val, int reg); + u32(*read_l) (struct sdhci_host * host, int reg); + u16(*read_w) (struct sdhci_host * host, int reg); + u8(*read_b) (struct sdhci_host * host, int reg); + void (*write_l) (struct sdhci_host * host, u32 val, int reg); + void (*write_w) (struct sdhci_host * host, u16 val, int reg); + void (*write_b) (struct sdhci_host * host, u8 val, int reg); #endif - void (*set_clock)(struct sdhci_host *host, unsigned int clock); - void (*set_power)(struct sdhci_host *host, unsigned char mode, - unsigned short vdd); + void (*set_clock) (struct sdhci_host * host, unsigned int clock); + void (*set_power) (struct sdhci_host * host, unsigned char mode, + unsigned short vdd); - u32 (*irq)(struct sdhci_host *host, u32 intmask); + u32(*irq) (struct sdhci_host * host, u32 intmask); - int (*enable_dma)(struct sdhci_host *host); - unsigned int (*get_max_clock)(struct sdhci_host *host); - unsigned int (*get_min_clock)(struct sdhci_host *host); + int (*set_dma_mask) (struct sdhci_host * host); + int (*enable_dma) (struct sdhci_host * host); + unsigned int (*get_max_clock) (struct sdhci_host * host); + unsigned int (*get_min_clock) (struct sdhci_host * host); /* get_timeout_clock should return clk rate in unit of Hz */ - unsigned int (*get_timeout_clock)(struct sdhci_host *host); - unsigned int (*get_max_timeout_count)(struct sdhci_host *host); - void (*set_timeout)(struct sdhci_host *host, - struct mmc_command *cmd); - void (*set_bus_width)(struct sdhci_host *host, int width); - void (*platform_send_init_74_clocks)(struct sdhci_host *host, - u8 power_mode); - unsigned int (*get_ro)(struct sdhci_host *host); - void (*reset)(struct sdhci_host *host, u8 mask); - int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); - void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); - void (*hw_reset)(struct sdhci_host *host); - void (*adma_workaround)(struct sdhci_host *host, u32 intmask); - void (*card_event)(struct sdhci_host *host); - void (*voltage_switch)(struct sdhci_host *host); + unsigned int (*get_timeout_clock) (struct sdhci_host * host); + unsigned int (*get_max_timeout_count) (struct sdhci_host * host); + void (*set_timeout) (struct sdhci_host * host, + struct mmc_command * cmd); + void (*set_bus_width) (struct sdhci_host * host, int width); + void (*platform_send_init_74_clocks) (struct sdhci_host * host, + u8 power_mode); + unsigned int (*get_ro) (struct sdhci_host * host); + void (*reset) (struct sdhci_host * host, u8 mask); + int (*platform_execute_tuning) (struct sdhci_host * host, u32 opcode); + void (*set_uhs_signaling) (struct sdhci_host * host, unsigned int uhs); + void (*hw_reset) (struct sdhci_host * host); + void (*adma_workaround) (struct sdhci_host * host, u32 intmask); + void (*card_event) (struct sdhci_host * host); + void (*voltage_switch) (struct sdhci_host * host); + void (*adma_write_desc) (struct sdhci_host * host, void **desc, + dma_addr_t addr, int len, unsigned int cmd); + void (*copy_to_bounce_buffer) (struct sdhci_host * host, + struct mmc_data * data, + unsigned int length); + void (*request_done) (struct sdhci_host * host, + struct mmc_request * mrq); + void (*dump_vendor_regs) (struct sdhci_host * host); }; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS @@ -703,33 +748,31 @@ static inline void *sdhci_priv(struct sdhci_host *host) } void sdhci_card_detect(struct sdhci_host *host); -void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, - u32 *caps1); +void __sdhci_read_caps(struct sdhci_host *host, const u16 * ver, + const u32 * caps, const u32 * caps1); int sdhci_setup_host(struct sdhci_host *host); void sdhci_cleanup_host(struct sdhci_host *host); int __sdhci_add_host(struct sdhci_host *host); int sdhci_add_host(struct sdhci_host *host); void sdhci_remove_host(struct sdhci_host *host, int dead); -void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); static inline void sdhci_read_caps(struct sdhci_host *host) { __sdhci_read_caps(host, NULL, NULL, NULL); } -static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) -{ - return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); -} - u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, unsigned int *actual_clock); void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); void sdhci_enable_clk(struct sdhci_host *host, u16 clk); void sdhci_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd); +void sdhci_set_power_and_bus_voltage(struct sdhci_host *host, + unsigned char mode, unsigned short vdd); void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, unsigned short vdd); +void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq); +int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq); void sdhci_set_bus_width(struct sdhci_host *host, int width); void sdhci_reset(struct sdhci_host *host, u8 mask); void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); @@ -738,12 +781,14 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios); void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); +void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, + dma_addr_t addr, int len, unsigned int cmd); #ifdef CONFIG_PM int sdhci_suspend_host(struct sdhci_host *host); int sdhci_resume_host(struct sdhci_host *host); int sdhci_runtime_suspend_host(struct sdhci_host *host); -int sdhci_runtime_resume_host(struct sdhci_host *host); +int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset); #endif void sdhci_cqe_enable(struct mmc_host *mmc); @@ -752,10 +797,15 @@ bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, int *data_error); void sdhci_dumpregs(struct sdhci_host *host); +void sdhci_enable_v4_mode(struct sdhci_host *host); void sdhci_start_tuning(struct sdhci_host *host); void sdhci_end_tuning(struct sdhci_host *host); void sdhci_reset_tuning(struct sdhci_host *host); void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); +void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode); +void sdhci_switch_external_dma(struct sdhci_host *host, bool en); +void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable); +void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); #endif /* __SDHCI_HW_H */ diff --git a/platform/centec-arm64/tsingma-bsp/src/spi-ctc-qspi/spi-ctc-qspi.c b/platform/centec-arm64/tsingma-bsp/src/spi-ctc-qspi/spi-ctc-qspi.c index 936459bd3e73..fe3b5b736503 100644 --- a/platform/centec-arm64/tsingma-bsp/src/spi-ctc-qspi/spi-ctc-qspi.c +++ b/platform/centec-arm64/tsingma-bsp/src/spi-ctc-qspi/spi-ctc-qspi.c @@ -111,7 +111,7 @@ enum type_mode { TYPE_MAX }; -static int ctc_reg_read(struct ctc_qspi *ctc_qspi, u32 reg, u32 *value) +static int ctc_reg_read(struct ctc_qspi *ctc_qspi, u32 reg, u32 * value) { *value = readl(ctc_qspi->regs + reg); return *value; @@ -169,12 +169,12 @@ static noinline int ctc_write_tx_buf(struct ctc_qspi *ctc_qspi, u8 offset, return 0; } -static noinline int check_buf_ok(u8 *buf, int i) +static noinline int check_buf_ok(u8 * buf, int i) { return buf && (buf + i); } -static noinline int fill_tx_entry(struct ctc_qspi *ctc_qspi, u8 *buf, int i, +static noinline int fill_tx_entry(struct ctc_qspi *ctc_qspi, u8 * buf, int i, u8 off) { ctc_qspi->tx_entry |= buf[i] << (off % 4) * 8; @@ -182,12 +182,12 @@ static noinline int fill_tx_entry(struct ctc_qspi *ctc_qspi, u8 *buf, int i, return 0; } -static noinline void update_offset(u8 *offset, u8 off) +static noinline void update_offset(u8 * offset, u8 off) { *offset = off; } -static void ctc_fill_tx_buf(struct ctc_qspi *ctc_qspi, u8 *offset, u8 *buf, +static void ctc_fill_tx_buf(struct ctc_qspi *ctc_qspi, u8 * offset, u8 * buf, u32 len) { @@ -195,8 +195,9 @@ static void ctc_fill_tx_buf(struct ctc_qspi *ctc_qspi, u8 *offset, u8 *buf, u8 off = *offset; while (i < len) { - if (check_buf_ok(buf, i)) + if (check_buf_ok(buf, i)) { fill_tx_entry(ctc_qspi, buf, i, off); + } if (off % 4 == 0) { ctc_write_tx_buf(ctc_qspi, off, ctc_qspi->tx_entry); @@ -210,7 +211,7 @@ static void ctc_fill_tx_buf(struct ctc_qspi *ctc_qspi, u8 *offset, u8 *buf, } -static void ctc_fill_pp_buf(struct ctc_qspi *ctc_qspi, u32 *offset, u8 *buf, +static void ctc_fill_pp_buf(struct ctc_qspi *ctc_qspi, u32 * offset, u8 * buf, u32 len) { u32 i = 0, j = 0; @@ -218,8 +219,9 @@ static void ctc_fill_pp_buf(struct ctc_qspi *ctc_qspi, u32 *offset, u8 *buf, while (i < len) { for (j = 0; j < 4; j++) { - if (buf && (buf + i)) + if (buf && (buf + i)) { ctc_qspi->tx_entry |= buf[i + j] << (j % 4) * 8; + } } ctc_write_tx_buf(ctc_qspi, off, ctc_qspi->tx_entry); ctc_qspi->tx_entry = 0; @@ -303,15 +305,17 @@ static void ctc_qspi_pio_ctrl(struct ctc_qspi *ctc_qspi) { u32 ctrl = 0; - ctrl = CTRL_IDLE_CYCLE(ctc_qspi->idlecycle) | - CTRL_PRE_CYCLE(ctc_qspi->precycle) | - CTRL_POST_CYCLE(ctc_qspi->postcycle) | - CTRL_SCLK_DEFAULT(ctc_qspi->sclkdef) | - CTRL_SOUT3_DEFAULT(ctc_qspi->sout3def) | - CTRL_SOUT2_DEFAULT(ctc_qspi->sout2def) | - CTRL_SOUT1_DEFAULT(ctc_qspi->sout1def) | - CTRL_CS(ctc_qspi->cs_select) | - CTRL_DIV_SCLK(ctc_qspi->clkdiv); + ctrl = + CTRL_IDLE_CYCLE(ctc_qspi->idlecycle) | CTRL_PRE_CYCLE(ctc_qspi-> + precycle) + | CTRL_POST_CYCLE(ctc_qspi-> + postcycle) | CTRL_SCLK_DEFAULT(ctc_qspi->sclkdef) + | CTRL_SOUT3_DEFAULT(ctc_qspi-> + sout3def) | CTRL_SOUT2_DEFAULT(ctc_qspi-> + sout2def) + | CTRL_SOUT1_DEFAULT(ctc_qspi->sout1def) | CTRL_CS(ctc_qspi-> + cs_select) + | CTRL_DIV_SCLK(ctc_qspi->clkdiv); ctc_reg_write_mask(ctc_qspi, PIO_CTRL(ctc_qspi->qspi_mode), ctrl, 0xffffffff); @@ -321,15 +325,17 @@ static void ctc_qspi_pp_ctrl(struct ctc_qspi *ctc_qspi) { u32 ctrl = 0; - ctrl = CTRL_IDLE_CYCLE(ctc_qspi->idlecycle) | - CTRL_PRE_CYCLE(ctc_qspi->precycle) | - CTRL_POST_CYCLE(ctc_qspi->postcycle) | - CTRL_SCLK_DEFAULT(ctc_qspi->sclkdef) | - CTRL_SOUT3_DEFAULT(ctc_qspi->sout3def) | - CTRL_SOUT2_DEFAULT(ctc_qspi->sout2def) | - CTRL_SOUT1_DEFAULT(ctc_qspi->sout1def) | - CTRL_CS(ctc_qspi->cs_select) | - CTRL_DIV_SCLK(ctc_qspi->clkdiv); + ctrl = + CTRL_IDLE_CYCLE(ctc_qspi->idlecycle) | CTRL_PRE_CYCLE(ctc_qspi-> + precycle) + | CTRL_POST_CYCLE(ctc_qspi-> + postcycle) | CTRL_SCLK_DEFAULT(ctc_qspi->sclkdef) + | CTRL_SOUT3_DEFAULT(ctc_qspi-> + sout3def) | CTRL_SOUT2_DEFAULT(ctc_qspi-> + sout2def) + | CTRL_SOUT1_DEFAULT(ctc_qspi->sout1def) | CTRL_CS(ctc_qspi-> + cs_select) + | CTRL_DIV_SCLK(ctc_qspi->clkdiv); ctc_reg_write_mask(ctc_qspi, PP_CTRL, ctrl, 0xffffffff); } @@ -343,18 +349,17 @@ static u32 ctc_pp_conf(u8 lanes, u32 len) return (lanes << 16) | (cycle); } -static int ctc_read_rx_buf(struct ctc_qspi *ctc_qspi, u8 offset, u8 *value) +static int ctc_read_rx_buf(struct ctc_qspi *ctc_qspi, u8 offset, u8 * value) { *value = readb(ctc_qspi->regs + CTC_QSPI_RX_BUFF + offset); return 0; } -static void ctc_extra_rx_buf(struct ctc_qspi *ctc_qspi, u8 offset, u8 *buf, +static void ctc_extra_rx_buf(struct ctc_qspi *ctc_qspi, u8 offset, u8 * buf, u8 len) { int i = 0; - while (i < len) { ctc_read_rx_buf(ctc_qspi, offset, &buf[i++]); offset--; @@ -523,11 +528,13 @@ int ctc_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) { //max data transfer size = tx buffer size - (cmd - addr -dummy ) if (op->data.dir == SPI_MEM_DATA_IN) { - if (op->data.nbytes > CTC_QSPI_RX_BUFFER_SIZE - 6) + if (op->data.nbytes > CTC_QSPI_RX_BUFFER_SIZE - 6) { op->data.nbytes = CTC_QSPI_RX_BUFFER_SIZE - 6; + } } else { - if (op->data.nbytes > CTC_QSPI_TX_BUFFER_SIZE) + if (op->data.nbytes > CTC_QSPI_TX_BUFFER_SIZE) { op->data.nbytes = CTC_QSPI_TX_BUFFER_SIZE; + } } return 0; @@ -558,7 +565,7 @@ static int ctc_qspi_probe(struct platform_device *pdev) return -ENOMEM; master->mode_bits = - SPI_MODE_3 | SPI_MODE_1 | SPI_TX_DUAL | SPI_RX_DUAL | SPI_TX_QUAD | + SPI_MODE_3 | SPI_MODE_0 | SPI_TX_DUAL | SPI_RX_DUAL | SPI_TX_QUAD | SPI_RX_QUAD; master->setup = ctc_qspi_setup; master->transfer_one_message = ctc_qspi_start_transfer_one; diff --git a/platform/centec/centec-dal/dal_kernel.c b/platform/centec/centec-dal/dal_kernel.c index 1651e803fabc..b70361825f3b 100644 --- a/platform/centec/centec-dal/dal_kernel.c +++ b/platform/centec/centec-dal/dal_kernel.c @@ -1176,7 +1176,12 @@ dal_alloc_dma_pool(int lchip, int size) if (use_high_memory) { dma_phy_base[lchip] = virt_to_bus(high_memory); - dma_virt_base[lchip] = ioremap_nocache(dma_phy_base[lchip], size); + /* + * ioremap has provided non-cached semantics by default + * since the Linux 2.6 days, so remove the additional + * ioremap_nocache interface. + */ + dma_virt_base[lchip] = ioremap(dma_phy_base[lchip], size); } else { @@ -1205,7 +1210,12 @@ dal_alloc_dma_pool(int lchip, int size) /* Get DMA memory from kernel */ dma_virt_base[lchip] = _dal_pgalloc(size); dma_phy_base[lchip] = virt_to_bus(dma_virt_base[lchip]); - //dma_virt_base [lchip]= ioremap_nocache(dma_phy_base[lchip], size); + /* + * ioremap has provided non-cached semantics by default + * since the Linux 2.6 days, so remove the additional + * ioremap_nocache interface. + */ + //dma_virt_base [lchip]= ioremap(dma_phy_base[lchip], size); #endif } } @@ -1943,7 +1953,12 @@ int linux_dal_pcie_probe(struct pci_dev* pdev, const struct pci_device_id* id) } dev->phys_address = pci_resource_start(pdev, bar); - dev->logic_address = (uintptr)ioremap_nocache(dev->phys_address, + /* + * ioremap has provided non-cached semantics by default + * since the Linux 2.6 days, so remove the additional + * ioremap_nocache interface. + */ + dev->logic_address = (uintptr)ioremap(dev->phys_address, pci_resource_len(dev->pci_dev, bar)); /*0: little endian 1: big endian*/ diff --git a/platform/centec/sonic-platform-modules-e582/48x2q4z/modules/Makefile b/platform/centec/sonic-platform-modules-e582/48x2q4z/modules/Makefile index 645ca1c2e9e1..a7839bc06016 100644 --- a/platform/centec/sonic-platform-modules-e582/48x2q4z/modules/Makefile +++ b/platform/centec/sonic-platform-modules-e582/48x2q4z/modules/Makefile @@ -1 +1,3 @@ -obj-m := centec_e582_48x2q4z_platform.o centec_at24c64.o +KBUILD_EXTRA_SYMBOLS = /sonic/platform/centec-arm64/sonic-platform-modules-e530/pca954x/Module.symvers + +obj-m := centec_e582_48x2q4z_platform.o diff --git a/platform/centec/sonic-platform-modules-e582/48x2q4z/modules/centec_at24c64.c b/platform/centec/sonic-platform-modules-e582/48x2q4z/modules/centec_at24c64.c deleted file mode 100644 index e1835df88625..000000000000 --- a/platform/centec/sonic-platform-modules-e582/48x2q4z/modules/centec_at24c64.c +++ /dev/null @@ -1,602 +0,0 @@ -/* - * at24.c - handle most I2C EEPROMs - * - * Copyright (C) 2005-2007 David Brownell - * Copyright (C) 2008 Wolfram Sang, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * I2C EEPROMs from most vendors are inexpensive and mostly interchangeable. - * Differences between different vendor product lines (like Atmel AT24C or - * MicroChip 24LC, etc) won't much matter for typical read/write access. - * There are also I2C RAM chips, likewise interchangeable. One example - * would be the PCF8570, which acts like a 24c02 EEPROM (256 bytes). - * - * However, misconfiguration can lose data. "Set 16-bit memory address" - * to a part with 8-bit addressing will overwrite data. Writing with too - * big a page size also loses data. And it's not safe to assume that the - * conventional addresses 0x50..0x57 only hold eeproms; a PCF8563 RTC - * uses 0x51, for just one example. - * - * Accordingly, explicit board-specific configuration data should be used - * in almost all cases. (One partial exception is an SMBus used to access - * "SPD" data for DRAM sticks. Those only use 24c02 EEPROMs.) - * - * So this driver uses "new style" I2C driver binding, expecting to be - * told what devices exist. That may be in arch/X/mach-Y/board-Z.c or - * similar kernel-resident tables; or, configuration data coming from - * a bootloader. - * - * Other than binding model, current differences from "eeprom" driver are - * that this one handles write access and isn't restricted to 24c02 devices. - * It also handles larger devices (32 kbit and up) with two-byte addresses, - * which won't work on pure SMBus systems. - */ - -struct at24_data { - struct at24_platform_data chip; - int use_smbus; - - /* - * Lock protects against activities from other Linux tasks, - * but not from changes by other I2C masters. - */ - struct mutex lock; - struct bin_attribute bin; - - u8 *writebuf; - unsigned write_max; - unsigned num_addresses; - - /* - * Some chips tie up multiple I2C addresses; dummy devices reserve - * them for us, and we'll use them with SMBus calls. - */ - struct i2c_client *client[]; -}; - -/* - * This parameter is to help this driver avoid blocking other drivers out - * of I2C for potentially troublesome amounts of time. With a 100 kHz I2C - * clock, one 256 byte read takes about 1/43 second which is excessive; - * but the 1/170 second it takes at 400 kHz may be quite reasonable; and - * at 1 MHz (Fm+) a 1/430 second delay could easily be invisible. - * - * This value is forced to be a power of two so that writes align on pages. - */ -static unsigned io_limit = 128; -module_param(io_limit, uint, 0); -MODULE_PARM_DESC(io_limit, "Maximum bytes per I/O (default 128)"); - -/* - * Specs often allow 5 msec for a page write, sometimes 20 msec; - * it's important to recover from write timeouts. - */ -static unsigned write_timeout = 25; -module_param(write_timeout, uint, 0); -MODULE_PARM_DESC(write_timeout, "Time (in ms) to try writes (default 25)"); - -#define AT24_SIZE_BYTELEN 5 -#define AT24_SIZE_FLAGS 8 - -#define AT24_BITMASK(x) (BIT(x) - 1) - -/* create non-zero magic value for given eeprom parameters */ -#define AT24_DEVICE_MAGIC(_len, _flags) \ - ((1 << AT24_SIZE_FLAGS | (_flags)) \ - << AT24_SIZE_BYTELEN | ilog2(_len)) - -static const struct i2c_device_id at24_ctc_ids[] = { - { "24c64-ctc", AT24_DEVICE_MAGIC(65536 / 8, AT24_FLAG_ADDR16 | AT24_FLAG_READONLY | AT24_FLAG_IRUGO) }, - { /* END OF LIST */ } -}; -MODULE_DEVICE_TABLE(i2c, at24_ctc_ids); - -/*-------------------------------------------------------------------------*/ - -/* - * This routine supports chips which consume multiple I2C addresses. It - * computes the addressing information to be used for a given r/w request. - * Assumes that sanity checks for offset happened at sysfs-layer. - */ -static struct i2c_client *at24_translate_offset(struct at24_data *at24, - unsigned *offset) -{ - unsigned i = 0; - - if (at24->chip.flags & AT24_FLAG_ADDR16) { - i = *offset >> 16; - *offset &= 0xffff; - } else { - i = *offset >> 8; - *offset &= 0xff; - } - - return at24->client[i]; -} - -static ssize_t at24_eeprom_read(struct at24_data *at24, char *buf, - unsigned offset, size_t count) -{ - struct i2c_msg msg[2]; - struct i2c_client *client; - unsigned long timeout, read_time; - int status; - - memset(msg, 0, sizeof(msg)); - - /* - * REVISIT some multi-address chips don't rollover page reads to - * the next slave address, so we may need to truncate the count. - * Those chips might need another quirk flag. - * - * If the real hardware used four adjacent 24c02 chips and that - * were misconfigured as one 24c08, that would be a similar effect: - * one "eeprom" file not four, but larger reads would fail when - * they crossed certain pages. - */ - - /* - * Slave address and byte offset derive from the offset. Always - * set the byte address; on a multi-master board, another master - * may have changed the chip's "current" address pointer. - */ - client = at24_translate_offset(at24, &offset); - - if (count > io_limit) - count = io_limit; - - count = 1; - - /* - * Reads fail if the previous write didn't complete yet. We may - * loop a few times until this one succeeds, waiting at least - * long enough for one entire page write to work. - */ - timeout = jiffies + msecs_to_jiffies(write_timeout); - do { - read_time = jiffies; - - status = i2c_smbus_write_byte_data(client, (offset >> 8) & 0x0ff, offset & 0x0ff ); - status = i2c_smbus_read_byte(client); - if (status >= 0) { - buf[0] = status; - status = count; - } - - dev_dbg(&client->dev, "read %zu@%d --> %d (%ld)\n", count, offset, status, jiffies); - - if (status == count) - return count; - - /* REVISIT: at HZ=100, this is sloooow */ - msleep(1); - } while (time_before(read_time, timeout)); - - return -ETIMEDOUT; -} - -static ssize_t at24_read(struct at24_data *at24, - char *buf, loff_t off, size_t count) -{ - ssize_t retval = 0; - - if (unlikely(!count)) - return count; - - memset(buf, 0, count); - - /* - * Read data from chip, protecting against concurrent updates - * from this host, but not from other I2C masters. - */ - mutex_lock(&at24->lock); - - while (count) { - ssize_t status; - - status = at24_eeprom_read(at24, buf, off, count); - if (status <= 0) { - if (retval == 0) - retval = status; - break; - } - buf += status; - off += status; - count -= status; - retval += status; - } - - mutex_unlock(&at24->lock); - - return retval; -} - -static ssize_t at24_bin_read(struct file *filp, struct kobject *kobj, - struct bin_attribute *attr, - char *buf, loff_t off, size_t count) -{ - struct at24_data *at24; - - at24 = dev_get_drvdata(container_of(kobj, struct device, kobj)); - return at24_read(at24, buf, off, count); -} - - -/* - * Note that if the hardware write-protect pin is pulled high, the whole - * chip is normally write protected. But there are plenty of product - * variants here, including OTP fuses and partial chip protect. - * - * We only use page mode writes; the alternative is sloooow. This routine - * writes at most one page. - */ -static ssize_t at24_eeprom_write(struct at24_data *at24, const char *buf, - unsigned offset, size_t count) -{ - struct i2c_client *client; - ssize_t status; - unsigned long timeout, write_time; - unsigned next_page; - - /* Get corresponding I2C address and adjust offset */ - client = at24_translate_offset(at24, &offset); - - /* write_max is at most a page */ - if (count > at24->write_max) - count = at24->write_max; - - /* Never roll over backwards, to the start of this page */ - next_page = roundup(offset + 1, at24->chip.page_size); - if (offset + count > next_page) - count = next_page - offset; - - /* - * Writes fail if the previous one didn't complete yet. We may - * loop a few times until this one succeeds, waiting at least - * long enough for one entire page write to work. - */ - timeout = jiffies + msecs_to_jiffies(write_timeout); - do { - write_time = jiffies; - - status = i2c_smbus_write_word_data(client, (offset >> 8) & 0x0ff, (offset & 0xFF) | buf[0]); - if (status == 0) - status = count; - - dev_dbg(&client->dev, "write %zu@%d --> %zd (%ld)\n", count, offset, status, jiffies); - - if (status == count) - return count; - - /* REVISIT: at HZ=100, this is sloooow */ - msleep(1); - } while (time_before(write_time, timeout)); - - return -ETIMEDOUT; -} - -static ssize_t at24_write(struct at24_data *at24, const char *buf, loff_t off, - size_t count) -{ - ssize_t retval = 0; - - if (unlikely(!count)) - return count; - - /* - * Write data to chip, protecting against concurrent updates - * from this host, but not from other I2C masters. - */ - mutex_lock(&at24->lock); - - while (count) { - ssize_t status; - - status = at24_eeprom_write(at24, buf, off, 1); /* only one-byte to write; TODO page wirte */ - if (status <= 0) { - if (retval == 0) - retval = status; - break; - } - buf += status; - off += status; - count -= status; - retval += status; - } - - mutex_unlock(&at24->lock); - - return retval; -} - -static ssize_t at24_bin_write(struct file *filp, struct kobject *kobj, - struct bin_attribute *attr, - char *buf, loff_t off, size_t count) -{ - struct at24_data *at24; - - if (unlikely(off >= attr->size)) - return -EFBIG; - - at24 = dev_get_drvdata(container_of(kobj, struct device, kobj)); - return at24_write(at24, buf, off, count); -} - -/*-------------------------------------------------------------------------*/ - -#ifdef CONFIG_OF -static void at24_get_ofdata(struct i2c_client *client, - struct at24_platform_data *chip) -{ - const __be32 *val; - struct device_node *node = client->dev.of_node; - - if (node) { - if (of_get_property(node, "read-only", NULL)) - chip->flags |= AT24_FLAG_READONLY; - val = of_get_property(node, "pagesize", NULL); - if (val) - chip->page_size = be32_to_cpup(val); - } -} -#else -static void at24_get_ofdata(struct i2c_client *client, - struct at24_platform_data *chip) -{ } -#endif /* CONFIG_OF */ - -static int at24_probe(struct i2c_client *client, const struct i2c_device_id *id) -{ - struct at24_platform_data chip; - bool writable; - int use_smbus = 0; - struct at24_data *at24; - int err; - unsigned i, num_addresses; - kernel_ulong_t magic; - - if (client->dev.platform_data) { - chip = *(struct at24_platform_data *)client->dev.platform_data; - } else { - if (!id->driver_data) - return -ENODEV; - - magic = id->driver_data; - chip.byte_len = BIT(magic & AT24_BITMASK(AT24_SIZE_BYTELEN)); - magic >>= AT24_SIZE_BYTELEN; - chip.flags = magic & AT24_BITMASK(AT24_SIZE_FLAGS); - - /* - * This is slow, but we can't know all eeproms, so we better - * play safe. Specifying custom eeprom-types via platform_data - * is recommended anyhow. - */ - chip.page_size = 1; - - /* update chipdata if OF is present */ - at24_get_ofdata(client, &chip); - - chip.setup = NULL; - chip.context = NULL; - } - - if (!is_power_of_2(chip.byte_len)) - dev_warn(&client->dev, - "byte_len looks suspicious (no power of 2)!\n"); - if (!chip.page_size) { - dev_err(&client->dev, "page_size must not be 0!\n"); - return -EINVAL; - } - if (!is_power_of_2(chip.page_size)) - dev_warn(&client->dev, - "page_size looks suspicious (no power of 2)!\n"); - - /* Use I2C operations unless we're stuck with SMBus extensions. */ - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { - if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { - use_smbus = I2C_SMBUS_I2C_BLOCK_DATA; - } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_WORD_DATA)) { - use_smbus = I2C_SMBUS_WORD_DATA; - } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_BYTE_DATA)) { - use_smbus = I2C_SMBUS_BYTE_DATA; - } else { - return -EPFNOSUPPORT; - } - use_smbus = I2C_SMBUS_BYTE_DATA; - } - - if (chip.flags & AT24_FLAG_TAKE8ADDR) - num_addresses = 8; - else - num_addresses = DIV_ROUND_UP(chip.byte_len, (chip.flags & AT24_FLAG_ADDR16) ? 65536 : 256); - - at24 = devm_kzalloc(&client->dev, sizeof(struct at24_data) + num_addresses * sizeof(struct i2c_client *), GFP_KERNEL); - if (!at24) - return -ENOMEM; - - mutex_init(&at24->lock); - at24->use_smbus = use_smbus; - at24->chip = chip; - at24->num_addresses = num_addresses; - - printk(KERN_ALERT "at24_probe chip.byte_len = 0x%x\n", chip.byte_len); - printk(KERN_ALERT "at24_probe chip.flags = 0x%x\n", chip.flags); - printk(KERN_ALERT "at24_probe chip.magic = 0x%lx\n", id->driver_data); - printk(KERN_ALERT "at24_probe use_smbus = %d\n", at24->use_smbus); - printk(KERN_ALERT "at24_probe num_addresses = %d\n", at24->num_addresses); - - /* - * Export the EEPROM bytes through sysfs, since that's convenient. - * By default, only root should see the data (maybe passwords etc) - */ - sysfs_bin_attr_init(&at24->bin); - at24->bin.attr.name = "eeprom"; - at24->bin.attr.mode = chip.flags & AT24_FLAG_IRUGO ? S_IRUGO : S_IRUSR; - at24->bin.read = at24_bin_read; - at24->bin.size = chip.byte_len; - - writable = !(chip.flags & AT24_FLAG_READONLY); - if (writable) { - if (!use_smbus || i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) { - unsigned write_max = chip.page_size; - - at24->bin.write = at24_bin_write; - at24->bin.attr.mode |= S_IWUSR; - - if (write_max > io_limit) - write_max = io_limit; - if (use_smbus && write_max > I2C_SMBUS_BLOCK_MAX) - write_max = I2C_SMBUS_BLOCK_MAX; - at24->write_max = write_max; - - /* buffer (data + address at the beginning) */ - at24->writebuf = devm_kzalloc(&client->dev, write_max + 2, GFP_KERNEL); - if (!at24->writebuf) - return -ENOMEM; - } else { - dev_warn(&client->dev, "cannot write due to controller restrictions."); - } - } - - at24->client[0] = client; - - /* use dummy devices for multiple-address chips */ - for (i = 1; i < num_addresses; i++) { - at24->client[i] = i2c_new_dummy(client->adapter, client->addr + i); - if (!at24->client[i]) { - dev_err(&client->dev, "address 0x%02x unavailable\n", client->addr + i); - err = -EADDRINUSE; - goto err_clients; - } - } - - err = sysfs_create_bin_file(&client->dev.kobj, &at24->bin); - if (err) - goto err_clients; - - i2c_set_clientdata(client, at24); - - printk(KERN_ALERT "at24_probe %s done\n", client->name); - - return 0; - -err_clients: - for (i = 1; i < num_addresses; i++) - if (at24->client[i]) - i2c_unregister_device(at24->client[i]); - - return err; -} - -static int at24_remove(struct i2c_client *client) -{ - struct at24_data *at24; - int i; - - at24 = i2c_get_clientdata(client); - sysfs_remove_bin_file(&client->dev.kobj, &at24->bin); - - for (i = 1; i < at24->num_addresses; i++) - i2c_unregister_device(at24->client[i]); - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -static struct i2c_board_info i2c_devs = { - I2C_BOARD_INFO("24c64-ctc", 0x57), -}; - -static struct i2c_adapter *adapter = NULL; -static struct i2c_client *client = NULL; - -static int ctc_at24c64_init(void) -{ - printk(KERN_ALERT "ctc_at24c64_init\n"); - - adapter = i2c_get_adapter(0); - if(adapter == NULL){ - printk(KERN_ALERT "i2c_get_adapter == NULL\n"); - return -1; - } - - client = i2c_new_device(adapter, &i2c_devs); - if(client == NULL){ - printk(KERN_ALERT "i2c_new_device == NULL\n"); - i2c_put_adapter(adapter); - adapter = NULL; - return -1; - } - - return 0; -} - -static void ctc_at24c64_exit(void) -{ - printk(KERN_ALERT "ctc_at24c64_exit\n"); - if(client){ - i2c_unregister_device(client); - } - if(adapter){ - i2c_put_adapter(adapter); - } -} - -static struct i2c_driver at24_ctc_driver = { - .driver = { - .name = "at24-ctc", - .owner = THIS_MODULE, - }, - .probe = at24_probe, - .remove = at24_remove, - .id_table = at24_ctc_ids, -}; - -static int __init at24_ctc_init(void) -{ - if (!io_limit) { - pr_err("at24_ctc: io_limit must not be 0!\n"); - return -EINVAL; - } - - io_limit = rounddown_pow_of_two(io_limit); - - ctc_at24c64_init(); - - return i2c_add_driver(&at24_ctc_driver); -} -module_init(at24_ctc_init); - -static void __exit at24_ctc_exit(void) -{ - ctc_at24c64_exit(); - i2c_del_driver(&at24_ctc_driver); -} -module_exit(at24_ctc_exit); - -MODULE_DESCRIPTION("Driver for most I2C EEPROMs"); -MODULE_AUTHOR("David Brownell and Wolfram Sang"); -MODULE_LICENSE("GPL"); -/* XXX */ - diff --git a/platform/centec/sonic-platform-modules-e582/48x2q4z/modules/centec_e582_48x2q4z_platform.c b/platform/centec/sonic-platform-modules-e582/48x2q4z/modules/centec_e582_48x2q4z_platform.c index 6e06a67f8dd2..c1d0c8aa5f20 100644 --- a/platform/centec/sonic-platform-modules-e582/48x2q4z/modules/centec_e582_48x2q4z_platform.c +++ b/platform/centec/sonic-platform-modules-e582/48x2q4z/modules/centec_e582_48x2q4z_platform.c @@ -1,7 +1,7 @@ #include #include #include -#include +#include "../../pca954x/ctc-pca954x.h" #include #include #include @@ -95,7 +95,7 @@ static struct pca954x_platform_data i2c_dev_pca9548_platform_data = { .num_modes = PCA9548_CHANNEL_NUM, }; static struct i2c_board_info i2c_dev_pca9548 = { - I2C_BOARD_INFO("pca9548", 0x70), + I2C_BOARD_INFO("ctc_pca9548", 0x70), .platform_data = &i2c_dev_pca9548_platform_data, }; static struct i2c_client *i2c_client_pca9548x = NULL; @@ -110,7 +110,7 @@ static int e582_48x2q4z_init_i2c_pca9548(void) } /* install i2c-mux */ - i2c_client_pca9548x = i2c_new_device(i2c_adp_master, &i2c_dev_pca9548); + i2c_client_pca9548x = i2c_new_client_device(i2c_adp_master, &i2c_dev_pca9548); if(IS_INVALID_PTR(i2c_client_pca9548x)) { i2c_client_pca9548x = NULL; @@ -150,7 +150,7 @@ static int e582_48x2q4z_init_i2c_adt7470(void) return -1; } - i2c_client_adt7470 = i2c_new_device(i2c_adp_adt7470, &i2c_dev_adt7470); + i2c_client_adt7470 = i2c_new_client_device(i2c_adp_adt7470, &i2c_dev_adt7470); if(IS_INVALID_PTR(i2c_client_adt7470)){ i2c_client_adt7470 = NULL; printk(KERN_CRIT "install e582_48x2q4z board adt7470 failed\n"); @@ -206,14 +206,14 @@ static int e582_48x2q4z_init_i2c_psu(void) return -1; } - i2c_client_psu1 = i2c_new_device(i2c_adp_psu1, &i2c_dev_psu1); + i2c_client_psu1 = i2c_new_client_device(i2c_adp_psu1, &i2c_dev_psu1); if(IS_INVALID_PTR(i2c_client_psu1)){ i2c_client_psu1 = NULL; printk(KERN_CRIT "create e582_48x2q4z board i2c client psu1 failed\n"); return -1; } - i2c_client_psu2 = i2c_new_device(i2c_adp_psu2, &i2c_dev_psu2); + i2c_client_psu2 = i2c_new_client_device(i2c_adp_psu2, &i2c_dev_psu2); if(IS_INVALID_PTR(i2c_client_psu2)){ i2c_client_psu2 = NULL; printk(KERN_CRIT "create e582_48x2q4z board i2c client psu2 failed\n"); @@ -265,7 +265,7 @@ static int e582_48x2q4z_init_i2c_epld(void) return -1; } - i2c_client_epld = i2c_new_device(i2c_adp_master, &i2c_dev_epld); + i2c_client_epld = i2c_new_client_device(i2c_adp_master, &i2c_dev_epld); if(IS_INVALID_PTR(i2c_client_epld)) { i2c_client_epld = NULL; @@ -362,7 +362,7 @@ static int e582_48x2q4z_init_i2c_gpio(void) return -1; } - i2c_client_gpio0 = i2c_new_device(i2c_adp_gpio0, &i2c_dev_gpio0); + i2c_client_gpio0 = i2c_new_client_device(i2c_adp_gpio0, &i2c_dev_gpio0); if(IS_INVALID_PTR(i2c_client_gpio0)) { i2c_client_gpio0 = NULL; @@ -370,7 +370,7 @@ static int e582_48x2q4z_init_i2c_gpio(void) return -1; } - i2c_client_gpio1 = i2c_new_device(i2c_adp_gpio1, &i2c_dev_gpio1); + i2c_client_gpio1 = i2c_new_client_device(i2c_adp_gpio1, &i2c_dev_gpio1); if(IS_INVALID_PTR(i2c_client_gpio1)) { i2c_client_gpio1 = NULL; @@ -378,7 +378,7 @@ static int e582_48x2q4z_init_i2c_gpio(void) return -1; } - i2c_client_gpio2 = i2c_new_device(i2c_adp_gpio2, &i2c_dev_gpio2); + i2c_client_gpio2 = i2c_new_client_device(i2c_adp_gpio2, &i2c_dev_gpio2); if(IS_INVALID_PTR(i2c_client_gpio2)) { i2c_client_gpio2 = NULL; @@ -386,7 +386,7 @@ static int e582_48x2q4z_init_i2c_gpio(void) return -1; } - i2c_client_gpio3 = i2c_new_device(i2c_adp_gpio3, &i2c_dev_gpio3); + i2c_client_gpio3 = i2c_new_client_device(i2c_adp_gpio3, &i2c_dev_gpio3); if(IS_INVALID_PTR(i2c_client_gpio3)) { i2c_client_gpio3 = NULL; @@ -394,7 +394,7 @@ static int e582_48x2q4z_init_i2c_gpio(void) return -1; } - i2c_client_gpio4 = i2c_new_device(i2c_adp_gpio4, &i2c_dev_gpio4); + i2c_client_gpio4 = i2c_new_client_device(i2c_adp_gpio4, &i2c_dev_gpio4); if(IS_INVALID_PTR(i2c_client_gpio4)) { i2c_client_gpio4 = NULL; diff --git a/platform/centec/sonic-platform-modules-e582/48x2q4z/scripts/48x2q4z_platform.sh b/platform/centec/sonic-platform-modules-e582/48x2q4z/scripts/48x2q4z_platform.sh index 0edb50901425..f797909fa848 100755 --- a/platform/centec/sonic-platform-modules-e582/48x2q4z/scripts/48x2q4z_platform.sh +++ b/platform/centec/sonic-platform-modules-e582/48x2q4z/scripts/48x2q4z_platform.sh @@ -25,12 +25,13 @@ if [ "$1" == "init" ]; then modprobe i2c-dev modprobe i2c-mux modprobe i2c-smbus - modprobe i2c-mux-pca954x force_deselect_on_exit=1 + modprobe ctc-i2c-mux-pca954x force_deselect_on_exit=1 i2cset -y 0 0x58 0x8 0x3f modprobe lm77 modprobe tun modprobe dal - modprobe centec_at24c64 + modprobe at24 + echo 24c64 0x57 > /sys/bus/i2c/devices/i2c-0/new_device modprobe centec_e582_48x2q4z_platform i2cset -y 15 0x21 0x18 0x0 i2cset -y 15 0x21 0x19 0x0 @@ -69,9 +70,9 @@ elif [ "$1" == "deinit" ]; then kill -9 $(pidof platform_monitor) > /dev/null 2>&1 rm -rf /usr/bin/platform_monitor modprobe -r centec_e582_48x2q4z_platform - modprobe -r centec_at24c64 + modprobe -r at24 modprobe -r dal - modprobe -r i2c-mux-pca954x + modprobe -r ctc-i2c-mux-pca954x modprobe -r i2c-dev else echo "e582-48x2q4z_platform : Invalid option !" diff --git a/platform/centec/sonic-platform-modules-e582/48x6q/modules/Makefile b/platform/centec/sonic-platform-modules-e582/48x6q/modules/Makefile index 2462555c8714..d87c7bd4aa63 100644 --- a/platform/centec/sonic-platform-modules-e582/48x6q/modules/Makefile +++ b/platform/centec/sonic-platform-modules-e582/48x6q/modules/Makefile @@ -1 +1,3 @@ -obj-m := centec_e582_48x6q_platform.o centec_at24c64.o +KBUILD_EXTRA_SYMBOLS = /sonic/platform/centec/sonic-platform-modules-e582/pca954x/Module.symvers + +obj-m := centec_e582_48x6q_platform.o diff --git a/platform/centec/sonic-platform-modules-e582/48x6q/modules/centec_at24c64.c b/platform/centec/sonic-platform-modules-e582/48x6q/modules/centec_at24c64.c deleted file mode 100644 index e1835df88625..000000000000 --- a/platform/centec/sonic-platform-modules-e582/48x6q/modules/centec_at24c64.c +++ /dev/null @@ -1,602 +0,0 @@ -/* - * at24.c - handle most I2C EEPROMs - * - * Copyright (C) 2005-2007 David Brownell - * Copyright (C) 2008 Wolfram Sang, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * I2C EEPROMs from most vendors are inexpensive and mostly interchangeable. - * Differences between different vendor product lines (like Atmel AT24C or - * MicroChip 24LC, etc) won't much matter for typical read/write access. - * There are also I2C RAM chips, likewise interchangeable. One example - * would be the PCF8570, which acts like a 24c02 EEPROM (256 bytes). - * - * However, misconfiguration can lose data. "Set 16-bit memory address" - * to a part with 8-bit addressing will overwrite data. Writing with too - * big a page size also loses data. And it's not safe to assume that the - * conventional addresses 0x50..0x57 only hold eeproms; a PCF8563 RTC - * uses 0x51, for just one example. - * - * Accordingly, explicit board-specific configuration data should be used - * in almost all cases. (One partial exception is an SMBus used to access - * "SPD" data for DRAM sticks. Those only use 24c02 EEPROMs.) - * - * So this driver uses "new style" I2C driver binding, expecting to be - * told what devices exist. That may be in arch/X/mach-Y/board-Z.c or - * similar kernel-resident tables; or, configuration data coming from - * a bootloader. - * - * Other than binding model, current differences from "eeprom" driver are - * that this one handles write access and isn't restricted to 24c02 devices. - * It also handles larger devices (32 kbit and up) with two-byte addresses, - * which won't work on pure SMBus systems. - */ - -struct at24_data { - struct at24_platform_data chip; - int use_smbus; - - /* - * Lock protects against activities from other Linux tasks, - * but not from changes by other I2C masters. - */ - struct mutex lock; - struct bin_attribute bin; - - u8 *writebuf; - unsigned write_max; - unsigned num_addresses; - - /* - * Some chips tie up multiple I2C addresses; dummy devices reserve - * them for us, and we'll use them with SMBus calls. - */ - struct i2c_client *client[]; -}; - -/* - * This parameter is to help this driver avoid blocking other drivers out - * of I2C for potentially troublesome amounts of time. With a 100 kHz I2C - * clock, one 256 byte read takes about 1/43 second which is excessive; - * but the 1/170 second it takes at 400 kHz may be quite reasonable; and - * at 1 MHz (Fm+) a 1/430 second delay could easily be invisible. - * - * This value is forced to be a power of two so that writes align on pages. - */ -static unsigned io_limit = 128; -module_param(io_limit, uint, 0); -MODULE_PARM_DESC(io_limit, "Maximum bytes per I/O (default 128)"); - -/* - * Specs often allow 5 msec for a page write, sometimes 20 msec; - * it's important to recover from write timeouts. - */ -static unsigned write_timeout = 25; -module_param(write_timeout, uint, 0); -MODULE_PARM_DESC(write_timeout, "Time (in ms) to try writes (default 25)"); - -#define AT24_SIZE_BYTELEN 5 -#define AT24_SIZE_FLAGS 8 - -#define AT24_BITMASK(x) (BIT(x) - 1) - -/* create non-zero magic value for given eeprom parameters */ -#define AT24_DEVICE_MAGIC(_len, _flags) \ - ((1 << AT24_SIZE_FLAGS | (_flags)) \ - << AT24_SIZE_BYTELEN | ilog2(_len)) - -static const struct i2c_device_id at24_ctc_ids[] = { - { "24c64-ctc", AT24_DEVICE_MAGIC(65536 / 8, AT24_FLAG_ADDR16 | AT24_FLAG_READONLY | AT24_FLAG_IRUGO) }, - { /* END OF LIST */ } -}; -MODULE_DEVICE_TABLE(i2c, at24_ctc_ids); - -/*-------------------------------------------------------------------------*/ - -/* - * This routine supports chips which consume multiple I2C addresses. It - * computes the addressing information to be used for a given r/w request. - * Assumes that sanity checks for offset happened at sysfs-layer. - */ -static struct i2c_client *at24_translate_offset(struct at24_data *at24, - unsigned *offset) -{ - unsigned i = 0; - - if (at24->chip.flags & AT24_FLAG_ADDR16) { - i = *offset >> 16; - *offset &= 0xffff; - } else { - i = *offset >> 8; - *offset &= 0xff; - } - - return at24->client[i]; -} - -static ssize_t at24_eeprom_read(struct at24_data *at24, char *buf, - unsigned offset, size_t count) -{ - struct i2c_msg msg[2]; - struct i2c_client *client; - unsigned long timeout, read_time; - int status; - - memset(msg, 0, sizeof(msg)); - - /* - * REVISIT some multi-address chips don't rollover page reads to - * the next slave address, so we may need to truncate the count. - * Those chips might need another quirk flag. - * - * If the real hardware used four adjacent 24c02 chips and that - * were misconfigured as one 24c08, that would be a similar effect: - * one "eeprom" file not four, but larger reads would fail when - * they crossed certain pages. - */ - - /* - * Slave address and byte offset derive from the offset. Always - * set the byte address; on a multi-master board, another master - * may have changed the chip's "current" address pointer. - */ - client = at24_translate_offset(at24, &offset); - - if (count > io_limit) - count = io_limit; - - count = 1; - - /* - * Reads fail if the previous write didn't complete yet. We may - * loop a few times until this one succeeds, waiting at least - * long enough for one entire page write to work. - */ - timeout = jiffies + msecs_to_jiffies(write_timeout); - do { - read_time = jiffies; - - status = i2c_smbus_write_byte_data(client, (offset >> 8) & 0x0ff, offset & 0x0ff ); - status = i2c_smbus_read_byte(client); - if (status >= 0) { - buf[0] = status; - status = count; - } - - dev_dbg(&client->dev, "read %zu@%d --> %d (%ld)\n", count, offset, status, jiffies); - - if (status == count) - return count; - - /* REVISIT: at HZ=100, this is sloooow */ - msleep(1); - } while (time_before(read_time, timeout)); - - return -ETIMEDOUT; -} - -static ssize_t at24_read(struct at24_data *at24, - char *buf, loff_t off, size_t count) -{ - ssize_t retval = 0; - - if (unlikely(!count)) - return count; - - memset(buf, 0, count); - - /* - * Read data from chip, protecting against concurrent updates - * from this host, but not from other I2C masters. - */ - mutex_lock(&at24->lock); - - while (count) { - ssize_t status; - - status = at24_eeprom_read(at24, buf, off, count); - if (status <= 0) { - if (retval == 0) - retval = status; - break; - } - buf += status; - off += status; - count -= status; - retval += status; - } - - mutex_unlock(&at24->lock); - - return retval; -} - -static ssize_t at24_bin_read(struct file *filp, struct kobject *kobj, - struct bin_attribute *attr, - char *buf, loff_t off, size_t count) -{ - struct at24_data *at24; - - at24 = dev_get_drvdata(container_of(kobj, struct device, kobj)); - return at24_read(at24, buf, off, count); -} - - -/* - * Note that if the hardware write-protect pin is pulled high, the whole - * chip is normally write protected. But there are plenty of product - * variants here, including OTP fuses and partial chip protect. - * - * We only use page mode writes; the alternative is sloooow. This routine - * writes at most one page. - */ -static ssize_t at24_eeprom_write(struct at24_data *at24, const char *buf, - unsigned offset, size_t count) -{ - struct i2c_client *client; - ssize_t status; - unsigned long timeout, write_time; - unsigned next_page; - - /* Get corresponding I2C address and adjust offset */ - client = at24_translate_offset(at24, &offset); - - /* write_max is at most a page */ - if (count > at24->write_max) - count = at24->write_max; - - /* Never roll over backwards, to the start of this page */ - next_page = roundup(offset + 1, at24->chip.page_size); - if (offset + count > next_page) - count = next_page - offset; - - /* - * Writes fail if the previous one didn't complete yet. We may - * loop a few times until this one succeeds, waiting at least - * long enough for one entire page write to work. - */ - timeout = jiffies + msecs_to_jiffies(write_timeout); - do { - write_time = jiffies; - - status = i2c_smbus_write_word_data(client, (offset >> 8) & 0x0ff, (offset & 0xFF) | buf[0]); - if (status == 0) - status = count; - - dev_dbg(&client->dev, "write %zu@%d --> %zd (%ld)\n", count, offset, status, jiffies); - - if (status == count) - return count; - - /* REVISIT: at HZ=100, this is sloooow */ - msleep(1); - } while (time_before(write_time, timeout)); - - return -ETIMEDOUT; -} - -static ssize_t at24_write(struct at24_data *at24, const char *buf, loff_t off, - size_t count) -{ - ssize_t retval = 0; - - if (unlikely(!count)) - return count; - - /* - * Write data to chip, protecting against concurrent updates - * from this host, but not from other I2C masters. - */ - mutex_lock(&at24->lock); - - while (count) { - ssize_t status; - - status = at24_eeprom_write(at24, buf, off, 1); /* only one-byte to write; TODO page wirte */ - if (status <= 0) { - if (retval == 0) - retval = status; - break; - } - buf += status; - off += status; - count -= status; - retval += status; - } - - mutex_unlock(&at24->lock); - - return retval; -} - -static ssize_t at24_bin_write(struct file *filp, struct kobject *kobj, - struct bin_attribute *attr, - char *buf, loff_t off, size_t count) -{ - struct at24_data *at24; - - if (unlikely(off >= attr->size)) - return -EFBIG; - - at24 = dev_get_drvdata(container_of(kobj, struct device, kobj)); - return at24_write(at24, buf, off, count); -} - -/*-------------------------------------------------------------------------*/ - -#ifdef CONFIG_OF -static void at24_get_ofdata(struct i2c_client *client, - struct at24_platform_data *chip) -{ - const __be32 *val; - struct device_node *node = client->dev.of_node; - - if (node) { - if (of_get_property(node, "read-only", NULL)) - chip->flags |= AT24_FLAG_READONLY; - val = of_get_property(node, "pagesize", NULL); - if (val) - chip->page_size = be32_to_cpup(val); - } -} -#else -static void at24_get_ofdata(struct i2c_client *client, - struct at24_platform_data *chip) -{ } -#endif /* CONFIG_OF */ - -static int at24_probe(struct i2c_client *client, const struct i2c_device_id *id) -{ - struct at24_platform_data chip; - bool writable; - int use_smbus = 0; - struct at24_data *at24; - int err; - unsigned i, num_addresses; - kernel_ulong_t magic; - - if (client->dev.platform_data) { - chip = *(struct at24_platform_data *)client->dev.platform_data; - } else { - if (!id->driver_data) - return -ENODEV; - - magic = id->driver_data; - chip.byte_len = BIT(magic & AT24_BITMASK(AT24_SIZE_BYTELEN)); - magic >>= AT24_SIZE_BYTELEN; - chip.flags = magic & AT24_BITMASK(AT24_SIZE_FLAGS); - - /* - * This is slow, but we can't know all eeproms, so we better - * play safe. Specifying custom eeprom-types via platform_data - * is recommended anyhow. - */ - chip.page_size = 1; - - /* update chipdata if OF is present */ - at24_get_ofdata(client, &chip); - - chip.setup = NULL; - chip.context = NULL; - } - - if (!is_power_of_2(chip.byte_len)) - dev_warn(&client->dev, - "byte_len looks suspicious (no power of 2)!\n"); - if (!chip.page_size) { - dev_err(&client->dev, "page_size must not be 0!\n"); - return -EINVAL; - } - if (!is_power_of_2(chip.page_size)) - dev_warn(&client->dev, - "page_size looks suspicious (no power of 2)!\n"); - - /* Use I2C operations unless we're stuck with SMBus extensions. */ - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { - if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { - use_smbus = I2C_SMBUS_I2C_BLOCK_DATA; - } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_WORD_DATA)) { - use_smbus = I2C_SMBUS_WORD_DATA; - } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_BYTE_DATA)) { - use_smbus = I2C_SMBUS_BYTE_DATA; - } else { - return -EPFNOSUPPORT; - } - use_smbus = I2C_SMBUS_BYTE_DATA; - } - - if (chip.flags & AT24_FLAG_TAKE8ADDR) - num_addresses = 8; - else - num_addresses = DIV_ROUND_UP(chip.byte_len, (chip.flags & AT24_FLAG_ADDR16) ? 65536 : 256); - - at24 = devm_kzalloc(&client->dev, sizeof(struct at24_data) + num_addresses * sizeof(struct i2c_client *), GFP_KERNEL); - if (!at24) - return -ENOMEM; - - mutex_init(&at24->lock); - at24->use_smbus = use_smbus; - at24->chip = chip; - at24->num_addresses = num_addresses; - - printk(KERN_ALERT "at24_probe chip.byte_len = 0x%x\n", chip.byte_len); - printk(KERN_ALERT "at24_probe chip.flags = 0x%x\n", chip.flags); - printk(KERN_ALERT "at24_probe chip.magic = 0x%lx\n", id->driver_data); - printk(KERN_ALERT "at24_probe use_smbus = %d\n", at24->use_smbus); - printk(KERN_ALERT "at24_probe num_addresses = %d\n", at24->num_addresses); - - /* - * Export the EEPROM bytes through sysfs, since that's convenient. - * By default, only root should see the data (maybe passwords etc) - */ - sysfs_bin_attr_init(&at24->bin); - at24->bin.attr.name = "eeprom"; - at24->bin.attr.mode = chip.flags & AT24_FLAG_IRUGO ? S_IRUGO : S_IRUSR; - at24->bin.read = at24_bin_read; - at24->bin.size = chip.byte_len; - - writable = !(chip.flags & AT24_FLAG_READONLY); - if (writable) { - if (!use_smbus || i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) { - unsigned write_max = chip.page_size; - - at24->bin.write = at24_bin_write; - at24->bin.attr.mode |= S_IWUSR; - - if (write_max > io_limit) - write_max = io_limit; - if (use_smbus && write_max > I2C_SMBUS_BLOCK_MAX) - write_max = I2C_SMBUS_BLOCK_MAX; - at24->write_max = write_max; - - /* buffer (data + address at the beginning) */ - at24->writebuf = devm_kzalloc(&client->dev, write_max + 2, GFP_KERNEL); - if (!at24->writebuf) - return -ENOMEM; - } else { - dev_warn(&client->dev, "cannot write due to controller restrictions."); - } - } - - at24->client[0] = client; - - /* use dummy devices for multiple-address chips */ - for (i = 1; i < num_addresses; i++) { - at24->client[i] = i2c_new_dummy(client->adapter, client->addr + i); - if (!at24->client[i]) { - dev_err(&client->dev, "address 0x%02x unavailable\n", client->addr + i); - err = -EADDRINUSE; - goto err_clients; - } - } - - err = sysfs_create_bin_file(&client->dev.kobj, &at24->bin); - if (err) - goto err_clients; - - i2c_set_clientdata(client, at24); - - printk(KERN_ALERT "at24_probe %s done\n", client->name); - - return 0; - -err_clients: - for (i = 1; i < num_addresses; i++) - if (at24->client[i]) - i2c_unregister_device(at24->client[i]); - - return err; -} - -static int at24_remove(struct i2c_client *client) -{ - struct at24_data *at24; - int i; - - at24 = i2c_get_clientdata(client); - sysfs_remove_bin_file(&client->dev.kobj, &at24->bin); - - for (i = 1; i < at24->num_addresses; i++) - i2c_unregister_device(at24->client[i]); - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -static struct i2c_board_info i2c_devs = { - I2C_BOARD_INFO("24c64-ctc", 0x57), -}; - -static struct i2c_adapter *adapter = NULL; -static struct i2c_client *client = NULL; - -static int ctc_at24c64_init(void) -{ - printk(KERN_ALERT "ctc_at24c64_init\n"); - - adapter = i2c_get_adapter(0); - if(adapter == NULL){ - printk(KERN_ALERT "i2c_get_adapter == NULL\n"); - return -1; - } - - client = i2c_new_device(adapter, &i2c_devs); - if(client == NULL){ - printk(KERN_ALERT "i2c_new_device == NULL\n"); - i2c_put_adapter(adapter); - adapter = NULL; - return -1; - } - - return 0; -} - -static void ctc_at24c64_exit(void) -{ - printk(KERN_ALERT "ctc_at24c64_exit\n"); - if(client){ - i2c_unregister_device(client); - } - if(adapter){ - i2c_put_adapter(adapter); - } -} - -static struct i2c_driver at24_ctc_driver = { - .driver = { - .name = "at24-ctc", - .owner = THIS_MODULE, - }, - .probe = at24_probe, - .remove = at24_remove, - .id_table = at24_ctc_ids, -}; - -static int __init at24_ctc_init(void) -{ - if (!io_limit) { - pr_err("at24_ctc: io_limit must not be 0!\n"); - return -EINVAL; - } - - io_limit = rounddown_pow_of_two(io_limit); - - ctc_at24c64_init(); - - return i2c_add_driver(&at24_ctc_driver); -} -module_init(at24_ctc_init); - -static void __exit at24_ctc_exit(void) -{ - ctc_at24c64_exit(); - i2c_del_driver(&at24_ctc_driver); -} -module_exit(at24_ctc_exit); - -MODULE_DESCRIPTION("Driver for most I2C EEPROMs"); -MODULE_AUTHOR("David Brownell and Wolfram Sang"); -MODULE_LICENSE("GPL"); -/* XXX */ - diff --git a/platform/centec/sonic-platform-modules-e582/48x6q/modules/centec_e582_48x6q_platform.c b/platform/centec/sonic-platform-modules-e582/48x6q/modules/centec_e582_48x6q_platform.c index f72efee2a0d6..a0d0e0ca99dd 100644 --- a/platform/centec/sonic-platform-modules-e582/48x6q/modules/centec_e582_48x6q_platform.c +++ b/platform/centec/sonic-platform-modules-e582/48x6q/modules/centec_e582_48x6q_platform.c @@ -1,7 +1,7 @@ #include #include #include -#include +#include "../../pca954x/ctc-pca954x.h" #include #include #include @@ -95,7 +95,7 @@ static struct pca954x_platform_data i2c_dev_pca9548_platform_data = { .num_modes = PCA9548_CHANNEL_NUM, }; static struct i2c_board_info i2c_dev_pca9548 = { - I2C_BOARD_INFO("pca9548", 0x70), + I2C_BOARD_INFO("ctc_pca9548", 0x70), .platform_data = &i2c_dev_pca9548_platform_data, }; static struct i2c_client *i2c_client_pca9548x = NULL; @@ -110,7 +110,7 @@ static int e582_48x6q_init_i2c_pca9548(void) } /* install i2c-mux */ - i2c_client_pca9548x = i2c_new_device(i2c_adp_master, &i2c_dev_pca9548); + i2c_client_pca9548x = i2c_new_client_device(i2c_adp_master, &i2c_dev_pca9548); if(IS_INVALID_PTR(i2c_client_pca9548x)) { i2c_client_pca9548x = NULL; @@ -150,7 +150,7 @@ static int e582_48x6q_init_i2c_adt7470(void) return -1; } - i2c_client_adt7470 = i2c_new_device(i2c_adp_adt7470, &i2c_dev_adt7470); + i2c_client_adt7470 = i2c_new_client_device(i2c_adp_adt7470, &i2c_dev_adt7470); if(IS_INVALID_PTR(i2c_client_adt7470)){ i2c_client_adt7470 = NULL; printk(KERN_CRIT "install e582_48x6q board adt7470 failed\n"); @@ -206,14 +206,14 @@ static int e582_48x6q_init_i2c_psu(void) return -1; } - i2c_client_psu1 = i2c_new_device(i2c_adp_psu1, &i2c_dev_psu1); + i2c_client_psu1 = i2c_new_client_device(i2c_adp_psu1, &i2c_dev_psu1); if(IS_INVALID_PTR(i2c_client_psu1)){ i2c_client_psu1 = NULL; printk(KERN_CRIT "create e582_48x6q board i2c client psu1 failed\n"); return -1; } - i2c_client_psu2 = i2c_new_device(i2c_adp_psu2, &i2c_dev_psu2); + i2c_client_psu2 = i2c_new_client_device(i2c_adp_psu2, &i2c_dev_psu2); if(IS_INVALID_PTR(i2c_client_psu2)){ i2c_client_psu2 = NULL; printk(KERN_CRIT "create e582_48x6q board i2c client psu2 failed\n"); @@ -265,7 +265,7 @@ static int e582_48x6q_init_i2c_epld(void) return -1; } - i2c_client_epld = i2c_new_device(i2c_adp_master, &i2c_dev_epld); + i2c_client_epld = i2c_new_client_device(i2c_adp_master, &i2c_dev_epld); if(IS_INVALID_PTR(i2c_client_epld)) { i2c_client_epld = NULL; @@ -317,7 +317,7 @@ static int e582_48x6q_init_i2c_gpio(void) return -1; } - i2c_client_gpio0 = i2c_new_device(i2c_adp_master, &i2c_dev_gpio0); + i2c_client_gpio0 = i2c_new_client_device(i2c_adp_master, &i2c_dev_gpio0); if(IS_INVALID_PTR(i2c_client_gpio0)) { i2c_client_gpio0 = NULL; @@ -325,7 +325,7 @@ static int e582_48x6q_init_i2c_gpio(void) return -1; } - i2c_client_gpio1 = i2c_new_device(i2c_adp_master, &i2c_dev_gpio1); + i2c_client_gpio1 = i2c_new_client_device(i2c_adp_master, &i2c_dev_gpio1); if(IS_INVALID_PTR(i2c_client_gpio1)) { i2c_client_gpio1 = NULL; @@ -333,7 +333,7 @@ static int e582_48x6q_init_i2c_gpio(void) return -1; } - i2c_client_gpio2 = i2c_new_device(i2c_adp_master, &i2c_dev_gpio2); + i2c_client_gpio2 = i2c_new_client_device(i2c_adp_master, &i2c_dev_gpio2); if(IS_INVALID_PTR(i2c_client_gpio2)) { i2c_client_gpio2 = NULL; @@ -341,7 +341,7 @@ static int e582_48x6q_init_i2c_gpio(void) return -1; } - i2c_client_gpio3 = i2c_new_device(i2c_adp_master, &i2c_dev_gpio3); + i2c_client_gpio3 = i2c_new_client_device(i2c_adp_master, &i2c_dev_gpio3); if(IS_INVALID_PTR(i2c_client_gpio3)) { i2c_client_gpio3 = NULL; @@ -349,7 +349,7 @@ static int e582_48x6q_init_i2c_gpio(void) return -1; } - i2c_client_gpio4 = i2c_new_device(i2c_adp_master, &i2c_dev_gpio4); + i2c_client_gpio4 = i2c_new_client_device(i2c_adp_master, &i2c_dev_gpio4); if(IS_INVALID_PTR(i2c_client_gpio4)) { i2c_client_gpio4 = NULL; diff --git a/platform/centec/sonic-platform-modules-e582/48x6q/scripts/48x6q_platform.sh b/platform/centec/sonic-platform-modules-e582/48x6q/scripts/48x6q_platform.sh index e8f81a20d9d1..3a7e52a59425 100755 --- a/platform/centec/sonic-platform-modules-e582/48x6q/scripts/48x6q_platform.sh +++ b/platform/centec/sonic-platform-modules-e582/48x6q/scripts/48x6q_platform.sh @@ -25,7 +25,7 @@ if [ "$1" == "init" ]; then modprobe i2c-dev modprobe i2c-mux modprobe i2c-smbus - modprobe i2c-mux-pca954x force_deselect_on_exit=1 + modprobe ctc-i2c-mux-pca954x force_deselect_on_exit=1 i2cset -y 0 0x58 0x8 0x3f i2cset -y 0 0x20 0x1b 0x0 i2cset -y 0 0x20 0xb 0x0 @@ -42,7 +42,8 @@ if [ "$1" == "init" ]; then modprobe lm77 modprobe tun modprobe dal - modprobe centec_at24c64 + modprobe at24 + echo 24c64 0x57 > /sys/bus/i2c/devices/i2c-0/new_device modprobe centec_e582_48x6q_platform #start platform monitor @@ -53,9 +54,9 @@ elif [ "$1" == "deinit" ]; then kill -9 $(pidof platform_monitor) > /dev/null 2>&1 rm -rf /usr/bin/platform_monitor modprobe -r centec_e582_48x6q_platform - modprobe -r centec_at24c64 + modprobe -r at24 modprobe -r dal - modprobe -r i2c-mux-pca954x + modprobe -r ctc-i2c-mux-pca954x modprobe -r i2c-dev else echo "e582-48x6q_platform : Invalid option !" diff --git a/platform/centec/sonic-platform-modules-e582/debian/control b/platform/centec/sonic-platform-modules-e582/debian/control index 97f617d4836a..cfd5e45d891c 100644 --- a/platform/centec/sonic-platform-modules-e582/debian/control +++ b/platform/centec/sonic-platform-modules-e582/debian/control @@ -7,11 +7,11 @@ Standards-Version: 3.9.3 Package: platform-modules-e582-48x2q4z Architecture: amd64 -Depends: linux-image-4.19.0-12-2-amd64-unsigned +Depends: linux-image-5.10.0-8-2-amd64-unsigned Description: kernel modules for platform devices such as fan, led, sfp Package: platform-modules-e582-48x6q Architecture: amd64 -Depends: linux-image-4.19.0-12-2-amd64-unsigned +Depends: linux-image-5.10.0-8-2-amd64-unsigned Description: kernel modules for platform devices such as fan, led, sfp diff --git a/platform/centec/sonic-platform-modules-e582/debian/rules b/platform/centec/sonic-platform-modules-e582/debian/rules index 45fd499e2495..4f7100f1172b 100755 --- a/platform/centec/sonic-platform-modules-e582/debian/rules +++ b/platform/centec/sonic-platform-modules-e582/debian/rules @@ -6,6 +6,7 @@ KVERSION ?= $(shell uname -r) KERNEL_SRC := /lib/modules/$(KVERSION) MOD_SRC_DIR:= $(shell pwd) MODULE_DIRS:= 48x6q 48x2q4z +PCA954X_DIR := pca954x %: dh $@ @@ -14,6 +15,9 @@ override_dh_auto_build: (for mod in $(MODULE_DIRS); do \ make -C $(KERNEL_SRC)/build M=$(MOD_SRC_DIR)/$${mod}/modules; \ done) + (for mod in $(PCA954X_DIR); do \ + make modules -C $(KERNEL_SRC)/build M=$(MOD_SRC_DIR)/$${mod}/; \ + done) rm $(MOD_SRC_DIR)/centec-dal -rf cp $(MOD_SRC_DIR)/../centec-dal $(MOD_SRC_DIR)/centec-dal -rf make -C $(KERNEL_SRC)/build M=$(MOD_SRC_DIR)/centec-dal @@ -25,6 +29,7 @@ override_dh_auto_install: cp -f $(MOD_SRC_DIR)/$${mod}/modules/*.ko \ debian/platform-modules-e582-$${mod}/$(KERNEL_SRC)/$(INSTALL_MOD_DIR); \ cp -f $(MOD_SRC_DIR)/centec-dal/*.ko debian/platform-modules-e582-$${mod}/$(KERNEL_SRC)/$(INSTALL_MOD_DIR); \ + cp -f $(MOD_SRC_DIR)/$(PCA954X_DIR)/*.ko debian/platform-modules-e582-$${mod}/$(KERNEL_SRC)/$(INSTALL_MOD_DIR); \ done) override_dh_usrlocal: diff --git a/platform/centec/sonic-platform-modules-e582/pca954x/Makefile b/platform/centec/sonic-platform-modules-e582/pca954x/Makefile new file mode 100644 index 000000000000..0cd3701f1b7f --- /dev/null +++ b/platform/centec/sonic-platform-modules-e582/pca954x/Makefile @@ -0,0 +1 @@ +obj-m := ctc-i2c-mux-pca954x.o diff --git a/platform/centec/sonic-platform-modules-e582/pca954x/ctc-i2c-mux-pca954x.c b/platform/centec/sonic-platform-modules-e582/pca954x/ctc-i2c-mux-pca954x.c new file mode 100644 index 000000000000..3c14bae6654b --- /dev/null +++ b/platform/centec/sonic-platform-modules-e582/pca954x/ctc-i2c-mux-pca954x.c @@ -0,0 +1,581 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * I2C multiplexer + * + * Copyright (c) 2008-2009 Rodolfo Giometti + * Copyright (c) 2008-2009 Eurotech S.p.A. + * + * This module supports the PCA954x and PCA984x series of I2C multiplexer/switch + * chips made by NXP Semiconductors. + * This includes the: + * PCA9540, PCA9542, PCA9543, PCA9544, PCA9545, PCA9546, PCA9547, + * PCA9548, PCA9846, PCA9847, PCA9848 and PCA9849. + * + * These chips are all controlled via the I2C bus itself, and all have a + * single 8-bit register. The upstream "parent" bus fans out to two, + * four, or eight downstream busses or channels; which of these + * are selected is determined by the chip type and register contents. A + * mux can select only one sub-bus at a time; a switch can select any + * combination simultaneously. + * + * Based on: + * pca954x.c from Kumar Gala + * Copyright (C) 2006 + * + * Based on: + * pca954x.c from Ken Harrenstien + * Copyright (C) 2004 Google, Inc. (Ken Harrenstien) + * + * Based on: + * i2c-virtual_cb.c from Brian Kuschak + * and + * pca9540.c from Jean Delvare . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ctc-pca954x.h" + +#define PCA954X_MAX_NCHANS 8 + +#define PCA954X_IRQ_OFFSET 4 + +enum pca_type { + pca_9540, + pca_9542, + pca_9543, + pca_9544, + pca_9545, + pca_9546, + pca_9547, + pca_9548, + pca_9846, + pca_9847, + pca_9848, + pca_9849, +}; + +struct chip_desc { + u8 nchans; + u8 enable; /* used for muxes only */ + u8 has_irq; + enum muxtype { + pca954x_ismux = 0, + pca954x_isswi + } muxtype; + struct i2c_device_identity id; +}; + +struct pca954x { + const struct chip_desc *chip; + + u8 last_chan; /* last register value */ + /* MUX_IDLE_AS_IS, MUX_IDLE_DISCONNECT or >= 0 for channel */ + s32 idle_state; + + struct i2c_client *client; + + struct irq_domain *irq; + unsigned int irq_mask; + raw_spinlock_t lock; +}; + +/* Provide specs for the PCA954x types we know about */ +static const struct chip_desc chips[] = { + [pca_9540] = { + .nchans = 2, + .enable = 0x4, + .muxtype = pca954x_ismux, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9542] = { + .nchans = 2, + .enable = 0x4, + .has_irq = 1, + .muxtype = pca954x_ismux, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9543] = { + .nchans = 2, + .has_irq = 1, + .muxtype = pca954x_isswi, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9544] = { + .nchans = 4, + .enable = 0x4, + .has_irq = 1, + .muxtype = pca954x_ismux, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9545] = { + .nchans = 4, + .has_irq = 1, + .muxtype = pca954x_isswi, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9546] = { + .nchans = 4, + .muxtype = pca954x_isswi, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9547] = { + .nchans = 8, + .enable = 0x8, + .muxtype = pca954x_ismux, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9548] = { + .nchans = 8, + .muxtype = pca954x_isswi, + .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, + }, + [pca_9846] = { + .nchans = 4, + .muxtype = pca954x_isswi, + .id = { + .manufacturer_id = I2C_DEVICE_ID_NXP_SEMICONDUCTORS, + .part_id = 0x10b, + }, + }, + [pca_9847] = { + .nchans = 8, + .enable = 0x8, + .muxtype = pca954x_ismux, + .id = { + .manufacturer_id = I2C_DEVICE_ID_NXP_SEMICONDUCTORS, + .part_id = 0x108, + }, + }, + [pca_9848] = { + .nchans = 8, + .muxtype = pca954x_isswi, + .id = { + .manufacturer_id = I2C_DEVICE_ID_NXP_SEMICONDUCTORS, + .part_id = 0x10a, + }, + }, + [pca_9849] = { + .nchans = 4, + .enable = 0x4, + .muxtype = pca954x_ismux, + .id = { + .manufacturer_id = I2C_DEVICE_ID_NXP_SEMICONDUCTORS, + .part_id = 0x109, + }, + }, +}; + +static const struct i2c_device_id pca954x_id[] = { + { "ctc_pca9540", pca_9540 }, + { "ctc_pca9542", pca_9542 }, + { "ctc_pca9543", pca_9543 }, + { "ctc_pca9544", pca_9544 }, + { "ctc_pca9545", pca_9545 }, + { "ctc_pca9546", pca_9546 }, + { "ctc_pca9547", pca_9547 }, + { "ctc_pca9548", pca_9548 }, + { "ctc_pca9846", pca_9846 }, + { "ctc_pca9847", pca_9847 }, + { "ctc_pca9848", pca_9848 }, + { "ctc_pca9849", pca_9849 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, pca954x_id); + +static const struct of_device_id pca954x_of_match[] = { + { .compatible = "nxp,ctc_pca9540", .data = &chips[pca_9540] }, + { .compatible = "nxp,ctc_pca9542", .data = &chips[pca_9542] }, + { .compatible = "nxp,ctc_pca9543", .data = &chips[pca_9543] }, + { .compatible = "nxp,ctc_pca9544", .data = &chips[pca_9544] }, + { .compatible = "nxp,ctc_pca9545", .data = &chips[pca_9545] }, + { .compatible = "nxp,ctc_pca9546", .data = &chips[pca_9546] }, + { .compatible = "nxp,ctc_pca9547", .data = &chips[pca_9547] }, + { .compatible = "nxp,ctc_pca9548", .data = &chips[pca_9548] }, + { .compatible = "nxp,ctc_pca9846", .data = &chips[pca_9846] }, + { .compatible = "nxp,ctc_pca9847", .data = &chips[pca_9847] }, + { .compatible = "nxp,ctc_pca9848", .data = &chips[pca_9848] }, + { .compatible = "nxp,ctc_pca9849", .data = &chips[pca_9849] }, + {} +}; +MODULE_DEVICE_TABLE(of, pca954x_of_match); + +/* Write to mux register. Don't use i2c_transfer()/i2c_smbus_xfer() + for this as they will try to lock adapter a second time */ +static int pca954x_reg_write(struct i2c_adapter *adap, + struct i2c_client *client, u8 val) +{ + union i2c_smbus_data dummy; + + return __i2c_smbus_xfer(adap, client->addr, client->flags, + I2C_SMBUS_WRITE, val, + I2C_SMBUS_BYTE, &dummy); +} + +static u8 pca954x_regval(struct pca954x *data, u8 chan) +{ + /* We make switches look like muxes, not sure how to be smarter. */ + if (data->chip->muxtype == pca954x_ismux) + return chan | data->chip->enable; + else + return 1 << chan; +} + +static int pca954x_select_chan(struct i2c_mux_core *muxc, u32 chan) +{ + struct pca954x *data = i2c_mux_priv(muxc); + struct i2c_client *client = data->client; + u8 regval; + int ret = 0; + + regval = pca954x_regval(data, chan); + /* Only select the channel if its different from the last channel */ + if (data->last_chan != regval) { + ret = pca954x_reg_write(muxc->parent, client, regval); + data->last_chan = ret < 0 ? 0 : regval; + } + + return ret; +} + +static int pca954x_deselect_mux(struct i2c_mux_core *muxc, u32 chan) +{ + struct pca954x *data = i2c_mux_priv(muxc); + struct i2c_client *client = data->client; + s32 idle_state; + + idle_state = READ_ONCE(data->idle_state); + if (idle_state >= 0) + /* Set the mux back to a predetermined channel */ + return pca954x_select_chan(muxc, idle_state); + + if (idle_state == MUX_IDLE_DISCONNECT) { + /* Deselect active channel */ + data->last_chan = 0; + return pca954x_reg_write(muxc->parent, client, + data->last_chan); + } + + /* otherwise leave as-is */ + + return 0; +} + +static ssize_t idle_state_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct i2c_mux_core *muxc = i2c_get_clientdata(client); + struct pca954x *data = i2c_mux_priv(muxc); + + return sprintf(buf, "%d\n", READ_ONCE(data->idle_state)); +} + +static ssize_t idle_state_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev); + struct i2c_mux_core *muxc = i2c_get_clientdata(client); + struct pca954x *data = i2c_mux_priv(muxc); + int val; + int ret; + + ret = kstrtoint(buf, 0, &val); + if (ret < 0) + return ret; + + if (val != MUX_IDLE_AS_IS && val != MUX_IDLE_DISCONNECT && + (val < 0 || val >= data->chip->nchans)) + return -EINVAL; + + i2c_lock_bus(muxc->parent, I2C_LOCK_SEGMENT); + + WRITE_ONCE(data->idle_state, val); + /* + * Set the mux into a state consistent with the new + * idle_state. + */ + if (data->last_chan || val != MUX_IDLE_DISCONNECT) + ret = pca954x_deselect_mux(muxc, 0); + + i2c_unlock_bus(muxc->parent, I2C_LOCK_SEGMENT); + + return ret < 0 ? ret : count; +} + +static DEVICE_ATTR_RW(idle_state); + +static irqreturn_t pca954x_irq_handler(int irq, void *dev_id) +{ + struct pca954x *data = dev_id; + unsigned long pending; + int ret, i; + + ret = i2c_smbus_read_byte(data->client); + if (ret < 0) + return IRQ_NONE; + + pending = (ret >> PCA954X_IRQ_OFFSET) & (BIT(data->chip->nchans) - 1); + for_each_set_bit(i, &pending, data->chip->nchans) + handle_nested_irq(irq_linear_revmap(data->irq, i)); + + return IRQ_RETVAL(pending); +} + +static int pca954x_irq_set_type(struct irq_data *idata, unsigned int type) +{ + if ((type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_LOW) + return -EINVAL; + return 0; +} + +static struct irq_chip pca954x_irq_chip = { + .name = "i2c-mux-pca954x", + .irq_set_type = pca954x_irq_set_type, +}; + +static int pca954x_irq_setup(struct i2c_mux_core *muxc) +{ + struct pca954x *data = i2c_mux_priv(muxc); + struct i2c_client *client = data->client; + int c, irq; + + if (!data->chip->has_irq || client->irq <= 0) + return 0; + + raw_spin_lock_init(&data->lock); + + data->irq = irq_domain_add_linear(client->dev.of_node, + data->chip->nchans, + &irq_domain_simple_ops, data); + if (!data->irq) + return -ENODEV; + + for (c = 0; c < data->chip->nchans; c++) { + irq = irq_create_mapping(data->irq, c); + if (!irq) { + dev_err(&client->dev, "failed irq create map\n"); + return -EINVAL; + } + irq_set_chip_data(irq, data); + irq_set_chip_and_handler(irq, &pca954x_irq_chip, + handle_simple_irq); + } + + return 0; +} + +static void pca954x_cleanup(struct i2c_mux_core *muxc) +{ + struct pca954x *data = i2c_mux_priv(muxc); + int c, irq; + + if (data->irq) { + for (c = 0; c < data->chip->nchans; c++) { + irq = irq_find_mapping(data->irq, c); + irq_dispose_mapping(irq); + } + irq_domain_remove(data->irq); + } + i2c_mux_del_adapters(muxc); +} + +static int pca954x_init(struct i2c_client *client, struct pca954x *data) +{ + int ret; + + if (data->idle_state >= 0) + data->last_chan = pca954x_regval(data, data->idle_state); + else + data->last_chan = 0; /* Disconnect multiplexer */ + + ret = i2c_smbus_write_byte(client, data->last_chan); + if (ret < 0) + data->last_chan = 0; + + return ret; +} + +/* + * I2C init/probing/exit functions + */ +static int pca954x_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct i2c_adapter *adap = client->adapter; + struct pca954x_platform_data *pdata = dev_get_platdata(&client->dev); + struct device *dev = &client->dev; + struct gpio_desc *gpio; + int num, force, class; + struct i2c_mux_core *muxc; + struct pca954x *data; + int ret; + + if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_BYTE)) + return -ENODEV; + + muxc = i2c_mux_alloc(adap, dev, PCA954X_MAX_NCHANS, sizeof(*data), 0, + pca954x_select_chan, pca954x_deselect_mux); + if (!muxc) + return -ENOMEM; + data = i2c_mux_priv(muxc); + + i2c_set_clientdata(client, muxc); + data->client = client; + + /* Reset the mux if a reset GPIO is specified. */ + gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(gpio)) + return PTR_ERR(gpio); + if (gpio) { + udelay(1); + gpiod_set_value_cansleep(gpio, 0); + /* Give the chip some time to recover. */ + udelay(1); + } + + data->chip = device_get_match_data(dev); + if (!data->chip) + data->chip = &chips[id->driver_data]; + + if (data->chip->id.manufacturer_id != I2C_DEVICE_ID_NONE) { + struct i2c_device_identity id; + + ret = i2c_get_device_id(client, &id); + if (ret && ret != -EOPNOTSUPP) + return ret; + + if (!ret && + (id.manufacturer_id != data->chip->id.manufacturer_id || + id.part_id != data->chip->id.part_id)) { + dev_warn(dev, "unexpected device id %03x-%03x-%x\n", + id.manufacturer_id, id.part_id, + id.die_revision); + return -ENODEV; + } + } + + data->idle_state = MUX_IDLE_AS_IS; + if (device_property_read_u32(dev, "idle-state", &data->idle_state)) { + if (device_property_read_bool(dev, "i2c-mux-idle-disconnect")) + data->idle_state = MUX_IDLE_DISCONNECT; + } + + /* + * Write the mux register at addr to verify + * that the mux is in fact present. This also + * initializes the mux to a channel + * or disconnected state. + */ + ret = pca954x_init(client, data); + if (ret < 0) { + dev_warn(dev, "probe failed\n"); + return -ENODEV; + } + + ret = pca954x_irq_setup(muxc); + if (ret) + goto fail_cleanup; + + /* Now create an adapter for each channel */ + for (num = 0; num < data->chip->nchans; num++) { + force = 0; /* dynamic adap number */ + class = 0; /* no class by default */ + if (pdata) { + if (num < pdata->num_modes) { + /* force static number */ + force = pdata->modes[num].adap_id; + class = pdata->modes[num].class; + } else + /* discard unconfigured channels */ + break; + } + + ret = i2c_mux_add_adapter(muxc, force, num, class); + if (ret) + goto fail_cleanup; + } + + if (data->irq) { + ret = devm_request_threaded_irq(dev, data->client->irq, + NULL, pca954x_irq_handler, + IRQF_ONESHOT | IRQF_SHARED, + "pca954x", data); + if (ret) + goto fail_cleanup; + } + + /* + * The attr probably isn't going to be needed in most cases, + * so don't fail completely on error. + */ + device_create_file(dev, &dev_attr_idle_state); + + dev_info(dev, "registered %d multiplexed busses for I2C %s %s\n", + num, data->chip->muxtype == pca954x_ismux + ? "mux" : "switch", client->name); + + return 0; + +fail_cleanup: + pca954x_cleanup(muxc); + return ret; +} + +static int pca954x_remove(struct i2c_client *client) +{ + struct i2c_mux_core *muxc = i2c_get_clientdata(client); + + device_remove_file(&client->dev, &dev_attr_idle_state); + + pca954x_cleanup(muxc); + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int pca954x_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct i2c_mux_core *muxc = i2c_get_clientdata(client); + struct pca954x *data = i2c_mux_priv(muxc); + int ret; + + ret = pca954x_init(client, data); + if (ret < 0) + dev_err(&client->dev, "failed to verify mux presence\n"); + + return ret; +} +#endif + +static SIMPLE_DEV_PM_OPS(pca954x_pm, NULL, pca954x_resume); + +static struct i2c_driver pca954x_driver = { + .driver = { + .name = "ctc_pca954x", + .pm = &pca954x_pm, + .of_match_table = pca954x_of_match, + }, + .probe = pca954x_probe, + .remove = pca954x_remove, + .id_table = pca954x_id, +}; + +module_i2c_driver(pca954x_driver); + +MODULE_AUTHOR("Rodolfo Giometti "); +MODULE_DESCRIPTION("PCA954x I2C mux/switch driver"); +MODULE_LICENSE("GPL v2"); diff --git a/platform/centec/sonic-platform-modules-e582/pca954x/ctc-pca954x.h b/platform/centec/sonic-platform-modules-e582/pca954x/ctc-pca954x.h new file mode 100644 index 000000000000..eab9cdd990c9 --- /dev/null +++ b/platform/centec/sonic-platform-modules-e582/pca954x/ctc-pca954x.h @@ -0,0 +1,48 @@ +/* + * + * pca954x.h - I2C multiplexer/switch support + * + * Copyright (c) 2008-2009 Rodolfo Giometti + * Copyright (c) 2008-2009 Eurotech S.p.A. + * Michael Lawnick + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + +#ifndef _LINUX_I2C_PCA954X_H +#define _LINUX_I2C_PCA954X_H + +/* Platform data for the PCA954x I2C multiplexers */ + +/* Per channel initialisation data: + * @adap_id: bus number for the adapter. 0 = don't care + * @deselect_on_exit: set this entry to 1, if your H/W needs deselection + * of this channel after transaction. + * + */ +struct pca954x_platform_mode { + int adap_id; + unsigned int deselect_on_exit:1; + unsigned int class; +}; + +/* Per mux/switch data, used with i2c_register_board_info */ +struct pca954x_platform_data { + struct pca954x_platform_mode *modes; + int num_modes; +}; + +#endif /* _LINUX_I2C_PCA954X_H */ diff --git a/platform/centec/sonic-platform-modules-embedway/debian/control b/platform/centec/sonic-platform-modules-embedway/debian/control index 6fb02a824826..1e51f7bc05c9 100644 --- a/platform/centec/sonic-platform-modules-embedway/debian/control +++ b/platform/centec/sonic-platform-modules-embedway/debian/control @@ -7,6 +7,6 @@ Standards-Version: 3.9.3 Package: platform-modules-embedway-es6220 Architecture: amd64 -Depends: linux-image-4.19.0-12-2-amd64-unsigned +Depends: linux-image-5.10.0-8-2-amd64-unsigned Description: kernel modules for platform devices such as fan, led, sfp diff --git a/scripts/build_debian_base_system.sh b/scripts/build_debian_base_system.sh index 63eb7555fe36..fc3e71290f02 100755 --- a/scripts/build_debian_base_system.sh +++ b/scripts/build_debian_base_system.sh @@ -20,12 +20,16 @@ generate_version_file() if [ "$ENABLE_VERSION_CONTROL_DEB" != "y" ]; then if [[ $CONFIGURED_ARCH == armhf || $CONFIGURED_ARCH == arm64 ]]; then - if [ $MULTIARCH_QEMU_ENVIRON == y ]; then + if [ $MULTIARCH_QEMU_ENVIRON == "y" ]; then # qemu arm bin executable for cross-building sudo mkdir -p $FILESYSTEM_ROOT/usr/bin sudo cp /usr/bin/qemu*static $FILESYSTEM_ROOT/usr/bin || true fi - sudo http_proxy=$HTTP_PROXY SKIP_BUILD_HOOK=y debootstrap --variant=minbase --arch $CONFIGURED_ARCH $IMAGE_DISTRO $FILESYSTEM_ROOT http://deb.debian.org/debian + sudo http_proxy=$HTTP_PROXY SKIP_BUILD_HOOK=y debootstrap --foreign --variant=minbase --arch $CONFIGURED_ARCH $IMAGE_DISTRO $FILESYSTEM_ROOT http://deb.debian.org/debian + sudo rm $FILESYSTEM_ROOT/proc -rf + sudo mkdir $FILESYSTEM_ROOT/proc + sudo mount -t proc proc $FILESYSTEM_ROOT/proc + sudo LANG=C chroot $FILESYSTEM_ROOT /debootstrap/debootstrap --second-stage else sudo http_proxy=$HTTP_PROXY SKIP_BUILD_HOOK=y debootstrap --variant=minbase --arch $CONFIGURED_ARCH $IMAGE_DISTRO $FILESYSTEM_ROOT http://debian-archive.trafficmanager.net/debian fi diff --git a/sonic-slave-bullseye/Dockerfile.j2 b/sonic-slave-bullseye/Dockerfile.j2 index 4abd9c28c4d4..197806f0deb4 100644 --- a/sonic-slave-bullseye/Dockerfile.j2 +++ b/sonic-slave-bullseye/Dockerfile.j2 @@ -3,7 +3,9 @@ FROM multiarch/qemu-user-static:x86_64-arm-5.0.0-2 as qemu FROM multiarch/debian-debootstrap:armhf-bullseye COPY --from=qemu /usr/bin/qemu-arm-static /usr/bin {%- elif CONFIGURED_ARCH == "arm64" and MULTIARCH_QEMU_ENVIRON == "y" %} +FROM multiarch/qemu-user-static:x86_64-aarch64-5.2.0-2 as qemu FROM multiarch/debian-debootstrap:arm64-bullseye +COPY --from=qemu /usr/bin/qemu-aarch64-static /usr/bin {%- else -%} FROM debian:bullseye {%- endif %} @@ -351,6 +353,11 @@ RUN apt-get update && apt-get install -y \ RUN apt-get -y build-dep openssh +# Build fix for ARM64 and ARMHF /etc/debian_version +{%- if CONFIGURED_ARCH == "armhf" or CONFIGURED_ARCH == "arm64" %} +RUN apt upgrade -y base-files +{%- endif %} + # Build fix for ARMHF bullseye libsairedis {%- if CONFIGURED_ARCH == "armhf" %} # Install doxygen build dependency packages