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Add flags for CR0, CR4 and XCR0, as well as extra checks for modification of XCR0 #273
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Note, I intentionally didn't add the following AMD only flags to /// Enables using the CET user state
/// with `XSAVE`/`XRSTOR` (AMD Only).
const CET_U = 1 << 11;
/// Enables using the CET supervisor state
/// with `XSAVE`/`XRSTOR` (AMD Only).
const CET_S = 1 << 12; This is because Intel (as well as AMD weirdly enough) also have these same flags in the |
Why did you want to eliminate the breaking changes? I only ask because I felt that it was a much better solution if our constants aligned with the intel documentation instead of coming up with our own. People would get less confused IMO. But if it truly must not exist, I'm alright with that. |
Alos, add extra checks when writing to XCR0. Signed-off-by: Ethin Probst <[email protected]> Signed-off-by: Joe Richey <[email protected]>
Sorry @ethindp I didn't make myself clear. I absolutely agree with you that some of the existing flag names are bad and should be changed. I just wanted to get most of your changes in as part of
Are there any other flag names that you think should be changed? |
Signed-off-by: Joe Richey <[email protected]>
This avoids getting a #GP when writing. Signed-off-by: Joe Richey <[email protected]>
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I didn't check the new flags against the manuals, but the changes look good to me overall.
#[cfg(docsrs)] | ||
use crate::{registers::rflags::RFlags, structures::paging::PageTableFlags}; |
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What is this about?
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This is needed for the doc comments to properly reference these other structures (like PageTableFlags::GLOBAL
). Without them, the docs don't properly link to the other sections.
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Oh ok. But there imports are then also needed for local doc builds, e.g. on cargo doc --open
. So we should probably use cfg(doc)
instead. I opened #287 for this.
Replacement for #272. @ethindp can you take a look?
My changes
Original PR description
This PR adds some extras to the three control registers
CR0
,CR4
, andXCR0
. It also adds some checks for XCR0. (We could extend this to other registers as well.)Bits added
Checks
This PR adds invariant checks that cannot be disabled via the
assert!
macro when using thewrite()
function on theXCr0
type. Primarily, these invariants enforce those listed on pg. 2-20 of volume 3A of the intel SDMs; they disallow attempts to:I missed the initial invariant (that setting any reserved bits causes a general-protection fault) but I will add that if you guys would like me to (somebody else can do so as well). We should probably consider enforcing all invariants on all control registers to catch problems like this before they arise and generate exceptions, since these APIs are supposed to be "safe". This PR unfortunately has a few breaking changes as well.