From c6e8ae1a6ceeffe343c214859e4eb686b7a71c95 Mon Sep 17 00:00:00 2001 From: Andrew Dona-Couch Date: Wed, 24 Nov 2021 23:04:27 -0500 Subject: [PATCH] Implement inline asm! for AVR platform --- compiler/rustc_codegen_gcc/src/asm.rs | 3 + compiler/rustc_codegen_llvm/src/asm.rs | 21 ++ compiler/rustc_span/src/symbol.rs | 4 + compiler/rustc_target/src/asm/avr.rs | 196 ++++++++++++++++ compiler/rustc_target/src/asm/mod.rs | 25 ++ .../unstable-book/src/library-features/asm.md | 19 +- src/test/assembly/asm/avr-modifiers.rs | 60 +++++ src/test/assembly/asm/avr-types.rs | 222 ++++++++++++++++++ 8 files changed, 549 insertions(+), 1 deletion(-) create mode 100644 compiler/rustc_target/src/asm/avr.rs create mode 100644 src/test/assembly/asm/avr-modifiers.rs create mode 100644 src/test/assembly/asm/avr-types.rs diff --git a/compiler/rustc_codegen_gcc/src/asm.rs b/compiler/rustc_codegen_gcc/src/asm.rs index 6a3b94a0d7018..7481b5db755e7 100644 --- a/compiler/rustc_codegen_gcc/src/asm.rs +++ b/compiler/rustc_codegen_gcc/src/asm.rs @@ -577,6 +577,7 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister { | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => unimplemented!(), InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg) | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => unimplemented!(), + InlineAsmRegClass::Avr(_) => unimplemented!(), InlineAsmRegClass::Bpf(_) => unimplemented!(), InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => unimplemented!(), InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => unimplemented!(), @@ -639,6 +640,7 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => { unimplemented!() } + InlineAsmRegClass::Avr(_) => unimplemented!(), InlineAsmRegClass::Bpf(_) => unimplemented!(), InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(), InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(), @@ -747,6 +749,7 @@ fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => { unimplemented!() } + InlineAsmRegClass::Avr(_) => unimplemented!(), InlineAsmRegClass::Bpf(_) => unimplemented!(), InlineAsmRegClass::Hexagon(_) => unimplemented!(), InlineAsmRegClass::Mips(_) => unimplemented!(), diff --git a/compiler/rustc_codegen_llvm/src/asm.rs b/compiler/rustc_codegen_llvm/src/asm.rs index 83c5cb6f1cf51..90d3c0fb2f173 100644 --- a/compiler/rustc_codegen_llvm/src/asm.rs +++ b/compiler/rustc_codegen_llvm/src/asm.rs @@ -319,6 +319,9 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> { "~{vxrm}".to_string(), ]); } + InlineAsmArch::Avr => { + constraints.push("~{sreg}".to_string()); + } InlineAsmArch::Nvptx64 => {} InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => {} InlineAsmArch::Hexagon => {} @@ -669,6 +672,11 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>) InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => "r", InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => "r", InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => "w", + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg) => "r", + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper) => "d", + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair) => "r", + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw) => "w", + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr) => "e", InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg) => "r", InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg) => "f", InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => { @@ -749,6 +757,14 @@ fn modifier_to_llvm( } InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => None, InlineAsmRegClass::Bpf(_) => None, + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair) + | InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw) + | InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr) => match modifier { + Some('h') => Some('B'), + Some('l') => Some('A'), + _ => None, + }, + InlineAsmRegClass::Avr(_) => None, InlineAsmRegClass::S390x(_) => None, InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => { bug!("LLVM backend does not support SPIR-V") @@ -812,6 +828,11 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => cx.type_i32(), InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => cx.type_i64(), InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => cx.type_i32(), + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg) => cx.type_i8(), + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper) => cx.type_i8(), + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair) => cx.type_i16(), + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw) => cx.type_i16(), + InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr) => cx.type_i16(), InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg) => cx.type_i32(), InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg) => cx.type_f64(), InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => { diff --git a/compiler/rustc_span/src/symbol.rs b/compiler/rustc_span/src/symbol.rs index 309c305293fd6..e5a30c1da80a9 100644 --- a/compiler/rustc_span/src/symbol.rs +++ b/compiler/rustc_span/src/symbol.rs @@ -1052,8 +1052,12 @@ symbols! { reg64, reg_abcd, reg_byte, + reg_iw, reg_nonzero, + reg_pair, + reg_ptr, reg_thumb, + reg_upper, register_attr, register_tool, relaxed_adts, diff --git a/compiler/rustc_target/src/asm/avr.rs b/compiler/rustc_target/src/asm/avr.rs new file mode 100644 index 0000000000000..82a4f8bacb3fa --- /dev/null +++ b/compiler/rustc_target/src/asm/avr.rs @@ -0,0 +1,196 @@ +use super::{InlineAsmArch, InlineAsmType}; +use rustc_macros::HashStable_Generic; +use std::fmt; + +def_reg_class! { + Avr AvrInlineAsmRegClass { + reg, + reg_upper, + reg_pair, + reg_iw, + reg_ptr, + } +} + +impl AvrInlineAsmRegClass { + pub fn valid_modifiers(self, _arch: InlineAsmArch) -> &'static [char] { + match self { + Self::reg_pair | Self::reg_iw | Self::reg_ptr => &['h', 'l'], + _ => &[], + } + } + + pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option { + None + } + + pub fn suggest_modifier( + self, + _arch: InlineAsmArch, + _ty: InlineAsmType, + ) -> Option<(char, &'static str)> { + None + } + + pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> { + None + } + + pub fn supported_types( + self, + _arch: InlineAsmArch, + ) -> &'static [(InlineAsmType, Option<&'static str>)] { + match self { + Self::reg => types! { _: I8; }, + Self::reg_upper => types! { _: I8; }, + Self::reg_pair => types! { _: I16; }, + Self::reg_iw => types! { _: I16; }, + Self::reg_ptr => types! { _: I16; }, + } + } +} + +def_regs! { + Avr AvrInlineAsmReg AvrInlineAsmRegClass { + r2: reg = ["r2"], + r3: reg = ["r3"], + r4: reg = ["r4"], + r5: reg = ["r5"], + r6: reg = ["r6"], + r7: reg = ["r7"], + r8: reg = ["r8"], + r9: reg = ["r9"], + r10: reg = ["r10"], + r11: reg = ["r11"], + r12: reg = ["r12"], + r13: reg = ["r13"], + r14: reg = ["r14"], + r15: reg = ["r15"], + r16: reg, reg_upper = ["r16"], + r17: reg, reg_upper = ["r17"], + r18: reg, reg_upper = ["r18"], + r19: reg, reg_upper = ["r19"], + r20: reg, reg_upper = ["r20"], + r21: reg, reg_upper = ["r21"], + r22: reg, reg_upper = ["r22"], + r23: reg, reg_upper = ["r23"], + r24: reg, reg_upper = ["r24"], + r25: reg, reg_upper = ["r25"], + r26: reg, reg_upper = ["r26", "XL"], + r27: reg, reg_upper = ["r27", "XH"], + r30: reg, reg_upper = ["r30", "ZL"], + r31: reg, reg_upper = ["r31", "ZH"], + + r3r2: reg_pair = ["r3r2"], + r5r4: reg_pair = ["r5r4"], + r7r6: reg_pair = ["r7r6"], + r9r8: reg_pair = ["r9r8"], + r11r10: reg_pair = ["r11r10"], + r13r12: reg_pair = ["r13r12"], + r15r14: reg_pair = ["r15r14"], + r17r16: reg_pair = ["r17r16"], + r19r18: reg_pair = ["r19r18"], + r21r20: reg_pair = ["r21r20"], + r23r22: reg_pair = ["r23r22"], + + r25r24: reg_iw, reg_pair = ["r25r24"], + + X: reg_ptr, reg_iw, reg_pair = ["r27r26", "X"], + Z: reg_ptr, reg_iw, reg_pair = ["r31r30", "Z"], + + #error = ["Y", "YL", "YH"] => + "the frame pointer cannot be used as an operand for inline asm", + #error = ["SP", "SPL", "SPH"] => + "the stack pointer cannot be used as an operand for inline asm", + #error = ["r0", "r1", "r1r0"] => + "r0 and r1 are not available due to an issue in LLVM", + } +} + +macro_rules! emit_pairs { + ( + $self:ident $modifier:ident, + $($pair:ident $name:literal $hi:literal $lo:literal,)* + ) => { + match ($self, $modifier) { + $( + (AvrInlineAsmReg::$pair, Some('h')) => $hi, + (AvrInlineAsmReg::$pair, Some('l')) => $lo, + (AvrInlineAsmReg::$pair, _) => $name, + )* + _ => $self.name(), + } + }; +} + +impl AvrInlineAsmReg { + pub fn emit( + self, + out: &mut dyn fmt::Write, + _arch: InlineAsmArch, + modifier: Option, + ) -> fmt::Result { + let name = emit_pairs! { + self modifier, + Z "Z" "ZH" "ZL", + X "X" "XH" "XL", + r25r24 "r25:r24" "r25" "r24", + r23r22 "r23:r22" "r23" "r22", + r21r20 "r21:r20" "r21" "r20", + r19r18 "r19:r18" "r19" "r18", + r17r16 "r17:r16" "r17" "r16", + r15r14 "r15:r14" "r15" "r14", + r13r12 "r13:r12" "r13" "r12", + r11r10 "r11:r10" "r11" "r10", + r9r8 "r9:r8" "r9" "r8", + r7r6 "r7:r6" "r7" "r6", + r5r4 "r5:r4" "r5" "r4", + r3r2 "r3:r2" "r3" "r2", + }; + out.write_str(name) + } + + pub fn overlapping_regs(self, mut cb: impl FnMut(AvrInlineAsmReg)) { + cb(self); + + macro_rules! reg_conflicts { + ( + $( + $pair:ident : $hi:ident $lo:ident, + )* + ) => { + match self { + $( + Self::$pair => { + cb(Self::$hi); + cb(Self::$lo); + } + Self::$hi => { + cb(Self::$pair); + } + Self::$lo => { + cb(Self::$pair); + } + )* + } + }; + } + + reg_conflicts! { + Z : r31 r30, + X : r27 r26, + r25r24 : r25 r24, + r23r22 : r23 r22, + r21r20 : r21 r20, + r19r18 : r19 r18, + r17r16 : r17 r16, + r15r14 : r15 r14, + r13r12 : r13 r12, + r11r10 : r11 r10, + r9r8 : r9 r8, + r7r6 : r7 r6, + r5r4 : r5 r4, + r3r2 : r3 r2, + } + } +} diff --git a/compiler/rustc_target/src/asm/mod.rs b/compiler/rustc_target/src/asm/mod.rs index bff132465215e..cf940594bc459 100644 --- a/compiler/rustc_target/src/asm/mod.rs +++ b/compiler/rustc_target/src/asm/mod.rs @@ -148,6 +148,7 @@ macro_rules! types { mod aarch64; mod arm; +mod avr; mod bpf; mod hexagon; mod mips; @@ -161,6 +162,7 @@ mod x86; pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass}; pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass}; +pub use avr::{AvrInlineAsmReg, AvrInlineAsmRegClass}; pub use bpf::{BpfInlineAsmReg, BpfInlineAsmRegClass}; pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass}; pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass}; @@ -191,6 +193,7 @@ pub enum InlineAsmArch { Wasm32, Wasm64, Bpf, + Avr, } impl FromStr for InlineAsmArch { @@ -215,6 +218,7 @@ impl FromStr for InlineAsmArch { "wasm32" => Ok(Self::Wasm32), "wasm64" => Ok(Self::Wasm64), "bpf" => Ok(Self::Bpf), + "avr" => Ok(Self::Avr), _ => Err(()), } } @@ -245,6 +249,7 @@ pub enum InlineAsmReg { SpirV(SpirVInlineAsmReg), Wasm(WasmInlineAsmReg), Bpf(BpfInlineAsmReg), + Avr(AvrInlineAsmReg), // Placeholder for invalid register constraints for the current target Err, } @@ -261,6 +266,7 @@ impl InlineAsmReg { Self::Mips(r) => r.name(), Self::S390x(r) => r.name(), Self::Bpf(r) => r.name(), + Self::Avr(r) => r.name(), Self::Err => "", } } @@ -276,6 +282,7 @@ impl InlineAsmReg { Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()), Self::S390x(r) => InlineAsmRegClass::S390x(r.reg_class()), Self::Bpf(r) => InlineAsmRegClass::Bpf(r.reg_class()), + Self::Avr(r) => InlineAsmRegClass::Avr(r.reg_class()), Self::Err => InlineAsmRegClass::Err, } } @@ -326,6 +333,9 @@ impl InlineAsmReg { InlineAsmArch::Bpf => { Self::Bpf(BpfInlineAsmReg::parse(arch, has_feature, target, &name)?) } + InlineAsmArch::Avr => { + Self::Avr(AvrInlineAsmReg::parse(arch, has_feature, target, &name)?) + } }) } @@ -347,6 +357,7 @@ impl InlineAsmReg { Self::Mips(r) => r.emit(out, arch, modifier), Self::S390x(r) => r.emit(out, arch, modifier), Self::Bpf(r) => r.emit(out, arch, modifier), + Self::Avr(r) => r.emit(out, arch, modifier), Self::Err => unreachable!("Use of InlineAsmReg::Err"), } } @@ -362,6 +373,7 @@ impl InlineAsmReg { Self::Mips(_) => cb(self), Self::S390x(_) => cb(self), Self::Bpf(r) => r.overlapping_regs(|r| cb(Self::Bpf(r))), + Self::Avr(r) => r.overlapping_regs(|r| cb(Self::Avr(r))), Self::Err => unreachable!("Use of InlineAsmReg::Err"), } } @@ -392,6 +404,7 @@ pub enum InlineAsmRegClass { SpirV(SpirVInlineAsmRegClass), Wasm(WasmInlineAsmRegClass), Bpf(BpfInlineAsmRegClass), + Avr(AvrInlineAsmRegClass), // Placeholder for invalid register constraints for the current target Err, } @@ -411,6 +424,7 @@ impl InlineAsmRegClass { Self::SpirV(r) => r.name(), Self::Wasm(r) => r.name(), Self::Bpf(r) => r.name(), + Self::Avr(r) => r.name(), Self::Err => rustc_span::symbol::sym::reg, } } @@ -432,6 +446,7 @@ impl InlineAsmRegClass { Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV), Self::Wasm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Wasm), Self::Bpf(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Bpf), + Self::Avr(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Avr), Self::Err => unreachable!("Use of InlineAsmRegClass::Err"), } } @@ -460,6 +475,7 @@ impl InlineAsmRegClass { Self::SpirV(r) => r.suggest_modifier(arch, ty), Self::Wasm(r) => r.suggest_modifier(arch, ty), Self::Bpf(r) => r.suggest_modifier(arch, ty), + Self::Avr(r) => r.suggest_modifier(arch, ty), Self::Err => unreachable!("Use of InlineAsmRegClass::Err"), } } @@ -484,6 +500,7 @@ impl InlineAsmRegClass { Self::SpirV(r) => r.default_modifier(arch), Self::Wasm(r) => r.default_modifier(arch), Self::Bpf(r) => r.default_modifier(arch), + Self::Avr(r) => r.default_modifier(arch), Self::Err => unreachable!("Use of InlineAsmRegClass::Err"), } } @@ -507,6 +524,7 @@ impl InlineAsmRegClass { Self::SpirV(r) => r.supported_types(arch), Self::Wasm(r) => r.supported_types(arch), Self::Bpf(r) => r.supported_types(arch), + Self::Avr(r) => r.supported_types(arch), Self::Err => unreachable!("Use of InlineAsmRegClass::Err"), } } @@ -535,6 +553,7 @@ impl InlineAsmRegClass { Self::Wasm(WasmInlineAsmRegClass::parse(arch, name)?) } InlineAsmArch::Bpf => Self::Bpf(BpfInlineAsmRegClass::parse(arch, name)?), + InlineAsmArch::Avr => Self::Avr(AvrInlineAsmRegClass::parse(arch, name)?), }) } @@ -554,6 +573,7 @@ impl InlineAsmRegClass { Self::SpirV(r) => r.valid_modifiers(arch), Self::Wasm(r) => r.valid_modifiers(arch), Self::Bpf(r) => r.valid_modifiers(arch), + Self::Avr(r) => r.valid_modifiers(arch), Self::Err => unreachable!("Use of InlineAsmRegClass::Err"), } } @@ -739,6 +759,11 @@ pub fn allocatable_registers( bpf::fill_reg_map(arch, has_feature, target, &mut map); map } + InlineAsmArch::Avr => { + let mut map = avr::regclass_map(); + avr::fill_reg_map(arch, has_feature, target, &mut map); + map + } } } diff --git a/src/doc/unstable-book/src/library-features/asm.md b/src/doc/unstable-book/src/library-features/asm.md index fa238a8b3bc65..dffa3a8b80f0f 100644 --- a/src/doc/unstable-book/src/library-features/asm.md +++ b/src/doc/unstable-book/src/library-features/asm.md @@ -32,6 +32,7 @@ Inline assembly is currently supported on the following architectures: - wasm32 - BPF - SPIR-V +- AVR ## Basic usage @@ -471,6 +472,7 @@ Inline assembly is currently supported on the following architectures: - wasm32 - BPF - SPIR-V +- AVR Support for more targets may be added in the future. The compiler will emit an error if `asm!` is used on an unsupported target. @@ -593,6 +595,11 @@ Here is the list of currently supported register classes: | wasm32 | `local` | None\* | `r` | | BPF | `reg` | `r[0-10]` | `r` | | BPF | `wreg` | `w[0-10]` | `w` | +| AVR | `reg` | `r[2-25]`, `XH`, `XL`, `ZH`, `ZL` | `r` | +| AVR | `reg_upper` | `r[16-25]`, `XH`, `XL`, `ZH`, `ZL` | `d` | +| AVR | `reg_pair` | `r3r2` .. `r25r24`, `X`, `Z` | `r` | +| AVR | `reg_iw` | `r25r24`, `X`, `Z` | `w` | +| AVR | `reg_ptr` | `X`, `Z` | `e` | > **Note**: On x86 we treat `reg_byte` differently from `reg` because the compiler can allocate `al` and `ah` separately whereas `reg` reserves the whole register. > @@ -648,6 +655,8 @@ Each register class has constraints on which value types they can be used with. | wasm32 | `local` | None | `i8` `i16` `i32` `i64` `f32` `f64` | | BPF | `reg` | None | `i8` `i16` `i32` `i64` | | BPF | `wreg` | `alu32` | `i8` `i16` `i32` | +| AVR | `reg`, `reg_upper` | None | `i8` | +| AVR | `reg_pair`, `reg_iw`, `reg_ptr` | None | `i16` | > **Note**: For the purposes of the above table pointers, function pointers and `isize`/`usize` are treated as the equivalent integer type (`i16`/`i32`/`i64` depending on the target). @@ -708,13 +717,17 @@ Some registers have multiple names. These are all treated by the compiler as ide | Hexagon | `r30` | `fr` | | Hexagon | `r31` | `lr` | | BPF | `r[0-10]` | `w[0-10]` | +| AVR | `XH` | `r27` | +| AVR | `XL` | `r26` | +| AVR | `ZH` | `r31` | +| AVR | `ZL` | `r30` | Some registers cannot be used for input or output operands: | Architecture | Unsupported register | Reason | | ------------ | -------------------- | ------ | | All | `sp` | The stack pointer must be restored to its original value at the end of an asm code block. | -| All | `bp` (x86), `x29` (AArch64), `x8` (RISC-V), `fr` (Hexagon), `$fp` (MIPS) | The frame pointer cannot be used as an input or output. | +| All | `bp` (x86), `x29` (AArch64), `x8` (RISC-V), `fr` (Hexagon), `$fp` (MIPS), `Y` (AVR) | The frame pointer cannot be used as an input or output. | | ARM | `r7` or `r11` | On ARM the frame pointer can be either `r7` or `r11` depending on the target. The frame pointer cannot be used as an input or output. | | All | `si` (x86-32), `bx` (x86-64), `r6` (ARM), `x19` (AArch64), `r19` (Hexagon), `x9` (RISC-V) | This is used internally by LLVM as a "base pointer" for functions with complex stack frames. | | x86 | `k0` | This is a constant zero register which can't be modified. | @@ -732,11 +745,13 @@ Some registers cannot be used for input or output operands: | RISC-V | `x0` | This is a constant zero register which can't be modified. | | RISC-V | `gp`, `tp` | These registers are reserved and cannot be used as inputs or outputs. | | Hexagon | `lr` | This is the link register which cannot be used as an input or output. | +| AVR | `r0`, `r1`, `r1r0` | Due to an issue in LLVM, the `r0` and `r1` registers cannot be used as inputs or outputs. If modified, they must be restored to their original values before the end of the block. | In some cases LLVM will allocate a "reserved register" for `reg` operands even though this register cannot be explicitly specified. Assembly code making use of reserved registers should be careful since `reg` operands may alias with those registers. Reserved registers are the frame pointer and base pointer - The frame pointer and LLVM base pointer on all architectures. - `r9` on ARM. - `x18` on AArch64. +- `r0` and `r1` on AVR. ## Template modifiers @@ -882,6 +897,8 @@ The compiler performs some additional checks on options: - RISC-V - Floating-point exception flags in `fcsr` (`fflags`). - Vector extension state (`vtype`, `vl`, `vcsr`). + - AVR + - The status register `SREG`. - On x86, the direction flag (DF in `EFLAGS`) is clear on entry to an asm block and must be clear on exit. - Behavior is undefined if the direction flag is set on exiting an asm block. - The requirement of restoring the stack pointer and non-output registers to their original value only applies when exiting an `asm!` block. diff --git a/src/test/assembly/asm/avr-modifiers.rs b/src/test/assembly/asm/avr-modifiers.rs new file mode 100644 index 0000000000000..aba4c982c7305 --- /dev/null +++ b/src/test/assembly/asm/avr-modifiers.rs @@ -0,0 +1,60 @@ +// min-llvm-version: 13.0 +// assembly-output: emit-asm +// compile-flags: --target avr-unknown-gnu-atmega328 +// needs-llvm-components: avr + +#![feature(no_core, lang_items, rustc_attrs, asm_experimental_arch)] +#![crate_type = "rlib"] +#![no_core] +#![allow(non_camel_case_types)] + +#[rustc_builtin_macro] +macro_rules! asm { + () => {}; +} +#[rustc_builtin_macro] +macro_rules! concat { + () => {}; +} + +#[lang = "sized"] +trait Sized {} +#[lang = "copy"] +trait Copy {} + +type ptr = *const u64; + +impl Copy for i8 {} +impl Copy for i16 {} +impl Copy for i32 {} +impl Copy for i64 {} +impl Copy for ptr {} + +macro_rules! check { + ($func:ident $hi:literal $lo:literal $reg:tt) => { + #[no_mangle] + unsafe fn $func() -> i16 { + let y; + asm!(concat!("mov {0:", $hi, "}, {0:", $lo, "}"), out($reg) y); + y + } + }; +} + +// CHECK-LABEL: reg_pair_modifiers: +// CHECK: ;APP +// CHECK: mov r{{[1-9]?[13579]}}, r{{[1-9]?[24680]}} +// CHECK: ;NO_APP +check!(reg_pair_modifiers "h" "l" reg_pair); + +// CHECK-LABEL: reg_iw_modifiers: +// CHECK: ;APP +// CHECK: mov r{{[1-9]?[13579]}}, r{{[1-9]?[24680]}} +// CHECK: ;NO_APP +check!(reg_iw_modifiers "h" "l" reg_iw); + +// CHECK-LABEL: reg_ptr_modifiers: +// CHECK: ;APP +// CHECK: mov r{{[1-9]?[13579]}}, r{{[1-9]?[24680]}} +// CHECK: ;NO_APP +check!(reg_ptr_modifiers "h" "l" reg_ptr); diff --git a/src/test/assembly/asm/avr-types.rs b/src/test/assembly/asm/avr-types.rs new file mode 100644 index 0000000000000..53a601e51c8bf --- /dev/null +++ b/src/test/assembly/asm/avr-types.rs @@ -0,0 +1,222 @@ +// min-llvm-version: 13.0 +// assembly-output: emit-asm +// compile-flags: --target avr-unknown-gnu-atmega328 +// needs-llvm-components: avr + +#![feature(no_core, lang_items, rustc_attrs, asm_sym, asm_experimental_arch)] +#![crate_type = "rlib"] +#![no_core] +#![allow(non_camel_case_types)] + +#[rustc_builtin_macro] +macro_rules! asm { + () => {}; +} +#[rustc_builtin_macro] +macro_rules! concat { + () => {}; +} + +#[lang = "sized"] +trait Sized {} +#[lang = "copy"] +trait Copy {} + +type ptr = *const u64; + +impl Copy for i8 {} +impl Copy for i16 {} +impl Copy for i32 {} +impl Copy for i64 {} +impl Copy for ptr {} + +macro_rules! check { + ($func:ident $ty:ident $class:ident) => { + #[no_mangle] + pub unsafe fn $func(x: $ty) -> $ty { + let y; + asm!("mov {}, {}", lateout($class) y, in($class) x); + y + } + }; +} + +macro_rules! checkw { + ($func:ident $ty:ident $class:ident) => { + #[no_mangle] + pub unsafe fn $func(x: $ty) -> $ty { + let y; + asm!("movw {}, {}", lateout($class) y, in($class) x); + y + } + }; +} + +macro_rules! check_reg { + ($func:ident $ty:ident $reg:tt) => { + #[no_mangle] + pub unsafe fn $func(x: $ty) -> $ty { + let y; + asm!(concat!("mov ", $reg, ", ", $reg), lateout($reg) y, in($reg) x); + y + } + }; +} + +macro_rules! check_regw { + ($func:ident $ty:ident $reg:tt $reg_lit:tt) => { + #[no_mangle] + pub unsafe fn $func(x: $ty) -> $ty { + let y; + asm!(concat!("movw ", $reg_lit, ", ", $reg_lit), lateout($reg) y, in($reg) x); + y + } + }; +} + +extern "C" { + fn extern_func(); + static extern_static: i8; +} + +// CHECK-LABEL: sym_fn +// CHECK: ;APP +// CHECK: call extern_func +// CHECK: ;NO_APP +#[no_mangle] +pub unsafe fn sym_fn() { + asm!("call {}", sym extern_func); +} + +// CHECK-LABEL: sym_static +// CHECK: ;APP +// CHECK: lds r{{[0-9]+}}, extern_static +// CHECK: ;NO_APP +#[no_mangle] +pub unsafe fn sym_static() -> i8 { + let y; + asm!("lds {}, {}", lateout(reg) y, sym extern_static); + y +} + +// CHECK-LABEL: ld_z: +// CHECK: ;APP +// CHECK: ld r{{[0-9]+}}, Z +// CHECK: ;NO_APP +#[no_mangle] +pub unsafe fn ld_z(x: i16) -> i8 { + let y; + asm!("ld {}, Z", out(reg) y, in("Z") x); + y +} + +// CHECK-LABEL: ldd_z: +// CHECK: ;APP +// CHECK: ldd r{{[0-9]+}}, Z+4 +// CHECK: ;NO_APP +#[no_mangle] +pub unsafe fn ldd_z(x: i16) -> i8 { + let y; + asm!("ldd {}, Z+4", out(reg) y, in("Z") x); + y +} + +// CHECK-LABEL: ld_predecrement: +// CHECK: ;APP +// CHECK: ld r{{[0-9]+}}, -Z +// CHECK: ;NO_APP +#[no_mangle] +pub unsafe fn ld_predecrement(x: i16) -> i8 { + let y; + asm!("ld {}, -Z", out(reg) y, in("Z") x); + y +} + +// CHECK-LABEL: ld_postincrement: +// CHECK: ;APP +// CHECK: ld r{{[0-9]+}}, Z+ +// CHECK: ;NO_APP +#[no_mangle] +pub unsafe fn ld_postincrement(x: i16) -> i8 { + let y; + asm!("ld {}, Z+", out(reg) y, in("Z") x); + y +} + +// CHECK-LABEL: muls_clobber: +// CHECK: ;APP +// CHECK: muls r{{[0-9]+}}, r{{[0-9]+}} +// CHECK: movw r{{[0-9]+}}, r0 +// CHECK: ;NO_APP +#[no_mangle] +pub unsafe fn muls_clobber(x: i8, y: i8) -> i16 { + let z; + asm!( + "muls {}, {}", + "movw {}, r1:r0", + out(reg_iw) z, + in(reg) x, + in(reg) y, + ); + z +} + +// CHECK-LABEL: reg_i8: +// CHECK: ;APP +// CHECK: mov r{{[0-9]+}}, r{{[0-9]+}} +// CHECK: ;NO_APP +check!(reg_i8 i8 reg); + +// CHECK-LABEL: reg_upper_i8: +// CHECK: ;APP +// CHECK: mov r{{[1-3][0-9]}}, r{{[1-3][0-9]}} +// CHECK: ;NO_APP +check!(reg_upper_i8 i8 reg_upper); + +// CHECK-LABEL: reg_pair_i16: +// CHECK: ;APP +// CHECK: movw r{{[0-9]+}}, r{{[0-9]+}} +// CHECK: ;NO_APP +checkw!(reg_pair_i16 i16 reg_pair); + +// CHECK-LABEL: reg_iw_i16: +// CHECK: ;APP +// CHECK: movw r{{[0-9]+}}, r{{[0-9]+}} +// CHECK: ;NO_APP +checkw!(reg_iw_i16 i16 reg_iw); + +// CHECK-LABEL: reg_ptr_i16: +// CHECK: ;APP +// CHECK: movw r{{[0-9]+}}, r{{[0-9]+}} +// CHECK: ;NO_APP +checkw!(reg_ptr_i16 i16 reg_ptr); + +// CHECK-LABEL: r2_i8: +// CHECK: ;APP +// CHECK: mov r2, r2 +// CHECK: ;NO_APP +check_reg!(r2_i8 i8 "r2"); + +// CHECK-LABEL: xl_i8: +// CHECK: ;APP +// CHECK: mov r26, r26 +// CHECK: ;NO_APP +check_reg!(xl_i8 i8 "XL"); + +// CHECK-LABEL: xh_i8: +// CHECK: ;APP +// CHECK: mov r27, r27 +// CHECK: ;NO_APP +check_reg!(xh_i8 i8 "XH"); + +// CHECK-LABEL: x_i16: +// CHECK: ;APP +// CHECK: movw r26, r26 +// CHECK: ;NO_APP +check_regw!(x_i16 i16 "X" "X"); + +// CHECK-LABEL: r25r24_i16: +// CHECK: ;APP +// CHECK: movw r24, r24 +// CHECK: ;NO_APP +check_regw!(r25r24_i16 i16 "r25r24" "r24");