Is generated atomic register access correct?

[9names]

svd2rust can generate atomic register operations by using the --atomics flag
https://docs.rs/svd2rust/latest/svd2rust/#the---atomics-flag
It generates code that looks like this:
https://github.com/ra-rs/ra/blob/main/pac/ra4m1/src/generic/atomic.rs

I'm not certain that these will act as intended, as atomic operations are not required to be volatile.
In particular, it's not clear that doing two of these operations back-to-back will not be optimised by the compiler and reduced to a single operation instead.

The discussions around volatile atomic access have not been resolved yet as far as I know:
https://rust-lang.zulipchat.com/#narrow/stream/136281-t-opsem/topic/volatile.20atomic.20in.20Rust.3F
https://internals.rust-lang.org/t/pre-pre-rfc-exploring-api-design-space-for-volatile-atomics/19989

[9names]

Also, as far as I am aware on cortex-m and for riscv it's implementation defined whether atomic access to peripheral registers is supported or not, but vendors do not always disclose this information.
At least on riscv this should trigger an exception, not sure what happens on cortex-m if it's not supported...