Overview:

This repository contains llvm passes which selectively introduce dynamic scheduling into SYCL HLS code. The passes are developed out-of-tree, and intended to be loaded as a .so by the llvm opt tool.

---

Build:

Pre-requisites:

• CMake >=3.16
• ninja (https://github.com/ninja-build/ninja)
• Intel llvm sycl branch built from source
• Intel SYCL compiler (the driver is invoked with icpx -fsycl). The version used in this project is 2023.1.0. To install it on Ubuntu: sudo apt install intel-basekit-2023.1.0
• The basekit allows only emulation. If you want to run simulation, you have to install Quartus Prime Pro and a some simulator, e.g. Questa FPGA Starter Edition (which is free).
• To run in hardware, you can sign up to the Intel DevCloud to access Arria 10 and Stratix 10 FPGAs (https://www.intel.com/content/www/us/en/developer/tools/devcloud/overview.html).

Build the intel llvm sycl branch from source:

# The assumed location is ~/git
git clone https://github.com/intel/llvm.git && cd llvm
# The LLVM version should match the version used to build the SYCL compiler: e.g. for intel-basekit-2023.1.0 the LLVM intel/sycl commit hash is 756ba26161
git checkout 756ba26161
python buildbot/configure.py --llvm-external-projects=clang-tools-extra && python buildbot/compile.py
cd build && ninja 

Build the passes in this repo:

mkdir -p build && cd build
# Add to your environment variables:
export LT_LLVM_INSTALL_DIR=$HOME/git/llvm/build
export LLVM_SYCL_PASSES_DIR=$HOME/git/llvm-sycl-passes 
cmake ..
make -j

Setup SYCL HLS compilation scripts: The SYCL compiler is multi-pass -- it consists of multiple sub-commands to build a host and device binary. To run the LLVM passes from this repo, we need to break up the driver into constituent commands such that we can run our passes on the kernel code and compile the transformed LLVM IR code into the final binary. The genCompileScripts.py runs the dpcpp driver in verbose mode and generates generic compile_to_bc.sh and compile_from_bc.sh scripts which automate this process.

# By defeault all targets are generated. Use --targets=emu,sim,hw to exclude unwanted targets.
# By defeault a full hw and sim compile is NOT done. Rather, the linking commands are autogenerated based on previous commands from the dpcpp driver. If this fails, add the --slow flag to run a full compilation.
$LLVM_SYCL_PASSES_DIR/scripts/compilation/scripts/gen_compile_scripts.py`

---

Run transformations (LSQ or CDDD):

driverLSQ.sh emu|sim|hw file [2|4|8|16|...] [-d]

driverCDDD.sh emu|sim|hw file [-d]