From a3fc7b9336c6a00c73250fc4cc92eab91c6e27a7 Mon Sep 17 00:00:00 2001 From: "River.Li" Date: Wed, 13 Sep 2023 18:27:03 +0800 Subject: [PATCH] Remove unnecessary convert in init_edge --- src/plugins/intel_cpu/src/graph.cpp | 54 +---------------------------- 1 file changed, 1 insertion(+), 53 deletions(-) diff --git a/src/plugins/intel_cpu/src/graph.cpp b/src/plugins/intel_cpu/src/graph.cpp index aa8acb24267c42..4f54dc8dc56ccc 100644 --- a/src/plugins/intel_cpu/src/graph.cpp +++ b/src/plugins/intel_cpu/src/graph.cpp @@ -535,33 +535,6 @@ void Graph::CreatePrimitivesAndExecConstants() const { } } -static bool isReorderAvailable(const MemoryDescPtr& parentDesc, const MemoryDescPtr& childDesc, const dnnl::engine& eng) { - auto definedParentDesc = parentDesc->isDefined() ? parentDesc : MemoryDescUtils::makeDummyDesc(*parentDesc); - memory::desc srcMemDesc = MemoryDescUtils::convertToDnnlMemoryDesc(definedParentDesc)->getDnnlDesc(); - - auto definedChildDesc = childDesc->isDefined() ? childDesc : MemoryDescUtils::makeDummyDesc(*childDesc); - memory::desc dstMemDesc = MemoryDescUtils::convertToDnnlMemoryDesc(definedChildDesc)->getDnnlDesc(); - - dnnl::primitive_attr attr; - - dnnl_primitive_desc_t result = nullptr; - auto status = dnnl_reorder_primitive_desc_create(&result, srcMemDesc.get(), eng.get(), dstMemDesc.get(), eng.get(), - attr.get()); -#if defined(OV_CPU_ARM_ENABLE_FP16) - // temporary WA for slow FP32->FP16 conversion reorder in oneDNN on ARM - // pretend the reorder is not available to use Convert node instead - if (result && parse_impl_name(result->impl()->name()) == ref_any) { - dnnl_primitive_desc_destroy(result); - return false; - } -#endif - if (result) { - dnnl_primitive_desc_destroy(result); - } - - return dnnl_success == status; -} - void Graph::InitEdges() { OV_ITT_SCOPE(FIRST_INFERENCE, itt::domains::intel_cpu_LT, "Graph::InitEdges"); @@ -599,32 +572,7 @@ void Graph::InitEdges() { auto reorderStatus = graphEdges[i]->needReorder(); DEBUG_LOG(graphEdges[i]->name(), " reorderStatus = ", reorderStatus); if (reorderStatus == Edge::ReorderStatus::Regular) { - Edge::ReorderStatus reorderStatusInternal = Edge::ReorderStatus::Regular; - // Check if there is a reorder that needs the precision conversion - if (edge->getInputDesc().getPrecision() != edge->getOutputDesc().getPrecision() && - !isReorderAvailable(edge->getInputPortDesc()->getMemDesc(), - edge->getOutputPortDesc()->getMemDesc(), - this->getEngine())) { - // If we are here, then we need to insert Convert, because there are no reorders that support such type conversion - const auto& inDesc = edge->getInputDesc(); - const auto& outDesc = edge->getOutputDesc(); - - std::string convertName = edge->getParent()->getName() + "_" + - inDesc.getPrecision().name() + "_" + outDesc.getPrecision().name(); - - auto convertNode = std::make_shared(inDesc.getShape(), inDesc.getPrecision(), outDesc.getPrecision(), - convertName, context); - convertNode->setDescs(inDesc, outDesc); - InsertNode(edge, convertNode, true); - - //Check if reorder is still needed - reorderStatusInternal = convertNode->getChildEdgeAt(0)->needReorder(); - if (reorderStatusInternal != Edge::ReorderStatus::No) - edge = convertNode->getChildEdgeAt(0); - } - if (reorderStatusInternal != Edge::ReorderStatus::No) { - insertReorder(edge, reorderStatusInternal == Edge::ReorderStatus::Optimized); - } + insertReorder(edge, false); updateEdge(i); } else if (reorderStatus == Edge::ReorderStatus::Optimized) { insertReorder(edge, true);