From 3cc4afdb712638ffee307eeb672047f91597386e Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Mon, 3 Dec 2018 16:37:02 -0800 Subject: [PATCH] Second version of gdb stub support, using new FSF GDB xml files. --- configure | 4 +- gdb-xml/riscv-32bit-cpu.xml | 43 +++++ gdb-xml/riscv-32bit-csr.xml | 250 +++++++++++++++++++++++++++++ gdb-xml/riscv-32bit-fpu.xml | 46 ++++++ gdb-xml/riscv-64bit-cpu.xml | 43 +++++ gdb-xml/riscv-64bit-csr.xml | 250 +++++++++++++++++++++++++++++ gdb-xml/riscv-64bit-fpu.xml | 52 +++++++ gdb-xml/riscv-cpu.xml | 43 ----- gdb-xml/riscv-csr.xml | 11 -- gdb-xml/riscv-fpu.xml | 43 ----- target/riscv/cpu.c | 6 +- target/riscv/cpu_bits.h | 35 ++++- target/riscv/gdbstub.c | 302 +++++++++++++++++++++++++++++++++++- 13 files changed, 1022 insertions(+), 106 deletions(-) create mode 100644 gdb-xml/riscv-32bit-cpu.xml create mode 100644 gdb-xml/riscv-32bit-csr.xml create mode 100644 gdb-xml/riscv-32bit-fpu.xml create mode 100644 gdb-xml/riscv-64bit-cpu.xml create mode 100644 gdb-xml/riscv-64bit-csr.xml create mode 100644 gdb-xml/riscv-64bit-fpu.xml delete mode 100644 gdb-xml/riscv-cpu.xml delete mode 100644 gdb-xml/riscv-csr.xml delete mode 100644 gdb-xml/riscv-fpu.xml diff --git a/configure b/configure index 7796c3b143d..9be0b3eb534 100755 --- a/configure +++ b/configure @@ -7172,14 +7172,14 @@ case "$target_name" in TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-cpu.xml riscv-fpu.xml riscv-csr.xml" + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml" target_compiler=$cross_cc_riscv32 ;; riscv64) TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-cpu.xml riscv-fpu.xml riscv-csr.xml" + gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml" target_compiler=$cross_cc_riscv64 ;; sh4|sh4eb) diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml new file mode 100644 index 00000000000..c02f86c0b03 --- /dev/null +++ b/gdb-xml/riscv-32bit-cpu.xml @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml new file mode 100644 index 00000000000..4aea9e657b9 --- /dev/null +++ b/gdb-xml/riscv-32bit-csr.xml @@ -0,0 +1,250 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml new file mode 100644 index 00000000000..783287d9362 --- /dev/null +++ b/gdb-xml/riscv-32bit-fpu.xml @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-64bit-cpu.xml b/gdb-xml/riscv-64bit-cpu.xml new file mode 100644 index 00000000000..f37d7f3ce36 --- /dev/null +++ b/gdb-xml/riscv-64bit-cpu.xml @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml new file mode 100644 index 00000000000..a3de83443a5 --- /dev/null +++ b/gdb-xml/riscv-64bit-csr.xml @@ -0,0 +1,250 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml new file mode 100644 index 00000000000..fb24b72bcaf --- /dev/null +++ b/gdb-xml/riscv-64bit-fpu.xml @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-cpu.xml b/gdb-xml/riscv-cpu.xml deleted file mode 100644 index ee3ff58f782..00000000000 --- a/gdb-xml/riscv-cpu.xml +++ /dev/null @@ -1,43 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/gdb-xml/riscv-csr.xml b/gdb-xml/riscv-csr.xml deleted file mode 100644 index 7945f7ffdd7..00000000000 --- a/gdb-xml/riscv-csr.xml +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - diff --git a/gdb-xml/riscv-fpu.xml b/gdb-xml/riscv-fpu.xml deleted file mode 100644 index a6b114484ab..00000000000 --- a/gdb-xml/riscv-fpu.xml +++ /dev/null @@ -1,43 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 77f882bee1d..3fa519c8eed 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -355,7 +355,11 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) cc->gdb_read_register = riscv_cpu_gdb_read_register; cc->gdb_write_register = riscv_cpu_gdb_write_register; cc->gdb_num_core_regs = 33; - cc->gdb_core_xml_file = "riscv-cpu.xml"; +#if defined(TARGET_RISCV32) + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; +#elif defined(TARGET_RISCV64) + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; +#endif cc->gdb_stop_before_watchpoint = true; cc->disas_set_info = riscv_cpu_disas_set_info; #ifdef CONFIG_USER_ONLY diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 926afd142dd..1eb9eb08d95 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -136,19 +136,25 @@ /* Legacy Counter Setup (priv v1.9.1) */ #define CSR_MUCOUNTEREN 0x320 #define CSR_MSCOUNTEREN 0x321 +#define CSR_MHCOUNTEREN 0x322 /* Machine Trap Handling */ #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 -#define CSR_MBADADDR 0x343 +#define CSR_MTVAL 0x343 #define CSR_MIP 0x344 #define CSR_MNXTI 0x345 /* clic-spec-draft */ #define CSR_MINTSTATUS 0x346 /* clic-spec-draft */ #define CSR_MSCRATCHCSW 0x348 /* clic-spec-draft */ +/* Legacy Machine Trap Handling (priv v1.9.1) */ +#define CSR_MBADADDR 0x343 + /* Supervisor Trap Setup */ #define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 #define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 @@ -158,12 +164,15 @@ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 -#define CSR_SBADADDR 0x143 +#define CSR_STVAL 0x143 #define CSR_SIP 0x144 #define CSR_SNXTI 0x145 /* clic-spec-draft */ #define CSR_SINTSTATUS 0x146 /* clic-spec-draft */ #define CSR_SSCRATCHCSW 0x148 /* clic-spec-draft */ +/* Legacy Supervisor Trap Handling (priv v1.9.1) */ +#define CSR_SBADADDR 0x143 + /* Supervisor Protection and Translation */ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 @@ -290,6 +299,28 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f +/* Legacy Hypervisor Trap Setup (priv v1.9.1) */ +#define CSR_HSTATUS 0x200 +#define CSR_HEDELEG 0x202 +#define CSR_HIDELEG 0x203 +#define CSR_HIE 0x204 +#define CSR_HTVEC 0x205 + +/* Legacy Hypervisor Trap Handling (priv v1.9.1) */ +#define CSR_HSCRATCH 0x240 +#define CSR_HEPC 0x241 +#define CSR_HCAUSE 0x242 +#define CSR_HBADADDR 0x243 +#define CSR_HIP 0x244 + +/* Legacy Machine Protection and Translation (priv v1.9.1) */ +#define CSR_MBASE 0x380 +#define CSR_MBOUND 0x381 +#define CSR_MIBASE 0x382 +#define CSR_MIBOUND 0x383 +#define CSR_MDBASE 0x384 +#define CSR_MDBOUND 0x385 + /* mstatus CSR bits */ #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index bf1301a1236..b1eb02b3709 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -57,6 +57,24 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) if (n < 32) { return gdb_get_reg64(mem_buf, env->fpr[n]); } + else if (n == 32) { + target_ulong val = 0; + if (riscv_csrrw(env, CSR_FFLAGS, &val, 0, 0) == 0) { + return gdb_get_regl(mem_buf, val); + } + } + else if (n == 33) { + target_ulong val = 0; + if (riscv_csrrw(env, CSR_FRM, &val, 0, 0) == 0) { + return gdb_get_regl(mem_buf, val); + } + } + else if (n == 34) { + target_ulong val = 0; + if (riscv_csrrw(env, CSR_FCSR, &val, 0, 0) == 0) { + return gdb_get_regl(mem_buf, val); + } + } return 0; } @@ -66,14 +84,281 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */ return sizeof(uint64_t); } + else if (n == 32) { + target_ulong val = ldtul_p(mem_buf); + if (riscv_csrrw(env, CSR_FFLAGS, NULL, val, -1) == 0) { + return sizeof(target_ulong); + } + } + else if (n == 33) { + target_ulong val = ldtul_p(mem_buf); + if (riscv_csrrw(env, CSR_FRM, NULL, val, -1) == 0) { + return sizeof(target_ulong); + } + } + else if (n == 34) { + target_ulong val = ldtul_p(mem_buf); + if (riscv_csrrw(env, CSR_FCSR, NULL, val, -1) == 0) { + return sizeof(target_ulong); + } + } return 0; } +/* The GDB CSR xml files list them in documentation order, not numerical order, + and are missing entries for unnamed CSRs. So we need to map the gdb numbers + to the hardware numbers. */ + +static int csr_register_map[] = +{ + CSR_USTATUS, + CSR_UIE, + CSR_UTVEC, + CSR_USCRATCH, + CSR_UEPC, + CSR_UCAUSE, + CSR_UTVAL, + CSR_UIP, + CSR_FFLAGS, + CSR_FRM, + CSR_FCSR, + CSR_CYCLE, + CSR_TIME, + CSR_INSTRET, + CSR_HPMCOUNTER3, + CSR_HPMCOUNTER4, + CSR_HPMCOUNTER5, + CSR_HPMCOUNTER6, + CSR_HPMCOUNTER7, + CSR_HPMCOUNTER8, + CSR_HPMCOUNTER9, + CSR_HPMCOUNTER10, + CSR_HPMCOUNTER11, + CSR_HPMCOUNTER12, + CSR_HPMCOUNTER13, + CSR_HPMCOUNTER14, + CSR_HPMCOUNTER15, + CSR_HPMCOUNTER16, + CSR_HPMCOUNTER17, + CSR_HPMCOUNTER18, + CSR_HPMCOUNTER19, + CSR_HPMCOUNTER20, + CSR_HPMCOUNTER21, + CSR_HPMCOUNTER22, + CSR_HPMCOUNTER23, + CSR_HPMCOUNTER24, + CSR_HPMCOUNTER25, + CSR_HPMCOUNTER26, + CSR_HPMCOUNTER27, + CSR_HPMCOUNTER28, + CSR_HPMCOUNTER29, + CSR_HPMCOUNTER30, + CSR_HPMCOUNTER31, + CSR_CYCLEH, + CSR_TIMEH, + CSR_INSTRETH, + CSR_HPMCOUNTER3H, + CSR_HPMCOUNTER4H, + CSR_HPMCOUNTER5H, + CSR_HPMCOUNTER6H, + CSR_HPMCOUNTER7H, + CSR_HPMCOUNTER8H, + CSR_HPMCOUNTER9H, + CSR_HPMCOUNTER10H, + CSR_HPMCOUNTER11H, + CSR_HPMCOUNTER12H, + CSR_HPMCOUNTER13H, + CSR_HPMCOUNTER14H, + CSR_HPMCOUNTER15H, + CSR_HPMCOUNTER16H, + CSR_HPMCOUNTER17H, + CSR_HPMCOUNTER18H, + CSR_HPMCOUNTER19H, + CSR_HPMCOUNTER20H, + CSR_HPMCOUNTER21H, + CSR_HPMCOUNTER22H, + CSR_HPMCOUNTER23H, + CSR_HPMCOUNTER24H, + CSR_HPMCOUNTER25H, + CSR_HPMCOUNTER26H, + CSR_HPMCOUNTER27H, + CSR_HPMCOUNTER28H, + CSR_HPMCOUNTER29H, + CSR_HPMCOUNTER30H, + CSR_HPMCOUNTER31H, + CSR_SSTATUS, + CSR_SEDELEG, + CSR_SIDELEG, + CSR_SIE, + CSR_STVEC, + CSR_SCOUNTEREN, + CSR_SSCRATCH, + CSR_SEPC, + CSR_SCAUSE, + CSR_STVAL, + CSR_SIP, + CSR_SATP, + CSR_MVENDORID, + CSR_MARCHID, + CSR_MIMPID, + CSR_MHARTID, + CSR_MSTATUS, + CSR_MISA, + CSR_MEDELEG, + CSR_MIDELEG, + CSR_MIE, + CSR_MTVEC, + CSR_MCOUNTEREN, + CSR_MSCRATCH, + CSR_MEPC, + CSR_MCAUSE, + CSR_MTVAL, + CSR_MIP, + CSR_PMPCFG0, + CSR_PMPCFG1, + CSR_PMPCFG2, + CSR_PMPCFG3, + CSR_PMPADDR0, + CSR_PMPADDR1, + CSR_PMPADDR2, + CSR_PMPADDR3, + CSR_PMPADDR4, + CSR_PMPADDR5, + CSR_PMPADDR6, + CSR_PMPADDR7, + CSR_PMPADDR8, + CSR_PMPADDR9, + CSR_PMPADDR10, + CSR_PMPADDR11, + CSR_PMPADDR12, + CSR_PMPADDR13, + CSR_PMPADDR14, + CSR_PMPADDR15, + CSR_MCYCLE, + CSR_MINSTRET, + CSR_MHPMCOUNTER3, + CSR_MHPMCOUNTER4, + CSR_MHPMCOUNTER5, + CSR_MHPMCOUNTER6, + CSR_MHPMCOUNTER7, + CSR_MHPMCOUNTER8, + CSR_MHPMCOUNTER9, + CSR_MHPMCOUNTER10, + CSR_MHPMCOUNTER11, + CSR_MHPMCOUNTER12, + CSR_MHPMCOUNTER13, + CSR_MHPMCOUNTER14, + CSR_MHPMCOUNTER15, + CSR_MHPMCOUNTER16, + CSR_MHPMCOUNTER17, + CSR_MHPMCOUNTER18, + CSR_MHPMCOUNTER19, + CSR_MHPMCOUNTER20, + CSR_MHPMCOUNTER21, + CSR_MHPMCOUNTER22, + CSR_MHPMCOUNTER23, + CSR_MHPMCOUNTER24, + CSR_MHPMCOUNTER25, + CSR_MHPMCOUNTER26, + CSR_MHPMCOUNTER27, + CSR_MHPMCOUNTER28, + CSR_MHPMCOUNTER29, + CSR_MHPMCOUNTER30, + CSR_MHPMCOUNTER31, + CSR_MCYCLEH, + CSR_MINSTRETH, + CSR_MHPMCOUNTER3H, + CSR_MHPMCOUNTER4H, + CSR_MHPMCOUNTER5H, + CSR_MHPMCOUNTER6H, + CSR_MHPMCOUNTER7H, + CSR_MHPMCOUNTER8H, + CSR_MHPMCOUNTER9H, + CSR_MHPMCOUNTER10H, + CSR_MHPMCOUNTER11H, + CSR_MHPMCOUNTER12H, + CSR_MHPMCOUNTER13H, + CSR_MHPMCOUNTER14H, + CSR_MHPMCOUNTER15H, + CSR_MHPMCOUNTER16H, + CSR_MHPMCOUNTER17H, + CSR_MHPMCOUNTER18H, + CSR_MHPMCOUNTER19H, + CSR_MHPMCOUNTER20H, + CSR_MHPMCOUNTER21H, + CSR_MHPMCOUNTER22H, + CSR_MHPMCOUNTER23H, + CSR_MHPMCOUNTER24H, + CSR_MHPMCOUNTER25H, + CSR_MHPMCOUNTER26H, + CSR_MHPMCOUNTER27H, + CSR_MHPMCOUNTER28H, + CSR_MHPMCOUNTER29H, + CSR_MHPMCOUNTER30H, + CSR_MHPMCOUNTER31H, + CSR_MHPMEVENT3, + CSR_MHPMEVENT4, + CSR_MHPMEVENT5, + CSR_MHPMEVENT6, + CSR_MHPMEVENT7, + CSR_MHPMEVENT8, + CSR_MHPMEVENT9, + CSR_MHPMEVENT10, + CSR_MHPMEVENT11, + CSR_MHPMEVENT12, + CSR_MHPMEVENT13, + CSR_MHPMEVENT14, + CSR_MHPMEVENT15, + CSR_MHPMEVENT16, + CSR_MHPMEVENT17, + CSR_MHPMEVENT18, + CSR_MHPMEVENT19, + CSR_MHPMEVENT20, + CSR_MHPMEVENT21, + CSR_MHPMEVENT22, + CSR_MHPMEVENT23, + CSR_MHPMEVENT24, + CSR_MHPMEVENT25, + CSR_MHPMEVENT26, + CSR_MHPMEVENT27, + CSR_MHPMEVENT28, + CSR_MHPMEVENT29, + CSR_MHPMEVENT30, + CSR_MHPMEVENT31, + CSR_TSELECT, + CSR_TDATA1, + CSR_TDATA2, + CSR_TDATA3, + CSR_DCSR, + CSR_DPC, + CSR_DSCRATCH, + CSR_HSTATUS, + CSR_HEDELEG, + CSR_HIDELEG, + CSR_HIE, + CSR_HTVEC, + CSR_HSCRATCH, + CSR_HEPC, + CSR_HCAUSE, + CSR_HBADADDR, + CSR_HIP, + CSR_MBASE, + CSR_MBOUND, + CSR_MIBASE, + CSR_MIBOUND, + CSR_MDBASE, + CSR_MDBOUND, + CSR_MUCOUNTEREN, + CSR_MSCOUNTEREN, + CSR_MHCOUNTEREN, +}; + static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n) { if (n < 4096) { target_ulong val = 0; - if (riscv_csrrw(env, n, &val, 0, 0) == 0) { + if (n < ARRAY_SIZE(csr_register_map) && + riscv_csrrw(env, csr_register_map[n], &val, 0, 0) == 0) { return gdb_get_regl(mem_buf, val); } } @@ -84,7 +369,8 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) { if (n < 4096) { target_ulong val = ldtul_p(mem_buf); - if (riscv_csrrw(env, n, NULL, val, -1) == 0) { + if (n < ARRAY_SIZE(csr_register_map) && + riscv_csrrw(env, n, NULL, val, -1) == 0) { return sizeof(target_ulong); } } @@ -94,9 +380,17 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { /* ??? Assume all targets have FPU regs for now. */ +#if defined(TARGET_RISCV32) + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, + 35, "riscv-32bit-fpu.xml", 0); + + gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, + 4096, "riscv-32bit-csr.xml", 0); +#elif defined(TARGET_RISCV64) gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 32, "riscv-fpu.xml", 0); + 35, "riscv-64bit-fpu.xml", 0); gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 4096, "riscv-csr.xml", 0); + 4096, "riscv-64bit-csr.xml", 0); +#endif }