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illegal vl1re64.v generated with zve32x and -mriscv_vector_bits=64 #372

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fabiovito opened this issue Mar 24, 2023 · 0 comments
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riscv_bug.tar.gz

In attachment it's possible replicate the issue with a standalone example build for riscv with gcc.
This is the scenario
riscv gcc repo: [email protected]:riscv-collab/riscv-gcc.git
branch: riscv-gcc-rvv-next
flag -march=rv32imc_zve32x_zicsr -mabi=ilp32 -mriscv-vector-bits=64

Output
/tmp/cc1WEqGj.s: Assembler messages:
/tmp/cc1WEqGj.s:24: Error: illegal opcode for zve32x vl1re64.v v24,0(a4)' /tmp/cc1WEqGj.s:25: Error: illegal opcode for zve32x vl1re64.v v25,0(a2)'

You can invoke this example extracting the tar.gz an invoke:
make

This are all combinations tested:
use ee_kws.c:15
#define PTR_INT uint32_t

  1. -march=rv32imc_zicsr -mabi=ilp32 -> OK -> no vector generated
  2. -march=rv32imc_zve32x_zicsr -mabi=ilp32 -> OK -> no vector generated
  3. -march=rv32imc_zve32x_zicsr -mabi=ilp32 -mriscv-vector-bits=64 -> OK -> vector generated

use ee_kws.c:16
#define PTR_INT uint64_t

  1. -march=rv32imc_zicsr -mabi=ilp32 -> OK -> no vector generated
  2. -march=rv32imc_zve32x_zicsr -mabi=ilp32 -> OK -> no vector generated
  3. -march=rv32imc_zve32x_zicsr -mabi=ilp32 -mriscv-vector-bits=64 -> BUG-> wrong vector generated vl1re64.v
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