Again about Zicif

[haosun86]

Hi,

In last issue link: #186, it seems to explain that:
The 2 16-bit part of one 32-bit instruction need to keep atomicity in the machine: ILEN = 32, XLEN =32, supporting 16-bit instruction.

I want to make sure that this requirement would constrain the following scenario?
Store A (low 16-bit part of 32-bit instruction)
Fence
Store B (high 16-bit part of 32-bit instruction)

If one hart can fetch B, it needs to fetch A? Especially, A and B are located in different cachelines.

Thanks so much
Wish for your reply.

[aswaterman]

No, that is not the requirement. Since those stores are not atomic with respect to each other, it is incorrect to assume their overall effect is atomic. Whether they are on the same cache line is not relevant.

If you want to atomically patch a 32-bit instruction, you need to meet three requirements:

• Zicif is implemented
• the instruction is 32-bit-aligned
• you use a 32-bit store (e.g. sw) to perform the patching

(None of this affects the profiles discussion; it's just a usage scenario for Zicif.)

[haosun86]

Thanks so much for your reply.

Could you please explain more about the usage cases of Zicif?
I am still confused about this extension use cases.

[aswaterman]

The goal is to support atomic patching of 32-bit-wide instructions, e.g., replacing an expensive instruction with a NOP in some cases, or replacing a JAL with a JAL to a different location. Sorry, I don't have time to elaborate.

[haosun86]

thanks so much