From 38d4c56686644019c61f0b4d0ec5f96d35e3508b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 1 Oct 2024 18:21:03 -0700 Subject: [PATCH] Use B instead of Zba/Zbb/Zbs in RVA23U64 --- src/rva23-profile.adoc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/rva23-profile.adoc b/src/rva23-profile.adoc index 8963796..2c47539 100644 --- a/src/rva23-profile.adoc +++ b/src/rva23-profile.adoc @@ -86,6 +86,7 @@ The following mandatory extensions were present in RVA22U64. - *F* Single-precision floating-point instructions. - *D* Double-precision floating-point instructions. - *C* Compressed instructions. +- *B* Bit-manipulation instructions. - *Zicsr* CSR instructions. These are implied by presence of F. - *Zicntr* Base counters and timers. - *Zihpm* Hardware performance counters. @@ -100,9 +101,6 @@ The following mandatory extensions were present in RVA22U64. - *Za64rs* Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes. - *Zihintpause* Pause hint. -- *Zba* Address generation. -- *Zbb* Basic bit-manipulation. -- *Zbs* Single-bit instructions. - *Zic64b* Cache blocks must be 64 bytes in size, naturally aligned in the address space. - *Zicbom* Cache-block management instructions. @@ -391,6 +389,7 @@ of the https://github.com/riscv/riscv-isa-manual[RISC-V Instruction Set Manual]. - H Hypervisor Extension - Q Extension for Quad-Precision Floating-Point - C Extension for Compressed Instructions +- B Extension for Bit Manipulation - V Extension for Vector Computation - Zifencei Instruction-Fetch Fence Extension - Zicsr Extension for Control and Status Register Access