Release riscv-isa-release-e24a456-2024-10-28

This release was created by: aswaterman
Release of RISC-V ISA, built from commit e24a456, is now available.

What's Changed

• Improve table: Compressed instruction formats by @cousteaulecommandant in #1696

New Contributors

• @cousteaulecommandant made their first contribution in #1696

Full Changelog: riscv-isa-release-084b690-2024-10-22...riscv-isa-release-e24a456-2024-10-28

Release riscv-isa-release-34b6e75-2024-10-28

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 34b6e75, is now available.

What's Changed

• Fix NOTE about ARM FMA mnemonics by @aswaterman in #1700

Full Changelog: riscv-isa-release-e24a456-2024-10-28...riscv-isa-release-34b6e75-2024-10-28

Release riscv-isa-release-084b690-2024-10-22

This release was created by: wmat
Release of RISC-V ISA, built from commit 084b690, is now available.

What's Changed

• Fix for issue 1693 (HSLEN should be HSXLEN) by @james-ball-qualcomm in #1694

New Contributors

• @james-ball-qualcomm made their first contribution in #1694

Full Changelog: riscv-isa-release-ae98787-2024-10-19...riscv-isa-release-084b690-2024-10-22

Release riscv-isa-release-ae98787-2024-10-19

This release was created by: aswaterman
Release of RISC-V ISA, built from commit ae98787, is now available.

What's Changed

• remove redundant 'rd == x0' by @kacouane in #1690

Full Changelog: riscv-isa-release-2c07aa2-2024-10-18...riscv-isa-release-ae98787-2024-10-19

Release riscv-isa-release-90f05f7-2024-10-18

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 90f05f7, is now available.

What's Changed

• Add NOTE that only G-stage PBMTs apply to VS-stage PTE accesses by @aswaterman in #1688

Full Changelog: riscv-isa-release-ef2ec9d-2024-10-16...riscv-isa-release-90f05f7-2024-10-18

Release riscv-isa-release-2c07aa2-2024-10-18

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 2c07aa2, is now available.

What's Changed

• priv 1.13 is ratified by @aswaterman in #1689

Full Changelog: riscv-isa-release-90f05f7-2024-10-18...riscv-isa-release-2c07aa2-2024-10-18

Release riscv-isa-release-ef2ec9d-2024-10-16

This release was created by: aswaterman
Release of RISC-V ISA, built from commit ef2ec9d, is now available.

What's Changed

• Remove future tense from description of now-ratified text by @aswaterman in #1685

Full Changelog: riscv-isa-release-f455143-2024-10-15...riscv-isa-release-ef2ec9d-2024-10-16

Release riscv-isa-release-f455143-2024-10-15

This release was created by: aswaterman
Release of RISC-V ISA, built from commit f455143, is now available.

What's Changed

• Mark CBIE field as WARL by @aswaterman in #1684

Full Changelog: riscv-isa-release-0ee55c0-2024-10-12...riscv-isa-release-f455143-2024-10-15

Release riscv-isa-release-0ee55c0-2024-10-12

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 0ee55c0, is now available.

What's Changed

• Add LCOFI priority info for HS-mode (#1678) by @demin-han in #1679

Full Changelog: riscv-isa-release-b22b28e-2024-10-10...riscv-isa-release-0ee55c0-2024-10-12

Release riscv-isa-release-b22b28e-2024-10-10

This release was created by: aswaterman
Release of RISC-V ISA, built from commit b22b28e, is now available.

What's Changed

• Remove pseudoinstructions from B instruction table by @aswaterman in #1676

Full Changelog: riscv-isa-release-1569c8d-2024-10-03...riscv-isa-release-b22b28e-2024-10-10