diff --git a/src/hypervisor-integration.adoc b/src/hypervisor-integration.adoc index 70225e6f..da6412e1 100644 --- a/src/hypervisor-integration.adoc +++ b/src/hypervisor-integration.adoc @@ -164,6 +164,36 @@ present when the implementation supports {cheri_default_ext_name}. .Virtual supervisor trap default capability register include::img/vstdcreg.edn[] +[#vstval,reftext="vstval"] +=== Virtual Supervisor Trap Value Register (vstval) + +The <> register is an SXLEN-bit read-write register. + +When a fault is taken into VS-mode <> is updated as for <> for all CHERI exceptions. + +.Virtual supervisor trap value register +[#vstval-format] +include::img/vstvalreg.edn[] + + +[#vstval2,reftext="vstval2"] +=== Virtual Supervisor Trap Value Register 2 (vstval2) + +The <> register is a VSXLEN-bit read-write register. + +The CSR address is 0x24b. + +When a fault is taken into VS-mode <> is updated as for <> for all CHERI exceptions. +It is set to zero in all other cases. + +NOTE: This is not a standard RISC-V CSR, but <> is. 0x24b is the regular location for the CSR. + +<> holds the same set of values that <> can hold. + +.Virtual supervisor trap value register 2 +[#vstval2-format] +include::img/vstval2reg.edn[] + === Existing Hypervisor Load and Store Instructions The hypervisor extension defines several integer load and store instructions diff --git a/src/img/mtval2reg.edn b/src/img/mtval2reg.edn new file mode 100644 index 00000000..bb2996b0 --- /dev/null +++ b/src/img/mtval2reg.edn @@ -0,0 +1,14 @@ +[bytefield] +---- +(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}]) +(def row-height 40) +(def row-header-fn nil) +(def left-margin 100) +(def right-margin 100) +(def boxes-per-row 32) +(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1"])}) + +(draw-box "Addr" {:span 32}) + +(draw-box "MXLEN" {:span 32 :borders {}}) +---- diff --git a/src/img/stval2reg.edn b/src/img/stval2reg.edn new file mode 100644 index 00000000..7be3c6d9 --- /dev/null +++ b/src/img/stval2reg.edn @@ -0,0 +1,14 @@ +[bytefield] +---- +(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}]) +(def row-height 40) +(def row-header-fn nil) +(def left-margin 100) +(def right-margin 100) +(def boxes-per-row 32) +(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "SXLEN-1"])}) + +(draw-box "Addr" {:span 32}) + +(draw-box "SXLEN" {:span 32 :borders {}}) +---- diff --git a/src/img/vstval2reg.edn b/src/img/vstval2reg.edn new file mode 100644 index 00000000..10f20dd9 --- /dev/null +++ b/src/img/vstval2reg.edn @@ -0,0 +1,14 @@ +[bytefield] +---- +(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}]) +(def row-height 40) +(def row-header-fn nil) +(def left-margin 100) +(def right-margin 100) +(def boxes-per-row 32) +(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "VSXLEN-1"])}) + +(draw-box "Addr" {:span 32}) + +(draw-box "VSXLEN" {:span 32 :borders {}}) +---- diff --git a/src/img/vstvalreg.edn b/src/img/vstvalreg.edn new file mode 100644 index 00000000..7c20561f --- /dev/null +++ b/src/img/vstvalreg.edn @@ -0,0 +1,20 @@ +[bytefield] +---- +(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}]) +(def row-height 40) +(def row-header-fn nil) +(def left-margin 100) +(def right-margin 100) +(def boxes-per-row 32) +(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "3" "4" "" "" "" "" "" "" "" "" "" "" "15" "16" "" "" "19" "20" "" "" "" "" "" "" "" "" "" "" "VSXLEN-1"])}) + +(draw-box "Reserved" {:span 12}) +(draw-box "TYPE" {:span 4}) +(draw-box "Reserved" {:span 12}) +(draw-box "CAUSE" {:span 4}) + +(draw-box "VSXLEN-20" {:span 12 :borders {}}) +(draw-box "4" {:span 4 :borders {}}) +(draw-box "12" {:span 12 :borders {}}) +(draw-box "4" {:span 4 :borders {}}) +---- diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc index 617f102a..2fff3a9c 100644 --- a/src/riscv-integration.adoc +++ b/src/riscv-integration.adoc @@ -791,6 +791,24 @@ CHERI violations have the following order in priority: . Invalid address violation . Bounds violation (_Lowest_) +[#mtval2,reftext="mtval2"] +==== Machine Trap Value Register 2 (mtval2) + +The <> register is an MXLEN-bit read-write register, which is added as part of the +Hypervisor extension. {cheri_base_ext_name} also requires the implementation of this CSR. + +When a CHERI fault is taken on any data memory access into into M-mode, <> is written +with the MXLEN-bit effective address which caused the fault. This follows the existing rules for reporting +load/store addresses to <> from cite:[riscv-priv-spec]. + +<> is set to zero for all other CHERI exceptions, and follows the standard rules for non-CHERI exceptions. + +If <> is read-only-zero then <> is also read-only-zero. + +.Machine trap value register 2 +[#mtval2-format] +include::img/mtval2reg.edn[] + [#supervisor-level-csrs-section] === Supervisor-Level CSRs @@ -993,10 +1011,25 @@ xref:stval-format[xrefstyle=short] to assist software in handling the trap. [#stval-format] include::img/stvalreg.edn[] -TYPE is a CHERI-specific fault type that caused the exception while CAUSE -is the cause of the fault. The possible CHERI types and causes are encoded as -shown in xref:mtval-cheri-type[xrefstyle=short] and -xref:mtval-cheri-causes[xrefstyle=short] respectively. +The fields are identical to <> for CHERI exceptions. + +[#stval2,reftext="stval2"] +==== Supervisor Trap Value Register 2 (stval2) + +The <> register is an SXLEN-bit read-write register. + +The CSR address is 0x24b. + +When a fault is taken into S-mode <> is updated as for <> for all CHERI exceptions. +It is set to zero in all other cases. + +NOTE: This is not a standard RISC-V CSR, but <> is. 0x14b is the regular location for the CSR. + +<> holds the same set of values that <> can hold. + +.Supervisor trap value register 2 +[#stval2-format] +include::img/stval2reg.edn[] === Unprivileged CSRs