From fa2fba5c5a15c69d8dc83c7c5e26eaeaf5b1b3c5 Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Thu, 8 Feb 2024 11:23:22 +0100 Subject: [PATCH 1/7] rename CSHxADD opcodes to SHxADD --- src/csv/CHERI_ISA.csv | 18 ++++++++---------- src/insns/sh123add_32bit.adoc | 25 ++++++------------------- src/insns/sh123adduw_32bit.adoc | 25 ++++++------------------- src/insns/sh4add_32bit.adoc | 18 ++++++------------ src/insns/sh4adduw_32bit.adoc | 18 ++++++------------ 5 files changed, 32 insertions(+), 72 deletions(-) diff --git a/src/csv/CHERI_ISA.csv b/src/csv/CHERI_ISA.csv index a81d0d04..7c567b24 100644 --- a/src/csv/CHERI_ISA.csv +++ b/src/csv/CHERI_ISA.csv @@ -137,13 +137,11 @@ "CM.JT","✔","✔","","","","✔","","Legacy","","","","","","","","","✔","","","","","","","C2","","","","Table jump","","","","","","","","" "CM.CJALT","✔","✔","","","","","✔","Capability","","","","","","","","","✔","","","","","","","C2","","CM.JALT","CM.JALT","Table jump and link","","","","","","","","" "CM.CJT","✔","✔","","","","","✔","Capability","","","","","","","","","✔","","","","","","","C2","","CM.JT","CM.JT","Table jump","","","","","","","","" -"CSH1ADD","✔","✔","","","","","✔","Capability","","","✔","","","","","","","","","","","","","OP","","SH1ADD","SH1ADD","shift and add, representability check on the result","","","","","","","","" -"CSH1ADD.UW","✔","✔","","","","","✔","Capability","","","✔","","","","","","","","","","","","","OP","","SH1ADD.UW","SH1ADD.UW","shift and add, representability check on the result","","","","","","","","" -"CSH2ADD","✔","✔","","","","","✔","Capability","","","✔","","","","","","","","","","","","","OP","","SH2ADD","SH2ADD","shift and add, representability check on the result","","","","","","","","" -"CSH2ADD.UW","✔","✔","","","","","✔","Capability","","","✔","","","","","","","","","","","","","OP","","SH2ADD.UW","SH2ADD.UW","shift and add, representability check on the result","","","","","","","","" -"CSH3ADD","✔","✔","","","","","✔","Capability","","","✔","","","","","","","","","","","","","OP","","SH3ADD","SH3ADD","shift and add, representability check on the result","","","","","","","","" -"CSH3ADD.UW","✔","✔","","","","","✔","Capability","","","✔","","","","","","","","","","","","","OP","","SH3ADD.UW","SH3ADD.UW","shift and add, representability check on the result","","","","","","","","" -"SH4ADD","","✔","","","","✔","","Legacy","","","","","","","","","","","","","","","","OP","","","","shift and add","","","","","","","","" -"SH4ADD.UW","","✔","","","","✔","","Legacy","","","","","","","","","","","","","","","","OP","","","","shift and add","","","","","","","","" -"CSH4ADD","","✔","","","","","✔","Capability","","","","","","","","","","","","","","","","OP","","SH4ADD","SH4ADD","shift and add, representability check on the result","","","","","","","","" -"CSH4ADD.UW","","✔","","","","","✔","Capability","","","","","","","","","","","","","","","","OP","","SH4ADD.UW","SH4ADD.UW","shift and add, representability check on the result","","","","","","","","" +"SH1ADD","✔","✔","","","","✔","✔","Both","","","✔","","","","","","","","","","","","","OP","","SH1ADD","SH1ADD","shift and add, representability check on the result","","","","","","","","" +"SH1ADD.UW","✔","✔","","","","✔","✔","Both","","","✔","","","","","","","","","","","","","OP","","SH1ADD.UW","SH1ADD.UW","shift and add, representability check on the result","","","","","","","","" +"SH2ADD","✔","✔","","","","✔","✔","Both","","","✔","","","","","","","","","","","","","OP","","SH2ADD","SH2ADD","shift and add, representability check on the result","","","","","","","","" +"SH2ADD.UW","✔","✔","","","","✔","✔","Both","","","✔","","","","","","","","","","","","","OP","","SH2ADD.UW","SH2ADD.UW","shift and add, representability check on the result","","","","","","","","" +"SH3ADD","✔","✔","","","","✔","✔","Both","","","✔","","","","","","","","","","","","","OP","","SH3ADD","SH3ADD","shift and add, representability check on the result","","","","","","","","" +"SH3ADD.UW","✔","✔","","","","✔","✔","Both","","","✔","","","","","","","","","","","","","OP","","SH3ADD.UW","SH3ADD.UW","shift and add, representability check on the result","","","","","","","","" +"SH4ADD","","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","","OP","","","","shift and add","","","","","","","","" +"SH4ADD.UW","","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","","OP","","","","shift and add","","","","","","","","" diff --git a/src/insns/sh123add_32bit.adoc b/src/insns/sh123add_32bit.adoc index e953766d..38e25348 100644 --- a/src/insns/sh123add_32bit.adoc +++ b/src/insns/sh123add_32bit.adoc @@ -1,17 +1,4 @@ <<< -//[#insns-sh123add-32bit,reftext="CSR access (CSH1ADD, CSH2ADD, CSH3ADD, SH1ADD, SH2ADD, SH3ADD), 32-bit encoding"] - -[#CSH1ADD,reftext="CSH1ADD"] -==== CSH1ADD -See <>. - -[#CSH2ADD,reftext="CSH2ADD"] -==== CSH2ADD -See <>. - -[#CSH3ADD,reftext="CSH3ADD"] -==== CSH3ADD -See <>. [#SH1ADD,reftext="SH1ADD"] ==== SH1ADD @@ -27,10 +14,10 @@ See <>. ==== SH3ADD Synopsis:: -Shift by _n_ and add for address generation +Shift by _n_ and add for address generation (SH1ADD, SH2ADD, SH3ADD) Capability Mode Mnemonics:: -`csh[1|2|3]add cd, rs1, cs2` +`sh[1|2|3]add cd, rs1, cs2` Legacy Mode Mnemonics:: `sh[1|2|3]add rd, rs1, rs2` @@ -41,10 +28,10 @@ Encoding:: {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, - { bits: 3, name: 0x2, attr: ['SH1ADD=010', 'CSH1ADD=010', 'SH2ADD=100', 'CSH2ADD=100', 'SH3ADD=110', 'CSH3ADD=110'] }, + { bits: 3, name: 0x2, attr: ['SH1ADD=010', 'SH2ADD=100', 'SH3ADD=110'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'cs2/rs2' }, - { bits: 7, name: 0x10, attr: ['SH[1|2|3]ADD', 'CSH[1|2|3]ADD'] }, + { bits: 7, name: 0x10, attr: ['SH[1|2|3]ADD'] }, ]} .... @@ -54,10 +41,10 @@ Increment the address field of `cs2` by `rs1` shifted left by _n_ bit positions. Legacy Mode Description:: Increment `rs2` by `rs1` shifted left by _n_ bit positions. -Prerequisites CSH[1|2|3]ADD:: +Prerequisites for Capability Mode:: {cheri_base_ext_name}, Zba -Prerequisites for SH[1|2|3]ADD:: +Prerequisites for Legacy Mode:: {cheri_legacy_ext_name}, Zba Capability Mode Operation:: diff --git a/src/insns/sh123adduw_32bit.adoc b/src/insns/sh123adduw_32bit.adoc index 837f8d65..091cd1f0 100644 --- a/src/insns/sh123adduw_32bit.adoc +++ b/src/insns/sh123adduw_32bit.adoc @@ -1,17 +1,4 @@ <<< -//[#insns-sh123adduw-32bit,reftext="CSR access (CSH1ADD.UW, CSH2ADD.UW, CSH3ADD.UW, SH1ADD.UW, SH2ADD.UW, SH3ADD.UW), 32-bit encoding"] - -[#CSH1ADD_UW,reftext="CSH1ADD.UW"] -==== CSH1ADD.UW -See <>. - -[#CSH2ADD_UW,reftext="CSH2ADD.UW"] -==== CSH2ADD.UW -See <>. - -[#CSH3ADD_UW,reftext="CSH3ADD.UW"] -==== CSH3ADD.UW -See <>. [#SH1ADD_UW,reftext="SH1ADD.UW"] ==== SH1ADD.UW @@ -27,10 +14,10 @@ See <>. ==== SH3ADD.UW Synopsis:: -Shift by _n_ and add unsigned word for address generation +Shift by _n_ and add unsigned word for address generation (SH1ADD.UW, SH2ADD.UW, SH3ADD.UW) Capability Mode Mnemonic (RV64):: -`csh[1|2|3]add.uw cd, rs1, cs2` +`sh[1|2|3]add.uw cd, rs1, cs2` Legacy Mode Mnemonics (RV64):: `sh[1|2|3]add.uw rd, rs1, rs2` @@ -41,10 +28,10 @@ Encoding:: {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, - { bits: 3, name: 0x2, attr: ['rv64: SH1ADD.UW=010', 'rv64: CSH1ADD.UW=010', 'rv64: SH2ADD.UW=100', 'rv64: CSH2ADD.UW=100', 'rv64: SH3ADD.UW=110', 'rv64: CSH3ADD.UW=110'] }, + { bits: 3, name: 0x2, attr: ['rv64: SH1ADD.UW=010', 'rv64: SH2ADD.UW=100', 'rv64: SH3ADD.UW=110'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'cs2/rs2' }, - { bits: 7, name: 0x10, attr: ['rv64: SH[1|2|3]ADD.UW', 'rv64: CSH[1|2|3]ADD.UW'] }, + { bits: 7, name: 0x10, attr: ['rv64: SH[1|2|3]ADD.UW'] }, ]} .... @@ -54,10 +41,10 @@ Increment the address field of `cs2` by the unsigned word in `rs1` shifted left Legacy Mode Description:: Increment `rs2` by the unsigned word in `rs1` shifted left by _n_ bit positions. -Prerequisites CSH[1|2|3]ADD.UW:: +Prerequisites for Capability Mode:: {cheri_base_ext_name}, Zba -Prerequisites for SH[1|2|3]ADD.UW:: +Prerequisites for Legacy Mode:: {cheri_legacy_ext_name}, Zba Capability Mode Operation:: diff --git a/src/insns/sh4add_32bit.adoc b/src/insns/sh4add_32bit.adoc index 0c9877cb..fef48783 100644 --- a/src/insns/sh4add_32bit.adoc +++ b/src/insns/sh4add_32bit.adoc @@ -1,23 +1,17 @@ <<< -//[#insns-sh4add-32bit,reftext="CSR access (CSH4ADD, SH4ADD), 32-bit encoding"] [#SH4ADD,reftext="SH4ADD"] ==== SH4ADD -See <>. - -[#CSH4ADD,reftext="CSH4ADD"] -==== CSH4ADD - ifdef::cheri_v9_annotations[] NOTE: *CHERI v9 Note:* This instruction is *new*. endif::[] Synopsis:: -Shift by 4 and add for address generation (CSH4ADD, SH4ADD) +Shift by 4 and add for address generation (SH4ADD) Capability Mode Mnemonics:: -`csh4add cd, rs1, cs2` +`sh4add cd, rs1, cs2` Legacy Mode Mnemonics:: `sh4add rd, rs1, rs2` @@ -28,10 +22,10 @@ Encoding:: {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, - { bits: 3, name: 0x7, attr: ['CSH4ADD','SH4ADD'] }, + { bits: 3, name: 0x7, attr: ['SH4ADD'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'cs2/rs2' }, - { bits: 7, name: 16, attr: ['CSH4ADD','SH4ADD'] }, + { bits: 7, name: 16, attr: ['SH4ADD'] }, ]} .... @@ -41,10 +35,10 @@ Increment the address field of `cs2` by `rs1` shifted left by 4 bit positions. C Legacy Mode Description:: Increment `rs2` by `rs1` shifted left by 4 bit positions. -Prerequisites CSH4ADD:: +Prerequisites for Capability Mode:: {cheri_base_ext_name} -Prerequisites for SH4ADD:: +Prerequisites for legacy Mode:: {cheri_legacy_ext_name} Capability Mode Operation:: diff --git a/src/insns/sh4adduw_32bit.adoc b/src/insns/sh4adduw_32bit.adoc index 5a4bccd6..cadd162b 100644 --- a/src/insns/sh4adduw_32bit.adoc +++ b/src/insns/sh4adduw_32bit.adoc @@ -1,19 +1,13 @@ <<< -//[#insns-sh4adduw-32bit,reftext="CSR access (CSH4ADD.UW, SH4ADD.UW), 32-bit encoding"] [#SH4ADD_UW,reftext="SH4ADD.UW"] ==== SH4ADD.UW -See <>. - -[#CSH4ADD_UW,reftext="CSH4ADD.UW"] -==== CSH4ADD.UW - Synopsis:: -Shift by 4 and add unsigned words for address generation (CSH4ADD.UW, SH4ADD.UW) +Shift by 4 and add unsigned words for address generation (SH4ADD.UW) Capability Mode Mnemonics:: -`csh4add.uw cd, rs1, cs2` +`sh4add.uw cd, rs1, cs2` Legacy Mode Mnemonics:: `sh4add.uw rd, rs1, rs2` @@ -24,10 +18,10 @@ Encoding:: {reg:[ { bits: 7, name: 0xe3, attr: ['OP'] }, { bits: 5, name: 'rd' }, - { bits: 3, name: 0x7, attr: ['CSH4ADD.UW', 'SH4ADD.UW'] }, + { bits: 3, name: 0x7, attr: ['SH4ADD.UW'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'cs2/rs2' }, - { bits: 7, name: 16, attr: ['CSH4ADD.UW', 'SH4ADD.UW'] }, + { bits: 7, name: 16, attr: ['SH4ADD.UW'] }, ]} .... @@ -37,10 +31,10 @@ Increment the address field of `cs2` by the unsigned word in `rs1` shifted left Legacy Mode Description:: Increment `rs2` by the unsigned word in `rs1` shifted left by 4 bit positions. -Prerequisites CSH4ADD:: +Prerequisites for Capability Mode:: {cheri_base_ext_name} -Prerequisites for SH4ADD:: +Prerequisites for Legacy Mode:: {cheri_legacy_ext_name} Capability Mode Operation:: From bd7f046f57b22150fa4df38cede33b0149567376 Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Thu, 8 Feb 2024 13:34:32 +0100 Subject: [PATCH 2/7] remove .cap suffix from prefetch.* and cbo.* --- src/csv/CHERI_ISA.csv | 21 +++++++-------------- src/insns/cbo.clean.adoc | 17 ++++++----------- src/insns/cbo.flush.adoc | 15 +++++---------- src/insns/cbo.inval.adoc | 15 +++++---------- src/insns/cbo.zero.adoc | 15 +++++---------- src/insns/cbo_exceptions.adoc | 2 +- src/insns/prefetch.i.adoc | 14 +++++--------- src/insns/prefetch.r.adoc | 16 ++++++---------- src/insns/prefetch.w.adoc | 14 +++++--------- src/riscv-integration.adoc | 2 +- 10 files changed, 46 insertions(+), 85 deletions(-) diff --git a/src/csv/CHERI_ISA.csv b/src/csv/CHERI_ISA.csv index 7c567b24..252e12a8 100644 --- a/src/csv/CHERI_ISA.csv +++ b/src/csv/CHERI_ISA.csv @@ -76,20 +76,13 @@ "CSRRWI","✔","✔","✔","","","","","Both","","","","","","","","","","","","","","","","SYSTEM","","","","CSR write - can also read/write a full capability through an address alias","CSR permission fault","","","","","","","" "CSRRSI","✔","✔","✔","","","","","Both","","","","","","","","","","","","","","","","SYSTEM","","","","CSR set - can also read/write a full capability through an address alias","CSR permission fault","","","","","","","" "CSRRCI","✔","✔","✔","","","","","Both","","","","","","","","","","","","","","","","SYSTEM","","","","CSR clear - can also read/write a full capability through an address alias","CSR permission fault","","","","","","","" -"CBO.INVAL","✔","✔","✔","","","✔","","Legacy","","✔","","","","","","","","","","","","","2","MISC-MEM","","","","Cache block invalidate (implemented as clean), authorise with DDC","MODE>. - -[#CBO_CLEAN_CAP,reftext="CBO.CLEAN.CAP"] -==== CBO.CLEAN.CAP - Synopsis:: Perform a clean operation on a cache block Capability Mode Mnemonic:: -`cbo.clean.cap 0(cs1)` +`cbo.clean 0(cs1)` Legacy Mode Mnemonic:: `cbo.clean 0(rs1)` @@ -24,13 +19,13 @@ Encoding:: {bits: 7, name: 'opcode', attr: ['7','MISC-MEM=0001111'], type: 8}, {bits: 5, name: 'funct5', attr: ['5','CBO=0000'], type: 2}, {bits: 3, name: 'funct3', attr: ['3','CBO=010'], type: 8}, - {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, - {bits: 12, name: 'funct12', attr: ['12','cap: CBO.CLEAN.CAP=00.001', 'leg: CBO.CLEAN=00.001'], type: 3}, + {bits: 5, name: 'cs1/rs1', attr: ['5','base'] + {bits: 12, name: 'funct12', attr: ['12','CBO.CLEAN=00.001'], type: 3}, ]} .... Capability Mode Description:: -A CBO.CLEAN.CAP instruction performs a clean operation on the cache block +A CBO.CLEAN instruction performs a clean operation on the cache block whose effective address is the base address specified in `cs1`. The authorising capability for this operation is `cs1`. @@ -42,10 +37,10 @@ capability for this operation is <>. :cbo_clean_flush: include::cbo_exceptions.adoc[] -Prerequisites for CBO.CLEAN.CAP:: +Prerequisites for Capability Mode:: Zicbom, {cheri_base_ext_name} -Prerequisites for CBO.CLEAN:: +Prerequisites for Legacy Mode:: Zicbom, {cheri_legacy_ext_name} Operation:: diff --git a/src/insns/cbo.flush.adoc b/src/insns/cbo.flush.adoc index 23edf3b7..3307543e 100644 --- a/src/insns/cbo.flush.adoc +++ b/src/insns/cbo.flush.adoc @@ -3,16 +3,11 @@ [#CBO_FLUSH,reftext="CBO.FLUSH"] ==== CBO.FLUSH -See <>. - -[#CBO_FLUSH_CAP,reftext="CBO.FLUSH.CAP"] -==== CBO.FLUSH.CAP - Synopsis:: Perform a flush operation on a cache block Capability Mode Mnemonic:: -`cbo.flush.cap 0(cs1)` +`cbo.flush 0(cs1)` Legacy Mode Mnemonic:: `cbo.flush 0(rs1)` @@ -25,12 +20,12 @@ Encoding:: {bits: 5, name: 'funct5', attr: ['5','CBO=0000'], type: 2}, {bits: 3, name: 'funct3', attr: ['3','CBO=010'], type: 8}, {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, - {bits: 12, name: 'funct12', attr: ['12','cap: CBO.FLUSH.CAP=00.0010', 'leg: CBO.FLUSH=00.0010'], type: 3}, + {bits: 12, name: 'funct12', attr: ['12','cap: CBO.FLUSH=00.0010'], type: 3}, ]} .... Capability Mode Description:: -A CBO.FLUSH.CAP instruction performs a flush operation on the cache block +A CBO.FLUSH instruction performs a flush operation on the cache block whose effective address is the base address specified in `cs1`. The authorising capability for this operation is `cs1`. @@ -42,10 +37,10 @@ capability for this operation is <>. :cbo_clean_flush: include::cbo_exceptions.adoc[] -Prerequisites for CBO.FLUSH.CAP:: +Prerequisites for Capability Mode:: Zicbom, {cheri_base_ext_name} -Prerequisites for CBO.FLUSH:: +Prerequisites for Legacy Mode:: Zicbom, {cheri_legacy_ext_name} Operation:: diff --git a/src/insns/cbo.inval.adoc b/src/insns/cbo.inval.adoc index bc8ce6cc..f1eb552d 100644 --- a/src/insns/cbo.inval.adoc +++ b/src/insns/cbo.inval.adoc @@ -3,16 +3,11 @@ [#CBO_INVAL,reftext="CBO.INVAL"] ==== CBO.INVAL -See <>. - -[#CBO_INVAL_CAP,reftext="CBO.INVAL.CAP"] -==== CBO.INVAL.CAP - Synopsis:: Perform an invalidate operation on a cache block Capability Mode Mnemonic:: -`cbo.inval.cap 0(cs1)` +`cbo.inval 0(cs1)` Legacy Mode Mnemonic:: `cbo.inval 0(rs1)` @@ -25,12 +20,12 @@ Encoding:: {bits: 5, name: 'funct5', attr: ['5','CBO=0000'], type: 2}, {bits: 3, name: 'funct3', attr: ['3','CBO=010'], type: 8}, {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, - {bits: 12, name: 'funct12', attr: ['12','cap: CBO.INVAL.CAP=00.0000', 'leg: CBO.INVAL=00.0000'], type: 3}, + {bits: 12, name: 'funct12', attr: ['12','CBO.INVAL=00.0000'], type: 3}, ]} .... Capability Mode Description:: -A CBO.INVAL.CAP instruction performs an invalidate operation on the cache block +A CBO.INVAL instruction performs an invalidate operation on the cache block whose effective address is the base address specified in `cs1`. The authorising capability for this operation is `cs1`. @@ -42,10 +37,10 @@ authorising capability for this operation in <>. :cbo_inval: include::cbo_exceptions.adoc[] -Prerequisites for CBO.INVAL.CAP:: +Prerequisites for Capability Mode:: Zicbom, {cheri_base_ext_name} -Prerequisites for CBO.INVAL:: +Prerequisites for Legacy Mode:: Zicbom, {cheri_legacy_ext_name} Operation:: diff --git a/src/insns/cbo.zero.adoc b/src/insns/cbo.zero.adoc index 9d3a5e1b..7487e727 100644 --- a/src/insns/cbo.zero.adoc +++ b/src/insns/cbo.zero.adoc @@ -3,16 +3,11 @@ [#CBO_ZERO,reftext="CBO.ZERO"] ==== CBO.ZERO -See <>. - -[#CBO_ZERO_CAP,reftext="CBO.ZERO.CAP"] -==== CBO.ZERO.CAP - Synopsis:: Store zeros to the full set of bytes corresponding to a cache block Capability Mode Mnemonic:: -`cbo.zero.cap 0(cs1)` +`cbo.zero 0(cs1)` Legacy Mode Mnemonic:: `cbo.zero 0(rs1)` @@ -25,12 +20,12 @@ Encoding:: {bits: 5, name: 'funct5', attr: ['5','CBO=0000'], type: 2}, {bits: 3, name: 'funct3', attr: ['3','CBO=010'], type: 8}, {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, - {bits: 12, name: 'funct12', attr: ['12','cap: CBO.ZERO.CAP=00.0100', 'leg: CBO.ZERO=00.0100'], type: 3}, + {bits: 12, name: 'funct12', attr: ['12','CBO.ZERO=00.0100'], type: 3}, ]} .... Capability Mode Description:: -A `cbo.zero.cap` instruction performs stores of zeros to the full set of bytes +A `cbo.zero` instruction performs stores of zeros to the full set of bytes corresponding to the cache block whose effective address is the base address specified in `cs1`. An implementation may or may not update the entire set of bytes atomically although each individual write must atomically clear the tag @@ -47,10 +42,10 @@ for this operation is <>. include::store_exceptions.adoc[] -Prerequisites for CBO.ZERO.CAP:: +Prerequisites for Capability Mode:: Zicboz, {cheri_base_ext_name} -Prerequisites for CBO.ZERO:: +Prerequisites for Legacy Mode:: Zicboz, {cheri_legacy_ext_name} Operation:: diff --git a/src/insns/cbo_exceptions.adoc b/src/insns/cbo_exceptions.adoc index 804625c5..c6707015 100644 --- a/src/insns/cbo_exceptions.adoc +++ b/src/insns/cbo_exceptions.adoc @@ -5,7 +5,7 @@ listed below; in this case, _CHERI data fault_ is reported in the <> or + ifdef::cbo_inval[] The CBIE bit in <> and <> indicates whether -CBO.INVAL.CAP and CBO.INVAL perform cache block flushes instead of +CBO.INVAL performs cache block flushes instead of invalidations for less privileged modes. The instruction checks shown in the table below remain unchanged regardless of the value of CBIE and the privilege mode. diff --git a/src/insns/prefetch.i.adoc b/src/insns/prefetch.i.adoc index 7a844e49..23df3475 100644 --- a/src/insns/prefetch.i.adoc +++ b/src/insns/prefetch.i.adoc @@ -2,17 +2,13 @@ [#PREFETCH_I,reftext="PREFETCH.I"] ==== PREFETCH.I -See <>. - -[#PREFETCH_I_CAP,reftext="PREFETCH.I.CAP"] -==== PREFETCH.I.CAP Synopsis:: Provide a HINT to hardware that a cache block is likely to be accessed by an instruction fetch in the near future Capability Mode Mnemonic:: -`prefetch.i.cap offset(cs1)` +`prefetch.i offset(cs1)` Legacy Mode Mnemonic:: `prefetch.i offset(rs1)` @@ -25,13 +21,13 @@ Encoding:: {bits: 5, name: 'imm[4:0]', attr: ['5','zero'], type: 2}, {bits: 3, name: 'funct3', attr: ['3','ORI=110'], type: 8}, {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, - {bits: 5, name: 'funct5', attr: ['5','cap: PREFETCH.I.CAP=00000', 'leg: PREFETCH.I=00000'], type: 3}, + {bits: 5, name: 'funct5', attr: ['5','PREFETCH.I=00000'], type: 3}, {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]'], type: 3}, ]} .... Capability Mode Description:: -A PREFETCH.I.CAP instruction indicates to hardware that the cache block whose +A PREFETCH.I instruction indicates to hardware that the cache block whose effective address is the sum of the base address specified in `cs1` and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by an instruction fetch in the near future. The encoding @@ -54,10 +50,10 @@ is only valid if imm[4:0]=0. The authorising capability for this operation is <>. -Prerequisites for PREFETCH.I.CAP:: +Prerequisites for Capability Mode:: Zicbop, {cheri_base_ext_name} -Prerequisites for PREFETCH.I:: +Prerequisites for Legacy Mode:: Zicbop, {cheri_legacy_ext_name} Operation:: diff --git a/src/insns/prefetch.r.adoc b/src/insns/prefetch.r.adoc index 28c81592..307303a3 100644 --- a/src/insns/prefetch.r.adoc +++ b/src/insns/prefetch.r.adoc @@ -2,17 +2,13 @@ [#PREFETCH_R,reftext="PREFETCH.R"] ==== PREFETCH.R -See <>. - -[#PREFETCH_R_CAP,reftext="PREFETCH.R.CAP"] -==== PREFETCH.R.CAP Synopsis:: Provide a HINT to hardware that a cache block is likely to be accessed by a data read in the near future Capability Mode Mnemonic:: -`prefetch.r.cap offset(cs1)` +`prefetch.r offset(cs1)` Legacy Mode Mnemonic:: `prefetch.r offset(rs1)` @@ -24,14 +20,14 @@ Encoding:: {bits: 7, name: 'opcode', attr: ['7','OP-IMM=0010011'], type: 8}, {bits: 5, name: 'imm[4:0]', attr: ['5','zero'], type: 2}, {bits: 3, name: 'funct3', attr: ['3','ORI=110'], type: 8}, - {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, - {bits: 5, name: 'funct5', attr: ['5','cap: PREFETCH.R.CAP=00001', 'leg: PREFETCH.R=00001'], type: 3}, + {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, + {bits: 5, name: 'funct5', attr: ['5','PREFETCH.R=00001'], type: 3}, {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]'], type: 3}, ]} .... Capability Mode Description:: -A PREFETCH.R.CAP instruction indicates to hardware that the cache block whose +A PREFETCH.R instruction indicates to hardware that the cache block whose effective address is the sum of the base address specified in `cs1` and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by a data read (i.e. load) in the near future. The @@ -54,10 +50,10 @@ encoding is only valid if imm[4:0]=0. The authorising capability for this operation is <>. -Prerequisites for PREFETCH.R.CAP:: +Prerequisites for Capability Mode:: Zicbop, {cheri_base_ext_name} -Prerequisites for PREFETCH.R:: +Prerequisites for Legacy Mode:: Zicbop, {cheri_legacy_ext_name} Operation:: diff --git a/src/insns/prefetch.w.adoc b/src/insns/prefetch.w.adoc index ed845385..a1fcd95d 100644 --- a/src/insns/prefetch.w.adoc +++ b/src/insns/prefetch.w.adoc @@ -2,17 +2,13 @@ [#PREFETCH_W,reftext="PREFETCH.W"] ==== PREFETCH.W -See <>. - -[#PREFETCH_W_CAP,reftext="PREFETCH.W.CAP"] -==== PREFETCH.W.CAP Synopsis:: Provide a HINT to hardware that a cache block is likely to be accessed by a data write in the near future Capability Mode Mnemonic:: -`prefetch.w.cap offset(cs1)` +`prefetch.w offset(cs1)` Legacy Mode Mnemonic:: `prefetch.w offset(rs1)` @@ -25,13 +21,13 @@ Encoding:: {bits: 5, name: 'imm[4:0]', attr: ['5','zero'], type: 2}, {bits: 3, name: 'funct3', attr: ['3','ORI=110'], type: 8}, {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, - {bits: 5, name: 'funct5', attr: ['5','cap: PREFETCH.W.CAP=00011', 'leg: PREFETCH.W=00011'], type: 3}, + {bits: 5, name: 'funct5', attr: ['5','PREFETCH.W=00011'], type: 3}, {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]'], type: 3}, ]} .... Capability Mode Description:: -A PREFETCH.W.CAP instruction indicates to hardware that the cache block whose +A PREFETCH.W instruction indicates to hardware that the cache block whose effective address is the sum of the base address specified in `cs1` and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by a data write (i.e. store) in the near future. The @@ -53,10 +49,10 @@ likely to be accessed by a data write (i.e. store) in the near future. The encoding is only valid if imm[4:0]=0. The authorising capability for this operation is <>. -Prerequisites for PREFETCH.W.CAP:: +Prerequisites for Capability Mode:: Zicbop, {cheri_base_ext_name} -Prerequisites for PREFETCH.W:: +Prerequisites for Legacy Mode:: Zicbop, {cheri_legacy_ext_name} Operation:: diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc index c59bc6c6..7c2f6703 100644 --- a/src/riscv-integration.adoc +++ b/src/riscv-integration.adoc @@ -1083,7 +1083,7 @@ NOTE: `auth_cap` is <> for Legacy mode and `cs1` for Capability Mode NOTE: Indirect branches are <>, <>, <>, <>, conditional branches are <>. -NOTE: <>, <> issues as a cache block wide store. All +NOTE: <> issues as a cache block wide store. All CMOs operate on the cache block which contains the address. Prefetches check that the capability is tagged, not sealed, has the permission (<>, <>, <>) corresponding to the instruction, and has bounds which From a4dcc01ef573cd0ae66fb4f2eca46f8d25ed585c Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Thu, 8 Feb 2024 13:39:21 +0100 Subject: [PATCH 3/7] fix accidental deletion (working in an airport isn't easy) --- src/insns/cbo.clean.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/insns/cbo.clean.adoc b/src/insns/cbo.clean.adoc index a0153e9d..38a31187 100644 --- a/src/insns/cbo.clean.adoc +++ b/src/insns/cbo.clean.adoc @@ -19,7 +19,7 @@ Encoding:: {bits: 7, name: 'opcode', attr: ['7','MISC-MEM=0001111'], type: 8}, {bits: 5, name: 'funct5', attr: ['5','CBO=0000'], type: 2}, {bits: 3, name: 'funct3', attr: ['3','CBO=010'], type: 8}, - {bits: 5, name: 'cs1/rs1', attr: ['5','base'] + {bits: 5, name: 'cs1/rs1', attr: ['5','base'], type: 4}, {bits: 12, name: 'funct12', attr: ['12','CBO.CLEAN=00.001'], type: 3}, ]} .... From 2577eb62c78ecfaa1189435c9431dfc5ac7af18c Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Thu, 8 Feb 2024 13:58:13 +0100 Subject: [PATCH 4/7] Rename acmp instructions --- src/csv/CHERI_ISA.csv | 24 ++++++++---------------- src/insns/zcmp_cmpop.adoc | 13 ++++--------- src/insns/zcmp_cmpopret.adoc | 13 ++++--------- src/insns/zcmp_cmpopretz.adoc | 13 ++++--------- src/insns/zcmp_cmpush.adoc | 13 ++++--------- src/insns/zcmp_cmva01s.adoc | 13 ++++--------- src/insns/zcmp_cmvsa01.adoc | 13 ++++--------- src/insns/zcmt_cmjalt.adoc | 15 +++++---------- src/insns/zcmt_cmjt.adoc | 15 +++++---------- src/instructions.adoc | 2 +- 10 files changed, 43 insertions(+), 91 deletions(-) diff --git a/src/csv/CHERI_ISA.csv b/src/csv/CHERI_ISA.csv index 252e12a8..ba0c7137 100644 --- a/src/csv/CHERI_ISA.csv +++ b/src/csv/CHERI_ISA.csv @@ -114,22 +114,14 @@ "FSW","✔","✔","","","","✔","✔","Both","","","","","","","","","","","✔","","","","","STORE-FP","","FSW","FSW","Store floating point word via cap","Xstatus.fs==0","","","","","","","" "FLD","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","✔","","","","LOAD-FP","","FLD","FLD","Load floating point double via cap","Xstatus.fs==0","","","","","","","" "FSD","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","✔","","","","STORE-FP","","FSD","FSD","Store floating point double via cap","Xstatus.fs==0","","","","","","","" -"CM.PUSH","✔","✔","","","","✔","","Legacy","","","","","","","","✔","","","","","","","","C2","","","","Push integer stack frame","","","","","","","","" -"CM.POP","✔","✔","","","","✔","","Legacy","","","","","","","","✔","","","","","","","","C2","","","","Pop integer stack frame","","","","","","","","" -"CM.POPRET","✔","✔","","","","✔","","Legacy","","","","","","","","✔","","","","","","","","C2","","","","Pop integer stack frame and return","","","","","","","","" -"CM.POPRETZ","✔","✔","","","","✔","","Legacy","","","","","","","","✔","","","","","","","","C2","","","","Pop integer stack frame and return zero","","","","","","","","" -"CM.MVSA01","✔","✔","","","","✔","","Legacy","","","","","","","","✔","","","","","","","","C2","","","","Move two integer registers","","","","","","","","" -"CM.MVA01S","✔","✔","","","","✔","","Legacy","","","","","","","","✔","","","","","","","","C2","","","","Move two integer registers","","","","","","","","" -"CM.CPUSH","✔","✔","","","","","✔","Capability","","","","","","","","✔","","","","","","","","C2","","CM.PUSH","CM.PUSH","Push capability stack frame","","","","","","","","" -"CM.CPOP","✔","✔","","","","","✔","Capability","","","","","","","","✔","","","","","","","","C2","","CM.POP","CM.POP","Pop capability stack frame","","","","","","","","" -"CM.CPOPRET","✔","✔","","","","","✔","Capability","","","","","","","","✔","","","","","","","","C2","","CM.POPRET","CM.POPRET","Pop capability stack frame and return","","","","","","","","" -"CM.CPOPRETZ","✔","✔","","","","","✔","Capability","","","","","","","","✔","","","","","","","","C2","","CM.POPRETZ","CM.POPRETZ","Pop capability stack frame and return zero","","","","","","","","" -"CM.CMVSA01","✔","✔","","","","","✔","Capability","","","","","","","","✔","","","","","","","","C2","","CM.MVSA01","CM.MVSA01","Move two capability registers","","","","","","","","" -"CM.CMVA01S","✔","✔","","","","","✔","Capability","","","","","","","","✔","","","","","","","","C2","","CM.MVA01S","CM.MVA01S","Move two capability registers","","","","","","","","" -"CM.JALT","✔","✔","","","","✔","","Legacy","","","","","","","","","✔","","","","","","","C2","","","","Table jump and link","","","","","","","","" -"CM.JT","✔","✔","","","","✔","","Legacy","","","","","","","","","✔","","","","","","","C2","","","","Table jump","","","","","","","","" -"CM.CJALT","✔","✔","","","","","✔","Capability","","","","","","","","","✔","","","","","","","C2","","CM.JALT","CM.JALT","Table jump and link","","","","","","","","" -"CM.CJT","✔","✔","","","","","✔","Capability","","","","","","","","","✔","","","","","","","C2","","CM.JT","CM.JT","Table jump","","","","","","","","" +"CM.PUSH","✔","✔","","","","✔","✔","Both","","","","","","","","✔","","","","","","","","C2","","","","Push integer stack frame","","","","","","","","" +"CM.POP","✔","✔","","","","✔","✔","Both","","","","","","","","✔","","","","","","","","C2","","","","Pop integer stack frame","","","","","","","","" +"CM.POPRET","✔","✔","","","","✔","✔","Both","","","","","","","","✔","","","","","","","","C2","","","","Pop integer stack frame and return","","","","","","","","" +"CM.POPRETZ","✔","✔","","","","✔","✔","Both","","","","","","","","✔","","","","","","","","C2","","","","Pop integer stack frame and return zero","","","","","","","","" +"CM.MVSA01","✔","✔","","","","✔","✔","Both","","","","","","","","✔","","","","","","","","C2","","","","Move two integer registers","","","","","","","","" +"CM.MVA01S","✔","✔","","","","✔","✔","Both","","","","","","","","✔","","","","","","","","C2","","","","Move two integer registers","","","","","","","","" +"CM.JALT","✔","✔","","","","✔","✔","Both","","","","","","","","","✔","","","","","","","C2","","","","Table jump and link","","","","","","","","" +"CM.JT","✔","✔","","","","✔","✔","Both","","","","","","","","","✔","","","","","","","C2","","","","Table jump","","","","","","","","" "SH1ADD","✔","✔","","","","✔","✔","Both","","","✔","","","","","","","","","","","","","OP","","SH1ADD","SH1ADD","shift and add, representability check on the result","","","","","","","","" "SH1ADD.UW","✔","✔","","","","✔","✔","Both","","","✔","","","","","","","","","","","","","OP","","SH1ADD.UW","SH1ADD.UW","shift and add, representability check on the result","","","","","","","","" "SH2ADD","✔","✔","","","","✔","✔","Both","","","✔","","","","","","","","","","","","","OP","","SH2ADD","SH2ADD","shift and add, representability check on the result","","","","","","","","" diff --git a/src/insns/zcmp_cmpop.adoc b/src/insns/zcmp_cmpop.adoc index aece8bf9..380a0f6b 100644 --- a/src/insns/zcmp_cmpop.adoc +++ b/src/insns/zcmp_cmpop.adoc @@ -3,16 +3,11 @@ [#CM_POP,reftext="CM.POP"] ==== CM.POP -See <> and cite:[riscv-code-size-spec]. - -[#CM_CPOP,reftext="CM.CPOP"] -==== CM.CPOP - Synopsis:: -Destroy stack frame (CM.CPOP, CM.POP): load the return address register and 0 to 12 saved registers from the stack frame, deallocate the stack frame. 16-bit encodings. +Destroy stack frame (CM.POP): load the return address register and 0 to 12 saved registers from the stack frame, deallocate the stack frame. 16-bit encodings. Capability Mode Mnemonic:: -`cm.cpop \{creg_list\}, -stack_adj` +`cm.pop \{creg_list\}, -stack_adj` Legacy Mode Mnemonics:: `cm.pop \{reg_list\}, -stack_adj` @@ -41,10 +36,10 @@ Load integer registers as specified in _reg_list_. Deallocate stack frame. All a include::load_exceptions.adoc[] -Prerequisites for CM.CPOP:: +Prerequisites for Capability Mode:: {c_cheri_base_ext_names}, Zcmp -Prerequisites for CM.POP:: +Prerequisites for Legacy Mode:: {c_cheri_legacy_ext_names}, Zcmp Operation:: diff --git a/src/insns/zcmp_cmpopret.adoc b/src/insns/zcmp_cmpopret.adoc index 5161be29..1eb7bf57 100644 --- a/src/insns/zcmp_cmpopret.adoc +++ b/src/insns/zcmp_cmpopret.adoc @@ -3,16 +3,11 @@ [#CM_POPRET,reftext="CM.POPRET"] ==== CM.POPRET -See <> and cite:[riscv-code-size-spec]. - -[#CM_CPOPRET,reftext="CM.CPOPRET"] -==== CM.CPOPRET - Synopsis:: -Destroy stack frame (CM.CPOPRET, CM.POPRET): load the return address register and 0 to 12 saved registers from the stack frame, deallocate the stack frame. Return through the return address register. 16-bit encodings. +Destroy stack frame (CM.POPRET): load the return address register and 0 to 12 saved registers from the stack frame, deallocate the stack frame. Return through the return address register. 16-bit encodings. Capability Mode Mnemonic:: -`cm.cpopret \{creg_list\}, -stack_adj` +`cm.popret \{creg_list\}, -stack_adj` Legacy Mode Mnemonics:: `cm.popret \{reg_list\}, -stack_adj` @@ -64,10 +59,10 @@ reported in the CAUSE field of <> or <>: include::pcrel_debug_warning.adoc[] -Prerequisites for CM.CPOPRET:: +Prerequisites for Capability Mode:: {c_cheri_base_ext_names}, Zcmp -Prerequisites for CM.POPRET:: +Prerequisites for Legacy Mode:: {c_cheri_legacy_ext_names}, Zcmp Operation:: diff --git a/src/insns/zcmp_cmpopretz.adoc b/src/insns/zcmp_cmpopretz.adoc index 56138288..bc542a8a 100644 --- a/src/insns/zcmp_cmpopretz.adoc +++ b/src/insns/zcmp_cmpopretz.adoc @@ -3,16 +3,11 @@ [#CM_POPRETZ,reftext="CM.POPRETZ"] ==== CM.POPRETZ -See <> and cite:[riscv-code-size-spec]. - -[#CM_CPOPRETZ,reftext="CM.CPOPRETZ"] -==== CM.CPOPRETZ - Synopsis:: -Destroy stack frame (CM.CPOPRETZ, CM.POPRETZ): load the return address register and register 0 to 12 saved registers from the stack frame, deallocate the stack frame. Move zero into argument register zero. Return through the return address register. 16-bit encodings. +Destroy stack frame (CM.POPRETZ): load the return address register and register 0 to 12 saved registers from the stack frame, deallocate the stack frame. Move zero into argument register zero. Return through the return address register. 16-bit encodings. Capability Mode Mnemonic:: -`cm.cpopretz \{creg_list\}, -stack_adj` +`cm.popretz \{creg_list\}, -stack_adj` Legacy Mode Mnemonics:: `cm.popretz \{reg_list\}, -stack_adj` @@ -64,10 +59,10 @@ reported in the CAUSE field of <> or <>: include::pcrel_debug_warning.adoc[] -Prerequisites for CM.CPOPRETZ:: +Prerequisites for Capability Mode:: {c_cheri_base_ext_names}, Zcmp -Prerequisites for CM.POPRETZ:: +Prerequisites for Legacy Mode:: {c_cheri_legacy_ext_names}, Zcmp Operation:: diff --git a/src/insns/zcmp_cmpush.adoc b/src/insns/zcmp_cmpush.adoc index 0800f9b4..8a28c3f4 100644 --- a/src/insns/zcmp_cmpush.adoc +++ b/src/insns/zcmp_cmpush.adoc @@ -3,16 +3,11 @@ [#CM_PUSH,reftext="CM.PUSH"] ==== CM.PUSH -See <> and cite:[riscv-code-size-spec]. - -[#CM_CPUSH,reftext="CM.CPUSH"] -==== CM.CPUSH - Synopsis:: -Create stack frame (CM.CPUSH, CM.PUSH): store the return address register and 0 to 12 saved registers to the stack frame, optionally allocate additional stack space. 16-bit encodings. +Create stack frame (CM.PUSH): store the return address register and 0 to 12 saved registers to the stack frame, optionally allocate additional stack space. 16-bit encodings. Capability Mode Mnemonic:: -`cm.cpush \{creg_list\}, -stack_adj` +`cm.push \{creg_list\}, -stack_adj` Legacy Mode Mnemonics:: `cm.push \{reg_list\}, -stack_adj` @@ -41,10 +36,10 @@ Create stack frame, store integer registers as specified in _reg_list_. Optional include::store_exceptions.adoc[] -Prerequisites for CM.CPUSH:: +Prerequisites for Capability Mode:: {c_cheri_base_ext_names}, Zcmp -Prerequisites for CM.PUSH:: +Prerequisites for Legacy Mode:: {c_cheri_legacy_ext_names}, Zcmp Operation:: diff --git a/src/insns/zcmp_cmva01s.adoc b/src/insns/zcmp_cmva01s.adoc index f8950334..1b993877 100644 --- a/src/insns/zcmp_cmva01s.adoc +++ b/src/insns/zcmp_cmva01s.adoc @@ -3,16 +3,11 @@ [#CM_MVA01S,reftext="CM.MVA01S"] ==== CM.MVA01S -See <> and cite:[riscv-code-size-spec]. - -[#CM_CMVA01S,reftext="CM.CMVA01S"] -==== CM.CMVA01S - Synopsis:: -CM.CMVA01S, CM.MVA01S: Move two saved registers into argument registers 0 and 1. +Move two saved registers into argument registers 0 and 1. Capability Mode Mnemonic:: -`cm.cmva01s cr1s', cr2s'` +`cm.mva01s cr1s', cr2s'` Legacy Mode Mnemonics:: `cm.mva01s r1s', r2s'` @@ -38,10 +33,10 @@ Atomically move two capability registers `ca0` and `ca1` into `cs0-cs7`. Legacy Mode Description:: Atomically move two integer registers `a0` and `a1` into `s0-s7`. -Prerequisites for CM.CMVA01S:: +Prerequisites for Capability Mode:: {c_cheri_base_ext_names}, Zcmp -Prerequisites for CM.MVA01S:: +Prerequisites for Legacy Mode:: {c_cheri_legacy_ext_names}, Zcmp Operation:: diff --git a/src/insns/zcmp_cmvsa01.adoc b/src/insns/zcmp_cmvsa01.adoc index 6f6a131f..a1015451 100644 --- a/src/insns/zcmp_cmvsa01.adoc +++ b/src/insns/zcmp_cmvsa01.adoc @@ -3,16 +3,11 @@ [#CM_MVSA01,reftext="CM.MVSA01"] ==== CM.MVSA01 -See <> and cite:[riscv-code-size-spec]. - -[#CM_CMVSA01,reftext="CM.CMVSA01"] -==== CM.CMVSA01 - Synopsis:: -CM.CMVSA01, CM.MVSA01: Move argument registers 0 and 1 into two saved registers. +CM.MVSA01: Move argument registers 0 and 1 into two saved registers. Capability Mode Mnemonic:: -`cm.cmvsa01 cr1s', cr2s'` +`cm.mvsa01 cr1s', cr2s'` Legacy Mode Mnemonics:: `cm.mvsa01 r1s', r2s'` @@ -38,10 +33,10 @@ Atomically move two saved capability registers `cs0-cs7` into `ca0` and `ca1`. Legacy Mode Description:: Atomically move two saved integer registers `s0-s7` into `a0` and `a1`. -Prerequisites for CM.CMVSA01:: +Prerequisites for Capability Mode:: {c_cheri_base_ext_names}, Zcmp -Prerequisites for CM.MVSA01:: +Prerequisites for Legacy Mode:: {c_cheri_legacy_ext_names}, Zcmp Operation:: diff --git a/src/insns/zcmt_cmjalt.adoc b/src/insns/zcmt_cmjalt.adoc index 720a3b57..b905981a 100644 --- a/src/insns/zcmt_cmjalt.adoc +++ b/src/insns/zcmt_cmjalt.adoc @@ -3,16 +3,11 @@ [#CM_JALT,reftext="CM.JALT"] ==== CM.JALT -See <> and cite:[riscv-code-size-spec]. - -[#CM_CJALT,reftext="CM.CJALT"] -==== CM.CJALT - Synopsis:: -Jump via table with link (CM.CJALT, CM.JALT), 16-bit encodings +Jump via table with link (CM.JALT), 16-bit encodings Capability Mode Mnemonic:: -`cm.cjalt _index_` +`cm.jalt _index_` Legacy Mode Mnemonics:: `cm.jalt _index_` @@ -30,7 +25,7 @@ Encoding:: [NOTE] - For this encoding to decode as <>/<>, _index>=32_, otherwise it decodes as <>/<>. + For this encoding to decode as <<>, _index>=32_, otherwise it decodes as <>. Capability Mode Description:: Redirect instruction fetch via the jump table defined by the indexing via `jvtc.address+ index*XLEN/8`, checking every byte of jump table access against <> bounds (not against <>) and requiring <>. Link to `cra`. @@ -57,10 +52,10 @@ reported in the CAUSE field of <> or <>: include::pcrel_debug_warning.adoc[] -Prerequisites for CM.CJALT:: +Prerequisites for Capability Mode:: {c_cheri_base_ext_names}, Zcmt -Prerequisites for CM.JALT:: +Prerequisites for Legacy Mode:: {c_cheri_legacy_ext_names}, Zcmt Operation:: diff --git a/src/insns/zcmt_cmjt.adoc b/src/insns/zcmt_cmjt.adoc index 7eb16660..a366e73a 100644 --- a/src/insns/zcmt_cmjt.adoc +++ b/src/insns/zcmt_cmjt.adoc @@ -3,16 +3,11 @@ [#CM_JT,reftext="CM.JT"] ==== CM.JT -See <> and cite:[riscv-code-size-spec]. - -[#CM_CJT,reftext="CM.CJT"] -==== CM.CJT - Synopsis:: -Jump via table with link (CM.CJT, CM.JT), 16-bit encodings +Jump via table with link (CM.JT), 16-bit encodings Capability Mode Mnemonic:: -`cm.cjt _index_` +`cm.jt _index_` Legacy Mode Mnemonics:: `cm.jt _index_` @@ -30,7 +25,7 @@ Encoding:: [NOTE] - For this encoding to decode as <>/<>, _index<32_, otherwise it decodes as <>/<>. + For this encoding to decode as <>, _index<32_, otherwise it decodes as <>. Capability Mode Description:: Redirect instruction fetch via the jump table defined by the indexing via `jvtc.address+ index*XLEN/8`, checking every byte of jump table access against <> bounds (not against <>) and requiring <>. @@ -57,10 +52,10 @@ reported in the CAUSE field of <> or <>: include::pcrel_debug_warning.adoc[] -Prerequisites for CM.CJT:: +Prerequisites for Capability Mode:: {c_cheri_base_ext_names}, Zcmt -Prerequisites for CM.JT:: +Prerequisites for Legacy Mode:: {c_cheri_legacy_ext_names}, Zcmt Operation:: diff --git a/src/instructions.adoc b/src/instructions.adoc index 0dab8e15..e013eb12 100644 --- a/src/instructions.adoc +++ b/src/instructions.adoc @@ -255,7 +255,7 @@ include::img/jvtcreg.edn[] All instruction fetches from the jump vector table are checked against <>. -See <>, <>, <>, <>. +See <>, <>. If the access to the jump table succeeds, then the instructions execute as follows: From 4f5f693860204437b894297409ebaab9c2e5032c Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Wed, 21 Feb 2024 12:50:32 +0000 Subject: [PATCH 5/7] remove exception check on PCC being sealed --- src/riscv-integration.adoc | 1 - 1 file changed, 1 deletion(-) diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc index e73ad4b5..7635d779 100644 --- a/src/riscv-integration.adoc +++ b/src/riscv-integration.adoc @@ -1059,7 +1059,6 @@ NOTE: `auth_cap` is <> for Legacy mode and `cs1` for Capability Mode | Instructions | Xcause | Xtval. TYPE | Xtval. CAUSE | Description | Check 6+| *All instructions have these exception checks first* | All | {cheri_excep_mcause} | {cheri_excep_type_pcc} | {cheri_excep_cause_tag} | <> tag | not(<>.tag) -| All | {cheri_excep_mcause} | {cheri_excep_type_pcc} | {cheri_excep_cause_seal} | <> seal | isCapSealed(<>) | All | {cheri_excep_mcause} | {cheri_excep_type_pcc} | {cheri_excep_cause_perm} | <> permission | not(<>.<>) | All | {cheri_excep_mcause} | {cheri_excep_type_pcc} | {cheri_excep_cause_length} | <> length | Any byte of current instruction out of <> bounds 6+| *CSR/Xret additional exception check* From 5c7aad26c03742ce2858280922ec290620e7b60a Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Fri, 23 Feb 2024 09:59:37 +0000 Subject: [PATCH 6/7] revert line and add note --- src/riscv-integration.adoc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc index 7635d779..48c4e3e2 100644 --- a/src/riscv-integration.adoc +++ b/src/riscv-integration.adoc @@ -1059,6 +1059,7 @@ NOTE: `auth_cap` is <> for Legacy mode and `cs1` for Capability Mode | Instructions | Xcause | Xtval. TYPE | Xtval. CAUSE | Description | Check 6+| *All instructions have these exception checks first* | All | {cheri_excep_mcause} | {cheri_excep_type_pcc} | {cheri_excep_cause_tag} | <> tag | not(<>.tag) +| All | {cheri_excep_mcause} | {cheri_excep_type_pcc} | {cheri_excep_cause_seal} | <> seal | isCapSealed(<>)^1^ | All | {cheri_excep_mcause} | {cheri_excep_type_pcc} | {cheri_excep_cause_perm} | <> permission | not(<>.<>) | All | {cheri_excep_mcause} | {cheri_excep_type_pcc} | {cheri_excep_cause_length} | <> length | Any byte of current instruction out of <> bounds 6+| *CSR/Xret additional exception check* @@ -1089,6 +1090,8 @@ NOTE: `auth_cap` is <> for Legacy mode and `cs1` for Capability Mode | capability stores | 6 | N/A | N/A |capability alignment | Misaligned capability store |========================================================================================= +^1^ this check is architecturally required, but is not required in an implementation + NOTE: Indirect branches are <>, <>, conditional branches are <>. NOTE: <> issues as a cache block wide store. All From 53d161eee7819086b7fd259755154544142c94bd Mon Sep 17 00:00:00 2001 From: Tariq Kurd Date: Fri, 23 Feb 2024 18:08:10 +0000 Subject: [PATCH 7/7] Update src/riscv-integration.adoc Co-authored-by: Alexander Richardson Signed-off-by: Tariq Kurd --- src/riscv-integration.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc index 48c4e3e2..dff6354a 100644 --- a/src/riscv-integration.adoc +++ b/src/riscv-integration.adoc @@ -1090,7 +1090,7 @@ NOTE: `auth_cap` is <> for Legacy mode and `cs1` for Capability Mode | capability stores | 6 | N/A | N/A |capability alignment | Misaligned capability store |========================================================================================= -^1^ this check is architecturally required, but is not required in an implementation +^1^ This check is architecturally required, but is impossible to encounter so may not required in an implementation. NOTE: Indirect branches are <>, <>, conditional branches are <>.