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Differentiate "get capability value" and "get capability low half" #341
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PAC and MTE, and all the various TBI things, expose the non-address portion in C as part of the address. Not doing so is unnecessary complication, and becomes problematic very quickly for uintptr_t code generation. |
But we can't permit |
uintptr_t needs to have full XLEN range for arithmetic, that's non-negotiable in the real world. That means the address needs to be the full XLEN bits. |
Not quite. |
I don't think a world where |
I'd like to see a concrete example of something that this would break. I've not encountered one yet, but I can believe it would exist. |
If revocation occurs during the update thanks to some other thread's free, the addresses seen for the pointers to the old allocation will change, because they'll no longer be tagged, giving incorrect offsets. One can argue about what ISO C actually says about whether this is defined behaviour, but this is a real world pattern seen all over the place that would break if the address changes when the tag is cleared. |
I see. Do you have a reference to where you've seen that? I've heard people mention it but never actually seen it. |
We found some in the desktop porting work that had the wrong provenance, so here are a few from that that come to mind. There are surely many others though, I remember seeing others, just not what they were in. https://gitlab.freedesktop.org/xorg/xserver/-/blob/386b54fbe95711e6ecb5c23cfdbf25a1571acf7b/dix/privates.c#L203 We're also often only aware of the ones that get the provenance wrong, the rest work fine and don't show up when porting. |
Thanks. I shouldn’t be surprised it’s xlib. |
(On second thought, moving this out from #340)
There's a subtle assumption in most CHERI work to date that the address field of a capability is a full machine word and is one half of the CHERI capability. There are a few reasons that might not always be true.
MTE, and TBI-like schemes in general, might strongly differentiate "the address field" from "the bottom half of the capability".
Similarly, a capability encoding like outlined in CHERIoT-sail: v2? Permuted capability encoding optimized for 33-bit busses
See https://github.com/CTSRD-CHERI/cheri-specification/wiki/Tracking-discussion-for-CGetAddr-vs-CToPtr-vs-as-integer-alias-vs-CGetLow for (many) more but incomplete thoughts on untangling this knot. It might be nice if the base Zcheri specification took this possible division into account and reserved the relevant opcodes, even if most CHERI capability encodings will have identical behavior for some pairs.
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