From 1cd124b578863f6fa2acd446923d3e1365a9483a Mon Sep 17 00:00:00 2001 From: Martin Kaiser Date: Thu, 1 Aug 2024 15:01:41 +0200 Subject: [PATCH] hybrid: fix a sentence that uses the old definition of M Integer pointer mode is now M = 1. Fix a sentence that hasn't been converted to the new definition of the M bit. Signed-off-by: Martin Kaiser --- src/riscv-hybrid-integration.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/riscv-hybrid-integration.adoc b/src/riscv-hybrid-integration.adoc index f0654fe3..58ecff1b 100644 --- a/src/riscv-hybrid-integration.adoc +++ b/src/riscv-hybrid-integration.adoc @@ -48,7 +48,7 @@ The CHERI execution mode is key in providing backwards compatibility with the base RISC-V ISA. RISC-V software is able to execute unchanged in implementations supporting both {cheri_base_ext_name} and {cheri_default_ext_name} provided that the <> capability is installed in <> and <> -(with <>, i.e. in pass:attributes,quotes[{cheri_int_mode_name}]). +(with <>, i.e. in pass:attributes,quotes[{cheri_int_mode_name}]). Setting both registers to <> ensures that: * All permissions are granted