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Add note to clarify coloring scheme of CSR bit fields (red & green) #156

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james-ball-qualcomm opened this issue Oct 21, 2024 · 2 comments · Fixed by #160
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Add note to clarify coloring scheme of CSR bit fields (red & green) #156

james-ball-qualcomm opened this issue Oct 21, 2024 · 2 comments · Fixed by #160
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@james-ball-qualcomm james-ball-qualcomm self-assigned this Oct 21, 2024
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Also found and fixed this typo in the latest Priv ISA manual repository and fixed it in UDB too:
riscv/riscv-isa-manual#1693

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BTW, what exactly are grey fields? Are they WPRI or read-only-0?

@james-ball-qualcomm james-ball-qualcomm linked a pull request Oct 22, 2024 that will close this issue
Fix for issue 156 #160
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Fix for issue 156 riscv-software-src/riscv-unified-db
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@dhower-qc @james-ball-qualcomm