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Diodes PCIe switch support #5609

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merged 4 commits into from
Oct 27, 2023
Merged

Diodes PCIe switch support #5609

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e239e71
dt-bindings: PCI: brcmstb: add optional property - "brcm,tperst-clk-ms"
P33M Sep 20, 2023
697b933
drivers: pci: brcmstb: optionally extend Tperst_clk time during link-up
P33M Sep 20, 2023
bdc0ca3
arm: dt: add dtparams for PCIe reset timing override
P33M Sep 20, 2023
9ffba7f
arm: dt: bcm2712: don't unconditionally enable MPS read completions
P33M Oct 26, 2023
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8 changes: 8 additions & 0 deletions Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -77,6 +77,14 @@ properties:
minItems: 1
maxItems: 3

brcm,tperst-clk-ms:
category: optional
type: int
description: u32 giving the number of milliseconds to extend
the time between internal release of fundamental reset and
the deassertion of the external PERST# pin. This has the
effect of increasing the Tperst_clk phase of link init.

required:
- compatible
- reg
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2 changes: 2 additions & 0 deletions arch/arm/boot/dts/bcm2711-rpi-cm4.dts
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Expand Up @@ -446,5 +446,7 @@ i2c_csi_dsi0: &i2c0 {
cam1_reg = <&cam1_reg>,"status";
cam1_reg_gpio = <&cam1_reg>,"gpio:4",
<&cam1_reg>,"gpio:0=", <&gpio>;

pcie_tperst_clk_ms = <&pcie0>,"brcm,tperst-clk-ms:0";
};
};
3 changes: 3 additions & 0 deletions arch/arm/boot/dts/bcm2712-rpi-5-b.dts
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Expand Up @@ -160,6 +160,7 @@
};

rp1_target: &pcie2 {
brcm,enable-mps-rcb;
brcm,vdm-qos-map = <0xbbaa9888>;
aspm-no-l0s;
status = "okay";
Expand Down Expand Up @@ -814,6 +815,8 @@ spi10_cs_pins: &spi10_cs_gpio1 {};
pciex1 = <&pciex1>, "status";
pciex1_gen = <&pciex1> , "max-link-speed:0";
pciex1_no_l0s = <&pciex1>, "aspm-no-l0s?";
pciex1_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0";
pcie_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0";
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We also need a line or two for each parameter in the top section of the README.

random = <&random>, "status";
rtc_bbat_vchg = <&rpi_rtc>, "trickle-charge-microvolt:0";
spi = <&spi0>, "status";
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1 change: 0 additions & 1 deletion arch/arm/boot/dts/bcm2712.dtsi
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Expand Up @@ -1086,7 +1086,6 @@
0x00 0x00000000
0x10 0x00000000>;

brcm,enable-mps-rcb;
brcm,enable-l1ss;
status = "disabled";
};
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7 changes: 7 additions & 0 deletions arch/arm/boot/dts/overlays/README
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Expand Up @@ -280,6 +280,10 @@ Params:
(2711 only, but not applicable on CM4S)
N.B. USB-A ports on 4B are subsequently disabled

pcie_tperst_clk_ms Add N milliseconds between PCIe reference clock
activation and PERST# deassertion
(CM4 and 2712, default "0")

pciex1 Set to "on" to enable the external PCIe link
(2712 only, default "off")

Expand All @@ -290,6 +294,9 @@ Params:
PCIe link for devices that have broken
implementations (2712 only, default "off")

pciex1_tperst_clk_ms Alias for pcie_tperst_clk_ms
(2712 only, default "0")

spi Set to "on" to enable the spi interfaces
(default "off")

Expand Down
24 changes: 23 additions & 1 deletion drivers/pci/controller/pcie-brcmstb.c
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Expand Up @@ -138,6 +138,7 @@

#define PCIE_MISC_HARD_PCIE_HARD_DEBUG pcie->reg_offsets[PCIE_HARD_DEBUG]
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK 0x8
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
#define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK 0x00200000
Expand Down Expand Up @@ -352,6 +353,7 @@ struct brcm_pcie {
bool (*rc_mode)(struct brcm_pcie *pcie);
struct subdev_regulators *sr;
bool ep_wakeup_capable;
u32 tperst_clk_ms;
};

static inline bool is_bmips(const struct brcm_pcie *pcie)
Expand Down Expand Up @@ -1388,9 +1390,28 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie)
u16 nlw, cls, lnksta;
bool ssc_good = false;
int ret, i;
u32 tmp;

/* Unassert the fundamental reset */
pcie->perst_set(pcie, 0);
if (pcie->tperst_clk_ms) {
/*
* Increase Tperst_clk time by forcing PERST# output low while
* the internal reset is released, so the PLL generates stable
* refclk output further in advance of PERST# deassertion.
*/
tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK);
writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);

pcie->perst_set(pcie, 0);
msleep(pcie->tperst_clk_ms);

tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK);
writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
} else {
pcie->perst_set(pcie, 0);
}

/*
* Wait for 100ms after PERST# deassertion; see PCIe CEM specification
Expand Down Expand Up @@ -1923,6 +1944,7 @@ static int brcm_pcie_probe(struct platform_device *pdev)
pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
pcie->l1ss = of_property_read_bool(np, "brcm,enable-l1ss");
pcie->rcb_mps_mode = of_property_read_bool(np, "brcm,enable-mps-rcb");
of_property_read_u32(np, "brcm,tperst-clk-ms", &pcie->tperst_clk_ms);

ret = clk_prepare_enable(pcie->clk);
if (ret) {
Expand Down