From e239e7102aa89cb2fb89089ecbfd2b3a8e5f8590 Mon Sep 17 00:00:00 2001 From: Jonathan Bell Date: Wed, 20 Sep 2023 10:04:15 +0100 Subject: [PATCH 1/4] dt-bindings: PCI: brcmstb: add optional property - "brcm,tperst-clk-ms" This property can be used to delay deassertion of external fundamental reset, which may be useful for endpoints that require an extended time for internal setup to complete. Signed-off-by: Jonathan Bell --- Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 7e15aae7d69e97..ad313d76eb7c4b 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -77,6 +77,14 @@ properties: minItems: 1 maxItems: 3 + brcm,tperst-clk-ms: + category: optional + type: int + description: u32 giving the number of milliseconds to extend + the time between internal release of fundamental reset and + the deassertion of the external PERST# pin. This has the + effect of increasing the Tperst_clk phase of link init. + required: - compatible - reg From 697b93349f2a3eba68a8a834e4b150015353c217 Mon Sep 17 00:00:00 2001 From: Jonathan Bell Date: Wed, 20 Sep 2023 13:01:11 +0100 Subject: [PATCH 2/4] drivers: pci: brcmstb: optionally extend Tperst_clk time during link-up The RC has a feature that allows for manual control over the deassertion of the PERST# output pin, which allows the time between refclk active and reset deassert at the EP to be increased. Signed-off-by: Jonathan Bell --- drivers/pci/controller/pcie-brcmstb.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 34f795101475f3..8cbcb6f7af2135 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -138,6 +138,7 @@ #define PCIE_MISC_HARD_PCIE_HARD_DEBUG pcie->reg_offsets[PCIE_HARD_DEBUG] #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK 0x8 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 #define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK 0x00200000 @@ -352,6 +353,7 @@ struct brcm_pcie { bool (*rc_mode)(struct brcm_pcie *pcie); struct subdev_regulators *sr; bool ep_wakeup_capable; + u32 tperst_clk_ms; }; static inline bool is_bmips(const struct brcm_pcie *pcie) @@ -1388,9 +1390,28 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) u16 nlw, cls, lnksta; bool ssc_good = false; int ret, i; + u32 tmp; /* Unassert the fundamental reset */ - pcie->perst_set(pcie, 0); + if (pcie->tperst_clk_ms) { + /* + * Increase Tperst_clk time by forcing PERST# output low while + * the internal reset is released, so the PLL generates stable + * refclk output further in advance of PERST# deassertion. + */ + tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK); + writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + + pcie->perst_set(pcie, 0); + msleep(pcie->tperst_clk_ms); + + tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK); + writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + } else { + pcie->perst_set(pcie, 0); + } /* * Wait for 100ms after PERST# deassertion; see PCIe CEM specification @@ -1923,6 +1944,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); pcie->l1ss = of_property_read_bool(np, "brcm,enable-l1ss"); pcie->rcb_mps_mode = of_property_read_bool(np, "brcm,enable-mps-rcb"); + of_property_read_u32(np, "brcm,tperst-clk-ms", &pcie->tperst_clk_ms); ret = clk_prepare_enable(pcie->clk); if (ret) { From bdc0ca3257951e4f0474dd7867d6f74d00994fb3 Mon Sep 17 00:00:00 2001 From: Jonathan Bell Date: Wed, 20 Sep 2023 13:04:54 +0100 Subject: [PATCH 3/4] arm: dt: add dtparams for PCIe reset timing override The Pi 5 variant gets two parameters so that the CM4-compatible name will also work on Pi 5. Signed-off-by: Jonathan Bell --- arch/arm/boot/dts/bcm2711-rpi-cm4.dts | 2 ++ arch/arm/boot/dts/bcm2712-rpi-5-b.dts | 2 ++ arch/arm/boot/dts/overlays/README | 7 +++++++ 3 files changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts index a5aae0a145d3b3..a94a79715bb9cf 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts @@ -446,5 +446,7 @@ i2c_csi_dsi0: &i2c0 { cam1_reg = <&cam1_reg>,"status"; cam1_reg_gpio = <&cam1_reg>,"gpio:4", <&cam1_reg>,"gpio:0=", <&gpio>; + + pcie_tperst_clk_ms = <&pcie0>,"brcm,tperst-clk-ms:0"; }; }; diff --git a/arch/arm/boot/dts/bcm2712-rpi-5-b.dts b/arch/arm/boot/dts/bcm2712-rpi-5-b.dts index db58d9662105b0..8f7f6f970421af 100644 --- a/arch/arm/boot/dts/bcm2712-rpi-5-b.dts +++ b/arch/arm/boot/dts/bcm2712-rpi-5-b.dts @@ -814,6 +814,8 @@ spi10_cs_pins: &spi10_cs_gpio1 {}; pciex1 = <&pciex1>, "status"; pciex1_gen = <&pciex1> , "max-link-speed:0"; pciex1_no_l0s = <&pciex1>, "aspm-no-l0s?"; + pciex1_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0"; + pcie_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0"; random = <&random>, "status"; rtc_bbat_vchg = <&rpi_rtc>, "trickle-charge-microvolt:0"; spi = <&spi0>, "status"; diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README index d9ef0cd7bb1cc1..1f3379caf79582 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -280,6 +280,10 @@ Params: (2711 only, but not applicable on CM4S) N.B. USB-A ports on 4B are subsequently disabled + pcie_tperst_clk_ms Add N milliseconds between PCIe reference clock + activation and PERST# deassertion + (CM4 and 2712, default "0") + pciex1 Set to "on" to enable the external PCIe link (2712 only, default "off") @@ -290,6 +294,9 @@ Params: PCIe link for devices that have broken implementations (2712 only, default "off") + pciex1_tperst_clk_ms Alias for pcie_tperst_clk_ms + (2712 only, default "0") + spi Set to "on" to enable the spi interfaces (default "off") From 9ffba7f9e53ab64d6e3583d7bf4ece60a19c6237 Mon Sep 17 00:00:00 2001 From: Jonathan Bell Date: Thu, 26 Oct 2023 13:47:54 +0100 Subject: [PATCH 4/4] arm: dt: bcm2712: don't unconditionally enable MPS read completions RP1 supports it, but it's not a given that an arbitrary EP device on PCIE2 will. Migrate the property to the rp1_target fragment. Signed-off-by: Jonathan Bell --- arch/arm/boot/dts/bcm2712-rpi-5-b.dts | 1 + arch/arm/boot/dts/bcm2712.dtsi | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm2712-rpi-5-b.dts b/arch/arm/boot/dts/bcm2712-rpi-5-b.dts index 8f7f6f970421af..1edc2394a5324e 100644 --- a/arch/arm/boot/dts/bcm2712-rpi-5-b.dts +++ b/arch/arm/boot/dts/bcm2712-rpi-5-b.dts @@ -160,6 +160,7 @@ }; rp1_target: &pcie2 { + brcm,enable-mps-rcb; brcm,vdm-qos-map = <0xbbaa9888>; aspm-no-l0s; status = "okay"; diff --git a/arch/arm/boot/dts/bcm2712.dtsi b/arch/arm/boot/dts/bcm2712.dtsi index e75cd97f033cea..11d0b69d089385 100644 --- a/arch/arm/boot/dts/bcm2712.dtsi +++ b/arch/arm/boot/dts/bcm2712.dtsi @@ -1086,7 +1086,6 @@ 0x00 0x00000000 0x10 0x00000000>; - brcm,enable-mps-rcb; brcm,enable-l1ss; status = "disabled"; };