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MKL02Z4.h
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MKL02Z4.h
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/*
** ###################################################################
** Processors: MKL02Z32CAF4
** MKL02Z32VFG4
** MKL02Z16VFG4
** MKL02Z8VFG4
** MKL02Z32VFK4
** MKL02Z16VFK4
** MKL02Z32VFM4
** MKL02Z16VFM4
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manuals: KL02P20M48SF0RM Rev2.1, July 2013
** KL02P32M48SF0RM Rev3.1, July 2013
**
** Version: rev. 1.1, 2013-04-05
** Build: b150309
**
** Abstract:
** This header file implements peripheral memory map for MKL02Z4
** processor.
**
** Copyright (c) 1997 - 2013 Freescale Semiconductor, Inc.
** All Rights Reserved.
**
** http: www.freescale.com
** mail: [email protected]
**
** Revisions:
** - rev. 1.0 (2012-10-04)
** Initial version.
** - rev. 1.1 (2013-04-05)
** Changed start of doxygen comment.
**
** ###################################################################
*/
/*!
* @file MKL02Z4.h
* @version 1.1
* @date 2013-04-05
* @brief Peripheral memory map for MKL02Z4
*
* This header file implements peripheral memory map for MKL02Z4 processor.
*/
/* ----------------------------------------------------------------------------
-- MCU activation
---------------------------------------------------------------------------- */
/* Prevention from multiple including the same memory map */
#if !defined(MCU_MKL02Z4) /* Check if memory map has not been already included */
#define MCU_MKL02Z4
/* Check if another memory map has not been also included */
#if (defined(MCU_ACTIVE))
#error MKL02Z4 memory map: There is already included another memory map. Only one memory map can be included.
#endif /* (defined(MCU_ACTIVE)) */
#define MCU_ACTIVE
#include <stdint.h>
/** Memory map major version (memory maps with equal major version number are
* compatible) */
#define MCU_MEM_MAP_VERSION 0x0100u
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0001u
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/*!
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
typedef enum {
INT_Initial_Stack_Pointer = 0, /**< Initial Stack Pointer */
INT_Initial_Program_Counter = 1, /**< Initial Program Counter */
INT_NMI = 2, /**< Non-maskable Interrupt (NMI) */
INT_Hard_Fault = 3, /**< Hard Fault */
INT_Reserved4 = 4, /**< Reserved interrupt */
INT_Reserved5 = 5, /**< Reserved interrupt */
INT_Reserved6 = 6, /**< Reserved interrupt */
INT_Reserved7 = 7, /**< Reserved interrupt */
INT_Reserved8 = 8, /**< Reserved interrupt */
INT_Reserved9 = 9, /**< Reserved interrupt */
INT_Reserved10 = 10, /**< Reserved interrupt */
INT_SVCall = 11, /**< Supervisor call (SVCall) */
INT_Reserved12 = 12, /**< Reserved interrupt */
INT_Reserved13 = 13, /**< Reserved interrupt */
INT_PendableSrvReq = 14, /**< Pendable request for system service (PendableSrvReq) */
INT_SysTick = 15, /**< System tick timer (SysTick) */
INT_Reserved16 = 16, /**< Reserved interrupt */
INT_Reserved17 = 17, /**< Reserved interrupt */
INT_Reserved18 = 18, /**< Reserved interrupt */
INT_Reserved19 = 19, /**< Reserved interrupt */
INT_Reserved20 = 20, /**< Reserved interrupt */
INT_FTFA = 21, /**< FTFA command complete and read collision */
INT_LVD_LVW = 22, /**< Low-voltage detect, low-voltage warning */
INT_Reserved23 = 23, /**< Reserved interrupt */
INT_I2C0 = 24, /**< I2C0 interrupt */
INT_I2C1 = 25, /**< I2C1 interrupt */
INT_SPI0 = 26, /**< SPI0 single interrupt vector for all sources */
INT_Reserved27 = 27, /**< Reserved interrupt */
INT_UART0 = 28, /**< UART0 status and error */
INT_Reserved29 = 29, /**< Reserved interrupt */
INT_Reserved30 = 30, /**< Reserved interrupt */
INT_ADC0 = 31, /**< ADC0 interrupt */
INT_CMP0 = 32, /**< CMP0 interrupt */
INT_TPM0 = 33, /**< TPM0 single interrupt vector for all sources */
INT_TPM1 = 34, /**< TPM1 single interrupt vector for all sources */
INT_Reserved35 = 35, /**< Reserved interrupt */
INT_Reserved36 = 36, /**< Reserved interrupt */
INT_Reserved37 = 37, /**< Reserved interrupt */
INT_Reserved38 = 38, /**< Reserved interrupt */
INT_Reserved39 = 39, /**< Reserved interrupt */
INT_Reserved40 = 40, /**< Reserved interrupt */
INT_Reserved41 = 41, /**< Reserved interrupt */
INT_Reserved42 = 42, /**< Reserved interrupt */
INT_MCG = 43, /**< MCG interrupt */
INT_LPTMR0 = 44, /**< LPTMR0 interrupt */
INT_Reserved45 = 45, /**< Reserved interrupt */
INT_PORTA = 46, /**< PORTA pin detect */
INT_PORTB = 47 /**< PORTB pin detect */
} IRQInterruptIndex;
/*!
* @}
*/ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Peripheral type defines
---------------------------------------------------------------------------- */
/*!
* @addtogroup Peripheral_defines Peripheral type defines
* @{
*/
/*
** Start of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma push
#pragma anon_unions
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- ADC
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Peripheral ADC
* @{
*/
/** ADC - Peripheral register structure */
typedef struct ADC_MemMap {
uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
uint8_t RESERVED_0[4];
uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
} volatile *ADC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- ADC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
* @{
*/
/* ADC - Register accessors */
#define ADC_SC1_REG(base,index) ((base)->SC1[index])
#define ADC_CFG1_REG(base) ((base)->CFG1)
#define ADC_CFG2_REG(base) ((base)->CFG2)
#define ADC_R_REG(base,index) ((base)->R[index])
#define ADC_CV1_REG(base) ((base)->CV1)
#define ADC_CV2_REG(base) ((base)->CV2)
#define ADC_SC2_REG(base) ((base)->SC2)
#define ADC_SC3_REG(base) ((base)->SC3)
#define ADC_OFS_REG(base) ((base)->OFS)
#define ADC_PG_REG(base) ((base)->PG)
#define ADC_CLPD_REG(base) ((base)->CLPD)
#define ADC_CLPS_REG(base) ((base)->CLPS)
#define ADC_CLP4_REG(base) ((base)->CLP4)
#define ADC_CLP3_REG(base) ((base)->CLP3)
#define ADC_CLP2_REG(base) ((base)->CLP2)
#define ADC_CLP1_REG(base) ((base)->CLP1)
#define ADC_CLP0_REG(base) ((base)->CLP0)
/*!
* @}
*/ /* end of group ADC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- ADC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Masks ADC Register Masks
* @{
*/
/* SC1 Bit Fields */
#define ADC_SC1_ADCH_MASK 0x1Fu
#define ADC_SC1_ADCH_SHIFT 0
#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
#define ADC_SC1_AIEN_MASK 0x40u
#define ADC_SC1_AIEN_SHIFT 6
#define ADC_SC1_COCO_MASK 0x80u
#define ADC_SC1_COCO_SHIFT 7
/* CFG1 Bit Fields */
#define ADC_CFG1_ADICLK_MASK 0x3u
#define ADC_CFG1_ADICLK_SHIFT 0
#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
#define ADC_CFG1_MODE_MASK 0xCu
#define ADC_CFG1_MODE_SHIFT 2
#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
#define ADC_CFG1_ADLSMP_MASK 0x10u
#define ADC_CFG1_ADLSMP_SHIFT 4
#define ADC_CFG1_ADIV_MASK 0x60u
#define ADC_CFG1_ADIV_SHIFT 5
#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
#define ADC_CFG1_ADLPC_MASK 0x80u
#define ADC_CFG1_ADLPC_SHIFT 7
/* CFG2 Bit Fields */
#define ADC_CFG2_ADLSTS_MASK 0x3u
#define ADC_CFG2_ADLSTS_SHIFT 0
#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
#define ADC_CFG2_ADHSC_MASK 0x4u
#define ADC_CFG2_ADHSC_SHIFT 2
#define ADC_CFG2_ADACKEN_MASK 0x8u
#define ADC_CFG2_ADACKEN_SHIFT 3
#define ADC_CFG2_MUXSEL_MASK 0x10u
#define ADC_CFG2_MUXSEL_SHIFT 4
/* R Bit Fields */
#define ADC_R_D_MASK 0xFFFFu
#define ADC_R_D_SHIFT 0
#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
/* CV1 Bit Fields */
#define ADC_CV1_CV_MASK 0xFFFFu
#define ADC_CV1_CV_SHIFT 0
#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
/* CV2 Bit Fields */
#define ADC_CV2_CV_MASK 0xFFFFu
#define ADC_CV2_CV_SHIFT 0
#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
/* SC2 Bit Fields */
#define ADC_SC2_REFSEL_MASK 0x3u
#define ADC_SC2_REFSEL_SHIFT 0
#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
#define ADC_SC2_ACREN_MASK 0x8u
#define ADC_SC2_ACREN_SHIFT 3
#define ADC_SC2_ACFGT_MASK 0x10u
#define ADC_SC2_ACFGT_SHIFT 4
#define ADC_SC2_ACFE_MASK 0x20u
#define ADC_SC2_ACFE_SHIFT 5
#define ADC_SC2_ADTRG_MASK 0x40u
#define ADC_SC2_ADTRG_SHIFT 6
#define ADC_SC2_ADACT_MASK 0x80u
#define ADC_SC2_ADACT_SHIFT 7
/* SC3 Bit Fields */
#define ADC_SC3_AVGS_MASK 0x3u
#define ADC_SC3_AVGS_SHIFT 0
#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
#define ADC_SC3_AVGE_MASK 0x4u
#define ADC_SC3_AVGE_SHIFT 2
#define ADC_SC3_ADCO_MASK 0x8u
#define ADC_SC3_ADCO_SHIFT 3
#define ADC_SC3_CALF_MASK 0x40u
#define ADC_SC3_CALF_SHIFT 6
#define ADC_SC3_CAL_MASK 0x80u
#define ADC_SC3_CAL_SHIFT 7
/* OFS Bit Fields */
#define ADC_OFS_OFS_MASK 0xFFFFu
#define ADC_OFS_OFS_SHIFT 0
#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
/* PG Bit Fields */
#define ADC_PG_PG_MASK 0xFFFFu
#define ADC_PG_PG_SHIFT 0
#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
/* CLPD Bit Fields */
#define ADC_CLPD_CLPD_MASK 0x3Fu
#define ADC_CLPD_CLPD_SHIFT 0
#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
/* CLPS Bit Fields */
#define ADC_CLPS_CLPS_MASK 0x3Fu
#define ADC_CLPS_CLPS_SHIFT 0
#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
/* CLP4 Bit Fields */
#define ADC_CLP4_CLP4_MASK 0x3FFu
#define ADC_CLP4_CLP4_SHIFT 0
#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
/* CLP3 Bit Fields */
#define ADC_CLP3_CLP3_MASK 0x1FFu
#define ADC_CLP3_CLP3_SHIFT 0
#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
/* CLP2 Bit Fields */
#define ADC_CLP2_CLP2_MASK 0xFFu
#define ADC_CLP2_CLP2_SHIFT 0
#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
/* CLP1 Bit Fields */
#define ADC_CLP1_CLP1_MASK 0x7Fu
#define ADC_CLP1_CLP1_SHIFT 0
#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
/* CLP0 Bit Fields */
#define ADC_CLP0_CLP0_MASK 0x3Fu
#define ADC_CLP0_CLP0_SHIFT 0
#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
/*!
* @}
*/ /* end of group ADC_Register_Masks */
/* ADC - Peripheral instance base addresses */
/** Peripheral ADC0 base pointer */
#define ADC0_BASE_PTR ((ADC_MemMapPtr)0x4003B000u)
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASE_PTRS { ADC0_BASE_PTR }
/* ----------------------------------------------------------------------------
-- ADC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
* @{
*/
/* ADC - Register instance definitions */
/* ADC0 */
#define ADC0_SC1A ADC_SC1_REG(ADC0_BASE_PTR,0)
#define ADC0_SC1B ADC_SC1_REG(ADC0_BASE_PTR,1)
#define ADC0_CFG1 ADC_CFG1_REG(ADC0_BASE_PTR)
#define ADC0_CFG2 ADC_CFG2_REG(ADC0_BASE_PTR)
#define ADC0_RA ADC_R_REG(ADC0_BASE_PTR,0)
#define ADC0_RB ADC_R_REG(ADC0_BASE_PTR,1)
#define ADC0_CV1 ADC_CV1_REG(ADC0_BASE_PTR)
#define ADC0_CV2 ADC_CV2_REG(ADC0_BASE_PTR)
#define ADC0_SC2 ADC_SC2_REG(ADC0_BASE_PTR)
#define ADC0_SC3 ADC_SC3_REG(ADC0_BASE_PTR)
#define ADC0_OFS ADC_OFS_REG(ADC0_BASE_PTR)
#define ADC0_PG ADC_PG_REG(ADC0_BASE_PTR)
#define ADC0_CLPD ADC_CLPD_REG(ADC0_BASE_PTR)
#define ADC0_CLPS ADC_CLPS_REG(ADC0_BASE_PTR)
#define ADC0_CLP4 ADC_CLP4_REG(ADC0_BASE_PTR)
#define ADC0_CLP3 ADC_CLP3_REG(ADC0_BASE_PTR)
#define ADC0_CLP2 ADC_CLP2_REG(ADC0_BASE_PTR)
#define ADC0_CLP1 ADC_CLP1_REG(ADC0_BASE_PTR)
#define ADC0_CLP0 ADC_CLP0_REG(ADC0_BASE_PTR)
/* ADC - Register array accessors */
#define ADC0_SC1(index) ADC_SC1_REG(ADC0_BASE_PTR,index)
#define ADC0_R(index) ADC_R_REG(ADC0_BASE_PTR,index)
/*!
* @}
*/ /* end of group ADC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group ADC_Peripheral */
/* ----------------------------------------------------------------------------
-- BP
---------------------------------------------------------------------------- */
/*!
* @addtogroup BP_Peripheral BP
* @{
*/
/** BP - Peripheral register structure */
typedef struct BP_MemMap {
uint32_t CTRL; /**< FlashPatch Control Register, offset: 0x0 */
uint8_t RESERVED_0[4];
uint32_t COMP[2]; /**< FlashPatch Comparator Register 0..FlashPatch Comparator Register 1, array offset: 0x8, array step: 0x4 */
uint8_t RESERVED_1[4032];
uint32_t PID4; /**< Peripheral Identification Register 4., offset: 0xFD0 */
uint32_t PID5; /**< Peripheral Identification Register 5., offset: 0xFD4 */
uint32_t PID6; /**< Peripheral Identification Register 6., offset: 0xFD8 */
uint32_t PID7; /**< Peripheral Identification Register 7., offset: 0xFDC */
uint32_t PID0; /**< Peripheral Identification Register 0., offset: 0xFE0 */
uint32_t PID1; /**< Peripheral Identification Register 1., offset: 0xFE4 */
uint32_t PID2; /**< Peripheral Identification Register 2., offset: 0xFE8 */
uint32_t PID3; /**< Peripheral Identification Register 3., offset: 0xFEC */
uint32_t CID0; /**< Component Identification Register 0., offset: 0xFF0 */
uint32_t CID1; /**< Component Identification Register 1., offset: 0xFF4 */
uint32_t CID2; /**< Component Identification Register 2., offset: 0xFF8 */
uint32_t CID3; /**< Component Identification Register 3., offset: 0xFFC */
} volatile *BP_MemMapPtr;
/* ----------------------------------------------------------------------------
-- BP - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup BP_Register_Accessor_Macros BP - Register accessor macros
* @{
*/
/* BP - Register accessors */
#define BP_CTRL_REG(base) ((base)->CTRL)
#define BP_COMP_REG(base,index) ((base)->COMP[index])
#define BP_PID4_REG(base) ((base)->PID4)
#define BP_PID5_REG(base) ((base)->PID5)
#define BP_PID6_REG(base) ((base)->PID6)
#define BP_PID7_REG(base) ((base)->PID7)
#define BP_PID0_REG(base) ((base)->PID0)
#define BP_PID1_REG(base) ((base)->PID1)
#define BP_PID2_REG(base) ((base)->PID2)
#define BP_PID3_REG(base) ((base)->PID3)
#define BP_CID0_REG(base) ((base)->CID0)
#define BP_CID1_REG(base) ((base)->CID1)
#define BP_CID2_REG(base) ((base)->CID2)
#define BP_CID3_REG(base) ((base)->CID3)
/*!
* @}
*/ /* end of group BP_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- BP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup BP_Register_Masks BP Register Masks
* @{
*/
/*!
* @}
*/ /* end of group BP_Register_Masks */
/* BP - Peripheral instance base addresses */
/** Peripheral BP base pointer */
#define BP_BASE_PTR ((BP_MemMapPtr)0xE0002000u)
/** Array initializer of BP peripheral base pointers */
#define BP_BASE_PTRS { BP_BASE_PTR }
/* ----------------------------------------------------------------------------
-- BP - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup BP_Register_Accessor_Macros BP - Register accessor macros
* @{
*/
/* BP - Register instance definitions */
/* BP */
#define BP_CTRL BP_CTRL_REG(BP_BASE_PTR)
#define BP_COMP0 BP_COMP_REG(BP_BASE_PTR,0)
#define BP_COMP1 BP_COMP_REG(BP_BASE_PTR,1)
#define BP_PID4 BP_PID4_REG(BP_BASE_PTR)
#define BP_PID5 BP_PID5_REG(BP_BASE_PTR)
#define BP_PID6 BP_PID6_REG(BP_BASE_PTR)
#define BP_PID7 BP_PID7_REG(BP_BASE_PTR)
#define BP_PID0 BP_PID0_REG(BP_BASE_PTR)
#define BP_PID1 BP_PID1_REG(BP_BASE_PTR)
#define BP_PID2 BP_PID2_REG(BP_BASE_PTR)
#define BP_PID3 BP_PID3_REG(BP_BASE_PTR)
#define BP_CID0 BP_CID0_REG(BP_BASE_PTR)
#define BP_CID1 BP_CID1_REG(BP_BASE_PTR)
#define BP_CID2 BP_CID2_REG(BP_BASE_PTR)
#define BP_CID3 BP_CID3_REG(BP_BASE_PTR)
/* BP - Register array accessors */
#define BP_COMP(index) BP_COMP_REG(BP_BASE_PTR,index)
/*!
* @}
*/ /* end of group BP_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group BP_Peripheral */
/* ----------------------------------------------------------------------------
-- CMP
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Peripheral CMP
* @{
*/
/** CMP - Peripheral register structure */
typedef struct CMP_MemMap {
uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
} volatile *CMP_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CMP - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
* @{
*/
/* CMP - Register accessors */
#define CMP_CR0_REG(base) ((base)->CR0)
#define CMP_CR1_REG(base) ((base)->CR1)
#define CMP_FPR_REG(base) ((base)->FPR)
#define CMP_SCR_REG(base) ((base)->SCR)
#define CMP_DACCR_REG(base) ((base)->DACCR)
#define CMP_MUXCR_REG(base) ((base)->MUXCR)
/*!
* @}
*/ /* end of group CMP_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CMP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Masks CMP Register Masks
* @{
*/
/* CR0 Bit Fields */
#define CMP_CR0_HYSTCTR_MASK 0x3u
#define CMP_CR0_HYSTCTR_SHIFT 0
#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
#define CMP_CR0_FILTER_CNT_MASK 0x70u
#define CMP_CR0_FILTER_CNT_SHIFT 4
#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
/* CR1 Bit Fields */
#define CMP_CR1_EN_MASK 0x1u
#define CMP_CR1_EN_SHIFT 0
#define CMP_CR1_OPE_MASK 0x2u
#define CMP_CR1_OPE_SHIFT 1
#define CMP_CR1_COS_MASK 0x4u
#define CMP_CR1_COS_SHIFT 2
#define CMP_CR1_INV_MASK 0x8u
#define CMP_CR1_INV_SHIFT 3
#define CMP_CR1_PMODE_MASK 0x10u
#define CMP_CR1_PMODE_SHIFT 4
#define CMP_CR1_TRIGM_MASK 0x20u
#define CMP_CR1_TRIGM_SHIFT 5
#define CMP_CR1_WE_MASK 0x40u
#define CMP_CR1_WE_SHIFT 6
#define CMP_CR1_SE_MASK 0x80u
#define CMP_CR1_SE_SHIFT 7
/* FPR Bit Fields */
#define CMP_FPR_FILT_PER_MASK 0xFFu
#define CMP_FPR_FILT_PER_SHIFT 0
#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
/* SCR Bit Fields */
#define CMP_SCR_COUT_MASK 0x1u
#define CMP_SCR_COUT_SHIFT 0
#define CMP_SCR_CFF_MASK 0x2u
#define CMP_SCR_CFF_SHIFT 1
#define CMP_SCR_CFR_MASK 0x4u
#define CMP_SCR_CFR_SHIFT 2
#define CMP_SCR_IEF_MASK 0x8u
#define CMP_SCR_IEF_SHIFT 3
#define CMP_SCR_IER_MASK 0x10u
#define CMP_SCR_IER_SHIFT 4
/* DACCR Bit Fields */
#define CMP_DACCR_VOSEL_MASK 0x3Fu
#define CMP_DACCR_VOSEL_SHIFT 0
#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
#define CMP_DACCR_VRSEL_MASK 0x40u
#define CMP_DACCR_VRSEL_SHIFT 6
#define CMP_DACCR_DACEN_MASK 0x80u
#define CMP_DACCR_DACEN_SHIFT 7
/* MUXCR Bit Fields */
#define CMP_MUXCR_MSEL_MASK 0x7u
#define CMP_MUXCR_MSEL_SHIFT 0
#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
#define CMP_MUXCR_PSEL_MASK 0x38u
#define CMP_MUXCR_PSEL_SHIFT 3
#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
/*!
* @}
*/ /* end of group CMP_Register_Masks */
/* CMP - Peripheral instance base addresses */
/** Peripheral CMP0 base pointer */
#define CMP0_BASE_PTR ((CMP_MemMapPtr)0x40073000u)
/** Array initializer of CMP peripheral base pointers */
#define CMP_BASE_PTRS { CMP0_BASE_PTR }
/* ----------------------------------------------------------------------------
-- CMP - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
* @{
*/
/* CMP - Register instance definitions */
/* CMP0 */
#define CMP0_CR0 CMP_CR0_REG(CMP0_BASE_PTR)
#define CMP0_CR1 CMP_CR1_REG(CMP0_BASE_PTR)
#define CMP0_FPR CMP_FPR_REG(CMP0_BASE_PTR)
#define CMP0_SCR CMP_SCR_REG(CMP0_BASE_PTR)
#define CMP0_DACCR CMP_DACCR_REG(CMP0_BASE_PTR)
#define CMP0_MUXCR CMP_MUXCR_REG(CMP0_BASE_PTR)
/*!
* @}
*/ /* end of group CMP_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group CMP_Peripheral */
/* ----------------------------------------------------------------------------
-- CoreDebug
---------------------------------------------------------------------------- */
/*!
* @addtogroup CoreDebug_Peripheral CoreDebug
* @{
*/
/** CoreDebug - Peripheral register structure */
typedef struct CoreDebug_MemMap {
union { /* offset: 0x0 */
uint32_t base_DHCSR_Read; /**< Debug Halting Control and Status Register, offset: 0x0 */
uint32_t base_DHCSR_Write; /**< Debug Halting Control and Status Register, offset: 0x0 */
};
uint32_t base_DCRSR; /**< Debug Core Register Selector Register, offset: 0x4 */
uint32_t base_DCRDR; /**< Debug Core Register Data Register, offset: 0x8 */
uint32_t base_DEMCR; /**< Debug Exception and Monitor Control Register, offset: 0xC */
} volatile *CoreDebug_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CoreDebug - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CoreDebug_Register_Accessor_Macros CoreDebug - Register accessor macros
* @{
*/
/* CoreDebug - Register accessors */
#define CoreDebug_base_DHCSR_Read_REG(base) ((base)->base_DHCSR_Read)
#define CoreDebug_base_DHCSR_Write_REG(base) ((base)->base_DHCSR_Write)
#define CoreDebug_base_DCRSR_REG(base) ((base)->base_DCRSR)
#define CoreDebug_base_DCRDR_REG(base) ((base)->base_DCRDR)
#define CoreDebug_base_DEMCR_REG(base) ((base)->base_DEMCR)
/*!
* @}
*/ /* end of group CoreDebug_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CoreDebug Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CoreDebug_Register_Masks CoreDebug Register Masks
* @{
*/
/*!
* @}
*/ /* end of group CoreDebug_Register_Masks */
/* CoreDebug - Peripheral instance base addresses */
/** Peripheral CoreDebug base pointer */
#define CoreDebug_BASE_PTR ((CoreDebug_MemMapPtr)0xE000EDF0u)
/** Array initializer of CoreDebug peripheral base pointers */
#define CoreDebug_BASE_PTRS { CoreDebug_BASE_PTR }
/* ----------------------------------------------------------------------------
-- CoreDebug - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CoreDebug_Register_Accessor_Macros CoreDebug - Register accessor macros
* @{
*/
/* CoreDebug - Register instance definitions */
/* CoreDebug */
#define DHCSR_Read CoreDebug_base_DHCSR_Read_REG(CoreDebug_BASE_PTR)
#define DHCSR_Write CoreDebug_base_DHCSR_Write_REG(CoreDebug_BASE_PTR)
#define DCRSR CoreDebug_base_DCRSR_REG(CoreDebug_BASE_PTR)
#define DCRDR CoreDebug_base_DCRDR_REG(CoreDebug_BASE_PTR)
#define DEMCR CoreDebug_base_DEMCR_REG(CoreDebug_BASE_PTR)
/*!
* @}
*/ /* end of group CoreDebug_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group CoreDebug_Peripheral */
/* ----------------------------------------------------------------------------
-- DWT
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWT_Peripheral DWT
* @{
*/
/** DWT - Peripheral register structure */
typedef struct DWT_MemMap {
uint32_t CTRL; /**< Control Register, offset: 0x0 */
uint8_t RESERVED_0[24];
uint32_t PCSR; /**< Program Counter Sample Register, offset: 0x1C */
struct { /* offset: 0x20, array step: 0x10 */
uint32_t COMP; /**< Comparator Register 0..Comparator Register 1, array offset: 0x20, array step: 0x10 */
uint32_t MASK; /**< Mask Register 0..Mask Register 1, array offset: 0x24, array step: 0x10 */
uint32_t FUNCTION; /**< Function Register 0..Function Register 1, array offset: 0x28, array step: 0x10 */
uint8_t RESERVED_0[4];
} COMPARATOR[2];
} volatile *DWT_MemMapPtr;
/* ----------------------------------------------------------------------------
-- DWT - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWT_Register_Accessor_Macros DWT - Register accessor macros
* @{
*/
/* DWT - Register accessors */
#define DWT_CTRL_REG(base) ((base)->CTRL)
#define DWT_PCSR_REG(base) ((base)->PCSR)
#define DWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP)
#define DWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK)
#define DWT_FUNCTION_REG(base,index) ((base)->COMPARATOR[index].FUNCTION)
/*!
* @}
*/ /* end of group DWT_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- DWT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWT_Register_Masks DWT Register Masks
* @{
*/
/*!
* @}
*/ /* end of group DWT_Register_Masks */
/* DWT - Peripheral instance base addresses */
/** Peripheral DWT base pointer */
#define DWT_BASE_PTR ((DWT_MemMapPtr)0xE0001000u)
/** Array initializer of DWT peripheral base pointers */
#define DWT_BASE_PTRS { DWT_BASE_PTR }
/* ----------------------------------------------------------------------------
-- DWT - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWT_Register_Accessor_Macros DWT - Register accessor macros
* @{
*/
/* DWT - Register instance definitions */
/* DWT */
#define DWT_CTRL DWT_CTRL_REG(DWT_BASE_PTR)
#define DWT_PCSR DWT_PCSR_REG(DWT_BASE_PTR)
#define DWT_COMP0 DWT_COMP_REG(DWT_BASE_PTR,0)
#define DWT_MASK0 DWT_MASK_REG(DWT_BASE_PTR,0)
#define DWT_FUNCTION0 DWT_FUNCTION_REG(DWT_BASE_PTR,0)
#define DWT_COMP1 DWT_COMP_REG(DWT_BASE_PTR,1)
#define DWT_MASK1 DWT_MASK_REG(DWT_BASE_PTR,1)
#define DWT_FUNCTION1 DWT_FUNCTION_REG(DWT_BASE_PTR,1)
/* DWT - Register array accessors */
#define DWT_COMP(index) DWT_COMP_REG(DWT_BASE_PTR,index)
#define DWT_MASK(index) DWT_MASK_REG(DWT_BASE_PTR,index)
#define DWT_FUNCTION(index) DWT_FUNCTION_REG(DWT_BASE_PTR,index)
/*!
* @}
*/ /* end of group DWT_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group DWT_Peripheral */
/* ----------------------------------------------------------------------------
-- FGPIO
---------------------------------------------------------------------------- */
/*!
* @addtogroup FGPIO_Peripheral FGPIO
* @{
*/
/** FGPIO - Peripheral register structure */
typedef struct FGPIO_MemMap {
uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
} volatile *FGPIO_MemMapPtr;
/* ----------------------------------------------------------------------------
-- FGPIO - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup FGPIO_Register_Accessor_Macros FGPIO - Register accessor macros
* @{
*/
/* FGPIO - Register accessors */
#define FGPIO_PDOR_REG(base) ((base)->PDOR)
#define FGPIO_PSOR_REG(base) ((base)->PSOR)
#define FGPIO_PCOR_REG(base) ((base)->PCOR)
#define FGPIO_PTOR_REG(base) ((base)->PTOR)
#define FGPIO_PDIR_REG(base) ((base)->PDIR)
#define FGPIO_PDDR_REG(base) ((base)->PDDR)
/*!
* @}
*/ /* end of group FGPIO_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- FGPIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FGPIO_Register_Masks FGPIO Register Masks
* @{
*/
/* PDOR Bit Fields */
#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
#define FGPIO_PDOR_PDO_SHIFT 0
#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
/* PSOR Bit Fields */
#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
#define FGPIO_PSOR_PTSO_SHIFT 0
#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
/* PCOR Bit Fields */
#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
#define FGPIO_PCOR_PTCO_SHIFT 0
#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
/* PTOR Bit Fields */
#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
#define FGPIO_PTOR_PTTO_SHIFT 0
#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
/* PDIR Bit Fields */
#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
#define FGPIO_PDIR_PDI_SHIFT 0
#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
/* PDDR Bit Fields */
#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
#define FGPIO_PDDR_PDD_SHIFT 0
#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
/*!
* @}
*/ /* end of group FGPIO_Register_Masks */
/* FGPIO - Peripheral instance base addresses */
/** Peripheral FGPIOA base pointer */
#define FGPIOA_BASE_PTR ((FGPIO_MemMapPtr)0xF80FF000u)
/** Peripheral FGPIOB base pointer */
#define FGPIOB_BASE_PTR ((FGPIO_MemMapPtr)0xF80FF040u)
/** Array initializer of FGPIO peripheral base pointers */
#define FGPIO_BASE_PTRS { FGPIOA_BASE_PTR, FGPIOB_BASE_PTR }
/* ----------------------------------------------------------------------------
-- FGPIO - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup FGPIO_Register_Accessor_Macros FGPIO - Register accessor macros
* @{
*/
/* FGPIO - Register instance definitions */
/* FGPIOA */
#define FGPIOA_PDOR FGPIO_PDOR_REG(FGPIOA_BASE_PTR)
#define FGPIOA_PSOR FGPIO_PSOR_REG(FGPIOA_BASE_PTR)
#define FGPIOA_PCOR FGPIO_PCOR_REG(FGPIOA_BASE_PTR)
#define FGPIOA_PTOR FGPIO_PTOR_REG(FGPIOA_BASE_PTR)
#define FGPIOA_PDIR FGPIO_PDIR_REG(FGPIOA_BASE_PTR)
#define FGPIOA_PDDR FGPIO_PDDR_REG(FGPIOA_BASE_PTR)
/* FGPIOB */
#define FGPIOB_PDOR FGPIO_PDOR_REG(FGPIOB_BASE_PTR)
#define FGPIOB_PSOR FGPIO_PSOR_REG(FGPIOB_BASE_PTR)
#define FGPIOB_PCOR FGPIO_PCOR_REG(FGPIOB_BASE_PTR)
#define FGPIOB_PTOR FGPIO_PTOR_REG(FGPIOB_BASE_PTR)
#define FGPIOB_PDIR FGPIO_PDIR_REG(FGPIOB_BASE_PTR)
#define FGPIOB_PDDR FGPIO_PDDR_REG(FGPIOB_BASE_PTR)
/*!
* @}
*/ /* end of group FGPIO_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group FGPIO_Peripheral */
/* ----------------------------------------------------------------------------
-- FTFA
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTFA_Peripheral FTFA
* @{
*/