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Inconsistent cycle count #26

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GoogleCodeExporter opened this issue Jan 26, 2016 · 0 comments
Open

Inconsistent cycle count #26

GoogleCodeExporter opened this issue Jan 26, 2016 · 0 comments

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@GoogleCodeExporter
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Experimenting with AGC API I've bumped into a strange phenomenon. Running the 
agc_engine() step by step, and printing the registers before calling the 
function, I got the following result:
PendDelay:0 A:0 L:0 Z: 4000 BB:0
PendDelay:0 A:0 L:0 Z: 4001 BB:0
PendDelay:1 A:0 L:0 Z: 4001 BB:0
PendDelay:0 A:0 L:0 Z: 4001 BB:0
PendDelay:0 A:12063 L:0 Z: 4002 BB:0
PendDelay:1 A:12063 L:0 Z: 4002 BB:0
PendDelay:0 A:12063 L:0 Z: 4002 BB:0
PendDelay:0 A:0 L:0 Z: 4003 BB:12003
PendDelay:0 A:0 L:0 Z: 2563 BB:12003

The ROM image was Artemis072, so the instructions are the following:

INHINT                                         
CAF      GOBB                                  
XCH      BBANK 
TCF      GOPROG
...

The INHINT and TCF consumes 1 machine cycle correctly, but the XCH and CAF 
consumes 3 machine cycles which contradicts to the language manual. It says 
that both of these two instructions needs 2 MCT to finish. I changed line 
agc_engince.c:1891   
    State->PendDelay = i; 
to
    State->PendDelay = i-1;
with the intention to decrease the machine cycle by 1 for every multi-MCT 
instuctions. This modification doesn't have any bad effect on the scheduled 
processes, I checked V16N36 and it worked correctly.

Original issue reported on code.google.com by [email protected] on 16 Nov 2010 at 10:43

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