- Revision numbers following the ArchC release
- Instructions with cycles annotations
- Two new .ac files to use with MPSoCBench (block and nonblock)
- mips_isa.cpp using the reserved work DATA_PORT to data request. See the commit message.
- Interrupt handler support. It is inactive in standalone simulator.
- New PowerSC tables
- Revision numbers following the ArchC release
- PowerSC support with power tables
- Memory instructions only use word size methods
- Added id register for core identification
- Bugfix in DEBUG mode
- Updated syscall emulation library to setup multiprocessor stack (this version can be used with the updated compilers)
- Changed name from mips1 to mips
- Added binary utilities support files
- ArchC 2.0 compliant
- Removed delayed assignements by creating the npc register
- Created lo and hi registers and removed them from RB[32] and RB[33]
- Added license headers
- Changed the assembly information for 'break' instruction
- Model compliant with ArchC 2.0beta1
- Added 'bgtu' pseudo-insn
- Added alternative assembly syntaxes to the lwl and lwr instructions
- Fixed the operand encoding of the nop 'instruction'
- Included assembly language syntax information
- Use ArchC support for debug messages: ac_debug_model.H
- Use operator[] syntax to read register banks, which is faster
- Included optimization instruction methods for compiled simulation
- Separate nop instruction from sll to optimize simulation
- Included file for GDB integration
- Model passed selected Mediabench and Mibench applications