From f2da16205bebe3bb8000afd63ab370934a11b64f Mon Sep 17 00:00:00 2001
From: Jim Huang <jserv.tw@gmail.com>
Date: Sat, 17 Dec 2022 22:02:02 +0800
Subject: [PATCH] Specify RV_N_REGS via C enum

In preparation for potential RV64 support, we might avoid specifying
essential constants manually. Instead, using C enum would thereby
automate the definitions.
---
 src/riscv.c         | 8 ++++----
 src/riscv.h         | 1 +
 src/riscv_private.h | 8 +++-----
 3 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/src/riscv.c b/src/riscv.c
index 30bc03e1..fb4a59ee 100644
--- a/src/riscv.c
+++ b/src/riscv.c
@@ -63,14 +63,14 @@ riscv_word_t rv_get_pc(riscv_t *rv)
 void rv_set_reg(riscv_t *rv, uint32_t reg, riscv_word_t in)
 {
     assert(rv);
-    if (reg < RV_NUM_REGS && reg != rv_reg_zero)
+    if (reg < RV_N_REGS && reg != rv_reg_zero)
         rv->X[reg] = in;
 }
 
 riscv_word_t rv_get_reg(riscv_t *rv, uint32_t reg)
 {
     assert(rv);
-    if (reg < RV_NUM_REGS)
+    if (reg < RV_N_REGS)
         return rv->X[reg];
 
     return ~0U;
@@ -117,7 +117,7 @@ void rv_delete(riscv_t *rv)
 void rv_reset(riscv_t *rv, riscv_word_t pc)
 {
     assert(rv);
-    memset(rv->X, 0, sizeof(uint32_t) * RV_NUM_REGS);
+    memset(rv->X, 0, sizeof(uint32_t) * RV_N_REGS);
 
     /* set the reset address */
     rv->PC = pc;
@@ -132,7 +132,7 @@ void rv_reset(riscv_t *rv, riscv_word_t pc)
 
 #if RV32_HAS(EXT_F)
     /* reset float registers */
-    memset(rv->F, 0, sizeof(float) * RV_NUM_REGS);
+    memset(rv->F, 0, sizeof(float) * RV_N_REGS);
     rv->csr_fcsr = 0;
 #endif
 
diff --git a/src/riscv.h b/src/riscv.h
index 199fa01c..cbb044f8 100644
--- a/src/riscv.h
+++ b/src/riscv.h
@@ -57,6 +57,7 @@ enum {
     rv_reg_t4,
     rv_reg_t5,
     rv_reg_t6,
+    RV_N_REGS, /* NOTE: shoule be the last */
 };
 
 /* forward declaration for internal structure */
diff --git a/src/riscv_private.h b/src/riscv_private.h
index cc5b18f9..d6db8475 100644
--- a/src/riscv_private.h
+++ b/src/riscv_private.h
@@ -13,8 +13,6 @@
 #include "decode.h"
 #include "riscv.h"
 
-#define RV_NUM_REGS 32
-
 /* CSRs */
 enum {
     /* floating point */
@@ -79,7 +77,7 @@ struct riscv_internal {
     riscv_io_t io;
 
     /* integer registers */
-    riscv_word_t X[RV_NUM_REGS];
+    riscv_word_t X[RV_N_REGS];
     riscv_word_t PC;
 
     /* user provided data */
@@ -96,8 +94,8 @@ struct riscv_internal {
 #if RV32_HAS(EXT_F)
     /* float registers */
     union {
-        riscv_float_t F[RV_NUM_REGS];
-        uint32_t F_int[RV_NUM_REGS]; /* integer shortcut */
+        riscv_float_t F[RV_N_REGS];
+        uint32_t F_int[RV_N_REGS]; /* integer shortcut */
     };
     uint32_t csr_fcsr;
 #endif