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Can you elaborate more? Do you mean that one may offload the entire stage after its forward pass? (And meanwhile bring back another stage from CPU to do the next forward?)
Can you elaborate more? Do you mean that one may offload the entire stage after its forward pass? (And meanwhile bring back another stage from CPU to do the next forward?)
It seems like pipelining could possibly greatly simplify the implementation of a feature such as fairscale's OffloadModel https://fairscale.readthedocs.io/en/latest/deep_dive/offload.html
Is this something that is feasible?
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