From ef7c39956c7e2faf6625f90397df21b496c2abb3 Mon Sep 17 00:00:00 2001 From: sumguytho Date: Sat, 13 Apr 2024 21:05:24 +0300 Subject: [PATCH] fixed kwargs not being expanded for actions on bit registers, adjusted tests to catch this issue --- pymodbus/datastore/simulator.py | 5 +++-- test/sub_server/test_simulator.py | 14 ++++++++++++-- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/pymodbus/datastore/simulator.py b/pymodbus/datastore/simulator.py index 4c73a86cc..31b61d856 100644 --- a/pymodbus/datastore/simulator.py +++ b/pymodbus/datastore/simulator.py @@ -435,7 +435,7 @@ class ModbusSimulatorContext(ModbusBaseSlaveContext): "write": [ --> allow write, efault is ReadOnly [5, 5] --> start, end bytes, repeated as needed ], - "bits": [ --> Define bits (1 register == 1 byte) + "bits": [ --> Define bits (1 register == 2 bytes) [30, 31], --> start, end registers, repeated as needed {"addr": [32, 34], "value": 0xF1}, --> with value {"addr": [35, 36], "action": "increment"}, --> with action @@ -602,8 +602,9 @@ def getValues(self, func_code, address, count=1): for i in range(real_address, real_address + reg_count): reg = self.registers[i] if reg.action: + kwargs = reg.action_kwargs or {} self.action_methods[reg.action]( - self.registers, i, reg, reg.action_kwargs + self.registers, i, reg, **kwargs ) self.registers[i].count_read += 1 while count and bit_index < 16: diff --git a/test/sub_server/test_simulator.py b/test/sub_server/test_simulator.py index 46288e57f..aeefed8b7 100644 --- a/test/sub_server/test_simulator.py +++ b/test/sub_server/test_simulator.py @@ -528,7 +528,12 @@ def test_simulator_action_increment( exc_simulator.registers[30].value = regs[0] exc_simulator.registers[31].value = regs[1] for expect_value in expected: - regs = exc_simulator.getValues(FX_READ_REG, 30, reg_count) + if celltype != CellType.BITS: + regs = exc_simulator.getValues(FX_READ_REG, 30, reg_count) + else: + reg_bits = exc_simulator.getValues(FX_READ_BIT, 30 * 16, 16) + reg_value = sum([ bit * 2 ** i for i, bit in enumerate(reg_bits)]) + regs = [reg_value] if reg_count == 1: assert expect_value == regs[0], f"type({celltype})" else: @@ -563,7 +568,12 @@ def test_simulator_action_random(self, celltype, minval, maxval): is_int = celltype != CellType.FLOAT32 reg_count = 1 if celltype in (CellType.BITS, CellType.UINT16) else 2 for _i in range(100): - regs = exc_simulator.getValues(FX_READ_REG, 30, reg_count) + if celltype != CellType.BITS: + regs = exc_simulator.getValues(FX_READ_REG, 30, reg_count) + else: + reg_bits = exc_simulator.getValues(FX_READ_BIT, 30 * 16, 16) + reg_value = sum([ bit * 2 ** i for i, bit in enumerate(reg_bits)]) + regs = [reg_value] if reg_count == 1: new_value = regs[0] else: