From 446ce4f9f1255ab61594d281476d97a2c5408db2 Mon Sep 17 00:00:00 2001
From: Cyril Koenig <cyril27koenig@gmail.com>
Date: Mon, 22 Apr 2024 19:25:55 +0200
Subject: [PATCH] fpga: Add new vregfile

---
 Bender.yml                       | 10 ++++++-
 hw/ip/spatz/src/vregfile_fpga.sv | 47 ++++++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+), 1 deletion(-)
 create mode 100644 hw/ip/spatz/src/vregfile_fpga.sv

diff --git a/Bender.yml b/Bender.yml
index e51c0e3a..03c60fff 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -140,7 +140,6 @@ sources:
   # Level 2
   - hw/ip/spatz/src/spatz_decoder.sv
   - hw/ip/spatz/src/spatz_simd_lane.sv
-  - hw/ip/spatz/src/vregfile.sv
   # Level 3
   - hw/ip/spatz/src/spatz_fpu_sequencer.sv
   - hw/ip/spatz/src/spatz_ipu.sv
@@ -153,6 +152,15 @@ sources:
   # Level 5
   - hw/ip/spatz/src/spatz.sv
 
+  - target: fpga
+      files:
+        # Level 2
+        - hw/ip/spatz/src/vregfile.sv
+  - target: not(fpga)
+      files:
+        # Level 2
+        - hw/ip/spatz/src/vregfile_fpga.sv
+
   ## hw/ip/spatz_cc ##
 
   # Level 0
diff --git a/hw/ip/spatz/src/vregfile_fpga.sv b/hw/ip/spatz/src/vregfile_fpga.sv
new file mode 100644
index 00000000..78a5935d
--- /dev/null
+++ b/hw/ip/spatz/src/vregfile_fpga.sv
@@ -0,0 +1,47 @@
+// Copyright 2024 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Author: Cyril Koenig, ETH Zurich
+//
+// Generic vector register file that makes use of latches to store data.
+
+module vregfile import spatz_pkg::*; #(
+    parameter int  unsigned NrReadPorts = 0,
+    parameter int  unsigned NrWords     = NRVREG,
+    parameter int  unsigned WordWidth   = VRFWordWidth,
+    // Derived parameters.  Do not change!
+    parameter type          addr_t      = logic[$clog2(NrWords)-1:0],
+    parameter type          data_t      = logic [WordWidth-1:0],
+    parameter type          strb_t      = logic [WordWidth/8-1:0]
+  ) (
+    input  logic                    clk_i,
+    input  logic                    rst_ni,
+    input  logic                    testmode_i,
+    // Write ports
+    input  addr_t                   waddr_i,
+    input  data_t                   wdata_i,
+    input  logic                    we_i,
+    input  strb_t                   wbe_i,
+    // Read ports
+    input  addr_t [NrReadPorts-1:0] raddr_i,
+    output data_t [NrReadPorts-1:0] rdata_o
+  );
+
+  // Just fall back on the snitch regfile that is already FPGA ready
+  snitch_regfile #(
+    .DATA_WIDTH(WordWidth),
+    .NR_READ_PORTS(NrReadPorts),
+    .NR_WRITE_PORTS(1),
+    .ZERO_REG_ZERO(0),
+    .ADDR_WIDTH($bits(addr_t))
+  ) i_snitch_regfile (
+    .clk_i,
+    .raddr_i,
+    .rdata_o,
+    .waddr_i,
+    .wdata_i,
+    .we_i
+  );
+
+endmodule : vregfile