From 203445ea0e9a5a006623423aa3d56443fc80c735 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Fri, 16 Feb 2024 15:15:13 +0100 Subject: [PATCH 01/12] treewide: Add idma to ethernet --- .gitignore | 1 + Bender.lock | 26 +- Bender.yml | 29 +- README.md | 6 + eth.mk | 46 +- gen/Makefile | 8 +- gen/eth_framing.h | 37 - gen/eth_framing_reg_pkg.sv | 83 -- gen/eth_framing_reg_top.sv | 438 -------- gen/eth_framing_regs.hjson | 65 -- gen/eth_idma_reg.h | 146 +++ gen/eth_idma_reg.hjson | 294 ++++++ gen/eth_idma_reg_pkg.sv | 270 +++++ gen/eth_idma_reg_top.sv | 1470 +++++++++++++++++++++++++++ rtl/clk_gen_hyper.sv | 61 ++ rtl/eth_clk_gen.sv | 47 + rtl/eth_idma_pkg.sv | 102 ++ rtl/eth_idma_wrap.sv | 299 ++++++ rtl/eth_mac_1g_rgmii.sv | 25 +- rtl/eth_rgmii_pkg.sv | 16 - rtl/eth_top.sv | 172 ++-- rtl/eth_top_pkg.sv | 41 - rtl/fll_dummy.sv | 89 ++ rtl/framing_top.sv | 91 +- target/.gitignore | 4 + target/sim/src/eth_tb.sv | 798 ++++++--------- target/sim/stimuli/eth_frame.vmem | 193 ++++ target/sim/stimuli/rx_mem_init.vmem | 128 +++ target/synth/eth_idma_wrap_synth.sv | 155 +++ target/synth/eth_top_synth.sv | 140 --- 30 files changed, 3820 insertions(+), 1460 deletions(-) create mode 100644 .gitignore delete mode 100644 gen/eth_framing.h delete mode 100644 gen/eth_framing_reg_pkg.sv delete mode 100644 gen/eth_framing_reg_top.sv delete mode 100644 gen/eth_framing_regs.hjson create mode 100644 gen/eth_idma_reg.h create mode 100644 gen/eth_idma_reg.hjson create mode 100644 gen/eth_idma_reg_pkg.sv create mode 100644 gen/eth_idma_reg_top.sv create mode 100644 rtl/clk_gen_hyper.sv create mode 100644 rtl/eth_clk_gen.sv create mode 100644 rtl/eth_idma_pkg.sv create mode 100644 rtl/eth_idma_wrap.sv delete mode 100644 rtl/eth_rgmii_pkg.sv delete mode 100644 rtl/eth_top_pkg.sv create mode 100644 rtl/fll_dummy.sv create mode 100644 target/.gitignore create mode 100644 target/sim/stimuli/eth_frame.vmem create mode 100644 target/sim/stimuli/rx_mem_init.vmem create mode 100644 target/synth/eth_idma_wrap_synth.sv delete mode 100644 target/synth/eth_top_synth.sv diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..092a4fa --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +.bender diff --git a/Bender.lock b/Bender.lock index ba1ab1b..5f4ed57 100644 --- a/Bender.lock +++ b/Bender.lock @@ -23,8 +23,8 @@ packages: dependencies: - axi axi_stream: - revision: 472751f550e3918215603e21734fe0ece3c66f79 - version: null + revision: 54891ff40455ca94a37641b9da4604647878cc07 + version: 0.1.1 source: Git: git@github.com:pulp-platform/axi_stream.git dependencies: @@ -43,15 +43,33 @@ packages: source: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] + idma: + revision: 18fa40f0b12927622c6a0ff771fb0142d20bcb3d + version: null + source: + Git: git@github.com:pulp-platform/iDMA.git + dependencies: + - axi + - common_cells + - common_verification + - idma_gen + - register_interface + idma_gen: + revision: null + version: null + source: + Path: .bender/git/checkouts/idma-c23dbd3f440503c0/target/rtl + dependencies: [] register_interface: - revision: 146501d80052b61475cdc333d3aab4cd769fd5dc - version: 0.3.9 + revision: d7693be4aef1fc7e7eb2b00b41c42e87d959866c + version: 0.4.2 source: Git: https://github.com/pulp-platform/register_interface.git dependencies: - apb - axi - common_cells + - common_verification tech_cells_generic: revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf version: 0.2.13 diff --git a/Bender.yml b/Bender.yml index bbdc021..67e5da6 100644 --- a/Bender.yml +++ b/Bender.yml @@ -1,3 +1,7 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + package: name: pulp-ethernet @@ -11,22 +15,25 @@ package: - "Davide Rossi " dependencies: - axi_mem_if : { git: git@github.com:pulp-platform/axi_mem_if.git, version: 0.2.1 } - axi : { git: "git@github.com:pulp-platform/axi.git", version: 0.39.1 } - common_verification : { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 } - register_interface : { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8 } - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 } - axi_stream: { git: "git@github.com:pulp-platform/axi_stream.git", rev: "472751f550e3918215603e21734fe0ece3c66f79" } + axi : { git: "git@github.com:pulp-platform/axi.git", version: 0.39.1 } + axi_mem_if : { git: git@github.com:pulp-platform/axi_mem_if.git, version: 0.2.1 } + axi_stream: { git: "git@github.com:pulp-platform/axi_stream.git", rev: "54891ff" } # branch: main + common_verification : { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 } + register_interface : { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.2 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 } + idma: { git: "git@github.com:pulp-platform/iDMA.git", rev: "18fa40f" } # branch: cl/idma-eth sources: # Source files grouped in levels. Files in level 0 have no dependencies on files in this # package. Files in level 1 only depend on files in level 0, files in level 2 on files in # levels 1 and 0, etc. Files within a level are ordered alphabetically. # Level 0 - - gen/eth_framing_reg_pkg.sv - - gen/eth_framing_reg_top.sv + - gen/eth_idma_reg_pkg.sv + - gen/eth_idma_reg_top.sv - rtl/axis_gmii_rx.sv - rtl/axis_gmii_tx.sv + - rtl/fll_dummy.sv + - rtl/clk_gen_hyper.sv # Level 1 - rtl/eth_mac_1g_rgmii_fifo.sv - rtl/eth_mac_1g_rgmii.sv @@ -40,9 +47,11 @@ sources: - rtl/ssio_ddr_in.sv # Level 2 - rtl/framing_top.sv - - rtl/eth_top_pkg.sv + - rtl/eth_idma_pkg.sv - rtl/eth_top.sv - - target/synth/eth_top_synth.sv + - rtl/eth_clk_gen.sv + - rtl/eth_idma_wrap.sv + - target/synth/eth_idma_wrap_synth.sv - target: test files: diff --git a/README.md b/README.md index deb71f6..0e4d402 100644 --- a/README.md +++ b/README.md @@ -17,6 +17,12 @@ used. `pulp-ethernet` is intended for use with https://github.com/pulp-platform/ariane (a RISCV Linux-capable soft core). +## Generate iDMA with AXIS support (Terminal) + +``` +make eth-gen +``` + ## Compile (Questa) ``` diff --git a/eth.mk b/eth.mk index f12c6d2..79276bd 100644 --- a/eth.mk +++ b/eth.mk @@ -17,10 +17,13 @@ BENDER ?= bender QUESTA ?= questa-2022.3 TBENCH ?= eth_tb -DUT ?= eth_rgmii_synth +DUT ?= eth_idma_wrap # Design and simulation variables ETH_ROOT ?= $(shell $(BENDER) path fe-ethernet) +ETH_VSIM_DIR := $(ETH_ROOT)/target/sim/vsim + +IDMA_ROOT ?= $(shell $(BENDER) path idma) QUESTA_FLAGS := -permissive -suppress 3009 -suppress 8386 -error 7 +UVM_NO_RELNOTES #QUESTA_FLAGS := @@ -34,6 +37,16 @@ else RUN_AND_EXIT := run -all; exit endif +######## +# Deps # +######## + +eth-checkout: + $(BENDER) checkout + touch Bender.lock + +include $(IDMA_ROOT)/idma.mk + ###################### # Nonfree components # ###################### @@ -47,31 +60,46 @@ eth-nonfree-init: -include $(ETH_ROOT)/nonfree/nonfree.mk +############## +# HW GEN # +############## + +eth-idma-gen: eth-checkout + make -C $(IDMA_ROOT) idma_hw_all + ############## # Simulation # ############## +# Questasim $(ETH_ROOT)/target/sim/vsim/compile.eth.tcl: Bender.yml - $(BENDER) script vsim -t test \ + $(BENDER) script vsim -t rtl -t test -t sim \ --vlog-arg="-svinputport=compat" \ --vlog-arg="-override_timescale 1ns/1ps" \ --vlog-arg="-suppress 2583" > $@ echo 'vopt $(VOPT_FLAGS) $(TBENCH) -o $(TBENCH)_opt' >> $@ -eth-sim-init: $(ETH_ROOT)/target/sim/vsim/compile.eth.tcl - -eth-hw-build: eth-sim-init - $(QUESTA) vsim -c -do "quit -code [source $(ETH_ROOT)/target/sim/vsim/compile.eth.tcl]" +eth-vsim-sim-build: eth-sim-init + cd $(ETH_VSIM_DIR) && $(QUESTA) vsim -c -do "quit -code [source $(ETH_ROOT)/target/sim/vsim/compile.eth.tcl]" -eth-hw-sim: - $(QUESTA) vsim $(VSIM_FLAGS) -do \ +eth-vsim-sim-run: + cd $(ETH_VSIM_DIR) && $(QUESTA) vsim $(VSIM_FLAGS) -do \ "set TESTBENCH $(TBENCH); \ set VSIM_FLAGS \"$(VSIM_FLAGS)\"; \ source $(ETH_ROOT)/target/sim/vsim/start.eth.tcl ; \ $(RUN_AND_EXIT)" +eth-vsim-sim-clean: + cd $(ETH_VSIM_DIR) && rm -rf work transcript + +# Global targets + +eth-sim-init: $(ETH_ROOT)/target/sim/vsim/compile.eth.tcl +eth-sim-build: eth-vsim-sim-build +eth-sim-clean: eth-vsim-sim-clean + ################################# # Phonies (KEEP AT END OF FILE) # ################################# -.PHONY: eth-all eth-nonfree-init eth-sim-init eth-hw-build eth-hw-sim +.PHONY: eth-all eth-nonfree-init eth-checkout eth-idma-gen eth-sim-init eth-sim-build eth-sim-clean eth-vsim-sim-build eth-vsim-sim-clean eth-vsim-sim-run diff --git a/gen/Makefile b/gen/Makefile index d44f842..ff48d2c 100644 --- a/gen/Makefile +++ b/gen/Makefile @@ -18,18 +18,18 @@ REGTOOL ?= regtool.py -SRCS = eth_framing_reg_top.sv eth_framing_reg_pkg.sv +SRCS = eth_idma_reg_top.sv eth_idma_reg_pkg.sv all: srcs headers srcs: $(SRCS) -eth_framing_reg_top.sv: eth_framing_regs.hjson +eth_idma_reg_top.sv: eth_idma_reg.hjson $(REGTOOL) -r $< -t . -headers: eth_framing.h +headers: eth_idma_reg.h -eth_framing.h: eth_framing_regs.hjson +eth_idma_reg.h: eth_idma_reg.hjson $(REGTOOL) --cdefines $< > $@ .PHONY: install diff --git a/gen/eth_framing.h b/gen/eth_framing.h deleted file mode 100644 index f514429..0000000 --- a/gen/eth_framing.h +++ /dev/null @@ -1,37 +0,0 @@ -// Generated register defines for eth_framing - -#ifndef _ETH_FRAMING_REG_DEFS_ -#define _ETH_FRAMING_REG_DEFS_ - -#ifdef __cplusplus -extern "C" { -#endif -// Register width -#define ETH_FRAMING_PARAM_REG_WIDTH 32 - -// Configures the lower 4 bytes of the devices MAC address -#define ETH_FRAMING_CONFIG0_REG_OFFSET 0x0 - -// Configures the: upper 2 bytes of the devices MAC address, promiscuous -// flag, MDIO interface -#define ETH_FRAMING_CONFIG1_REG_OFFSET 0x4 -#define ETH_FRAMING_CONFIG1_UPPER_MAC_ADDRESS_MASK 0xffff -#define ETH_FRAMING_CONFIG1_UPPER_MAC_ADDRESS_OFFSET 0 -#define ETH_FRAMING_CONFIG1_UPPER_MAC_ADDRESS_FIELD \ - ((bitfield_field32_t) { .mask = ETH_FRAMING_CONFIG1_UPPER_MAC_ADDRESS_MASK, .index = ETH_FRAMING_CONFIG1_UPPER_MAC_ADDRESS_OFFSET }) -#define ETH_FRAMING_CONFIG1_PROMISCUOUS_BIT 16 -#define ETH_FRAMING_CONFIG1_PHY_MDCLK_BIT 17 -#define ETH_FRAMING_CONFIG1_PHY_MDIO_O_BIT 18 -#define ETH_FRAMING_CONFIG1_PHY_MDIO_OE_BIT 19 - -// The FCS TX status -#define ETH_FRAMING_CONFIG2_REG_OFFSET 0x8 - -// The FCS RX status -#define ETH_FRAMING_CONFIG3_REG_OFFSET 0xc - -#ifdef __cplusplus -} // extern "C" -#endif -#endif // _ETH_FRAMING_REG_DEFS_ -// End generated register defines for eth_framing \ No newline at end of file diff --git a/gen/eth_framing_reg_pkg.sv b/gen/eth_framing_reg_pkg.sv deleted file mode 100644 index f7427e3..0000000 --- a/gen/eth_framing_reg_pkg.sv +++ /dev/null @@ -1,83 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Package auto-generated by `reggen` containing data structure - -package eth_framing_reg_pkg; - - // Address widths within the block - parameter int BlockAw = 4; - - //////////////////////////// - // Typedefs for registers // - //////////////////////////// - - typedef struct packed { - logic [31:0] q; - } eth_framing_reg2hw_config0_reg_t; - - typedef struct packed { - struct packed { - logic [15:0] q; - } upper_mac_address; - struct packed { - logic q; - } promiscuous; - struct packed { - logic q; - } phy_mdclk; - struct packed { - logic q; - } phy_mdio_o; - struct packed { - logic q; - } phy_mdio_oe; - } eth_framing_reg2hw_config1_reg_t; - - typedef struct packed { - logic [31:0] d; - logic de; - } eth_framing_hw2reg_config2_reg_t; - - typedef struct packed { - logic [31:0] d; - logic de; - } eth_framing_hw2reg_config3_reg_t; - - // Register -> HW type - typedef struct packed { - eth_framing_reg2hw_config0_reg_t config0; // [51:20] - eth_framing_reg2hw_config1_reg_t config1; // [19:0] - } eth_framing_reg2hw_t; - - // HW -> register type - typedef struct packed { - eth_framing_hw2reg_config2_reg_t config2; // [65:33] - eth_framing_hw2reg_config3_reg_t config3; // [32:0] - } eth_framing_hw2reg_t; - - // Register offsets - parameter logic [BlockAw-1:0] ETH_FRAMING_CONFIG0_OFFSET = 4'h 0; - parameter logic [BlockAw-1:0] ETH_FRAMING_CONFIG1_OFFSET = 4'h 4; - parameter logic [BlockAw-1:0] ETH_FRAMING_CONFIG2_OFFSET = 4'h 8; - parameter logic [BlockAw-1:0] ETH_FRAMING_CONFIG3_OFFSET = 4'h c; - - // Register index - typedef enum int { - ETH_FRAMING_CONFIG0, - ETH_FRAMING_CONFIG1, - ETH_FRAMING_CONFIG2, - ETH_FRAMING_CONFIG3 - } eth_framing_id_e; - - // Register width information to check illegal writes - parameter logic [3:0] ETH_FRAMING_PERMIT [4] = '{ - 4'b 1111, // index[0] ETH_FRAMING_CONFIG0 - 4'b 0111, // index[1] ETH_FRAMING_CONFIG1 - 4'b 1111, // index[2] ETH_FRAMING_CONFIG2 - 4'b 1111 // index[3] ETH_FRAMING_CONFIG3 - }; - -endpackage - diff --git a/gen/eth_framing_reg_top.sv b/gen/eth_framing_reg_top.sv deleted file mode 100644 index 2d7ae9e..0000000 --- a/gen/eth_framing_reg_top.sv +++ /dev/null @@ -1,438 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Top module auto-generated by `reggen` - - -`include "common_cells/assertions.svh" - -module eth_framing_reg_top #( - parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic, - parameter int AW = 4 -) ( - input logic clk_i, - input logic rst_ni, - input reg_req_t reg_req_i, - output reg_rsp_t reg_rsp_o, - // To HW - output eth_framing_reg_pkg::eth_framing_reg2hw_t reg2hw, // Write - input eth_framing_reg_pkg::eth_framing_hw2reg_t hw2reg, // Read - - - // Config - input devmode_i // If 1, explicit error return for unmapped register access -); - - import eth_framing_reg_pkg::* ; - - localparam int DW = 32; - localparam int DBW = DW/8; // Byte Width - - // register signals - logic reg_we; - logic reg_re; - logic [BlockAw-1:0] reg_addr; - logic [DW-1:0] reg_wdata; - logic [DBW-1:0] reg_be; - logic [DW-1:0] reg_rdata; - logic reg_error; - - logic addrmiss, wr_err; - - logic [DW-1:0] reg_rdata_next; - - // Below register interface can be changed - reg_req_t reg_intf_req; - reg_rsp_t reg_intf_rsp; - - - assign reg_intf_req = reg_req_i; - assign reg_rsp_o = reg_intf_rsp; - - - assign reg_we = reg_intf_req.valid & reg_intf_req.write; - assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; - assign reg_addr = reg_intf_req.addr[BlockAw-1:0]; - assign reg_wdata = reg_intf_req.wdata; - assign reg_be = reg_intf_req.wstrb; - assign reg_intf_rsp.rdata = reg_rdata; - assign reg_intf_rsp.error = reg_error; - assign reg_intf_rsp.ready = 1'b1; - - assign reg_rdata = reg_rdata_next ; - assign reg_error = (devmode_i & addrmiss) | wr_err; - - - // Define SW related signals - // Format: __{wd|we|qs} - // or _{wd|we|qs} if field == 1 or 0 - logic [31:0] config0_qs; - logic [31:0] config0_wd; - logic config0_we; - logic [15:0] config1_upper_mac_address_qs; - logic [15:0] config1_upper_mac_address_wd; - logic config1_upper_mac_address_we; - logic config1_promiscuous_qs; - logic config1_promiscuous_wd; - logic config1_promiscuous_we; - logic config1_phy_mdclk_qs; - logic config1_phy_mdclk_wd; - logic config1_phy_mdclk_we; - logic config1_phy_mdio_o_qs; - logic config1_phy_mdio_o_wd; - logic config1_phy_mdio_o_we; - logic config1_phy_mdio_oe_qs; - logic config1_phy_mdio_oe_wd; - logic config1_phy_mdio_oe_we; - logic [31:0] config2_qs; - logic [31:0] config3_qs; - - // Register instances - // R[config0]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h890702) - ) u_config0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (config0_we), - .wd (config0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.config0.q ), - - // to register interface (read) - .qs (config0_qs) - ); - - - // R[config1]: V(False) - - // F[upper_mac_address]: 15:0 - prim_subreg #( - .DW (16), - .SWACCESS("RW"), - .RESVAL (16'h2301) - ) u_config1_upper_mac_address ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (config1_upper_mac_address_we), - .wd (config1_upper_mac_address_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.config1.upper_mac_address.q ), - - // to register interface (read) - .qs (config1_upper_mac_address_qs) - ); - - - // F[promiscuous]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_config1_promiscuous ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (config1_promiscuous_we), - .wd (config1_promiscuous_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.config1.promiscuous.q ), - - // to register interface (read) - .qs (config1_promiscuous_qs) - ); - - - // F[phy_mdclk]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_config1_phy_mdclk ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (config1_phy_mdclk_we), - .wd (config1_phy_mdclk_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.config1.phy_mdclk.q ), - - // to register interface (read) - .qs (config1_phy_mdclk_qs) - ); - - - // F[phy_mdio_o]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_config1_phy_mdio_o ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (config1_phy_mdio_o_we), - .wd (config1_phy_mdio_o_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.config1.phy_mdio_o.q ), - - // to register interface (read) - .qs (config1_phy_mdio_o_qs) - ); - - - // F[phy_mdio_oe]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_config1_phy_mdio_oe ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (config1_phy_mdio_oe_we), - .wd (config1_phy_mdio_oe_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.config1.phy_mdio_oe.q ), - - // to register interface (read) - .qs (config1_phy_mdio_oe_qs) - ); - - - // R[config2]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RO"), - .RESVAL (32'h0) - ) u_config2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (hw2reg.config2.de), - .d (hw2reg.config2.d ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (config2_qs) - ); - - - // R[config3]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RO"), - .RESVAL (32'h0) - ) u_config3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (hw2reg.config3.de), - .d (hw2reg.config3.d ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (config3_qs) - ); - - - - - logic [3:0] addr_hit; - always_comb begin - addr_hit = '0; - addr_hit[0] = (reg_addr == ETH_FRAMING_CONFIG0_OFFSET); - addr_hit[1] = (reg_addr == ETH_FRAMING_CONFIG1_OFFSET); - addr_hit[2] = (reg_addr == ETH_FRAMING_CONFIG2_OFFSET); - addr_hit[3] = (reg_addr == ETH_FRAMING_CONFIG3_OFFSET); - end - - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - - // Check sub-word write is permitted - always_comb begin - wr_err = (reg_we & - ((addr_hit[0] & (|(ETH_FRAMING_PERMIT[0] & ~reg_be))) | - (addr_hit[1] & (|(ETH_FRAMING_PERMIT[1] & ~reg_be))) | - (addr_hit[2] & (|(ETH_FRAMING_PERMIT[2] & ~reg_be))) | - (addr_hit[3] & (|(ETH_FRAMING_PERMIT[3] & ~reg_be))))); - end - - assign config0_we = addr_hit[0] & reg_we & !reg_error; - assign config0_wd = reg_wdata[31:0]; - - assign config1_upper_mac_address_we = addr_hit[1] & reg_we & !reg_error; - assign config1_upper_mac_address_wd = reg_wdata[15:0]; - - assign config1_promiscuous_we = addr_hit[1] & reg_we & !reg_error; - assign config1_promiscuous_wd = reg_wdata[16]; - - assign config1_phy_mdclk_we = addr_hit[1] & reg_we & !reg_error; - assign config1_phy_mdclk_wd = reg_wdata[17]; - - assign config1_phy_mdio_o_we = addr_hit[1] & reg_we & !reg_error; - assign config1_phy_mdio_o_wd = reg_wdata[18]; - - assign config1_phy_mdio_oe_we = addr_hit[1] & reg_we & !reg_error; - assign config1_phy_mdio_oe_wd = reg_wdata[19]; - - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[31:0] = config0_qs; - end - - addr_hit[1]: begin - reg_rdata_next[15:0] = config1_upper_mac_address_qs; - reg_rdata_next[16] = config1_promiscuous_qs; - reg_rdata_next[17] = config1_phy_mdclk_qs; - reg_rdata_next[18] = config1_phy_mdio_o_qs; - reg_rdata_next[19] = config1_phy_mdio_oe_qs; - end - - addr_hit[2]: begin - reg_rdata_next[31:0] = config2_qs; - end - - addr_hit[3]: begin - reg_rdata_next[31:0] = config3_qs; - end - - default: begin - reg_rdata_next = '1; - end - endcase - end - - // Unused signal tieoff - - // wdata / byte enable are not always fully used - // add a blanket unused statement to handle lint waivers - logic unused_wdata; - logic unused_be; - assign unused_wdata = ^reg_wdata; - assign unused_be = ^reg_be; - - // Assertions for Register Interface - `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) - -endmodule - -module eth_framing_reg_top_intf -#( - parameter int AW = 4, - localparam int DW = 32 -) ( - input logic clk_i, - input logic rst_ni, - REG_BUS.in regbus_slave, - // To HW - output eth_framing_reg_pkg::eth_framing_reg2hw_t reg2hw, // Write - input eth_framing_reg_pkg::eth_framing_hw2reg_t hw2reg, // Read - // Config - input devmode_i // If 1, explicit error return for unmapped register access -); - localparam int unsigned STRB_WIDTH = DW/8; - -`include "register_interface/typedef.svh" -`include "register_interface/assign.svh" - - // Define structs for reg_bus - typedef logic [AW-1:0] addr_t; - typedef logic [DW-1:0] data_t; - typedef logic [STRB_WIDTH-1:0] strb_t; - `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t) - - reg_bus_req_t s_reg_req; - reg_bus_rsp_t s_reg_rsp; - - // Assign SV interface to structs - `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave) - `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp) - - - - eth_framing_reg_top #( - .reg_req_t(reg_bus_req_t), - .reg_rsp_t(reg_bus_rsp_t), - .AW(AW) - ) i_regs ( - .clk_i, - .rst_ni, - .reg_req_i(s_reg_req), - .reg_rsp_o(s_reg_rsp), - .reg2hw, // Write - .hw2reg, // Read - .devmode_i - ); - -endmodule - - diff --git a/gen/eth_framing_regs.hjson b/gen/eth_framing_regs.hjson deleted file mode 100644 index b025661..0000000 --- a/gen/eth_framing_regs.hjson +++ /dev/null @@ -1,65 +0,0 @@ -{ - name: "eth_framing", - clock_primary: "msoc_clk", - reset_primary: "rst_int", - bus_interfaces: [ - { protocol: "reg_iface", direction: "device"} - ] - regwidth: "32", - registers: [ - { name: "CONFIG0", - desc: "Configures the lower 4 bytes of the devices MAC address", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:0", name: "lower_mac_address", - desc: "Lower 32 bit of the devices MAC address" - resval: "8980226" - } - ] - }, - { name: "CONFIG1", - desc: "Configures the: upper 2 bytes of the devices MAC address, promiscuous flag, MDIO interface", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "15:0", name: "upper_mac_address", - desc: "Upper 16 bit of the devices MAC address" - resval: "8961" - }, - { bits: "16", name: "promiscuous", - desc: "promiscuous flag" - }, - { bits: "17", name: "phy_mdclk", - desc: "MDIO clock" - }, - { bits: "18", name: "phy_mdio_o", - desc: "MDIO output" - }, - { bits: "19", name: "phy_mdio_oe", - desc: "MDIO output enable" - } - ] - }, - { name: "CONFIG2", - desc: "The FCS TX status", - swaccess: "ro", - hwaccess: "hwo", - fields: [ - { bits: "31:0", name: "tx_fcs_reg", - desc: "FCS TX status" - } - ] - }, - { name: "CONFIG3", - desc: "The FCS RX status", - swaccess: "ro", - hwaccess: "hwo", - fields: [ - { bits: "31:0", name: "rx_fcs_reg", - desc: "FCS RX status" - } - ] - } - ] -} \ No newline at end of file diff --git a/gen/eth_idma_reg.h b/gen/eth_idma_reg.h new file mode 100644 index 0000000..b56e7ef --- /dev/null +++ b/gen/eth_idma_reg.h @@ -0,0 +1,146 @@ +// Generated register defines for eth_idma + +#ifndef _ETH_IDMA_REG_DEFS_ +#define _ETH_IDMA_REG_DEFS_ + +#ifdef __cplusplus +extern "C" { +#endif +// Register width +#define ETH_IDMA_PARAM_REG_WIDTH 32 + +// lower 4 bytes of the devices MAC address +#define ETH_IDMA_MACLO_ADDR_REG_OFFSET 0x0 + +// upper 2 bytes of the devices MAC address, promiscuous flag, MDIO interface +#define ETH_IDMA_MACHI_MDIO_REG_OFFSET 0x4 +#define ETH_IDMA_MACHI_MDIO_UPPER_MAC_ADDRESS_MASK 0xffff +#define ETH_IDMA_MACHI_MDIO_UPPER_MAC_ADDRESS_OFFSET 0 +#define ETH_IDMA_MACHI_MDIO_UPPER_MAC_ADDRESS_FIELD \ + ((bitfield_field32_t) { .mask = ETH_IDMA_MACHI_MDIO_UPPER_MAC_ADDRESS_MASK, .index = ETH_IDMA_MACHI_MDIO_UPPER_MAC_ADDRESS_OFFSET }) +#define ETH_IDMA_MACHI_MDIO_PROMISCUOUS_BIT 16 +#define ETH_IDMA_MACHI_MDIO_PHY_MDCLK_BIT 17 +#define ETH_IDMA_MACHI_MDIO_PHY_MDIO_O_BIT 18 +#define ETH_IDMA_MACHI_MDIO_PHY_MDIO_OE_BIT 19 + +// The FCS TX status +#define ETH_IDMA_TX_FCS_REG_OFFSET 0x8 + +// The FCS RX status +#define ETH_IDMA_RX_FCS_REG_OFFSET 0xc + +// Source Address +#define ETH_IDMA_SRC_ADDR_REG_OFFSET 0x10 + +// Destination Address +#define ETH_IDMA_DST_ADDR_REG_OFFSET 0x14 + +// Number of bytes +#define ETH_IDMA_LENGTH_REG_OFFSET 0x18 + +// Source protocol of iDMA +#define ETH_IDMA_SRC_PROTOCOL_REG_OFFSET 0x1c +#define ETH_IDMA_SRC_PROTOCOL_SRC_PROTOCOL_MASK 0x7 +#define ETH_IDMA_SRC_PROTOCOL_SRC_PROTOCOL_OFFSET 0 +#define ETH_IDMA_SRC_PROTOCOL_SRC_PROTOCOL_FIELD \ + ((bitfield_field32_t) { .mask = ETH_IDMA_SRC_PROTOCOL_SRC_PROTOCOL_MASK, .index = ETH_IDMA_SRC_PROTOCOL_SRC_PROTOCOL_OFFSET }) + +// Destination protocol of iDMA +#define ETH_IDMA_DST_PROTOCOL_REG_OFFSET 0x20 +#define ETH_IDMA_DST_PROTOCOL_DST_PROTOCOL_MASK 0x7 +#define ETH_IDMA_DST_PROTOCOL_DST_PROTOCOL_OFFSET 0 +#define ETH_IDMA_DST_PROTOCOL_DST_PROTOCOL_FIELD \ + ((bitfield_field32_t) { .mask = ETH_IDMA_DST_PROTOCOL_DST_PROTOCOL_MASK, .index = ETH_IDMA_DST_PROTOCOL_DST_PROTOCOL_OFFSET }) + +// iDMA transaction ID +#define ETH_IDMA_AXI_ID_REG_OFFSET 0x24 +#define ETH_IDMA_AXI_ID_AXI_ID_BIT 0 + +// src options +#define ETH_IDMA_OPT_SRC_REG_OFFSET 0x28 +#define ETH_IDMA_OPT_SRC_BURST_MASK 0x3 +#define ETH_IDMA_OPT_SRC_BURST_OFFSET 0 +#define ETH_IDMA_OPT_SRC_BURST_FIELD \ + ((bitfield_field32_t) { .mask = ETH_IDMA_OPT_SRC_BURST_MASK, .index = ETH_IDMA_OPT_SRC_BURST_OFFSET }) +#define ETH_IDMA_OPT_SRC_CACHE_MASK 0xf +#define ETH_IDMA_OPT_SRC_CACHE_OFFSET 2 +#define ETH_IDMA_OPT_SRC_CACHE_FIELD \ + ((bitfield_field32_t) { .mask = ETH_IDMA_OPT_SRC_CACHE_MASK, .index = ETH_IDMA_OPT_SRC_CACHE_OFFSET }) +#define ETH_IDMA_OPT_SRC_LOCK_BIT 6 +#define ETH_IDMA_OPT_SRC_PROT_MASK 0x7 +#define ETH_IDMA_OPT_SRC_PROT_OFFSET 7 +#define ETH_IDMA_OPT_SRC_PROT_FIELD \ + ((bitfield_field32_t) { .mask = ETH_IDMA_OPT_SRC_PROT_MASK, .index = ETH_IDMA_OPT_SRC_PROT_OFFSET }) +#define ETH_IDMA_OPT_SRC_QOS_MASK 0xf +#define ETH_IDMA_OPT_SRC_QOS_OFFSET 10 +#define ETH_IDMA_OPT_SRC_QOS_FIELD \ + ((bitfield_field32_t) { .mask = ETH_IDMA_OPT_SRC_QOS_MASK, .index = ETH_IDMA_OPT_SRC_QOS_OFFSET }) +#define ETH_IDMA_OPT_SRC_REGION_MASK 0xf +#define ETH_IDMA_OPT_SRC_REGION_OFFSET 14 +#define ETH_IDMA_OPT_SRC_REGION_FIELD \ + ((bitfield_field32_t) { .mask = ETH_IDMA_OPT_SRC_REGION_MASK, .index = ETH_IDMA_OPT_SRC_REGION_OFFSET }) + +// dst options +#define ETH_IDMA_OPT_DST_REG_OFFSET 0x2c +#define ETH_IDMA_OPT_DST_BURST_MASK 0x3 +#define ETH_IDMA_OPT_DST_BURST_OFFSET 0 +#define ETH_IDMA_OPT_DST_BURST_FIELD \ + ((bitfield_field32_t) { .mask = ETH_IDMA_OPT_DST_BURST_MASK, .index = ETH_IDMA_OPT_DST_BURST_OFFSET }) +#define ETH_IDMA_OPT_DST_CACHE_MASK 0xf +#define ETH_IDMA_OPT_DST_CACHE_OFFSET 2 +#define ETH_IDMA_OPT_DST_CACHE_FIELD \ + ((bitfield_field32_t) { .mask = ETH_IDMA_OPT_DST_CACHE_MASK, .index = ETH_IDMA_OPT_DST_CACHE_OFFSET }) +#define ETH_IDMA_OPT_DST_LOCK_BIT 6 +#define ETH_IDMA_OPT_DST_PROT_MASK 0x7 +#define ETH_IDMA_OPT_DST_PROT_OFFSET 7 +#define ETH_IDMA_OPT_DST_PROT_FIELD \ + ((bitfield_field32_t) { .mask = ETH_IDMA_OPT_DST_PROT_MASK, .index = ETH_IDMA_OPT_DST_PROT_OFFSET }) +#define ETH_IDMA_OPT_DST_QOS_MASK 0xf +#define ETH_IDMA_OPT_DST_QOS_OFFSET 10 +#define ETH_IDMA_OPT_DST_QOS_FIELD \ + ((bitfield_field32_t) { .mask = ETH_IDMA_OPT_DST_QOS_MASK, .index = ETH_IDMA_OPT_DST_QOS_OFFSET }) +#define ETH_IDMA_OPT_DST_REGION_MASK 0xf +#define ETH_IDMA_OPT_DST_REGION_OFFSET 14 +#define ETH_IDMA_OPT_DST_REGION_FIELD \ + ((bitfield_field32_t) { .mask = ETH_IDMA_OPT_DST_REGION_MASK, .index = ETH_IDMA_OPT_DST_REGION_OFFSET }) + +// backend options +#define ETH_IDMA_BEO_REG_OFFSET 0x30 +#define ETH_IDMA_BEO_DECOUPLE_AW_BIT 0 +#define ETH_IDMA_BEO_DECOUPLE_RW_BIT 1 +#define ETH_IDMA_BEO_SRC_MAX_LLEN_MASK 0x7 +#define ETH_IDMA_BEO_SRC_MAX_LLEN_OFFSET 2 +#define ETH_IDMA_BEO_SRC_MAX_LLEN_FIELD \ + ((bitfield_field32_t) { .mask = ETH_IDMA_BEO_SRC_MAX_LLEN_MASK, .index = ETH_IDMA_BEO_SRC_MAX_LLEN_OFFSET }) +#define ETH_IDMA_BEO_DST_MAX_LLEN_MASK 0x7 +#define ETH_IDMA_BEO_DST_MAX_LLEN_OFFSET 5 +#define ETH_IDMA_BEO_DST_MAX_LLEN_FIELD \ + ((bitfield_field32_t) { .mask = ETH_IDMA_BEO_DST_MAX_LLEN_MASK, .index = ETH_IDMA_BEO_DST_MAX_LLEN_OFFSET }) +#define ETH_IDMA_BEO_SRC_REDUCE_LEN_BIT 8 +#define ETH_IDMA_BEO_DST_REDUCE_LEN_BIT 9 + +// last transfer +#define ETH_IDMA_LAST_REG_OFFSET 0x34 +#define ETH_IDMA_LAST_LAST_BIT 0 + +// idma request valid +#define ETH_IDMA_REQ_VALID_REG_OFFSET 0x38 +#define ETH_IDMA_REQ_VALID_REQ_VALID_BIT 0 + +// idma request ready +#define ETH_IDMA_REQ_READY_REG_OFFSET 0x3c +#define ETH_IDMA_REQ_READY_REQ_READY_BIT 0 + +// idma response ready +#define ETH_IDMA_RSP_READY_REG_OFFSET 0x40 +#define ETH_IDMA_RSP_READY_RSP_READY_BIT 0 + +// idma response valid +#define ETH_IDMA_RSP_VALID_REG_OFFSET 0x44 +#define ETH_IDMA_RSP_VALID_RSP_VALID_BIT 0 + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _ETH_IDMA_REG_DEFS_ +// End generated register defines for eth_idma \ No newline at end of file diff --git a/gen/eth_idma_reg.hjson b/gen/eth_idma_reg.hjson new file mode 100644 index 0000000..7e53b1f --- /dev/null +++ b/gen/eth_idma_reg.hjson @@ -0,0 +1,294 @@ +{ + name: "eth_idma", + clock_primary: "msoc_clk", + reset_primary: "rst_int", + bus_interfaces: [ + { protocol: "reg_iface", direction: "device"} + ] + regwidth: "32", + registers: [ + { name: "maclo_addr", + desc: "lower 4 bytes of the devices MAC address", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "31:0", name: "lower_mac_address", + desc: "Lower 32 bit of the devices MAC address" + resval: "8980226" + } + ] + }, + { name: "machi_mdio", + desc: "upper 2 bytes of the devices MAC address, promiscuous flag, MDIO interface", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "15:0", name: "upper_mac_address", + desc: "Upper 16 bit of the devices MAC address" + resval: "8961" + }, + { bits: "16", name: "promiscuous", + desc: "promiscuous flag" + }, + { bits: "17", name: "phy_mdclk", + desc: "MDIO clock" + }, + { bits: "18", name: "phy_mdio_o", + desc: "MDIO output" + }, + { bits: "19", name: "phy_mdio_oe", + desc: "MDIO output enable" + } + ] + }, + { name: "tx_fcs", + desc: "The FCS TX status", + swaccess: "ro", + hwaccess: "hwo", + fields: [ + { bits: "31:0", name: "tx_fcs_reg", + desc: "FCS TX status" + } + ] + }, + { name: "rx_fcs", + desc: "The FCS RX status", + swaccess: "ro", + hwaccess: "hwo", + fields: [ + { bits: "31:0", name: "rx_fcs_reg", + desc: "FCS RX status" + } + ] + }, + { name: "src_addr", + desc: "Source Address", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "31:0", + name: "src_addr", + desc: "Source Address" + resval: "0000" + } + ] + }, + { name: "dst_addr", + desc: "Destination Address", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "31:0", + name: "dst_addr", + desc: "Destination Address" + resval: "0000" + } + ] + }, + { name: "length", + desc: "Number of bytes", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "31:0", + name: "num_bytes", + desc: "Number of bytes" + resval: "0000" + } + ] + }, + { name: "src_protocol", + desc: "Source protocol of iDMA", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "2:0", + name: "src_protocol", + desc: "iDMA source protocol" + resval: "000" + } + ] + }, + { name: "dst_protocol", + desc: "Destination protocol of iDMA", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "2:0", + name: "dst_protocol", + desc: "iDMA destination protocol " + resval: "000" + } + ] + }, + { name: "axi_id", + desc: "iDMA transaction ID", + swaccess: "rw", + hwaccess: "hrw", + fields: [ + { bits: "0", + name: "axi_id", + desc: "transaction ID" + resval: "0" + } + ] + }, + { name: "opt_src", + desc: "src options", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0", name: "burst", + desc: "burst opt" + resval: "1" + }, + { bits: "5:2", name: "cache", + desc: "cache opt" + resval: "0" + }, + { bits: "6", name: "lock", + desc: "lock opt" + resval: "0" + }, + { bits: "9:7", name: "prot", + desc: "prot opt" + resval: "0" + }, + { bits: "13:10", name: "qos", + desc: "qos opt" + resval: "0" + } + { bits: "17:14", name: "region", + desc: "region opt" + resval: "0" + } + ] + }, + { name: "opt_dst", + desc: "dst options", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0", name: "burst", + desc: "burst opt" + resval: "1" + }, + { bits: "5:2", name: "cache", + desc: "cache opt" + resval: "0" + }, + { bits: "6", name: "lock", + desc: "lock opt" + resval: "0" + }, + { bits: "9:7", name: "prot", + desc: "prot opt" + resval: "0" + }, + { bits: "13:10", name: "qos", + desc: "qos opt" + resval: "0" + } + { bits: "17:14", name: "region", + desc: "region opt" + resval: "0" + } + ] + }, + { name: "beo", + desc: "backend options", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "0", name: "decouple_aw", + desc: "aw decouple enable" + resval: "0" + }, + { bits: "1", name: "decouple_rw", + desc: "rw decouple enable" + resval: "0" + }, + { bits: "4:2", name: "src_max_llen", + desc: "source max length" + resval: "0" + }, + { bits: "7:5", name: "dst_max_llen", + desc: "destination max length" + resval: "0" + }, + { bits: "8", name: "src_reduce_len", + desc: "srouce reduce length" + resval: "0" + } + { bits: "9", name: "dst_reduce_len", + desc: "destination reduce length" + resval: "0" + } + ] + }, + { name:"last", + desc: "last transfer", + swaccess: "rw", + hwaccess: "hrw", + fields: [ + { bits: "0", + name: "last", + desc: "last transfer" + } + ] + }, + { name:"req_valid", + desc: "idma request valid", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "0", + name: "req_valid", + desc: "valid idma request" + resval: "0" + } + ] + }, + { name:"req_ready", + desc: "idma request ready", + swaccess: "ro", + hwaccess: "hrw", + fields: [ + { bits: "0", + name: "req_ready", + desc: "idma request ready" + resval: "0" + } + ] + }, + { name:"rsp_ready", + desc: "idma response ready", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "0", + name: "rsp_ready", + desc: "idma response ready" + resval: "0" + } + ] + }, + { name:"rsp_valid", + desc: "idma response valid", + swaccess: "ro", + hwaccess: "hrw", + fields: [ + { bits: "0", + name: "rsp_valid", + desc: "idma response valid" + resval: "0" + } + ] + }, + ] +} + + + + + diff --git a/gen/eth_idma_reg_pkg.sv b/gen/eth_idma_reg_pkg.sv new file mode 100644 index 0000000..2b23046 --- /dev/null +++ b/gen/eth_idma_reg_pkg.sv @@ -0,0 +1,270 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package eth_idma_reg_pkg; + + // Address widths within the block + parameter int BlockAw = 7; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + logic [31:0] q; + } eth_idma_reg2hw_maclo_addr_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] q; + } upper_mac_address; + struct packed { + logic q; + } promiscuous; + struct packed { + logic q; + } phy_mdclk; + struct packed { + logic q; + } phy_mdio_o; + struct packed { + logic q; + } phy_mdio_oe; + } eth_idma_reg2hw_machi_mdio_reg_t; + + typedef struct packed { + logic [31:0] q; + } eth_idma_reg2hw_src_addr_reg_t; + + typedef struct packed { + logic [31:0] q; + } eth_idma_reg2hw_dst_addr_reg_t; + + typedef struct packed { + logic [31:0] q; + } eth_idma_reg2hw_length_reg_t; + + typedef struct packed { + logic [2:0] q; + } eth_idma_reg2hw_src_protocol_reg_t; + + typedef struct packed { + logic [2:0] q; + } eth_idma_reg2hw_dst_protocol_reg_t; + + typedef struct packed { + logic q; + } eth_idma_reg2hw_axi_id_reg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } burst; + struct packed { + logic [3:0] q; + } cache; + struct packed { + logic q; + } lock; + struct packed { + logic [2:0] q; + } prot; + struct packed { + logic [3:0] q; + } qos; + struct packed { + logic [3:0] q; + } region; + } eth_idma_reg2hw_opt_src_reg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } burst; + struct packed { + logic [3:0] q; + } cache; + struct packed { + logic q; + } lock; + struct packed { + logic [2:0] q; + } prot; + struct packed { + logic [3:0] q; + } qos; + struct packed { + logic [3:0] q; + } region; + } eth_idma_reg2hw_opt_dst_reg_t; + + typedef struct packed { + struct packed { + logic q; + } decouple_aw; + struct packed { + logic q; + } decouple_rw; + struct packed { + logic [2:0] q; + } src_max_llen; + struct packed { + logic [2:0] q; + } dst_max_llen; + struct packed { + logic q; + } src_reduce_len; + struct packed { + logic q; + } dst_reduce_len; + } eth_idma_reg2hw_beo_reg_t; + + typedef struct packed { + logic q; + } eth_idma_reg2hw_last_reg_t; + + typedef struct packed { + logic q; + } eth_idma_reg2hw_req_valid_reg_t; + + typedef struct packed { + logic q; + } eth_idma_reg2hw_req_ready_reg_t; + + typedef struct packed { + logic q; + } eth_idma_reg2hw_rsp_ready_reg_t; + + typedef struct packed { + logic q; + } eth_idma_reg2hw_rsp_valid_reg_t; + + typedef struct packed { + logic [31:0] d; + logic de; + } eth_idma_hw2reg_tx_fcs_reg_t; + + typedef struct packed { + logic [31:0] d; + logic de; + } eth_idma_hw2reg_rx_fcs_reg_t; + + typedef struct packed { + logic d; + logic de; + } eth_idma_hw2reg_axi_id_reg_t; + + typedef struct packed { + logic d; + logic de; + } eth_idma_hw2reg_last_reg_t; + + typedef struct packed { + logic d; + logic de; + } eth_idma_hw2reg_req_ready_reg_t; + + typedef struct packed { + logic d; + logic de; + } eth_idma_hw2reg_rsp_valid_reg_t; + + // Register -> HW type + typedef struct packed { + eth_idma_reg2hw_maclo_addr_reg_t maclo_addr; // [205:174] + eth_idma_reg2hw_machi_mdio_reg_t machi_mdio; // [173:154] + eth_idma_reg2hw_src_addr_reg_t src_addr; // [153:122] + eth_idma_reg2hw_dst_addr_reg_t dst_addr; // [121:90] + eth_idma_reg2hw_length_reg_t length; // [89:58] + eth_idma_reg2hw_src_protocol_reg_t src_protocol; // [57:55] + eth_idma_reg2hw_dst_protocol_reg_t dst_protocol; // [54:52] + eth_idma_reg2hw_axi_id_reg_t axi_id; // [51:51] + eth_idma_reg2hw_opt_src_reg_t opt_src; // [50:33] + eth_idma_reg2hw_opt_dst_reg_t opt_dst; // [32:15] + eth_idma_reg2hw_beo_reg_t beo; // [14:5] + eth_idma_reg2hw_last_reg_t last; // [4:4] + eth_idma_reg2hw_req_valid_reg_t req_valid; // [3:3] + eth_idma_reg2hw_req_ready_reg_t req_ready; // [2:2] + eth_idma_reg2hw_rsp_ready_reg_t rsp_ready; // [1:1] + eth_idma_reg2hw_rsp_valid_reg_t rsp_valid; // [0:0] + } eth_idma_reg2hw_t; + + // HW -> register type + typedef struct packed { + eth_idma_hw2reg_tx_fcs_reg_t tx_fcs; // [73:41] + eth_idma_hw2reg_rx_fcs_reg_t rx_fcs; // [40:8] + eth_idma_hw2reg_axi_id_reg_t axi_id; // [7:6] + eth_idma_hw2reg_last_reg_t last; // [5:4] + eth_idma_hw2reg_req_ready_reg_t req_ready; // [3:2] + eth_idma_hw2reg_rsp_valid_reg_t rsp_valid; // [1:0] + } eth_idma_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] ETH_IDMA_MACLO_ADDR_OFFSET = 7'h 0; + parameter logic [BlockAw-1:0] ETH_IDMA_MACHI_MDIO_OFFSET = 7'h 4; + parameter logic [BlockAw-1:0] ETH_IDMA_TX_FCS_OFFSET = 7'h 8; + parameter logic [BlockAw-1:0] ETH_IDMA_RX_FCS_OFFSET = 7'h c; + parameter logic [BlockAw-1:0] ETH_IDMA_SRC_ADDR_OFFSET = 7'h 10; + parameter logic [BlockAw-1:0] ETH_IDMA_DST_ADDR_OFFSET = 7'h 14; + parameter logic [BlockAw-1:0] ETH_IDMA_LENGTH_OFFSET = 7'h 18; + parameter logic [BlockAw-1:0] ETH_IDMA_SRC_PROTOCOL_OFFSET = 7'h 1c; + parameter logic [BlockAw-1:0] ETH_IDMA_DST_PROTOCOL_OFFSET = 7'h 20; + parameter logic [BlockAw-1:0] ETH_IDMA_AXI_ID_OFFSET = 7'h 24; + parameter logic [BlockAw-1:0] ETH_IDMA_OPT_SRC_OFFSET = 7'h 28; + parameter logic [BlockAw-1:0] ETH_IDMA_OPT_DST_OFFSET = 7'h 2c; + parameter logic [BlockAw-1:0] ETH_IDMA_BEO_OFFSET = 7'h 30; + parameter logic [BlockAw-1:0] ETH_IDMA_LAST_OFFSET = 7'h 34; + parameter logic [BlockAw-1:0] ETH_IDMA_REQ_VALID_OFFSET = 7'h 38; + parameter logic [BlockAw-1:0] ETH_IDMA_REQ_READY_OFFSET = 7'h 3c; + parameter logic [BlockAw-1:0] ETH_IDMA_RSP_READY_OFFSET = 7'h 40; + parameter logic [BlockAw-1:0] ETH_IDMA_RSP_VALID_OFFSET = 7'h 44; + + // Register index + typedef enum int { + ETH_IDMA_MACLO_ADDR, + ETH_IDMA_MACHI_MDIO, + ETH_IDMA_TX_FCS, + ETH_IDMA_RX_FCS, + ETH_IDMA_SRC_ADDR, + ETH_IDMA_DST_ADDR, + ETH_IDMA_LENGTH, + ETH_IDMA_SRC_PROTOCOL, + ETH_IDMA_DST_PROTOCOL, + ETH_IDMA_AXI_ID, + ETH_IDMA_OPT_SRC, + ETH_IDMA_OPT_DST, + ETH_IDMA_BEO, + ETH_IDMA_LAST, + ETH_IDMA_REQ_VALID, + ETH_IDMA_REQ_READY, + ETH_IDMA_RSP_READY, + ETH_IDMA_RSP_VALID + } eth_idma_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] ETH_IDMA_PERMIT [18] = '{ + 4'b 1111, // index[ 0] ETH_IDMA_MACLO_ADDR + 4'b 0111, // index[ 1] ETH_IDMA_MACHI_MDIO + 4'b 1111, // index[ 2] ETH_IDMA_TX_FCS + 4'b 1111, // index[ 3] ETH_IDMA_RX_FCS + 4'b 1111, // index[ 4] ETH_IDMA_SRC_ADDR + 4'b 1111, // index[ 5] ETH_IDMA_DST_ADDR + 4'b 1111, // index[ 6] ETH_IDMA_LENGTH + 4'b 0001, // index[ 7] ETH_IDMA_SRC_PROTOCOL + 4'b 0001, // index[ 8] ETH_IDMA_DST_PROTOCOL + 4'b 0001, // index[ 9] ETH_IDMA_AXI_ID + 4'b 0111, // index[10] ETH_IDMA_OPT_SRC + 4'b 0111, // index[11] ETH_IDMA_OPT_DST + 4'b 0011, // index[12] ETH_IDMA_BEO + 4'b 0001, // index[13] ETH_IDMA_LAST + 4'b 0001, // index[14] ETH_IDMA_REQ_VALID + 4'b 0001, // index[15] ETH_IDMA_REQ_READY + 4'b 0001, // index[16] ETH_IDMA_RSP_READY + 4'b 0001 // index[17] ETH_IDMA_RSP_VALID + }; + +endpackage + diff --git a/gen/eth_idma_reg_top.sv b/gen/eth_idma_reg_top.sv new file mode 100644 index 0000000..3c52819 --- /dev/null +++ b/gen/eth_idma_reg_top.sv @@ -0,0 +1,1470 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + + +`include "common_cells/assertions.svh" + +module eth_idma_reg_top #( + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter int AW = 7 +) ( + input logic clk_i, + input logic rst_ni, + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o, + // To HW + output eth_idma_reg_pkg::eth_idma_reg2hw_t reg2hw, // Write + input eth_idma_reg_pkg::eth_idma_hw2reg_t hw2reg, // Read + + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + + import eth_idma_reg_pkg::* ; + + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [BlockAw-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + + // Below register interface can be changed + reg_req_t reg_intf_req; + reg_rsp_t reg_intf_rsp; + + + assign reg_intf_req = reg_req_i; + assign reg_rsp_o = reg_intf_rsp; + + + assign reg_we = reg_intf_req.valid & reg_intf_req.write; + assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; + assign reg_addr = reg_intf_req.addr[BlockAw-1:0]; + assign reg_wdata = reg_intf_req.wdata; + assign reg_be = reg_intf_req.wstrb; + assign reg_intf_rsp.rdata = reg_rdata; + assign reg_intf_rsp.error = reg_error; + assign reg_intf_rsp.ready = 1'b1; + + assign reg_rdata = reg_rdata_next ; + assign reg_error = (devmode_i & addrmiss) | wr_err; + + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic [31:0] maclo_addr_qs; + logic [31:0] maclo_addr_wd; + logic maclo_addr_we; + logic [15:0] machi_mdio_upper_mac_address_qs; + logic [15:0] machi_mdio_upper_mac_address_wd; + logic machi_mdio_upper_mac_address_we; + logic machi_mdio_promiscuous_qs; + logic machi_mdio_promiscuous_wd; + logic machi_mdio_promiscuous_we; + logic machi_mdio_phy_mdclk_qs; + logic machi_mdio_phy_mdclk_wd; + logic machi_mdio_phy_mdclk_we; + logic machi_mdio_phy_mdio_o_qs; + logic machi_mdio_phy_mdio_o_wd; + logic machi_mdio_phy_mdio_o_we; + logic machi_mdio_phy_mdio_oe_qs; + logic machi_mdio_phy_mdio_oe_wd; + logic machi_mdio_phy_mdio_oe_we; + logic [31:0] tx_fcs_qs; + logic [31:0] rx_fcs_qs; + logic [31:0] src_addr_qs; + logic [31:0] src_addr_wd; + logic src_addr_we; + logic [31:0] dst_addr_qs; + logic [31:0] dst_addr_wd; + logic dst_addr_we; + logic [31:0] length_qs; + logic [31:0] length_wd; + logic length_we; + logic [2:0] src_protocol_qs; + logic [2:0] src_protocol_wd; + logic src_protocol_we; + logic [2:0] dst_protocol_qs; + logic [2:0] dst_protocol_wd; + logic dst_protocol_we; + logic axi_id_qs; + logic axi_id_wd; + logic axi_id_we; + logic [1:0] opt_src_burst_qs; + logic [1:0] opt_src_burst_wd; + logic opt_src_burst_we; + logic [3:0] opt_src_cache_qs; + logic [3:0] opt_src_cache_wd; + logic opt_src_cache_we; + logic opt_src_lock_qs; + logic opt_src_lock_wd; + logic opt_src_lock_we; + logic [2:0] opt_src_prot_qs; + logic [2:0] opt_src_prot_wd; + logic opt_src_prot_we; + logic [3:0] opt_src_qos_qs; + logic [3:0] opt_src_qos_wd; + logic opt_src_qos_we; + logic [3:0] opt_src_region_qs; + logic [3:0] opt_src_region_wd; + logic opt_src_region_we; + logic [1:0] opt_dst_burst_qs; + logic [1:0] opt_dst_burst_wd; + logic opt_dst_burst_we; + logic [3:0] opt_dst_cache_qs; + logic [3:0] opt_dst_cache_wd; + logic opt_dst_cache_we; + logic opt_dst_lock_qs; + logic opt_dst_lock_wd; + logic opt_dst_lock_we; + logic [2:0] opt_dst_prot_qs; + logic [2:0] opt_dst_prot_wd; + logic opt_dst_prot_we; + logic [3:0] opt_dst_qos_qs; + logic [3:0] opt_dst_qos_wd; + logic opt_dst_qos_we; + logic [3:0] opt_dst_region_qs; + logic [3:0] opt_dst_region_wd; + logic opt_dst_region_we; + logic beo_decouple_aw_qs; + logic beo_decouple_aw_wd; + logic beo_decouple_aw_we; + logic beo_decouple_rw_qs; + logic beo_decouple_rw_wd; + logic beo_decouple_rw_we; + logic [2:0] beo_src_max_llen_qs; + logic [2:0] beo_src_max_llen_wd; + logic beo_src_max_llen_we; + logic [2:0] beo_dst_max_llen_qs; + logic [2:0] beo_dst_max_llen_wd; + logic beo_dst_max_llen_we; + logic beo_src_reduce_len_qs; + logic beo_src_reduce_len_wd; + logic beo_src_reduce_len_we; + logic beo_dst_reduce_len_qs; + logic beo_dst_reduce_len_wd; + logic beo_dst_reduce_len_we; + logic last_qs; + logic last_wd; + logic last_we; + logic req_valid_qs; + logic req_valid_wd; + logic req_valid_we; + logic req_ready_qs; + logic rsp_ready_qs; + logic rsp_ready_wd; + logic rsp_ready_we; + logic rsp_valid_qs; + + // Register instances + // R[maclo_addr]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h890702) + ) u_maclo_addr ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (maclo_addr_we), + .wd (maclo_addr_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.maclo_addr.q ), + + // to register interface (read) + .qs (maclo_addr_qs) + ); + + + // R[machi_mdio]: V(False) + + // F[upper_mac_address]: 15:0 + prim_subreg #( + .DW (16), + .SWACCESS("RW"), + .RESVAL (16'h2301) + ) u_machi_mdio_upper_mac_address ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (machi_mdio_upper_mac_address_we), + .wd (machi_mdio_upper_mac_address_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.machi_mdio.upper_mac_address.q ), + + // to register interface (read) + .qs (machi_mdio_upper_mac_address_qs) + ); + + + // F[promiscuous]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_machi_mdio_promiscuous ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (machi_mdio_promiscuous_we), + .wd (machi_mdio_promiscuous_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.machi_mdio.promiscuous.q ), + + // to register interface (read) + .qs (machi_mdio_promiscuous_qs) + ); + + + // F[phy_mdclk]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_machi_mdio_phy_mdclk ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (machi_mdio_phy_mdclk_we), + .wd (machi_mdio_phy_mdclk_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.machi_mdio.phy_mdclk.q ), + + // to register interface (read) + .qs (machi_mdio_phy_mdclk_qs) + ); + + + // F[phy_mdio_o]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_machi_mdio_phy_mdio_o ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (machi_mdio_phy_mdio_o_we), + .wd (machi_mdio_phy_mdio_o_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.machi_mdio.phy_mdio_o.q ), + + // to register interface (read) + .qs (machi_mdio_phy_mdio_o_qs) + ); + + + // F[phy_mdio_oe]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_machi_mdio_phy_mdio_oe ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (machi_mdio_phy_mdio_oe_we), + .wd (machi_mdio_phy_mdio_oe_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.machi_mdio.phy_mdio_oe.q ), + + // to register interface (read) + .qs (machi_mdio_phy_mdio_oe_qs) + ); + + + // R[tx_fcs]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RO"), + .RESVAL (32'h0) + ) u_tx_fcs ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.tx_fcs.de), + .d (hw2reg.tx_fcs.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (tx_fcs_qs) + ); + + + // R[rx_fcs]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RO"), + .RESVAL (32'h0) + ) u_rx_fcs ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.rx_fcs.de), + .d (hw2reg.rx_fcs.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (rx_fcs_qs) + ); + + + // R[src_addr]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_src_addr ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (src_addr_we), + .wd (src_addr_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.src_addr.q ), + + // to register interface (read) + .qs (src_addr_qs) + ); + + + // R[dst_addr]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_dst_addr ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dst_addr_we), + .wd (dst_addr_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dst_addr.q ), + + // to register interface (read) + .qs (dst_addr_qs) + ); + + + // R[length]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_length ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (length_we), + .wd (length_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.length.q ), + + // to register interface (read) + .qs (length_qs) + ); + + + // R[src_protocol]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_src_protocol ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (src_protocol_we), + .wd (src_protocol_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.src_protocol.q ), + + // to register interface (read) + .qs (src_protocol_qs) + ); + + + // R[dst_protocol]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_dst_protocol ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (dst_protocol_we), + .wd (dst_protocol_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.dst_protocol.q ), + + // to register interface (read) + .qs (dst_protocol_qs) + ); + + + // R[axi_id]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_axi_id ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (axi_id_we), + .wd (axi_id_wd), + + // from internal hardware + .de (hw2reg.axi_id.de), + .d (hw2reg.axi_id.d ), + + // to internal hardware + .qe (), + .q (reg2hw.axi_id.q ), + + // to register interface (read) + .qs (axi_id_qs) + ); + + + // R[opt_src]: V(False) + + // F[burst]: 1:0 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h1) + ) u_opt_src_burst ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (opt_src_burst_we), + .wd (opt_src_burst_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.opt_src.burst.q ), + + // to register interface (read) + .qs (opt_src_burst_qs) + ); + + + // F[cache]: 5:2 + prim_subreg #( + .DW (4), + .SWACCESS("RW"), + .RESVAL (4'h0) + ) u_opt_src_cache ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (opt_src_cache_we), + .wd (opt_src_cache_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.opt_src.cache.q ), + + // to register interface (read) + .qs (opt_src_cache_qs) + ); + + + // F[lock]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_opt_src_lock ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (opt_src_lock_we), + .wd (opt_src_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.opt_src.lock.q ), + + // to register interface (read) + .qs (opt_src_lock_qs) + ); + + + // F[prot]: 9:7 + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_opt_src_prot ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (opt_src_prot_we), + .wd (opt_src_prot_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.opt_src.prot.q ), + + // to register interface (read) + .qs (opt_src_prot_qs) + ); + + + // F[qos]: 13:10 + prim_subreg #( + .DW (4), + .SWACCESS("RW"), + .RESVAL (4'h0) + ) u_opt_src_qos ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (opt_src_qos_we), + .wd (opt_src_qos_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.opt_src.qos.q ), + + // to register interface (read) + .qs (opt_src_qos_qs) + ); + + + // F[region]: 17:14 + prim_subreg #( + .DW (4), + .SWACCESS("RW"), + .RESVAL (4'h0) + ) u_opt_src_region ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (opt_src_region_we), + .wd (opt_src_region_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.opt_src.region.q ), + + // to register interface (read) + .qs (opt_src_region_qs) + ); + + + // R[opt_dst]: V(False) + + // F[burst]: 1:0 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h1) + ) u_opt_dst_burst ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (opt_dst_burst_we), + .wd (opt_dst_burst_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.opt_dst.burst.q ), + + // to register interface (read) + .qs (opt_dst_burst_qs) + ); + + + // F[cache]: 5:2 + prim_subreg #( + .DW (4), + .SWACCESS("RW"), + .RESVAL (4'h0) + ) u_opt_dst_cache ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (opt_dst_cache_we), + .wd (opt_dst_cache_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.opt_dst.cache.q ), + + // to register interface (read) + .qs (opt_dst_cache_qs) + ); + + + // F[lock]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_opt_dst_lock ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (opt_dst_lock_we), + .wd (opt_dst_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.opt_dst.lock.q ), + + // to register interface (read) + .qs (opt_dst_lock_qs) + ); + + + // F[prot]: 9:7 + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_opt_dst_prot ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (opt_dst_prot_we), + .wd (opt_dst_prot_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.opt_dst.prot.q ), + + // to register interface (read) + .qs (opt_dst_prot_qs) + ); + + + // F[qos]: 13:10 + prim_subreg #( + .DW (4), + .SWACCESS("RW"), + .RESVAL (4'h0) + ) u_opt_dst_qos ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (opt_dst_qos_we), + .wd (opt_dst_qos_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.opt_dst.qos.q ), + + // to register interface (read) + .qs (opt_dst_qos_qs) + ); + + + // F[region]: 17:14 + prim_subreg #( + .DW (4), + .SWACCESS("RW"), + .RESVAL (4'h0) + ) u_opt_dst_region ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (opt_dst_region_we), + .wd (opt_dst_region_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.opt_dst.region.q ), + + // to register interface (read) + .qs (opt_dst_region_qs) + ); + + + // R[beo]: V(False) + + // F[decouple_aw]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_beo_decouple_aw ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (beo_decouple_aw_we), + .wd (beo_decouple_aw_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.beo.decouple_aw.q ), + + // to register interface (read) + .qs (beo_decouple_aw_qs) + ); + + + // F[decouple_rw]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_beo_decouple_rw ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (beo_decouple_rw_we), + .wd (beo_decouple_rw_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.beo.decouple_rw.q ), + + // to register interface (read) + .qs (beo_decouple_rw_qs) + ); + + + // F[src_max_llen]: 4:2 + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_beo_src_max_llen ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (beo_src_max_llen_we), + .wd (beo_src_max_llen_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.beo.src_max_llen.q ), + + // to register interface (read) + .qs (beo_src_max_llen_qs) + ); + + + // F[dst_max_llen]: 7:5 + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_beo_dst_max_llen ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (beo_dst_max_llen_we), + .wd (beo_dst_max_llen_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.beo.dst_max_llen.q ), + + // to register interface (read) + .qs (beo_dst_max_llen_qs) + ); + + + // F[src_reduce_len]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_beo_src_reduce_len ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (beo_src_reduce_len_we), + .wd (beo_src_reduce_len_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.beo.src_reduce_len.q ), + + // to register interface (read) + .qs (beo_src_reduce_len_qs) + ); + + + // F[dst_reduce_len]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_beo_dst_reduce_len ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (beo_dst_reduce_len_we), + .wd (beo_dst_reduce_len_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.beo.dst_reduce_len.q ), + + // to register interface (read) + .qs (beo_dst_reduce_len_qs) + ); + + + // R[last]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_last ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (last_we), + .wd (last_wd), + + // from internal hardware + .de (hw2reg.last.de), + .d (hw2reg.last.d ), + + // to internal hardware + .qe (), + .q (reg2hw.last.q ), + + // to register interface (read) + .qs (last_qs) + ); + + + // R[req_valid]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_req_valid ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (req_valid_we), + .wd (req_valid_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.req_valid.q ), + + // to register interface (read) + .qs (req_valid_qs) + ); + + + // R[req_ready]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_req_ready ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.req_ready.de), + .d (hw2reg.req_ready.d ), + + // to internal hardware + .qe (), + .q (reg2hw.req_ready.q ), + + // to register interface (read) + .qs (req_ready_qs) + ); + + + // R[rsp_ready]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_rsp_ready ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (rsp_ready_we), + .wd (rsp_ready_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.rsp_ready.q ), + + // to register interface (read) + .qs (rsp_ready_qs) + ); + + + // R[rsp_valid]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_rsp_valid ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.rsp_valid.de), + .d (hw2reg.rsp_valid.d ), + + // to internal hardware + .qe (), + .q (reg2hw.rsp_valid.q ), + + // to register interface (read) + .qs (rsp_valid_qs) + ); + + + + + logic [17:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == ETH_IDMA_MACLO_ADDR_OFFSET); + addr_hit[ 1] = (reg_addr == ETH_IDMA_MACHI_MDIO_OFFSET); + addr_hit[ 2] = (reg_addr == ETH_IDMA_TX_FCS_OFFSET); + addr_hit[ 3] = (reg_addr == ETH_IDMA_RX_FCS_OFFSET); + addr_hit[ 4] = (reg_addr == ETH_IDMA_SRC_ADDR_OFFSET); + addr_hit[ 5] = (reg_addr == ETH_IDMA_DST_ADDR_OFFSET); + addr_hit[ 6] = (reg_addr == ETH_IDMA_LENGTH_OFFSET); + addr_hit[ 7] = (reg_addr == ETH_IDMA_SRC_PROTOCOL_OFFSET); + addr_hit[ 8] = (reg_addr == ETH_IDMA_DST_PROTOCOL_OFFSET); + addr_hit[ 9] = (reg_addr == ETH_IDMA_AXI_ID_OFFSET); + addr_hit[10] = (reg_addr == ETH_IDMA_OPT_SRC_OFFSET); + addr_hit[11] = (reg_addr == ETH_IDMA_OPT_DST_OFFSET); + addr_hit[12] = (reg_addr == ETH_IDMA_BEO_OFFSET); + addr_hit[13] = (reg_addr == ETH_IDMA_LAST_OFFSET); + addr_hit[14] = (reg_addr == ETH_IDMA_REQ_VALID_OFFSET); + addr_hit[15] = (reg_addr == ETH_IDMA_REQ_READY_OFFSET); + addr_hit[16] = (reg_addr == ETH_IDMA_RSP_READY_OFFSET); + addr_hit[17] = (reg_addr == ETH_IDMA_RSP_VALID_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(ETH_IDMA_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(ETH_IDMA_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(ETH_IDMA_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(ETH_IDMA_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(ETH_IDMA_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(ETH_IDMA_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(ETH_IDMA_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(ETH_IDMA_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(ETH_IDMA_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(ETH_IDMA_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(ETH_IDMA_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(ETH_IDMA_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(ETH_IDMA_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(ETH_IDMA_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(ETH_IDMA_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(ETH_IDMA_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(ETH_IDMA_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(ETH_IDMA_PERMIT[17] & ~reg_be))))); + end + + assign maclo_addr_we = addr_hit[0] & reg_we & !reg_error; + assign maclo_addr_wd = reg_wdata[31:0]; + + assign machi_mdio_upper_mac_address_we = addr_hit[1] & reg_we & !reg_error; + assign machi_mdio_upper_mac_address_wd = reg_wdata[15:0]; + + assign machi_mdio_promiscuous_we = addr_hit[1] & reg_we & !reg_error; + assign machi_mdio_promiscuous_wd = reg_wdata[16]; + + assign machi_mdio_phy_mdclk_we = addr_hit[1] & reg_we & !reg_error; + assign machi_mdio_phy_mdclk_wd = reg_wdata[17]; + + assign machi_mdio_phy_mdio_o_we = addr_hit[1] & reg_we & !reg_error; + assign machi_mdio_phy_mdio_o_wd = reg_wdata[18]; + + assign machi_mdio_phy_mdio_oe_we = addr_hit[1] & reg_we & !reg_error; + assign machi_mdio_phy_mdio_oe_wd = reg_wdata[19]; + + assign src_addr_we = addr_hit[4] & reg_we & !reg_error; + assign src_addr_wd = reg_wdata[31:0]; + + assign dst_addr_we = addr_hit[5] & reg_we & !reg_error; + assign dst_addr_wd = reg_wdata[31:0]; + + assign length_we = addr_hit[6] & reg_we & !reg_error; + assign length_wd = reg_wdata[31:0]; + + assign src_protocol_we = addr_hit[7] & reg_we & !reg_error; + assign src_protocol_wd = reg_wdata[2:0]; + + assign dst_protocol_we = addr_hit[8] & reg_we & !reg_error; + assign dst_protocol_wd = reg_wdata[2:0]; + + assign axi_id_we = addr_hit[9] & reg_we & !reg_error; + assign axi_id_wd = reg_wdata[0]; + + assign opt_src_burst_we = addr_hit[10] & reg_we & !reg_error; + assign opt_src_burst_wd = reg_wdata[1:0]; + + assign opt_src_cache_we = addr_hit[10] & reg_we & !reg_error; + assign opt_src_cache_wd = reg_wdata[5:2]; + + assign opt_src_lock_we = addr_hit[10] & reg_we & !reg_error; + assign opt_src_lock_wd = reg_wdata[6]; + + assign opt_src_prot_we = addr_hit[10] & reg_we & !reg_error; + assign opt_src_prot_wd = reg_wdata[9:7]; + + assign opt_src_qos_we = addr_hit[10] & reg_we & !reg_error; + assign opt_src_qos_wd = reg_wdata[13:10]; + + assign opt_src_region_we = addr_hit[10] & reg_we & !reg_error; + assign opt_src_region_wd = reg_wdata[17:14]; + + assign opt_dst_burst_we = addr_hit[11] & reg_we & !reg_error; + assign opt_dst_burst_wd = reg_wdata[1:0]; + + assign opt_dst_cache_we = addr_hit[11] & reg_we & !reg_error; + assign opt_dst_cache_wd = reg_wdata[5:2]; + + assign opt_dst_lock_we = addr_hit[11] & reg_we & !reg_error; + assign opt_dst_lock_wd = reg_wdata[6]; + + assign opt_dst_prot_we = addr_hit[11] & reg_we & !reg_error; + assign opt_dst_prot_wd = reg_wdata[9:7]; + + assign opt_dst_qos_we = addr_hit[11] & reg_we & !reg_error; + assign opt_dst_qos_wd = reg_wdata[13:10]; + + assign opt_dst_region_we = addr_hit[11] & reg_we & !reg_error; + assign opt_dst_region_wd = reg_wdata[17:14]; + + assign beo_decouple_aw_we = addr_hit[12] & reg_we & !reg_error; + assign beo_decouple_aw_wd = reg_wdata[0]; + + assign beo_decouple_rw_we = addr_hit[12] & reg_we & !reg_error; + assign beo_decouple_rw_wd = reg_wdata[1]; + + assign beo_src_max_llen_we = addr_hit[12] & reg_we & !reg_error; + assign beo_src_max_llen_wd = reg_wdata[4:2]; + + assign beo_dst_max_llen_we = addr_hit[12] & reg_we & !reg_error; + assign beo_dst_max_llen_wd = reg_wdata[7:5]; + + assign beo_src_reduce_len_we = addr_hit[12] & reg_we & !reg_error; + assign beo_src_reduce_len_wd = reg_wdata[8]; + + assign beo_dst_reduce_len_we = addr_hit[12] & reg_we & !reg_error; + assign beo_dst_reduce_len_wd = reg_wdata[9]; + + assign last_we = addr_hit[13] & reg_we & !reg_error; + assign last_wd = reg_wdata[0]; + + assign req_valid_we = addr_hit[14] & reg_we & !reg_error; + assign req_valid_wd = reg_wdata[0]; + + assign rsp_ready_we = addr_hit[16] & reg_we & !reg_error; + assign rsp_ready_wd = reg_wdata[0]; + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[31:0] = maclo_addr_qs; + end + + addr_hit[1]: begin + reg_rdata_next[15:0] = machi_mdio_upper_mac_address_qs; + reg_rdata_next[16] = machi_mdio_promiscuous_qs; + reg_rdata_next[17] = machi_mdio_phy_mdclk_qs; + reg_rdata_next[18] = machi_mdio_phy_mdio_o_qs; + reg_rdata_next[19] = machi_mdio_phy_mdio_oe_qs; + end + + addr_hit[2]: begin + reg_rdata_next[31:0] = tx_fcs_qs; + end + + addr_hit[3]: begin + reg_rdata_next[31:0] = rx_fcs_qs; + end + + addr_hit[4]: begin + reg_rdata_next[31:0] = src_addr_qs; + end + + addr_hit[5]: begin + reg_rdata_next[31:0] = dst_addr_qs; + end + + addr_hit[6]: begin + reg_rdata_next[31:0] = length_qs; + end + + addr_hit[7]: begin + reg_rdata_next[2:0] = src_protocol_qs; + end + + addr_hit[8]: begin + reg_rdata_next[2:0] = dst_protocol_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = axi_id_qs; + end + + addr_hit[10]: begin + reg_rdata_next[1:0] = opt_src_burst_qs; + reg_rdata_next[5:2] = opt_src_cache_qs; + reg_rdata_next[6] = opt_src_lock_qs; + reg_rdata_next[9:7] = opt_src_prot_qs; + reg_rdata_next[13:10] = opt_src_qos_qs; + reg_rdata_next[17:14] = opt_src_region_qs; + end + + addr_hit[11]: begin + reg_rdata_next[1:0] = opt_dst_burst_qs; + reg_rdata_next[5:2] = opt_dst_cache_qs; + reg_rdata_next[6] = opt_dst_lock_qs; + reg_rdata_next[9:7] = opt_dst_prot_qs; + reg_rdata_next[13:10] = opt_dst_qos_qs; + reg_rdata_next[17:14] = opt_dst_region_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = beo_decouple_aw_qs; + reg_rdata_next[1] = beo_decouple_rw_qs; + reg_rdata_next[4:2] = beo_src_max_llen_qs; + reg_rdata_next[7:5] = beo_dst_max_llen_qs; + reg_rdata_next[8] = beo_src_reduce_len_qs; + reg_rdata_next[9] = beo_dst_reduce_len_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = last_qs; + end + + addr_hit[14]: begin + reg_rdata_next[0] = req_valid_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = req_ready_qs; + end + + addr_hit[16]: begin + reg_rdata_next[0] = rsp_ready_qs; + end + + addr_hit[17]: begin + reg_rdata_next[0] = rsp_valid_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) + +endmodule + +module eth_idma_reg_top_intf +#( + parameter int AW = 7, + localparam int DW = 32 +) ( + input logic clk_i, + input logic rst_ni, + REG_BUS.in regbus_slave, + // To HW + output eth_idma_reg_pkg::eth_idma_reg2hw_t reg2hw, // Write + input eth_idma_reg_pkg::eth_idma_hw2reg_t hw2reg, // Read + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + localparam int unsigned STRB_WIDTH = DW/8; + +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" + + // Define structs for reg_bus + typedef logic [AW-1:0] addr_t; + typedef logic [DW-1:0] data_t; + typedef logic [STRB_WIDTH-1:0] strb_t; + `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t) + + reg_bus_req_t s_reg_req; + reg_bus_rsp_t s_reg_rsp; + + // Assign SV interface to structs + `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave) + `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp) + + + + eth_idma_reg_top #( + .reg_req_t(reg_bus_req_t), + .reg_rsp_t(reg_bus_rsp_t), + .AW(AW) + ) i_regs ( + .clk_i, + .rst_ni, + .reg_req_i(s_reg_req), + .reg_rsp_o(s_reg_rsp), + .reg2hw, // Write + .hw2reg, // Read + .devmode_i + ); + +endmodule + + diff --git a/rtl/clk_gen_hyper.sv b/rtl/clk_gen_hyper.sv new file mode 100644 index 0000000..adf9c8b --- /dev/null +++ b/rtl/clk_gen_hyper.sv @@ -0,0 +1,61 @@ +// Copyright 2018-2021 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//// Hayate Okuhara + +// Description: Generates 4 phase shifted clocks out of one faster clock +module clk_gen_hyper ( + input logic clk_i, // input clock + input logic rst_ni, + output logic clk0_o, // have the input clock - 0deg phase shift + output logic clk90_o, // have the input clock - 90deg phase shift + output logic clk180_o, // have the input clock - 180deg phase shift + output logic clk270_o // have the input clock - 270deg phase shift +); + +//`ifndef PULP_FPGA_EMUL + logic r_clk0_o; + logic r_clk90_o; + logic r_clk180_o; + logic r_clk270_o; + + assign clk0_o = r_clk0_o; + assign clk90_o = r_clk90_o; + assign clk180_o = r_clk180_o; + assign clk270_o = r_clk270_o; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + r_clk0_o <= 0; + r_clk180_o <= 1; + end else begin + r_clk0_o <= ~r_clk0_o; + r_clk180_o <= r_clk90_o; + end + end + + always_ff @(negedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + r_clk90_o <= 0; + r_clk270_o <= 1; + end else begin + r_clk90_o <= r_clk0_o; + r_clk270_o <= r_clk180_o; + end + end +/*`else + assign clk0_o = clk_i; + assign clk90_o = clk_i; + assign clk180_o = clk_i; + assign clk270_o = clk_i; +`endif*/ +endmodule + diff --git a/rtl/eth_clk_gen.sv b/rtl/eth_clk_gen.sv new file mode 100644 index 0000000..3939de3 --- /dev/null +++ b/rtl/eth_clk_gen.sv @@ -0,0 +1,47 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// +// Chaoqun Liang + +module eth_clk_gen ( + input logic ref_clk_i, + input logic rst_ni, + output logic clk_eth_125_o, + output logic clk_eth_125_90_o +); + +logic clk_eth_125; +assign clk_eth_125 = clk_eth_125_o; + +fll_dummy i_gf12_fll ( // Clock & reset + .OUTCLK ( clk_eth_125_o ), // FLL clock outputs + .REFCLK ( ref_clk_i ), // Reference clock input + .RSTB ( rst_ni ), // Asynchronous reset (active low) + .CFGREQ ( ), // CFG I/F access request (active high) + .CFGACK ( ), // CFG I/F access granted (active high) + .CFGAD ( ), // CFG I/F address bus + .CFGD ( ), // CFG I/F input data bus (write) + .CFGQ ( ), // CFG I/F output data bus (read) + .CFGWEB ( ), // CFG I/F write enable (active low) + .PWD ( 1'b0 ), // Asynchronous power down (active high) + .RET ( 1'b0 ), // Asynchronous retention/isolation control (active high) + .TM ( 1'b0 ), // Test mode (active high) + .TE ( 1'b0 ), // Scan enable (active high) + .TD ( '0 ), // Scan data input for chain 1:4 + .TQ ( ), // Scan data output for chain 1:4 + .JTD ( 1'b0 ), // Scan data in 5 + .JTQ ( ) // Scan data out 5 +); + +clk_gen_hyper i_clk_gen_ethernet ( + .clk_i ( clk_eth_125 ), + .rst_ni ( rst_ni ), + .clk0_o ( ), + .clk90_o ( clk_eth_125_90_o ), + .clk180_o ( ), + .clk270_o ( ) +); + +endmodule : eth_clk_gen \ No newline at end of file diff --git a/rtl/eth_idma_pkg.sv b/rtl/eth_idma_pkg.sv new file mode 100644 index 0000000..af6b722 --- /dev/null +++ b/rtl/eth_idma_pkg.sv @@ -0,0 +1,102 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + + +`include "axi_stream/assign.svh" +`include "axi_stream/typedef.svh" +`include "axi/typedef.svh" +`include "idma/typedef.svh" +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" + +package eth_idma_pkg; + + /// Ethernet reg typedefs + parameter int AW_REGBUS = 32; + localparam int DW_REGBUS = 32; + localparam int unsigned STRB_WIDTH = DW_REGBUS/8; + + typedef logic [AW_REGBUS-1:0] reg_bus_addr_t; + typedef logic [DW_REGBUS-1:0] reg_bus_data_t; + typedef logic [STRB_WIDTH-1:0] reg_bus_strb_t; + + `REG_BUS_TYPEDEF_ALL(reg_bus, reg_bus_addr_t, reg_bus_data_t, reg_bus_strb_t) + + parameter int unsigned DataWidth = 64; + parameter int unsigned AddrWidth = 64; + parameter int unsigned UserWidth = 1; + parameter int unsigned AxiIdWidth = 5; + parameter int unsigned TFLenWidth = 32; + + localparam int unsigned StrbWidth = DataWidth / 8; + localparam int unsigned OffsetWidth = $clog2(StrbWidth); + + typedef logic [AddrWidth-1:0] addr_t; + typedef logic [AxiIdWidth-1:0] id_t; + typedef logic [UserWidth-1:0] user_t; + typedef logic [StrbWidth-1:0] strb_t; + typedef logic [DataWidth-1:0] data_t; + typedef logic [TFLenWidth-1:0] tf_len_t; + + /// AXI4+ATOP typedefs + `AXI_TYPEDEF_AW_CHAN_T(axi_aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(axi_w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(axi_b_chan_t, id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(axi_ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(axi_r_chan_t, data_t, id_t, user_t) + + `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_chan_t, axi_w_chan_t, axi_ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_rsp_t, axi_b_chan_t, axi_r_chan_t) + + /// AXI Stream typedefs + `IDMA_AXI_STREAM_TYPEDEF_S_CHAN_T(axis_t_chan_t, data_t, strb_t, strb_t, id_t, id_t, user_t) + `IDMA_AXI_STREAM_TYPEDEF_REQ_T(axi_stream_req_t, axis_t_chan_t) + `IDMA_AXI_STREAM_TYPEDEF_RSP_T(axi_stream_rsp_t) + + /// Meta Channel Widths + localparam int unsigned axi_aw_chan_width = axi_pkg::aw_width(AddrWidth, AxiIdWidth, UserWidth); + localparam int unsigned axi_ar_chan_width = axi_pkg::ar_width(AddrWidth, AxiIdWidth, UserWidth); + localparam int unsigned axis_t_chan_width = $bits(axis_t_chan_t); + + `IDMA_TYPEDEF_OPTIONS_T(options_t, id_t) + `IDMA_TYPEDEF_REQ_T(idma_req_t, tf_len_t, addr_t, options_t) + `IDMA_TYPEDEF_ERR_PAYLOAD_T(err_payload_t, addr_t) + `IDMA_TYPEDEF_RSP_T(idma_rsp_t, err_payload_t) + + function int unsigned max_width(input int unsigned a, b); + return (a > b) ? a : b; + endfunction + +typedef struct packed { + axi_ar_chan_t ar_chan; + logic[max_width(axi_ar_chan_width, axis_t_chan_width)-axi_ar_chan_width:0] padding; +} axi_read_ar_chan_padded_t; + +typedef struct packed { + axis_t_chan_t t_chan; + logic[max_width(axi_ar_chan_width, axis_t_chan_width)-axis_t_chan_width:0] padding; +} axis_read_t_chan_padded_t; + +typedef union packed { + axi_read_ar_chan_padded_t axi; + axis_read_t_chan_padded_t axis; +} read_meta_channel_t; + +typedef struct packed { + axi_aw_chan_t aw_chan; + logic[max_width(axi_aw_chan_width, axis_t_chan_width)-axi_aw_chan_width:0] padding; +} axi_write_aw_chan_padded_t; + +typedef struct packed { + axis_t_chan_t t_chan; + logic[max_width(axi_aw_chan_width, axis_t_chan_width)-axis_t_chan_width:0] padding; +} axis_write_t_chan_padded_t; + +typedef union packed { + axi_write_aw_chan_padded_t axi; + axis_write_t_chan_padded_t axis; +} write_meta_channel_t; + +endpackage : eth_idma_pkg diff --git a/rtl/eth_idma_wrap.sv b/rtl/eth_idma_wrap.sv new file mode 100644 index 0000000..3db60a0 --- /dev/null +++ b/rtl/eth_idma_wrap.sv @@ -0,0 +1,299 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Chaoqun Liang + +`include "axi/assign.svh" +`include "axi/typedef.svh" +`include "axi_stream/assign.svh" +`include "axi_stream/typedef.svh" +`include "idma/typedef.svh" +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" +`include "common_cells/registers.svh" + +module eth_idma_wrap #( + /// Data width + parameter int unsigned DataWidth = 32'd32, + /// Address width + parameter int unsigned AddrWidth = 32'd32, + /// AXI User width + parameter int unsigned UserWidth = 32'd1, + /// AXI ID width + parameter int unsigned AxiIdWidth = 32'd1, + /// Number of transaction that can be in-flight concurrently + parameter int unsigned NumAxInFlight = 32'd3, + /// The depth of the internal reorder buffer + parameter int unsigned BufferDepth = 32'd3, + /// With of a transfer: max transfer size is `2**TFLenWidth` bytes + parameter int unsigned TFLenWidth = 32'd32, + /// The depth of the memory system the backend is attached to + parameter int unsigned MemSysDepth = 32'd0, + /// Should the `R`-`AW` coupling hardware be present? (recommended) + parameter bit RAWCouplingAvail = 1'b0, + /// Mask invalid data on the manager interface + parameter bit MaskInvalidData = 1'b1, + parameter bit CombinedShifter = 1'b1, + /// hardware legalization present + parameter bit HardwareLegalizer = 1'b1, + /// Reject zero-length transfers + parameter bit RejectZeroTransfers = 1'b1, + /// Enable error handling + parameter bit ErrorHandling = 1'b0, + /// CDC FIFO + parameter int unsigned TxFifoLogDepth = 32'd8, + parameter int unsigned RxFifoLogDepth = 32'd8, + /// Register bus + parameter type reg_req_t = eth_idma_pkg::reg_bus_req_t, + parameter type reg_rsp_t = eth_idma_pkg::reg_bus_rsp_t +)( + input logic clk_i, + input logic rst_ni, + /// Ethernet: 1000BASE-T RGMII + input logic phy_rx_clk_i, + input logic [3:0] phy_rxd_i, + input logic phy_rx_ctl_i, + output logic phy_tx_clk_o, + output logic [3:0] phy_txd_o, + output logic phy_tx_ctl_o, + output logic phy_resetn_o, + input logic phy_intn_i, + input logic phy_pme_i, + /// Ethernet MDIO + input logic phy_mdio_i, + output logic phy_mdio_o, + output logic phy_mdio_oe, + output wire phy_mdc_o, + /// iDMA testmode + input logic testmode_i, + /// Error handler request + input idma_pkg::idma_eh_req_t idma_eh_req_i, + input logic eh_req_valid_i, + output logic eh_req_ready_o, + output eth_idma_pkg::axi_req_t axi_req_o, + input eth_idma_pkg::axi_rsp_t axi_rsp_i, + /// iDMA busy flags + output idma_pkg::idma_busy_t idma_busy_o, + /// REGBUS Configuration Interface + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o +); + + import eth_idma_pkg::*; + import eth_idma_reg_pkg::*; + import idma_pkg::*; + + logic eth_clk, eth_clk90; + logic idma_req_valid, req_ready, idma_rsp_ready, rsp_valid; + + localparam idma_pkg::error_cap_e ErrorCap = ErrorHandling ? ERROR_HANDLING : NO_ERROR_HANDLING; + localparam int unsigned AW_REGBUS = 8; + + eth_idma_reg_pkg::eth_idma_reg2hw_t reg2hw; // Write + eth_idma_reg_pkg::eth_idma_hw2reg_t hw2reg; // Read + + eth_idma_reg_top #( + .reg_req_t(reg_req_t), + .reg_rsp_t(reg_rsp_t), + .AW(AW_REGBUS) + ) i_regs ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .reg_req_i(reg_req_i), + .reg_rsp_o(reg_rsp_o), + .reg2hw(reg2hw), // Write + .hw2reg(hw2reg), // Read + .devmode_i(1'b1) + ); + + /// AXI request and response + eth_idma_pkg::axi_req_t axi_read_req,axi_write_req; + eth_idma_pkg::axi_rsp_t axi_read_rsp,axi_write_rsp; + + /// AXI Stream request and response + axi_stream_rsp_t idma_axis_read_rsp, eth_axis_tx_rsp; + axi_stream_req_t idma_axis_read_req, eth_axis_tx_req; + + axi_stream_req_t idma_axis_write_req, eth_axis_rx_rsp; + axi_stream_rsp_t idma_axis_write_rsp, eth_axis_rx_req; + + idma_req_t idma_reg_req; + idma_rsp_t idma_reg_rsp; + + assign idma_reg_req.length = reg2hw.length.q; + assign idma_reg_req.src_addr = reg2hw.src_addr.q; + assign idma_reg_req.dst_addr = reg2hw.dst_addr.q; + + assign idma_reg_req.opt.src_protocol = protocol_e'(reg2hw.src_protocol.q); + assign idma_reg_req.opt.dst_protocol = protocol_e'(reg2hw.dst_protocol.q); + + assign idma_reg_req.opt.axi_id = reg2hw.axi_id.q; + + assign idma_reg_req.opt.src.burst = reg2hw.opt_src.burst.q; + assign idma_reg_req.opt.src.cache = reg2hw.opt_src.cache.q; + assign idma_reg_req.opt.src.lock = reg2hw.opt_src.lock.q; + assign idma_reg_req.opt.src.prot = reg2hw.opt_src.prot.q; + assign idma_reg_req.opt.src.qos = reg2hw.opt_src.qos.q; + assign idma_reg_req.opt.src.region = reg2hw.opt_src.region.q; + + assign idma_reg_req.opt.dst.burst = reg2hw.opt_dst.burst.q; + assign idma_reg_req.opt.dst.cache = reg2hw.opt_dst.cache.q; + assign idma_reg_req.opt.dst.lock = reg2hw.opt_dst.lock.q; + assign idma_reg_req.opt.dst.prot = reg2hw.opt_dst.prot.q; + assign idma_reg_req.opt.dst.qos = reg2hw.opt_dst.qos.q; + assign idma_reg_req.opt.dst.region = reg2hw.opt_dst.region.q; + + assign idma_reg_req.opt.beo.decouple_aw = reg2hw.beo.decouple_aw.q; + assign idma_reg_req.opt.beo.decouple_rw = reg2hw.beo.decouple_rw.q; + assign idma_reg_req.opt.beo.src_max_llen = reg2hw.beo.src_max_llen.q; + assign idma_reg_req.opt.beo.dst_max_llen = reg2hw.beo.dst_max_llen.q; + assign idma_reg_req.opt.beo.src_reduce_len = reg2hw.beo.src_reduce_len.q; + assign idma_reg_req.opt.beo.dst_reduce_len = reg2hw.beo.dst_reduce_len.q; + + assign idma_reg_req.opt.last = reg2hw.last.q; + /// idma start signals + assign idma_req_valid = reg2hw.req_valid.q; + assign idma_rsp_ready = reg2hw.rsp_ready.q; + + idma_backend_rw_axi_rw_axis #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .AxiIdWidth ( AxiIdWidth ), + .UserWidth ( UserWidth ), + .TFLenWidth ( TFLenWidth ), + .BufferDepth ( BufferDepth ), + .NumAxInFlight ( NumAxInFlight ), + .MemSysDepth ( MemSysDepth ), + .RAWCouplingAvail ( RAWCouplingAvail ), + .MaskInvalidData ( MaskInvalidData ), + .HardwareLegalizer ( HardwareLegalizer ), + .RejectZeroTransfers ( RejectZeroTransfers ), + .ErrorCap ( ErrorCap ), + .idma_req_t ( idma_req_t ), + .idma_rsp_t ( idma_rsp_t ), + .idma_eh_req_t ( idma_eh_req_t ), + .idma_busy_t ( idma_busy_t ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ), + .axis_req_t ( axi_stream_req_t ), + .axis_rsp_t ( axi_stream_rsp_t ), + .write_meta_channel_t ( write_meta_channel_t ), + .read_meta_channel_t ( read_meta_channel_t ) + ) i_idma_backend ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( testmode_i ), + .idma_req_i ( idma_reg_req ), + .req_valid_i ( idma_req_valid ), + .req_ready_o ( req_ready ), + .idma_rsp_o ( idma_reg_rsp ), + .rsp_valid_o ( rsp_valid ), + .rsp_ready_i ( idma_rsp_ready ), + .idma_eh_req_i ( idma_eh_req_i ), + .eh_req_valid_i ( eh_req_valid_i ), + .eh_req_ready_o ( eh_req_ready_o ), + .axi_write_req_o ( axi_write_req ), + .axi_write_rsp_i ( axi_write_rsp ), + .axi_read_req_o ( axi_read_req ), + .axi_read_rsp_i ( axi_read_rsp ), + .axis_read_req_i ( idma_axis_read_req ), + .axis_read_rsp_o ( idma_axis_read_rsp ), + .axis_write_req_o ( idma_axis_write_req ), + .axis_write_rsp_i ( idma_axis_write_rsp ), + .busy_o ( idma_busy_o ) + ); + + eth_clk_gen i_eth_clk_gen( + .ref_clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clk_eth_125_o ( eth_clk ), + .clk_eth_125_90_o ( eth_clk90 ) + ); + + eth_top #( + .axi_stream_req_t ( axi_stream_req_t ), + .axi_stream_rsp_t ( axi_stream_rsp_t ), + .DataWidth ( DataWidth ), + .IdWidth ( 32'd0 ), + .DestWidth ( 32'd0 ), + .UserWidth ( 32'd1 ), + .AW_REGBUS ( AW_REGBUS ), + .reg2hw_itf_t ( eth_idma_reg2hw_t ), + .hw2reg_itf_t ( eth_idma_hw2reg_t ) + ) i_eth_top ( + .rst_ni ( rst_ni ), + .clk_i ( eth_clk ), + .clk90_int ( eth_clk90 ), + .phy_rx_clk ( phy_rx_clk_i ), + .phy_rxd ( phy_rxd_i ), + .phy_rx_ctl ( phy_rx_ctl_i ), + .phy_tx_clk ( phy_tx_clk_o ), + .phy_txd ( phy_txd_o ), + .phy_tx_ctl ( phy_tx_ctl_o ), + .phy_reset_n ( phy_resetn_o ), + .phy_int_n ( phy_intn_i ), + .phy_pme_n ( phy_pme_i ), + .phy_mdio_i ( phy_mdio_i ), + .phy_mdio_o ( phy_mdio_o ), + .phy_mdio_oe ( phy_mdio_oe ), + .phy_mdc ( phy_mdc ), + .tx_axis_req_i ( eth_axis_tx_req ), + .tx_axis_rsp_o ( eth_axis_tx_rsp ), + .rx_axis_req_o ( eth_axis_rx_rsp ), + .rx_axis_rsp_i ( eth_axis_rx_req ), + .idma_req_ready ( req_ready ), + .idma_rsp_valid ( rsp_valid ), + .reg2hw_i ( reg2hw ), + .hw2reg_o ( hw2reg ) + ); + + // TX CDC FIFO + cdc_fifo_gray #( + .T ( axis_t_chan_t ), + .LOG_DEPTH ( TxFifoLogDepth ) + ) i_cdc_fifo_tx ( + .src_rst_ni ( rst_ni ), + .src_clk_i ( clk_i ), + .src_data_i ( idma_axis_write_req.t ), + .src_valid_i ( idma_axis_write_req.tvalid ), + .src_ready_o ( idma_axis_write_rsp.tready ), + .dst_rst_ni ( rst_ni ), + .dst_clk_i ( eth_clk ), + .dst_data_o ( eth_axis_tx_req.t ), + .dst_valid_o ( eth_axis_tx_req.tvalid ), + .dst_ready_i ( eth_axis_tx_rsp.tready ) + ); + + // RX CDC FIFO + cdc_fifo_gray #( + .T ( axis_t_chan_t ), + .LOG_DEPTH ( RxFifoLogDepth ) + ) i_cdc_fifo_rx ( + .src_rst_ni ( rst_ni ), + .src_clk_i ( eth_clk ), + .src_data_i ( eth_axis_rx_rsp.t ), + .src_valid_i ( eth_axis_rx_rsp.tvalid ), + .src_ready_o ( eth_axis_rx_req.tready ), + .dst_rst_ni ( rst_ni ), + .dst_clk_i ( clk_i ), + .dst_data_o ( idma_axis_read_req.t ), + .dst_valid_o ( idma_axis_read_req.tvalid ), + .dst_ready_i ( idma_axis_read_rsp.tready ) + ); + + axi_rw_join #( + .axi_req_t ( eth_idma_pkg::axi_req_t ), + .axi_resp_t ( eth_idma_pkg::axi_rsp_t ) + ) i_axi_tx_rw_join ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_read_req_i ( axi_read_req ), + .slv_read_resp_o ( axi_read_rsp ), + .slv_write_req_i ( axi_write_req ), + .slv_write_resp_o ( axi_write_rsp ), + .mst_req_o ( axi_req_o ), + .mst_resp_i ( axi_rsp_i ) + ); + +endmodule : eth_idma_wrap diff --git a/rtl/eth_mac_1g_rgmii.sv b/rtl/eth_mac_1g_rgmii.sv index f61e07f..87ae33e 100644 --- a/rtl/eth_mac_1g_rgmii.sv +++ b/rtl/eth_mac_1g_rgmii.sv @@ -105,6 +105,7 @@ wire [7:0] mac_gmii_txd; wire mac_gmii_tx_er; reg [1:0] speed_reg; +reg rxclk_enable; wire mii_select; reg tx_mii_select_1; @@ -133,7 +134,9 @@ reg [2:0] rx_prescale = 3'd0; always_ff @(posedge rx_clk or posedge gtx_rst) begin if (gtx_rst) begin rx_prescale <= 3'd0; + rxclk_enable <= 1'b0; end else begin + rxclk_enable <= 1'b1; rx_prescale <= rx_prescale + 3'd1; end end @@ -142,12 +145,19 @@ reg rx_prescale_sync_1; reg rx_prescale_sync_2; reg rx_prescale_sync_3; -always @(posedge gtx_clk) begin - rx_prescale_sync_1 <= rx_prescale[2]; - rx_prescale_sync_2 <= rx_prescale_sync_1; - rx_prescale_sync_3 <= rx_prescale_sync_2; +always_ff @(posedge gtx_clk or posedge gtx_rst) begin + if (gtx_rst) begin + rx_prescale_sync_1 <= 1'b0; + rx_prescale_sync_2 <= 1'b0; + rx_prescale_sync_3 <= 1'b0; + end else begin + rx_prescale_sync_1 <= rx_prescale[2]; + rx_prescale_sync_2 <= rx_prescale_sync_1; + rx_prescale_sync_3 <= rx_prescale_sync_2; + end end + reg [6:0] rx_speed_count_1; reg [1:0] rx_speed_count_2; @@ -157,8 +167,10 @@ always_ff @(posedge gtx_clk or posedge gtx_rst) begin rx_speed_count_2 <= 0; speed_reg <= 2'b10; end else begin + + if (rxclk_enable) begin rx_speed_count_1 <= rx_speed_count_1 + 1; - + if (rx_prescale_sync_2 ^ rx_prescale_sync_3) begin rx_speed_count_2 <= rx_speed_count_2 + 1; end @@ -184,6 +196,7 @@ always_ff @(posedge gtx_clk or posedge gtx_rst) begin end end end +end assign speed = speed_reg; assign mii_select = speed != 2'b10; @@ -256,4 +269,4 @@ eth_mac_1g_inst ( .ifg_delay(ifg_delay) ); -endmodule +endmodule \ No newline at end of file diff --git a/rtl/eth_rgmii_pkg.sv b/rtl/eth_rgmii_pkg.sv deleted file mode 100644 index 7411836..0000000 --- a/rtl/eth_rgmii_pkg.sv +++ /dev/null @@ -1,16 +0,0 @@ -package eth_rgmii_pkg; - - parameter int unsigned AXI_ADDR_WIDTH = 32; - parameter int unsigned AXI_DATA_WIDTH = 64; - parameter int unsigned AXI_ID_WIDTH = 8; - parameter int unsigned AXI_USER_WIDTH = 8; - - localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; - - typedef logic [AXI_ID_WIDTH-1:0] id_t; - typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; - typedef logic [AXI_DATA_WIDTH-1:0] data_t; - typedef logic [AXI_STRB_WIDTH-1:0] strb_t; - typedef logic [AXI_USER_WIDTH-1:0] user_t; - -endpackage : eth_rgmii_pkg diff --git a/rtl/eth_top.sv b/rtl/eth_top.sv index 80b1990..d908768 100644 --- a/rtl/eth_top.sv +++ b/rtl/eth_top.sv @@ -12,9 +12,9 @@ module eth_top #( /// AXI Stream in request struct - parameter type axi_stream_req_t = eth_top_pkg::s_req_t, + parameter type axi_stream_req_t = eth_idma_pkg::axi_stream_req_t, /// AXI Stream in response struct - parameter type axi_stream_rsp_t = eth_top_pkg::s_rsp_t, + parameter type axi_stream_rsp_t = eth_idma_pkg::axi_stream_rsp_t, /// AXI Stream Data Width parameter int unsigned DataWidth = 64, /// AXI Stream Id Width @@ -24,38 +24,42 @@ module eth_top #( /// AXI Stream User Width parameter int unsigned UserWidth = 1, /// REGBUS - parameter type reg_req_t = eth_top_pkg::reg_bus_req_t, - parameter type reg_rsp_t = eth_top_pkg::reg_bus_rsp_t, + //parameter type reg2hw_itf_t = eth_idma_reg_pkg::eth_idma_reg2hw_t, + //parameter type hw2reg_itf_t = eth_idma_reg_pkg::eth_idma_hw2reg_t, + parameter type reg2hw_itf_t = logic, + parameter type hw2reg_itf_t = logic, parameter int AW_REGBUS = 4 ) ( // Internal 125 MHz clock - input wire clk_i , - input wire rst_ni , - input wire clk90_int , - input wire clk_200_int , + input wire clk_i, + input wire rst_ni, + input wire clk90_int, // Ethernet: 1000BASE-T RGMII - input wire phy_rx_clk , - input wire [3:0] phy_rxd , - input wire phy_rx_ctl , - output wire phy_tx_clk , - output wire [3:0] phy_txd , - output wire phy_tx_ctl , - output wire phy_reset_n , - input wire phy_int_n , - input wire phy_pme_n , + input wire phy_rx_clk, + input wire [3:0] phy_rxd, + input wire phy_rx_ctl, + output wire phy_tx_clk, + output wire [3:0] phy_txd, + output wire phy_tx_ctl, + output wire phy_reset_n, + input wire phy_int_n, + input wire phy_pme_n, // MDIO - input wire phy_mdio_i , - output reg phy_mdio_o , - output reg phy_mdio_oe , - output wire phy_mdc , + input wire phy_mdio_i, + output reg phy_mdio_o, + output reg phy_mdio_oe, + output wire phy_mdc, // AXIS TX/RX - input axi_stream_req_t tx_axis_req_i, - output axi_stream_rsp_t tx_axis_rsp_o, - output axi_stream_req_t rx_axis_req_o, - input axi_stream_rsp_t rx_axis_rsp_i, - // configuration (register interface) - input reg_req_t reg_req_i , - output reg_rsp_t reg_rsp_o + input axi_stream_req_t tx_axis_req_i, + output axi_stream_rsp_t tx_axis_rsp_o, + output axi_stream_req_t rx_axis_req_o, + input axi_stream_rsp_t rx_axis_rsp_i, + + input logic idma_req_ready, + input logic idma_rsp_valid, + // Reg configs + input reg2hw_itf_t reg2hw_i, + output hw2reg_itf_t hw2reg_o ); // ---------------- axis streams for the framing module ---------------------- @@ -81,33 +85,32 @@ module eth_top #( // ---------------- END: axis streams for the framing module ---------------------- framing_top #( - .axi_stream_req_t(s_framing_req_t), - .axi_stream_rsp_t(s_framing_rsp_t), - .reg_req_t (reg_req_t), - .reg_rsp_t (reg_rsp_t), - .AW_REGBUS (AW_REGBUS) + .axi_stream_req_t ( s_framing_req_t ), + .axi_stream_rsp_t ( s_framing_rsp_t ), + .reg2hw_itf_t ( reg2hw_itf_t ), + .hw2reg_itf_t ( hw2reg_itf_t ), + .AW_REGBUS ( AW_REGBUS ) ) i_framing_top ( - .rst_ni(rst_ni), - .clk_i(clk_i), - .clk90_int(clk90_int), - .clk_200_int(clk_200_int), + .rst_ni ( rst_ni ), + .clk_i ( clk_i ), + .clk90_int ( clk90_int ), // Ethernet: 1000BASE-T RGMII - .phy_rx_clk(phy_rx_clk), - .phy_rxd(phy_rxd), - .phy_rx_ctl(phy_rx_ctl), - .phy_tx_clk(phy_tx_clk), - .phy_txd(phy_txd), - .phy_tx_ctl(phy_tx_ctl), - .phy_reset_n(phy_reset_n), - .phy_int_n(phy_int_n), - .phy_pme_n(phy_pme_n), + .phy_rx_clk ( phy_rx_clk ), + .phy_rxd ( phy_rxd ), + .phy_rx_ctl ( phy_rx_ctl ), + .phy_tx_clk ( phy_tx_clk ), + .phy_txd ( phy_txd ), + .phy_tx_ctl ( phy_tx_ctl ), + .phy_reset_n ( phy_reset_n ), + .phy_int_n ( phy_int_n ), + .phy_pme_n ( phy_pme_n ), // MDIO - .phy_mdio_i(phy_mdio_i), - .phy_mdio_o(phy_mdio_o), - .phy_mdio_oe(phy_mdio_oe), - .phy_mdc(phy_mdc), + .phy_mdio_i ( phy_mdio_i ), + .phy_mdio_o ( phy_mdio_o ), + .phy_mdio_oe ( phy_mdio_oe ), + .phy_mdc ( phy_mdc ), // AXIS TX/RX .tx_axis_req_i(s_framing_tx_req), @@ -115,47 +118,50 @@ module eth_top #( .rx_axis_req_o(s_framing_rx_req), .rx_axis_rsp_i(s_framing_rx_rsp), - // REGBUS Configuration Interface - .reg_req_i(reg_req_i), - .reg_rsp_o(reg_rsp_o) + .idma_req_ready (idma_req_ready), + .idma_rsp_valid (idma_rsp_valid), + + // Reg Interface + .reg2hw_i ( reg2hw_i ), + .hw2reg_o ( hw2reg_o ) ); axi_stream_dw_downsizer #( - .DataWidthIn (DataWidth), - .DataWidthOut (FramingDataWidth), - .IdWidth (IdWidth), - .DestWidth (DestWidth), - .UserWidth (UserWidth), - .axi_stream_in_req_t(axi_stream_req_t), - .axi_stream_in_rsp_t(axi_stream_rsp_t), - .axi_stream_out_req_t(s_framing_req_t), - .axi_stream_out_rsp_t(s_framing_rsp_t) + .DataWidthIn ( DataWidth ), + .DataWidthOut ( FramingDataWidth ), + .IdWidth ( IdWidth ), + .DestWidth ( DestWidth ), + .UserWidth ( UserWidth ), + .axi_stream_in_req_t ( axi_stream_req_t ), + .axi_stream_in_rsp_t ( axi_stream_rsp_t ), + .axi_stream_out_req_t ( s_framing_req_t ), + .axi_stream_out_rsp_t ( s_framing_rsp_t ) ) i_axi_stream_dw_downsizer ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .in_req_i (tx_axis_req_i), - .in_rsp_o (tx_axis_rsp_o), - .out_req_o(s_framing_tx_req), - .out_rsp_i(s_framing_tx_rsp) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .in_req_i ( tx_axis_req_i ), + .in_rsp_o ( tx_axis_rsp_o ), + .out_req_o ( s_framing_tx_req ), + .out_rsp_i ( s_framing_tx_rsp ) ); axi_stream_dw_upsizer #( - .DataWidthIn (FramingDataWidth), - .DataWidthOut (DataWidth), - .IdWidth (IdWidth), - .DestWidth (DestWidth), - .UserWidth (UserWidth), - .axi_stream_in_req_t(s_framing_req_t), - .axi_stream_in_rsp_t(s_framing_rsp_t), - .axi_stream_out_req_t(axi_stream_req_t), - .axi_stream_out_rsp_t(axi_stream_rsp_t) + .DataWidthIn ( FramingDataWidth ), + .DataWidthOut ( DataWidth ), + .IdWidth ( IdWidth ), + .DestWidth ( DestWidth ), + .UserWidth ( UserWidth ), + .axi_stream_in_req_t ( s_framing_req_t ), + .axi_stream_in_rsp_t ( s_framing_rsp_t ), + .axi_stream_out_req_t ( axi_stream_req_t ), + .axi_stream_out_rsp_t ( axi_stream_rsp_t ) ) i_axi_stream_dw_upsizer ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .in_req_i (s_framing_rx_req), - .in_rsp_o (s_framing_rx_rsp), - .out_req_o(rx_axis_req_o), - .out_rsp_i(rx_axis_rsp_i) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .in_req_i ( s_framing_rx_req ), + .in_rsp_o ( s_framing_rx_rsp ), + .out_req_o ( rx_axis_req_o ), + .out_rsp_i ( rx_axis_rsp_i ) ); endmodule : eth_top diff --git a/rtl/eth_top_pkg.sv b/rtl/eth_top_pkg.sv deleted file mode 100644 index eb4367b..0000000 --- a/rtl/eth_top_pkg.sv +++ /dev/null @@ -1,41 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Authors: -// - Thiemo Zaugg - -`include "axi_stream/assign.svh" -`include "axi_stream/typedef.svh" -`include "register_interface/typedef.svh" -`include "register_interface/assign.svh" - -package eth_top_pkg; - - parameter int unsigned DataWidth = 64; - parameter int unsigned IdWidth = 0; - parameter int unsigned DestWidth = 0; - parameter int unsigned UserWidth = 1; - - // AXI stream channels typedefs - typedef logic [DataWidth-1:0] axis_tdata_t; - typedef logic [DataWidth/8-1:0] axis_tstrb_t; - typedef logic [DataWidth/8-1:0] axis_tkeep_t; - typedef logic [IdWidth-1:0] axis_tid_t; - typedef logic [DestWidth-1:0] axis_tdest_t; - typedef logic [UserWidth-1:0] axis_tuser_t; - - `AXI_STREAM_TYPEDEF_ALL(s, axis_tdata_t, axis_tstrb_t, axis_tkeep_t, axis_tid_t, axis_tdest_t, axis_tuser_t) - - - parameter int AW_REGBUS = 4; - localparam int DW_REGBUS = 32; - localparam int unsigned STRB_WIDTH = DW_REGBUS/8; - - // Define structs for reg_bus - typedef logic [AW_REGBUS-1:0] reg_bus_addr_t; - typedef logic [DW_REGBUS-1:0] reg_bus_data_t; - typedef logic [STRB_WIDTH-1:0] reg_bus_strb_t; - `REG_BUS_TYPEDEF_ALL(reg_bus, reg_bus_addr_t, reg_bus_data_t, reg_bus_strb_t) - -endpackage : eth_top_pkg diff --git a/rtl/fll_dummy.sv b/rtl/fll_dummy.sv new file mode 100644 index 0000000..04fd06f --- /dev/null +++ b/rtl/fll_dummy.sv @@ -0,0 +1,89 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +`ifndef TEST_CLOCK_BYPASS + `timescale 1ns/1ns + `endif + +module fll_dummy #( + parameter int unsigned NB_FLL = 4, + parameter int unsigned CFG_ADDR_WIDTH = 4, + parameter int unsigned CFG_DATA_WIDTH = 32, + parameter int unsigned NB_SCAN_CHAIN = 1 +) ( + // Clock & reset + output logic [NB_FLL-1:0] OUTCLK, // FLL clock outputs + input logic REFCLK, // Reference clock input + input logic RSTB, // Asynchronous reset (active low) + + // Configuration I/F + input logic CFGREQ, // CFG I/F access request (active high) + output logic CFGACK, // CFG I/F access granted (active high) + input logic [CFG_ADDR_WIDTH-1:0] CFGAD, // CFG I/F address bus + input logic [CFG_DATA_WIDTH-1:0] CFGD, // CFG I/F input data bus (write) + output logic [CFG_DATA_WIDTH-1:0] CFGQ, // CFG I/F output data bus (read) + input logic CFGWEB, // CFG I/F write enable (active low) + + // Power management + input logic PWD, // Asynchronous power down (active high) + input logic RET, // Asynchronous retention/isolation control (active high) + + // Test I/F + input logic TM, // Test mode (active high) + input logic TE, // Scan enable (active high) + input logic [NB_SCAN_CHAIN-1:0] TD, // Scan data input for chain 1:4 + output logic [NB_SCAN_CHAIN-1:0] TQ, // Scan data output for chain 1:4 + input logic JTD, // Scan data in 5 + output logic JTQ // Scan data out 5 +); + + `ifdef TARGET_ASIC + `ifdef TARGET_TOP_POST_SYNTH_SIM + `define GENERATE_CLOCK + `endif + `else + `define GENERATE_CLOCK + `endif + + `ifdef GENERATE_CLOCK + logic clk; + parameter time ClkPeriod = 8ns; + + + assign CFGACK = 1'b1; + assign CFGQ = 32'hdeadbeef; + + assign TQ = 1'b0; + assign JTQ = 1'b0; + + `ifndef TEST_CLOCK_BYPASS + initial begin + clk = 1'b0; + end + always begin + // Emit rising clock edge. + clk = 1'b1; + // Wait for at most half the clock period before emitting falling clock edge. Due to integer + // division, this is not always exactly half the clock period but as close as we can get. + #(ClkPeriod/2); + // Emit falling clock edge. + clk = 1'b0; + // Wait for remainder of clock period before continuing with next cycle. + #(ClkPeriod/2); + end // always + + for (genvar i=0;i -// - Thiemo Zaugg +// See LICENSE for license details. -`ifdef GENESYSII - `default_nettype none -`endif module framing_top #( /// AXI Stream in request struct - parameter type axi_stream_req_t = logic, + parameter type axi_stream_req_t = logic, /// AXI Stream in response struct - parameter type axi_stream_rsp_t = logic, - /// REGBUS - parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic, - parameter int AW_REGBUS = 4 + parameter type axi_stream_rsp_t = logic, + /// reg intf + parameter type reg2hw_itf_t = logic, + parameter type hw2reg_itf_t = logic, + /// regbus address width + parameter int AW_REGBUS = 4 ) ( // Internal 125 MHz clock input wire clk_i , input wire rst_ni , input wire clk90_int , - input wire clk_200_int , // Ethernet: 1000BASE-T RGMII input wire phy_rx_clk , input wire [3:0] phy_rxd , @@ -37,22 +28,23 @@ module framing_top #( input wire phy_pme_n , // MDIO input wire phy_mdio_i , - output reg phy_mdio_o , - output reg phy_mdio_oe , + output reg phy_mdio_o , + output reg phy_mdio_oe , output wire phy_mdc , // AXIS TX/RX - input axi_stream_req_t tx_axis_req_i, - output axi_stream_rsp_t tx_axis_rsp_o, - output axi_stream_req_t rx_axis_req_o, - input axi_stream_rsp_t rx_axis_rsp_i, - // configuration (register interface) - input reg_req_t reg_req_i , - output reg_rsp_t reg_rsp_o + input axi_stream_req_t tx_axis_req_i, + output axi_stream_rsp_t tx_axis_rsp_o, + output axi_stream_req_t rx_axis_req_o, + input axi_stream_rsp_t rx_axis_rsp_i, + // ugly fix (to-do) + input logic idma_req_ready, + input logic idma_rsp_valid, + // REGBUS configs + input reg2hw_itf_t reg2hw_i, + output hw2reg_itf_t hw2reg_o ); - import eth_framing_reg_pkg::* ; - eth_framing_reg_pkg::eth_framing_reg2hw_t reg2hw; // Read from HW - eth_framing_reg_pkg::eth_framing_hw2reg_t hw2reg; // Write from HW + import eth_idma_reg_pkg::* ; logic mac_gmii_tx_en; logic accept_frame_q, accept_frame_d; @@ -69,14 +61,19 @@ module framing_top #( logic rx_axis_tuser_5_q, rx_axis_tuser_4_q, rx_axis_tuser_3_q, rx_axis_tuser_2_q, rx_axis_tuser_1_q, rx_axis_tuser_0_q; logic rx_axis_tuser_5_d, rx_axis_tuser_4_d, rx_axis_tuser_3_d, rx_axis_tuser_2_d, rx_axis_tuser_1_d, rx_axis_tuser_0_d; - assign mac_address = {reg2hw.config1.upper_mac_address.q, reg2hw.config0.q}; // combine upper and lower mac address from registers - assign promiscuous = reg2hw.config1.promiscuous.q; - assign phy_mdc = reg2hw.config1.phy_mdclk.q; - assign phy_mdio_o = reg2hw.config1.phy_mdio_o.q; - assign phy_mdio_oe = reg2hw.config1.phy_mdio_oe.q; + assign mac_address = {reg2hw_i.machi_mdio.upper_mac_address.q, reg2hw_i.maclo_addr.q}; // combine upper and lower mac address from registers + assign promiscuous = reg2hw_i.machi_mdio.promiscuous.q; + assign phy_mdc = reg2hw_i.machi_mdio.phy_mdclk.q; + assign phy_mdio_o = reg2hw_i.machi_mdio.phy_mdio_o.q; + assign phy_mdio_oe = reg2hw_i.machi_mdio.phy_mdio_oe.q; + + assign hw2reg_o.tx_fcs.de = 1'b1; + assign hw2reg_o.rx_fcs.de = 1'b1; + assign hw2reg_o.req_ready.de = 1'b1; + assign hw2reg_o.rsp_valid.de = 1'b1; - assign hw2reg.config2.de = 1'b1; - assign hw2reg.config3.de = 1'b1; + assign hw2reg_o.req_ready.d = idma_req_ready; + assign hw2reg_o.rsp_valid.d = idma_rsp_valid; always_comb begin rx_axis_tdata_4_d = rx_axis_tdata_5_q; @@ -175,26 +172,10 @@ module framing_top #( end end - - eth_framing_reg_top #( - .reg_req_t(reg_req_t), - .reg_rsp_t(reg_rsp_t), - .AW(AW_REGBUS) - ) i_regs ( - .clk_i(clk_i), - .rst_ni(rst_ni), - .reg_req_i(reg_req_i), - .reg_rsp_o(reg_rsp_o), - .reg2hw(reg2hw), // Write - .hw2reg(hw2reg), // Read - .devmode_i(1'b1) - ); - rgmii_soc rgmii_soc1 ( .rst_int (~rst_ni ), .clk_int (clk_i ), .clk90_int (clk90_int ), - .clk_200_int (clk_200_int ), // Ethernet: 1000BASE-T RGMII .phy_rx_clk (phy_rx_clk ), @@ -224,8 +205,8 @@ module framing_top #( .rx_axis_tuser (rx_axis_tuser_5_d ), // Error registers - .rx_fcs_reg (hw2reg.config3.d ), - .tx_fcs_reg (hw2reg.config2.d ) + .rx_fcs_reg (hw2reg_o.rx_fcs.d ), + .tx_fcs_reg (hw2reg_o.tx_fcs.d ) ); endmodule // framing_top @@ -244,7 +225,6 @@ module framing_top_intf ( input wire clk_i , input wire rst_ni , input wire clk90_int , - input wire clk_200_int , /// Ethernet: 1000BASE-T RGMII input wire phy_rx_clk , input wire [3:0] phy_rxd , @@ -326,7 +306,6 @@ module framing_top_intf ( .rst_ni(rst_ni), .clk_i(clk_i), .clk90_int(clk90_int), - .clk_200_int(clk_200_int), // Ethernet: 1000BASE-T RGMII .phy_rx_clk(phy_rx_clk), diff --git a/target/.gitignore b/target/.gitignore new file mode 100644 index 0000000..26daa8c --- /dev/null +++ b/target/.gitignore @@ -0,0 +1,4 @@ +sim/vsim/compile.eth.tcl +sim/vsim/modelsim.ini +sim/vsim/transcript +sim/vsim/work diff --git a/target/sim/src/eth_tb.sv b/target/sim/src/eth_tb.sv index 9678592..a0eedc2 100644 --- a/target/sim/src/eth_tb.sv +++ b/target/sim/src/eth_tb.sv @@ -6,509 +6,371 @@ // - Davide Rossi // - Thiemo Zaugg // - Alessandro Ottaviano +// - Chaoqun Liang -`timescale 1 ns/1 ps +`timescale 1 ns/1 ns -`include "axi_stream/assign.svh" -`include "axi_stream/typedef.svh" +`include "axi/typedef.svh" +`include "idma/typedef.svh" `include "register_interface/typedef.svh" `include "register_interface/assign.svh" -module eth_tb (); - localparam tCK = 8ns; - localparam tCK200 = 5ns; - - localparam TEST_TIME = 6ns; - localparam APPLY_TIME = 2ns; - - localparam int unsigned REG_BUS_DW = 32; - localparam int unsigned REG_BUS_AW = 4; - - localparam int unsigned DW = 64; - localparam int unsigned DW_FRAMING = 8; - localparam int unsigned ID_WIDTH = 0; - localparam int unsigned DEST_WIDTH = 0; - localparam int unsigned USER_WIDTH = 1; - - logic clk_i = 0; // 125 MHz - logic clk_90_i = 0; // 125 MHz phase shifted - logic clk_200MHz_i = 0; // 200 MHz - logic rst_ni = 1; - logic done = 0; - - // signals to instantiate the DUT - wire eth_rxck ; - wire eth_rxctl ; - wire [3:0] eth_rxd ; - wire eth_txck ; - wire eth_txctl ; - wire [3:0] eth_txd ; - wire eth_tx_rst_n; - wire eth_rx_rst_n; - - logic [7:0] tx_axis_tdata ; - logic tx_axis_tvalid; - logic tx_axis_tready; - logic tx_axis_tlast ; - - // ----------------------- AXI-Stream master drivers -------------------------- - typedef axi_stream_test::axi_stream_rand_tx #( - .DataWidth (DW), - .IdWidth (ID_WIDTH), - .DestWidth (DEST_WIDTH), - .UserWidth (USER_WIDTH), - .TestTime (TEST_TIME), - .ApplTime (APPLY_TIME), - .MinWaitCycles(0), - .MaxWaitCycles(50) - ) master_drv_t; - - // TX_FRAMING master driver - AXI_STREAM_BUS_DV #( - .DataWidth(DW), - .IdWidth (ID_WIDTH), - .DestWidth(DEST_WIDTH), - .UserWidth(USER_WIDTH) - ) tx_framing_master_dv ( - .clk_i(clk_i) +module eth_tb + #( + parameter int unsigned DataWidth = 32'd64, + parameter int unsigned AddrWidth = 32'd64, + parameter int unsigned UserWidth = 32'd1, + parameter int unsigned AxiIdWidth = 32'd5, + parameter int unsigned NumAxInFlight = 32'd3, + parameter int unsigned BufferDepth = 32'd3, + parameter int unsigned TFLenWidth = 32'd32, + parameter int unsigned MemSysDepth = 32'd0, + parameter bit RAWCouplingAvail = 1'b0, + parameter bit MaskInvalidData = 1'b1, + parameter bit HardwareLegalizer = 1'b1, + parameter bit RejectZeroTransfers = 1'b1, + parameter bit ErrorHandling = 1'b0 +); + + import idma_pkg::*; + import eth_idma_pkg::*; + import reg_test::*; + + /// timing parameters + localparam time SYS_TCK = 8ns; + localparam time SYS_TA = 2ns; + localparam time SYS_TT = 6ns; + + /// regbus + localparam int unsigned REG_BUS_DW = 32; + localparam int unsigned REG_BUS_AW = 32; + + /// parse error handling caps + localparam error_cap_e ErrorCap = ErrorHandling ? ERROR_HANDLING : NO_ERROR_HANDLING; + + /// ethernet pads + logic s_clk; + logic s_rst_n; + logic done = 0; + logic error_found = 0; + + logic [REG_BUS_DW-1:0] tx_req_ready, tx_rsp_valid; + logic [REG_BUS_DW-1:0] rx_req_ready, rx_rsp_valid; + + logic eth_rxck; + logic eth_rxctl; + logic [3:0] eth_rxd; + logic eth_txck; + logic eth_txctl; + logic [3:0] eth_txd; + logic eth_tx_rstn, eth_rx_rstn; + + logic tx_idma_req_valid, tx_idma_req_ready, tx_idma_rsp_valid, tx_idma_rsp_ready; + logic rx_idma_req_valid, rx_idma_req_ready, rx_idma_rsp_valid, rx_idma_rsp_ready; + + /// AXI4+ATOP request and response + axi_req_t axi_tx_req_mem, axi_rx_req_mem; + axi_rsp_t axi_tx_rsp_mem, axi_rx_rsp_mem; + + /// error handler + idma_eh_req_t idma_eh_req; + logic eh_req_valid; + logic eh_req_ready; + + /// busy signal + idma_busy_t tx_busy, rx_busy; + + /// -------------------- REG Drivers ----------------------- + typedef reg_test::reg_driver #( + .AW(REG_BUS_AW), + .DW(REG_BUS_DW), + .TT(SYS_TT), + .TA(SYS_TA) + ) reg_bus_drv_t; + + REG_BUS #( + .DATA_WIDTH(REG_BUS_DW), + .ADDR_WIDTH(REG_BUS_AW) + ) reg_bus_tx ( + .clk_i(s_clk) + ); + + REG_BUS #( + .DATA_WIDTH(REG_BUS_DW), + .ADDR_WIDTH(REG_BUS_AW) + ) reg_bus_rx ( + .clk_i(s_clk) ); - AXI_STREAM_BUS #( - .DataWidth(DW), - .IdWidth (ID_WIDTH), - .DestWidth(DEST_WIDTH), - .UserWidth(USER_WIDTH) - ) tx_axis_tx_big(); + logic reg_error; - `AXI_STREAM_ASSIGN(tx_axis_tx_big, tx_framing_master_dv); + reg_bus_drv_t reg_drv_tx = new(reg_bus_tx); + reg_bus_drv_t reg_drv_rx = new(reg_bus_rx); - master_drv_t tx_framing_master_drv = new(tx_framing_master_dv, "tx_framing_master_dvr_tx_path"); + reg_bus_req_t reg_bus_tx_req, reg_bus_rx_req; + reg_bus_rsp_t reg_bus_tx_rsp, reg_bus_rx_rsp; - eth_top_pkg::s_req_t tx_axis_tx_req_i; - eth_top_pkg::s_rsp_t tx_axis_tx_rsp_o; - `AXI_STREAM_ASSIGN_TO_REQ(tx_axis_tx_req_i, tx_axis_tx_big) - `AXI_STREAM_ASSIGN_FROM_RSP(tx_axis_tx_big, tx_axis_tx_rsp_o) + `REG_BUS_ASSIGN_TO_REQ (reg_bus_tx_req, reg_bus_tx) + `REG_BUS_ASSIGN_FROM_RSP (reg_bus_tx, reg_bus_tx_rsp) + `REG_BUS_ASSIGN_TO_REQ (reg_bus_rx_req, reg_bus_rx) + `REG_BUS_ASSIGN_FROM_RSP (reg_bus_rx, reg_bus_rx_rsp) - // RX_FRAMING master driver - AXI_STREAM_BUS_DV #( - .DataWidth(DW), - .IdWidth (ID_WIDTH), - .DestWidth(DEST_WIDTH), - .UserWidth(USER_WIDTH) - ) rx_framing_master_dv ( - .clk_i(clk_i) + // clocking block + clk_rst_gen #( + .ClkPeriod ( SYS_TCK ), + .RstClkCycles ( 1 ) + ) i_clk_rst_gen ( + .clk_o ( s_clk ), + .rst_no ( s_rst_n ) ); - AXI_STREAM_BUS #( - .DataWidth(DW), - .IdWidth (ID_WIDTH), - .DestWidth(DEST_WIDTH), - .UserWidth(USER_WIDTH) - ) tx_axis_rx_big(); - - `AXI_STREAM_ASSIGN(tx_axis_rx_big, rx_framing_master_dv); - - master_drv_t rx_framing_master_drv = new(rx_framing_master_dv, "rx_framing_master_dvr_tx_path"); - - eth_top_pkg::s_req_t tx_axis_rx_req_i; - eth_top_pkg::s_rsp_t tx_axis_rx_rsp_o; - `AXI_STREAM_ASSIGN_TO_REQ(tx_axis_rx_req_i, tx_axis_rx_big) - `AXI_STREAM_ASSIGN_FROM_RSP(tx_axis_rx_big, tx_axis_rx_rsp_o) - - -// ----------------------- AXI-Stream slave drivers ------------------------- - typedef axi_stream_test::axi_stream_rand_rx #( - .DataWidth (DW), - .IdWidth (ID_WIDTH), - .DestWidth (DEST_WIDTH), - .UserWidth (USER_WIDTH), - .TestTime (TEST_TIME), - .ApplTime (APPLY_TIME), - .MinWaitCycles(0), - .MaxWaitCycles(50) - ) slave_drv_t; - - // TX_FRAMING slave driver - AXI_STREAM_BUS_DV #( - .DataWidth(DW), - .IdWidth (ID_WIDTH), - .DestWidth(DEST_WIDTH), - .UserWidth(USER_WIDTH) - ) tx_framing_slave_dv ( - .clk_i(clk_i) + // AXI4 TX sim memory + axi_sim_mem #( + .AddrWidth ( AddrWidth ), + .DataWidth ( DataWidth ), + .IdWidth ( AxiIdWidth ), + .UserWidth ( UserWidth ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ), + .WarnUninitialized ( 1'b0 ), + .ClearErrOnAccess ( 1'b1 ), + .ApplDelay ( SYS_TA ), + .AcqDelay ( SYS_TT ) + ) i_tx_axi_sim_mem ( + .clk_i ( s_clk ), + .rst_ni ( s_rst_n ), + .axi_req_i ( axi_tx_req_mem ), + .axi_rsp_o ( axi_tx_rsp_mem ), + .mon_r_last_o ( /* NOT CONNECTED */ ), + .mon_r_beat_count_o ( /* NOT CONNECTED */ ), + .mon_r_user_o ( /* NOT CONNECTED */ ), + .mon_r_id_o ( /* NOT CONNECTED */ ), + .mon_r_data_o ( /* NOT CONNECTED */ ), + .mon_r_addr_o ( /* NOT CONNECTED */ ), + .mon_r_valid_o ( /* NOT CONNECTED */ ), + .mon_w_last_o ( /* NOT CONNECTED */ ), + .mon_w_beat_count_o ( /* NOT CONNECTED */ ), + .mon_w_user_o ( /* NOT CONNECTED */ ), + .mon_w_id_o ( /* NOT CONNECTED */ ), + .mon_w_data_o ( /* NOT CONNECTED */ ), + .mon_w_addr_o ( /* NOT CONNECTED */ ), + .mon_w_valid_o ( /* NOT CONNECTED */ ) ); - AXI_STREAM_BUS #( - .DataWidth(DW), - .IdWidth (ID_WIDTH), - .DestWidth(DEST_WIDTH), - .UserWidth(USER_WIDTH) - ) rx_axis_tx_big(); - - `AXI_STREAM_ASSIGN(tx_framing_slave_dv, rx_axis_tx_big); - - slave_drv_t tx_framing_slave_drv = new(tx_framing_slave_dv, "tx_framing_slave_dvr_rx_path"); - - eth_top_pkg::s_req_t rx_axis_tx_req_o; - eth_top_pkg::s_rsp_t rx_axis_tx_rsp_i; - `AXI_STREAM_ASSIGN_FROM_REQ(rx_axis_tx_big, rx_axis_tx_req_o) - `AXI_STREAM_ASSIGN_TO_RSP(rx_axis_tx_rsp_i, rx_axis_tx_big) - - // RX_FRAMING slave driver - AXI_STREAM_BUS_DV #( - .DataWidth(DW), - .IdWidth (ID_WIDTH), - .DestWidth(DEST_WIDTH), - .UserWidth(USER_WIDTH) - ) rx_framing_slave_dv ( - .clk_i(clk_i) + // AXI4 RX sim memory + axi_sim_mem #( + .AddrWidth ( AddrWidth ), + .DataWidth ( DataWidth ), + .IdWidth ( AxiIdWidth ), + .UserWidth ( UserWidth ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ), + .WarnUninitialized ( 1'b0 ), + .ClearErrOnAccess ( 1'b1 ), + .ApplDelay ( SYS_TA ), + .AcqDelay ( SYS_TT ) + ) i_rx_axi_sim_mem ( + .clk_i ( s_clk ), + .rst_ni ( s_rst_n ), + .axi_req_i ( axi_rx_req_mem ), + .axi_rsp_o ( axi_rx_rsp_mem ), + .mon_r_last_o ( /* NOT CONNECTED */ ), + .mon_r_beat_count_o ( /* NOT CONNECTED */ ), + .mon_r_user_o ( /* NOT CONNECTED */ ), + .mon_r_id_o ( /* NOT CONNECTED */ ), + .mon_r_data_o ( /* NOT CONNECTED */ ), + .mon_r_addr_o ( /* NOT CONNECTED */ ), + .mon_r_valid_o ( /* NOT CONNECTED */ ), + .mon_w_last_o ( /* NOT CONNECTED */ ), + .mon_w_beat_count_o ( /* NOT CONNECTED */ ), + .mon_w_user_o ( /* NOT CONNECTED */ ), + .mon_w_id_o ( /* NOT CONNECTED */ ), + .mon_w_data_o ( /* NOT CONNECTED */ ), + .mon_w_addr_o ( /* NOT CONNECTED */ ), + .mon_w_valid_o ( /* NOT CONNECTED */ ) + ); + + eth_idma_wrap#( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .UserWidth ( UserWidth ), + .AxiIdWidth ( AxiIdWidth ), + .NumAxInFlight ( NumAxInFlight ), + .BufferDepth ( BufferDepth ), + .TFLenWidth ( TFLenWidth ), + .MemSysDepth ( MemSysDepth ), + .RAWCouplingAvail ( RAWCouplingAvail ), + .HardwareLegalizer ( HardwareLegalizer ), + .RejectZeroTransfers ( RejectZeroTransfers ) + ) i_tx_eth_idma_wrap ( + .clk_i ( s_clk ), + .rst_ni ( s_rst_n ), + /// Etherent Internal clocks + .phy_rx_clk_i ( eth_rxck ), + .phy_rxd_i ( eth_rxd ), + .phy_rx_ctl_i ( eth_rxctl ), + .phy_tx_clk_o ( eth_txck ), + .phy_txd_o ( eth_txd ), + .phy_tx_ctl_o ( eth_txctl ), + .phy_resetn_o ( eth_tx_rstn ), + .phy_intn_i ( 1'b1 ), + .phy_pme_i ( 1'b1 ), + .phy_mdio_i ( 1'b0 ), + .phy_mdio_o ( ), + .phy_mdio_oe ( ), + .phy_mdc_o ( ), + .reg_req_i ( reg_bus_tx_req ), + .reg_rsp_o ( reg_bus_tx_rsp ), + .testmode_i ( 1'b0 ), + .idma_eh_req_i ( idma_eh_req ), // error handling disabled now + .eh_req_valid_i ( eh_req_valid ), + .eh_req_ready_o ( eh_req_ready ), + .axi_req_o ( axi_tx_req_mem ), + .axi_rsp_i ( axi_tx_rsp_mem ), + .idma_busy_o ( tx_busy ) ); - AXI_STREAM_BUS #( - .DataWidth(DW), - .IdWidth (ID_WIDTH), - .DestWidth(DEST_WIDTH), - .UserWidth(USER_WIDTH) - ) rx_axis_rx_big(); + reg_bus_req_t rx_reg_idma_req, tx_reg_idma_req; + reg_bus_rsp_t rx_reg_idma_rsp, tx_reg_idma_rsp; + + eth_idma_wrap #( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .UserWidth ( UserWidth ), + .AxiIdWidth ( AxiIdWidth ), + .NumAxInFlight ( NumAxInFlight ), + .BufferDepth ( BufferDepth ), + .TFLenWidth ( TFLenWidth ), + .MemSysDepth ( MemSysDepth ), + .RAWCouplingAvail ( RAWCouplingAvail ), + .HardwareLegalizer ( HardwareLegalizer ), + .RejectZeroTransfers ( RejectZeroTransfers ) + )i_rx_eth_idma_wrap ( + .clk_i ( s_clk ), + .rst_ni ( s_rst_n ), + .phy_rx_clk_i ( eth_txck ), + .phy_rxd_i ( eth_txd ), + .phy_rx_ctl_i ( eth_txctl ), + .phy_tx_clk_o ( eth_rxck ), + .phy_txd_o ( eth_rxd ), + .phy_tx_ctl_o ( eth_rxctl ), + .phy_resetn_o ( eth_rx_rstn ), + .phy_intn_i ( 1'b1 ), + .phy_pme_i ( 1'b1 ), + .phy_mdio_i ( 1'b0 ), + .phy_mdio_o ( ), + .phy_mdio_oe ( ), + .phy_mdc_o ( ), + .reg_req_i ( reg_bus_rx_req ), + .reg_rsp_o ( reg_bus_rx_rsp ), + .testmode_i ( 1'b0 ), + .idma_eh_req_i ( ), // error handling disabled now + .eh_req_valid_i ( ), + .eh_req_ready_o ( ), + .axi_req_o ( axi_rx_req_mem ), + .axi_rsp_i ( axi_rx_rsp_mem ), + .idma_busy_o ( rx_busy ) + ); - `AXI_STREAM_ASSIGN(rx_framing_slave_dv, rx_axis_rx_big); + // ------------------------ BEGINNING OF SIMULATION ------------------------ - slave_drv_t rx_framing_slave_drv = new(rx_framing_slave_dv, "rx_framing_slave_dvr_rx_path"); + initial begin - eth_top_pkg::s_req_t rx_axis_rx_req_o; - eth_top_pkg::s_rsp_t rx_axis_rx_rsp_i; - `AXI_STREAM_ASSIGN_FROM_REQ(rx_axis_rx_big, rx_axis_rx_req_o) - `AXI_STREAM_ASSIGN_TO_RSP(rx_axis_rx_rsp_i, rx_axis_rx_big) + @(posedge s_rst_n); + @(posedge s_clk); + $readmemh("../stimuli/rx_mem_init.vmem", i_rx_axi_sim_mem.mem); + $readmemh("../stimuli/eth_frame.vmem", i_tx_axi_sim_mem.mem); -// -------------------- (configuration) REG Drivers ------------------------ - REG_BUS #( - .DATA_WIDTH(REG_BUS_DW), - .ADDR_WIDTH(REG_BUS_AW) - ) reg_bus_mst_tx (.clk_i(clk_i)); + /// TX eth configs + reg_drv_tx.send_write( 'h00, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address + @(posedge s_clk); - logic reg_tx_error; + reg_drv_tx.send_write( 'h04, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + @(posedge s_clk); - REG_BUS #( - .DATA_WIDTH(REG_BUS_DW), - .ADDR_WIDTH(REG_BUS_AW) - ) reg_bus_mst_rx (.clk_i(clk_i)); + reg_drv_tx.send_write( 'h10, 32'h0, 'hf, reg_error ); // SRC_ADDR + @(posedge s_clk); - logic reg_rx_error; + reg_drv_tx.send_write( 'h14, 32'h0, 'hf, reg_error); // DST_ADDR + @(posedge s_clk); - typedef reg_test::reg_driver #( - .AW(REG_BUS_AW), - .DW(REG_BUS_DW), - .TT(TEST_TIME), - .TA(APPLY_TIME) - ) reg_bus_master_t; - - reg_bus_master_t reg_master_tx = new(reg_bus_mst_tx); - reg_bus_master_t reg_master_rx = new(reg_bus_mst_rx); - - eth_top_pkg::reg_bus_req_t rx_reg_req_i, tx_reg_req_i; - eth_top_pkg::reg_bus_rsp_t rx_reg_rsp_o, tx_reg_rsp_o; - - `REG_BUS_ASSIGN_TO_REQ(rx_reg_req_i, reg_bus_mst_rx) - `REG_BUS_ASSIGN_TO_REQ(tx_reg_req_i, reg_bus_mst_tx) - `REG_BUS_ASSIGN_FROM_RSP(reg_bus_mst_rx, rx_reg_rsp_o) - `REG_BUS_ASSIGN_FROM_RSP(reg_bus_mst_tx, tx_reg_rsp_o) - -// -------------------------------- DUT --------------------------------- - // TX ETH_RGMII - eth_top_synth tx_eth_top_synth ( - .rst_ni (rst_ni ), - .clk_i (clk_i ), - .clk90_i (clk_90_i ), - .clk_200MHz_i(clk_200MHz_i ), - - - // Ethernet: 1000BASE-T RGMII - .phy_rx_clk (eth_rxck ), - .phy_rxd (eth_rxd ), - .phy_rx_ctl (eth_rxctl ), - - .phy_tx_clk (eth_txck ), - .phy_txd (eth_txd ), - .phy_tx_ctl (eth_txctl ), - - .phy_reset_n (eth_tx_rst_n ), - .phy_int_n (1'b1 ), - .phy_pme_n (1'b1 ), - - // MDIO - .phy_mdio_i (1'b0 ), - .phy_mdio_o ( ), - .phy_mdio_oe ( ), - .phy_mdc ( ), - // TX AXIS - .tx_axis_tdata_i (tx_axis_tx_req_i.t.data), - .tx_axis_tstrb_i (tx_axis_tx_req_i.t.strb), - .tx_axis_tkeep_i (tx_axis_tx_req_i.t.keep), - .tx_axis_tlast_i (tx_axis_tx_req_i.t.last), - .tx_axis_tid_i (tx_axis_tx_req_i.t.id), - .tx_axis_tdest_i (tx_axis_tx_req_i.t.dest), - .tx_axis_tuser_i (tx_axis_tx_req_i.t.user), // set tuser to 1'b0 to indicate no error - .tx_axis_tvalid_i(tx_axis_tx_req_i.tvalid), - .tx_axis_tready_o(tx_axis_tx_rsp_o.tready), - // RX AXIS - .rx_axis_tdata_o (rx_axis_tx_req_o.t.data), - .rx_axis_tstrb_o (rx_axis_tx_req_o.t.strb), - .rx_axis_tkeep_o (rx_axis_tx_req_o.t.keep), - .rx_axis_tlast_o (rx_axis_tx_req_o.t.last), - .rx_axis_tid_o (rx_axis_tx_req_o.t.id), - .rx_axis_tdest_o (rx_axis_tx_req_o.t.dest), - .rx_axis_tuser_o (rx_axis_tx_req_o.t.user), - .rx_axis_tvalid_o(rx_axis_tx_req_o.tvalid), - .rx_axis_tready_i(rx_axis_tx_rsp_i.tready), - - // Configuration Interface - .reg_bus_addr_i (tx_reg_req_i.addr), - .reg_bus_write_i (tx_reg_req_i.write), - .reg_bus_wdata_i (tx_reg_req_i.wdata), - .reg_bus_valid_i (tx_reg_req_i.valid), - .reg_bus_wstrb_i (tx_reg_req_i.wstrb), - .reg_bus_rdata_o (tx_reg_rsp_o.rdata), - .reg_bus_ready_o (tx_reg_rsp_o.ready), - .reg_bus_error_o (tx_reg_rsp_o.error) - ); + reg_drv_tx.send_write( 'h18, 32'h40, 'hf, reg_error); // Size in bytes + @(posedge s_clk); + reg_drv_tx.send_write( 'h1c, 32'h0, 'hf, reg_error); // src protocol AXI + @(posedge s_clk); + reg_drv_tx.send_write( 'h20, 32'h5, 'hf, reg_error); // dst protocol AXIS + @(posedge s_clk); - // RX ETH_RGMII - eth_top_synth rx_eth_top_synth ( - .rst_ni (rst_ni ), - .clk_i (clk_i ), - .clk90_i (clk_90_i ), - .clk_200MHz_i(clk_200MHz_i ), - - // Ethernet: 1000BASE-T RGMII - .phy_rx_clk (eth_txck ), - .phy_rxd (eth_txd ), - .phy_rx_ctl (eth_txctl ), - - .phy_tx_clk (eth_rxck ), - .phy_txd (eth_rxd ), - .phy_tx_ctl (eth_rxctl ), - - .phy_reset_n (eth_rx_rst_n ), - .phy_int_n (1'b1 ), - .phy_pme_n (1'b1 ), - - // MDIO - .phy_mdio_i (1'b0 ), - .phy_mdio_o ( ), - .phy_mdio_oe ( ), - .phy_mdc ( ), - - // TX AXIS - .tx_axis_tdata_i (tx_axis_rx_req_i.t.data), - .tx_axis_tstrb_i (tx_axis_rx_req_i.t.strb), - .tx_axis_tkeep_i (tx_axis_rx_req_i.t.keep), - .tx_axis_tlast_i (tx_axis_rx_req_i.t.last), - .tx_axis_tid_i (tx_axis_rx_req_i.t.id), - .tx_axis_tdest_i (tx_axis_rx_req_i.t.dest), - .tx_axis_tuser_i (tx_axis_rx_req_i.t.user), // set tuser to 1'b0 to indicate no error - .tx_axis_tvalid_i(tx_axis_rx_req_i.tvalid), - .tx_axis_tready_o(tx_axis_rx_rsp_o.tready), - // RX AXIS - .rx_axis_tdata_o (rx_axis_rx_req_o.t.data), - .rx_axis_tstrb_o (rx_axis_rx_req_o.t.strb), - .rx_axis_tkeep_o (rx_axis_rx_req_o.t.keep), - .rx_axis_tlast_o (rx_axis_rx_req_o.t.last), - .rx_axis_tid_o (rx_axis_rx_req_o.t.id), - .rx_axis_tdest_o (rx_axis_rx_req_o.t.dest), - .rx_axis_tuser_o (rx_axis_rx_req_o.t.user), - .rx_axis_tvalid_o(rx_axis_rx_req_o.tvalid), - .rx_axis_tready_i(rx_axis_rx_rsp_i.tready), - - // Configuration Interface - .reg_bus_addr_i (rx_reg_req_i.addr), - .reg_bus_write_i (rx_reg_req_i.write), - .reg_bus_wdata_i (rx_reg_req_i.wdata), - .reg_bus_valid_i (rx_reg_req_i.valid), - .reg_bus_wstrb_i (rx_reg_req_i.wstrb), - .reg_bus_rdata_o (rx_reg_rsp_o.rdata), - .reg_bus_ready_o (rx_reg_rsp_o.ready), - .reg_bus_error_o (rx_reg_rsp_o.error) - ); + /// RX eth configs + reg_drv_rx.send_write( 'h0, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address + @(posedge s_clk); -// ------------------------- DATA ---------------------------- - - // initialization data array (data to be sent by TX) - logic [DW-1:0] data_array[7:0]; - initial begin - data_array[0] = 64'h1032207098001032; //1 --> 230100890702 (Multicast Address) 2301, mac dest + begi of src mac address - data_array[1] = 64'h3210E20020709800; //2 --> 00890702 002E 0123, end of soource mac address + length/Ethertype(002E=IEEE802.3) + payload (2 byte) - data_array[2] = 64'h1716151413121110; //3 --> payload 8 byte - data_array[3] = 64'h2726252423222120; //4 --> payload 8 byte - data_array[4] = 64'h3736353433323130; //5 --> payload 8 byte - data_array[5] = 64'h4746454443424140; //6 --> payload 8 byte - data_array[6] = 64'h5756555453525150; //7 --> payload 8 byte - data_array[7] = 64'h6766656463626160; //8 --> payload 8 byte - end - - logic [DW-1:0] data_recv_array[8:0]; - logic last_recv; - - - // ---------------------- CLOCK GENERATION ------------------------ - initial begin - while (!done) begin //SYSTEM CLOCK - clk_i <= 1; - #(tCK/2); - clk_i <= 0; - #(tCK/2); - end - end - - initial begin - while (!done) begin - clk_90_i <= 0; - #(tCK/2); - clk_90_i <= 1; - #(tCK/2); - end - end - - initial begin - while (!done) begin - clk_200MHz_i <= 1; - #(tCK200/2); - clk_200MHz_i <= 0; - #(tCK200/2); - end - end - - // ------------------------ BEGINNING OF SIMULATION ------------------------ - initial begin - // General reset - - // Reset axi master and reg master - reg_master_tx.reset_master(); - reg_master_rx.reset_master(); - // Master drivers TX-paths - tx_framing_master_drv.reset(); - rx_framing_master_drv.reset(); - // Slave drivers RX-paths - tx_framing_slave_drv.reset(); - rx_framing_slave_drv.reset(); - - @(posedge clk_i); - rst_ni <= 0; - repeat(10000) @(posedge clk_i); - rst_ni <= 1; - @(posedge clk_i); - - // set receive array to 0; - reset_recv_array(); - repeat(5) @(posedge clk_i); - - //set framing rx mac address to 48'h207098001032 - reg_master_rx.send_write(4'h0, 32'h98001032, 4'b1111, reg_tx_error); //lower 32bits of MAC address - @(posedge clk_i); - reg_master_rx.send_write(4'h4, 32'h00002070, 4'b1111, reg_tx_error); //upper 16bits of MAC address + other configuration set to false/0 - - // TEST 1: Send Frame with the destination_MAC = RX_module_MAC - $display("Test 1"); - data_array[0] = 64'h1032_207098001032; - send_and_receive(); - check_data_received(); - @(posedge clk_i); - - // TEST 2: Send Broadcast Frame - $display("Test 2"); - reset_recv_array(); - data_array[0] = 64'h1032_FFFFFFFFFFFF; - send_and_receive(); - check_data_received(); - @(posedge clk_i); - - // TEST 3: Send Multicast Frame - $display("Test 3"); - reset_recv_array(); - data_array[0] = 64'h1032_01005EFFFFFF; - send_and_receive(); - check_data_received(); - @(posedge clk_i); - - // TEST 4: Send Frame not addressed to RX_module without promiscuous flag - $display("Test 4"); - reset_recv_array(); - data_array[0] = 64'h1032_00015EFF3FFF; - send_and_receive(); - check_no_data_received(); - @(posedge clk_i); - - // TEST 5: Send Frame not addressed to RX_module with promiscuous flag - $display("Test 5"); - reset_recv_array(); - data_array[0] = 64'h1032_00015EFF3FFF; - reg_master_rx.send_write(4'h4, 32'h00012070, 4'b1111, reg_tx_error); // set promiscuous flag - @(posedge clk_i); - send_and_receive(); - check_data_received(); - @(posedge clk_i); - - $display("[SUCCESS] All written and read data match"); - - $stop(); - end - - task reset_recv_array(); - for (int i = 0; i < 8; i++) begin - data_recv_array[i] = 'd0; - end - endtask : reset_recv_array - - task send_and_receive(); - fork - begin // send - tx_framing_master_drv.send(data_array[0], 1'b0); - tx_framing_master_drv.send(data_array[1], 1'b0); - tx_framing_master_drv.send(data_array[2], 1'b0); - tx_framing_master_drv.send(data_array[3], 1'b0); - tx_framing_master_drv.send(data_array[4], 1'b0); - tx_framing_master_drv.send(data_array[5], 1'b0); - tx_framing_master_drv.send(data_array[6], 1'b0); - tx_framing_master_drv.send(data_array[7], 1'b1); - repeat(34) @(posedge clk_i); - end - begin // receive - rx_framing_slave_drv.recv(data_recv_array[0], last_recv); - rx_framing_slave_drv.recv(data_recv_array[1], last_recv); - rx_framing_slave_drv.recv(data_recv_array[2], last_recv); - rx_framing_slave_drv.recv(data_recv_array[3], last_recv); - rx_framing_slave_drv.recv(data_recv_array[4], last_recv); - rx_framing_slave_drv.recv(data_recv_array[5], last_recv); - rx_framing_slave_drv.recv(data_recv_array[6], last_recv); - rx_framing_slave_drv.recv(data_recv_array[7], last_recv); - rx_framing_slave_drv.recv(data_recv_array[8], last_recv); // SFD + reg_drv_rx.send_write( 'h4, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + @(posedge s_clk); + + reg_drv_rx.send_write( 'h10, 32'h0, 'hf, reg_error ); // SRC_ADDR 64'h0000207098001032 + @(posedge s_clk); + + reg_drv_rx.send_write( 'h14, 32'h0, 'hf, reg_error); // DST_ADDR + @(posedge s_clk); + + reg_drv_rx.send_write( 'h18, 32'h40, 'hf, reg_error); // Size in bytes, 48 for transmission including appended FCS + @(posedge s_clk); + + reg_drv_rx.send_write( 'h1c, 32'h5, 'hf, reg_error); // src protocol + @(posedge s_clk); + + reg_drv_rx.send_write( 'h20, 32'h0, 'hf, reg_error); // dst protocol + @(posedge s_clk); + + /// Transaction configs + while(1) begin + reg_drv_tx.send_read( 'h3c, tx_req_ready, reg_error); // req ready + if( tx_req_ready ) begin + reg_drv_tx.send_write( 'h38, 32'h1, 'hf , reg_error); // req valid - req start + @(posedge s_clk); + break; end - join_any - endtask : send_and_receive - - task check_data_received(); - for(int j=0; j<8; j++) begin - if (data_array[j] != data_recv_array[j]) begin - $display("Data at j= %d was received %h but was sent as %h", j, data_recv_array[j], data_array[j]); - $display("[FAIL] At least one mismatch between written and read data"); - $stop(); - end else begin - $display("Data at j= %d was correctly recived: %h", j, data_recv_array[j]); + @(posedge s_clk); + end + + reg_drv_tx.send_write( 'h38, 32'h0, 'hf, reg_error); // req valid - lock in + reg_drv_tx.send_write( 'h40, 32'h1, 'hf, reg_error); // rsp_ready - data transfer launch + @(posedge s_clk); + + while(1) begin + reg_drv_rx.send_read( 'h3c, rx_req_ready, reg_error); // req ready + if( rx_req_ready ) begin + reg_drv_rx.send_write( 'h38, 32'h1, 'hf, reg_error); // req_valid + @(posedge s_clk); + break; end + @(posedge s_clk); end - endtask : check_data_received - - task check_no_data_received(); - for(int j=0; j<8; j++) begin - if (data_recv_array[j] != 'd0) begin - $display("Data at j= %d was recived %h but no data should have been received", j, data_recv_array[j]); - $display("[FAIL] At least one mismatch between written and read data"); - $stop(); + + reg_drv_rx.send_write( 'h38, 32'h0, 'hf, reg_error); // req valid + reg_drv_rx.send_write( 'h40, 32'h1, 'hf, reg_error); // rsp ready + @(posedge s_clk); + + repeat(160) @(posedge s_clk); // adjust based on num_bytes to write into rx sim mem + + for (int j = 0; j < 64; j++) begin + if (i_tx_axi_sim_mem.mem[j] != i_rx_axi_sim_mem.mem[j]) begin + $display("Test FAIL"); + error_found = 1; + break; end end - endtask : check_no_data_received + + if (!error_found) begin + $display("Test PASS"); + end + + $finish; + end endmodule diff --git a/target/sim/stimuli/eth_frame.vmem b/target/sim/stimuli/eth_frame.vmem new file mode 100644 index 0000000..f7b7f96 --- /dev/null +++ b/target/sim/stimuli/eth_frame.vmem @@ -0,0 +1,193 @@ +/* This code is autogenerated. */ +@00 32 +@01 10 +@02 00 +@03 98 +@04 70 +@05 20 +@06 32 +@07 10 +@08 00 +@09 98 +@0A 70 +@0B 20 +@0C 00 +@0D E2 +@0E 10 +@0F 32 +@10 BA +@11 89 +@12 FC +@13 93 +@14 7D +@15 07 +@16 ED +@17 35 +@18 8C +@19 6B +@1A A4 +@1B 79 +@1C 8D +@1D 7F +@1E BE +@1F 56 +@20 9E +@21 E1 +@22 6F +@23 44 +@24 D1 +@25 F2 +@26 B3 +@27 AE +@28 B8 +@29 6D +@2A 97 +@2B FF +@2C 3E +@2D C8 +@2E 21 +@2F 7D +@30 07 +@31 AC +@32 89 +@33 EB +@34 24 +@35 20 +@36 0D +@37 94 +@38 5C +@39 DA +@3A 61 +@3B 45 +@3C DC +@3D BC +@3E 9E +@3F 2B +@40 F9 +@41 88 +@42 3B +@43 A8 +@44 CE +@45 56 +@46 20 +@47 EA +@48 9B +@49 23 +@4A 32 +@4B 51 +@4C E7 +@4D 97 +@4E FD +@4F 3C +@50 B8 +@51 DE +@52 41 +@53 48 +@54 38 +@55 C3 +@56 11 +@57 C9 +@58 59 +@59 65 +@5A 11 +@5B CC +@5C 1D +@5D 1C +@5E C8 +@5F 0E +@60 4D +@61 13 +@62 D5 +@63 29 +@64 51 +@65 30 +@66 77 +@67 FA +@68 C9 +@69 12 +@6A D5 +@6B A5 +@6C 57 +@6D 1E +@6E 1A +@6F 15 +@70 9D +@71 CF +@72 63 +@73 87 +@74 A8 +@75 BF +@76 47 +@77 3A +@78 0D +@79 FA +@7A 11 +@7B 58 +@7C 99 +@7D 1B +@7E 67 +@7F BA +@80 A3 +@81 5A +@82 09 +@83 32 +@84 62 +@85 05 +@86 5D +@87 00 +@88 6C +@89 F4 +@8A 33 +@8B 76 +@8C 3A +@8D B8 +@8E A2 +@8F B0 +@90 01 +@91 50 +@92 60 +@93 04 +@94 60 +@95 D6 +@96 49 +@97 E7 +@98 E6 +@99 0A +@9A 64 +@9B A5 +@9C 96 +@9D A7 +@9E 4B +@9F 5A +@A0 91 +@A1 DA +@A2 F3 +@A3 0E +@A4 DC +@A5 91 +@A6 3A +@A7 ED +@A8 30 +@A9 9C +@AA CD +@AB DF +@AC 72 +@AD 01 +@AE 55 +@AF 40 +@B0 CA +@B1 F0 +@B2 BA +@B3 FC +@B4 A1 +@B5 CA +@B6 D8 +@B7 72 +@B8 D9 +@B9 C1 +@BA E9 +@BB A7 +@BC 70 +@BD 32 +@BE AE +@BF F1 diff --git a/target/sim/stimuli/rx_mem_init.vmem b/target/sim/stimuli/rx_mem_init.vmem new file mode 100644 index 0000000..5bd1d21 --- /dev/null +++ b/target/sim/stimuli/rx_mem_init.vmem @@ -0,0 +1,128 @@ +/* This code is autogenerated. */ +@00 00 +@01 00 +@02 00 +@04 00 +@05 00 +@06 00 +@07 00 +@08 00 +@09 00 +@0A 00 +@0B 00 +@0C 00 +@0D 00 +@0E 00 +@0F 00 +@10 00 +@11 00 +@12 00 +@13 00 +@14 00 +@15 00 +@16 00 +@17 00 +@18 00 +@19 00 +@1A 00 +@1B 00 +@1C 00 +@1D 00 +@1E 00 +@1F 00 +@20 00 +@21 00 +@22 00 +@23 00 +@24 00 +@25 00 +@26 00 +@27 00 +@28 00 +@29 00 +@2A 00 +@2B 00 +@2C 00 +@2D 00 +@2E 00 +@2F 00 +@30 00 +@31 00 +@32 00 +@33 00 +@34 00 +@35 00 +@36 00 +@37 00 +@38 00 +@39 00 +@3A 00 +@3B 00 +@3C 00 +@3D 00 +@3E 00 +@3F 00 +@40 00 +@41 00 +@42 00 +@43 00 +@44 00 +@45 00 +@46 00 +@47 00 +@48 00 +@49 00 +@4A 00 +@4B 00 +@4C 00 +@4D 00 +@4E 00 +@4F 00 +@50 00 +@51 00 +@52 00 +@53 00 +@54 00 +@55 00 +@56 00 +@57 00 +@58 00 +@59 00 +@5A 00 +@5B 00 +@5C 00 +@5D 00 +@5E 00 +@5F 00 +@60 00 +@61 00 +@62 00 +@63 00 +@64 00 +@65 00 +@66 00 +@67 00 +@68 00 +@69 00 +@6A 00 +@6B 00 +@6C 00 +@6D 00 +@6E 00 +@6F 00 +@70 00 +@71 00 +@72 00 +@73 00 +@74 00 +@75 00 +@76 00 +@77 00 +@78 00 +@79 00 +@7A 00 +@7B 00 +@7C 00 +@7D 00 +@7E 00 +@7F 00 \ No newline at end of file diff --git a/target/synth/eth_idma_wrap_synth.sv b/target/synth/eth_idma_wrap_synth.sv new file mode 100644 index 0000000..ad01bbd --- /dev/null +++ b/target/synth/eth_idma_wrap_synth.sv @@ -0,0 +1,155 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Authors: +// - Thiemo Zaugg +// - Alessandro Ottaviano + +`include "axi/assign.svh" +`include "axi/typedef.svh" +`include "axi/port.svh" +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" + +module eth_idma_wrap_synth #( + /// Data width + parameter int unsigned DataWidth = 32'd32, + /// Address width + parameter int unsigned AddrWidth = 32'd32, + /// AXI User width + parameter int unsigned UserWidth = 32'd1, + /// AXI ID width + parameter int unsigned AxiIdWidth = 32'd1, + /// Number of transaction that can be in-flight concurrently + parameter int unsigned NumAxInFlight = 32'd3, + /// The depth of the internal reorder buffer + parameter int unsigned BufferDepth = 32'd3, + /// With of a transfer: max transfer size is `2**TFLenWidth` bytes + parameter int unsigned TFLenWidth = 32'd32, + /// The depth of the memory system the backend is attached to + parameter int unsigned MemSysDepth = 32'd0, + /// Should the `R`-`AW` coupling hardware be present? (recommended) + parameter bit RAWCouplingAvail = 1'b0, + /// Mask invalid data on the manager interface + parameter bit MaskInvalidData = 1'b1, + parameter bit CombinedShifter = 1'b1, + /// hardware legalization present + parameter bit HardwareLegalizer = 1'b1, + /// Reject zero-length transfers + parameter bit RejectZeroTransfers = 1'b1, + /// Enable error handling + parameter bit ErrorHandling = 1'b0, + /// CDC FIFO + parameter int unsigned TxFifoLogDepth = 32'd8, + parameter int unsigned RxFifoLogDepth = 32'd8, + /// Derived types + parameter type id_t = logic [AxiIdWidth-1 :0], + parameter type addr_t = logic [AddrWidth-1 :0], + parameter type data_t = logic [DataWidth-1 :0], + parameter type strb_t = logic [DataWidth/8-1:0], + parameter type user_t = logic [UserWidth-1 :0], + parameter type reg_data_t = logic [31 :0], + parameter type reg_strb_t = logic [3 :0] +)( + input logic clk_i, + input logic rst_ni, + /// Ethernet: 1000BASE-T RGMII + input logic phy_rx_clk_i, + input logic [3:0] phy_rxd_i, + input logic phy_rx_ctl_i, + output logic phy_tx_clk_o, + output logic [3:0] phy_txd_o, + output logic phy_tx_ctl_o, + output logic phy_resetn_o, + input logic phy_intn_i, + input logic phy_pme_i, + /// Ethernet MDIO + input logic phy_mdio_i, + output logic phy_mdio_o, + output logic phy_mdio_oe, + output wire phy_mdc_o, + /// iDMA testmode + input logic testmode_i, + /// Error handler request + input idma_pkg::idma_eh_req_t idma_eh_req_i, + input logic eh_req_valid_i, + output logic eh_req_ready_o, + /// AXI ports + `AXI_M_PORT(eth, addr_t, data_t, strb_t, id_t, user_t, user_t, user_t, user_t, user_t) + /// iDMA busy flags + output idma_pkg::idma_busy_t idma_busy_o, + /// REGBUS Configuration Interface + input addr_t cfg_addr_i, + input reg_data_t cfg_wdata_i, + input reg_strb_t cfg_wstrb_i, + input logic cfg_write_i, + input logic cfg_valid_i, + output reg_data_t cfg_rdata_o, + output logic cfg_error_o, + output logic cfg_ready_o +); + + `AXI_TYPEDEF_ALL(axi, addr_t, id_t, data_t, strb_t, user_t) + + axi_req_t m_req; + axi_resp_t m_rsp; + + `AXI_ASSIGN_MASTER_TO_FLAT(eth, m_req, m_rsp) + + `REG_BUS_TYPEDEF_ALL(cfg, addr_t, reg_data_t, reg_strb_t) + + cfg_req_t cfg_req; + cfg_rsp_t cfg_rsp; + + assign cfg_req.addr = cfg_addr_i; + assign cfg_req.wdata = cfg_wdata_i; + assign cfg_req.wstrb = cfg_wstrb_i; + assign cfg_req.write = cfg_write_i; + assign cfg_req.valid = cfg_valid_i; + assign cfg_rdata_o = cfg_rsp.rdata; + assign cfg_error_o = cfg_rsp.error; + assign cfg_ready_o = cfg_rsp.ready; + + /// DUT + eth_idma_wrap#( + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .UserWidth ( UserWidth ), + .AxiIdWidth ( AxiIdWidth ), + .NumAxInFlight ( NumAxInFlight ), + .BufferDepth ( BufferDepth ), + .TFLenWidth ( TFLenWidth ), + .MemSysDepth ( MemSysDepth ), + .RAWCouplingAvail ( RAWCouplingAvail ), + .HardwareLegalizer ( HardwareLegalizer ), + .RejectZeroTransfers ( RejectZeroTransfers ) + ) i_eth_idma_wrap ( + .clk_i, + .rst_ni, + /// Etherent Internal clocks + .phy_rx_clk_i, + .phy_rxd_i, + .phy_rx_ctl_i, + .phy_tx_clk_o, + .phy_txd_o, + .phy_tx_ctl_o, + .phy_resetn_o, + .phy_intn_i, + .phy_pme_i, + .phy_mdio_i, + .phy_mdio_o, + .phy_mdio_oe, + .phy_mdc_o, + .reg_req_i ( cfg_req ), + .reg_rsp_o ( cfg_rsp ), + .testmode_i, + .idma_eh_req_i, + .eh_req_valid_i, + .eh_req_ready_o, + .axi_req_o ( m_req ), + .axi_rsp_i ( m_rsp ), + .idma_busy_o + ); + +endmodule : eth_idma_wrap_synth diff --git a/target/synth/eth_top_synth.sv b/target/synth/eth_top_synth.sv deleted file mode 100644 index 7fde4ef..0000000 --- a/target/synth/eth_top_synth.sv +++ /dev/null @@ -1,140 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Authors: -// - Thiemo Zaugg - -`include "axi_stream/assign.svh" -`include "axi_stream/typedef.svh" -`include "register_interface/typedef.svh" -`include "register_interface/assign.svh" - -module eth_top_synth ( - input wire rst_ni , - input wire clk_i , - input wire clk90_i , - input wire clk_200MHz_i , - // Ethernet: 1000BASE-T RGMII - input wire phy_rx_clk , - input wire [3:0] phy_rxd , - input wire phy_rx_ctl , - output wire phy_tx_clk , - output wire [3:0] phy_txd , - output wire phy_tx_ctl , - output wire phy_reset_n , - input wire phy_int_n , - input wire phy_pme_n , - // MDIO - input wire phy_mdio_i , - output reg phy_mdio_o , - output reg phy_mdio_oe , - output wire phy_mdc , - - // AXIS TX - input eth_top_pkg::axis_tdata_t tx_axis_tdata_i, - input eth_top_pkg::axis_tstrb_t tx_axis_tstrb_i, - input eth_top_pkg::axis_tkeep_t tx_axis_tkeep_i, - input logic tx_axis_tlast_i, - input eth_top_pkg::axis_tid_t tx_axis_tid_i, - input eth_top_pkg::axis_tdest_t tx_axis_tdest_i, - input eth_top_pkg::axis_tuser_t tx_axis_tuser_i, - input logic tx_axis_tvalid_i, - output logic tx_axis_tready_o, - // AXIS RX - output eth_top_pkg::axis_tdata_t rx_axis_tdata_o, - output eth_top_pkg::axis_tstrb_t rx_axis_tstrb_o, - output eth_top_pkg::axis_tkeep_t rx_axis_tkeep_o, - output logic rx_axis_tlast_o, - output eth_top_pkg::axis_tid_t rx_axis_tid_o, - output eth_top_pkg::axis_tdest_t rx_axis_tdest_o, - output eth_top_pkg::axis_tuser_t rx_axis_tuser_o, - output logic rx_axis_tvalid_o, - input logic rx_axis_tready_i, - - // configuration (register interface) - input eth_top_pkg::reg_bus_addr_t reg_bus_addr_i, - input logic reg_bus_write_i, - input eth_top_pkg::reg_bus_data_t reg_bus_wdata_i, - input eth_top_pkg::reg_bus_strb_t reg_bus_wstrb_i, - input logic reg_bus_valid_i, - output eth_top_pkg::reg_bus_data_t reg_bus_rdata_o, - output logic reg_bus_error_o, - output logic reg_bus_ready_o -); - -eth_top_pkg::s_req_t tx_axis_req_i, rx_axis_req_o; -eth_top_pkg::s_rsp_t tx_axis_rsp_o, rx_axis_rsp_i; - -eth_top_pkg::reg_bus_req_t reg_req_i; -eth_top_pkg::reg_bus_rsp_t reg_rsp_o; - - - eth_top i_eth_top ( - .rst_ni (rst_ni ), - .clk_i (clk_i ), - .clk90_int (clk_90_i ), - .clk_200_int (clk_200MHz_i ), - - // Ethernet: 1000BASE-T RGMII - .phy_rx_clk (phy_rx_clk ), - .phy_rxd (phy_rxd ), - .phy_rx_ctl (phy_rx_ctl ), - - .phy_tx_clk (phy_tx_clk ), - .phy_txd (phy_txd ), - .phy_tx_ctl (phy_tx_ctl ), - - .phy_reset_n (phy_reset_n ), - .phy_int_n (phy_int_n ), - .phy_pme_n (phy_pme_n ), - - // MDIO - .phy_mdio_i (phy_mdio_i ), - .phy_mdio_o (phy_mdio_o ), - .phy_mdio_oe (phy_mdio_oe ), - .phy_mdc (phy_mdc ), - - .tx_axis_req_i(tx_axis_req_i), // set tuser to 1'b0 to indicate no error - .tx_axis_rsp_o(tx_axis_rsp_o), - .rx_axis_req_o(rx_axis_req_o), - .rx_axis_rsp_i(rx_axis_rsp_i), - - // Configuration Interface - .reg_req_i (reg_req_i), - .reg_rsp_o (reg_rsp_o) - ); - - // AXIS TX - assign tx_axis_req_i.t.data = tx_axis_tdata_i; - assign tx_axis_req_i.t.strb = tx_axis_tstrb_i; - assign tx_axis_req_i.t.keep = tx_axis_tkeep_i; - assign tx_axis_req_i.t.last = tx_axis_tlast_i; - assign tx_axis_req_i.t.id = tx_axis_tid_i; - assign tx_axis_req_i.t.dest = tx_axis_tdest_i; - assign tx_axis_req_i.t.user = tx_axis_tuser_i; - assign tx_axis_req_i.tvalid = tx_axis_tvalid_i; - assign tx_axis_tready_o = tx_axis_rsp_o.tready; - //AXIS RX - assign rx_axis_tdata_o = rx_axis_req_o.t.data; - assign rx_axis_tstrb_o = rx_axis_req_o.t.strb; - assign rx_axis_tkeep_o = rx_axis_req_o.t.keep; - assign rx_axis_tlast_o = rx_axis_req_o.t.last; - assign rx_axis_tid_o = rx_axis_req_o.t.id; - assign rx_axis_tdest_o = rx_axis_req_o.t.dest; - assign rx_axis_tuser_o = rx_axis_req_o.t.user; - assign rx_axis_tvalid_o = rx_axis_req_o.tvalid; - assign rx_axis_rsp_i.tready = rx_axis_tready_i; - - - // Regbus - assign reg_req_i.addr = reg_bus_addr_i; - assign reg_req_i.write = reg_bus_write_i; - assign reg_req_i.wdata = reg_bus_wdata_i; - assign reg_req_i.wstrb = reg_bus_wstrb_i; - assign reg_req_i.valid = reg_bus_valid_i; - assign reg_bus_rdata_o = reg_rsp_o.rdata; - assign reg_bus_ready_o = reg_rsp_o.ready; - assign reg_bus_error_o = reg_rsp_o.error; - -endmodule : eth_top_synth From 2af170cb259d7c9ecd6e6bf0fc7f43438ba73e76 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Fri, 16 Feb 2024 15:59:46 +0100 Subject: [PATCH 02/12] treewide: Mixed fixes --- Bender.lock | 2 +- Bender.yml | 7 +- eth.mk | 2 +- rtl/eth_clk_gen.sv | 6 +- rtl/eth_idma_pkg.sv | 122 ++++++++++++++-------------- rtl/eth_idma_wrap.sv | 4 +- target/synth/eth_idma_wrap_synth.sv | 4 +- 7 files changed, 76 insertions(+), 71 deletions(-) diff --git a/Bender.lock b/Bender.lock index 5f4ed57..7b37788 100644 --- a/Bender.lock +++ b/Bender.lock @@ -44,7 +44,7 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] idma: - revision: 18fa40f0b12927622c6a0ff771fb0142d20bcb3d + revision: a80fcace92b1562e7cd76c8615298b5623ba74d2 version: null source: Git: git@github.com:pulp-platform/iDMA.git diff --git a/Bender.yml b/Bender.yml index 67e5da6..b1e67d8 100644 --- a/Bender.yml +++ b/Bender.yml @@ -21,7 +21,7 @@ dependencies: common_verification : { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 } register_interface : { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 } - idma: { git: "git@github.com:pulp-platform/iDMA.git", rev: "18fa40f" } # branch: cl/idma-eth + idma: { git: "git@github.com:pulp-platform/iDMA.git", rev: "a80fcace" } # branch: cl/idma-eth sources: # Source files grouped in levels. Files in level 0 have no dependencies on files in this @@ -51,7 +51,10 @@ sources: - rtl/eth_top.sv - rtl/eth_clk_gen.sv - rtl/eth_idma_wrap.sv - - target/synth/eth_idma_wrap_synth.sv + + - target: any(synthesis, asic) + files: + - target/synth/eth_idma_wrap_synth.sv - target: test files: diff --git a/eth.mk b/eth.mk index 79276bd..81e1c11 100644 --- a/eth.mk +++ b/eth.mk @@ -52,7 +52,7 @@ include $(IDMA_ROOT)/idma.mk ###################### ETH_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-ethernet-nonfree.git -ETH_NONFREE_COMMIT ?= cd8dcd3 +ETH_NONFREE_COMMIT ?= 5633df7 eth-nonfree-init: git clone $(ETH_NONFREE_REMOTE) $(ETH_ROOT)/nonfree diff --git a/rtl/eth_clk_gen.sv b/rtl/eth_clk_gen.sv index 3939de3..86063c6 100644 --- a/rtl/eth_clk_gen.sv +++ b/rtl/eth_clk_gen.sv @@ -15,7 +15,9 @@ module eth_clk_gen ( logic clk_eth_125; assign clk_eth_125 = clk_eth_125_o; -fll_dummy i_gf12_fll ( // Clock & reset +fll_dummy #( + .NB_FLL (1) +) i_gf12_fll ( // Clock & reset .OUTCLK ( clk_eth_125_o ), // FLL clock outputs .REFCLK ( ref_clk_i ), // Reference clock input .RSTB ( rst_ni ), // Asynchronous reset (active low) @@ -44,4 +46,4 @@ clk_gen_hyper i_clk_gen_ethernet ( .clk270_o ( ) ); -endmodule : eth_clk_gen \ No newline at end of file +endmodule : eth_clk_gen diff --git a/rtl/eth_idma_pkg.sv b/rtl/eth_idma_pkg.sv index af6b722..3aff68a 100644 --- a/rtl/eth_idma_pkg.sv +++ b/rtl/eth_idma_pkg.sv @@ -24,7 +24,7 @@ package eth_idma_pkg; `REG_BUS_TYPEDEF_ALL(reg_bus, reg_bus_addr_t, reg_bus_data_t, reg_bus_strb_t) parameter int unsigned DataWidth = 64; - parameter int unsigned AddrWidth = 64; + parameter int unsigned AddrWidth = 32; parameter int unsigned UserWidth = 1; parameter int unsigned AxiIdWidth = 5; parameter int unsigned TFLenWidth = 32; @@ -33,70 +33,70 @@ package eth_idma_pkg; localparam int unsigned OffsetWidth = $clog2(StrbWidth); typedef logic [AddrWidth-1:0] addr_t; - typedef logic [AxiIdWidth-1:0] id_t; + typedef logic [AxiIdWidth-1:0] id_t; typedef logic [UserWidth-1:0] user_t; typedef logic [StrbWidth-1:0] strb_t; typedef logic [DataWidth-1:0] data_t; typedef logic [TFLenWidth-1:0] tf_len_t; - /// AXI4+ATOP typedefs - `AXI_TYPEDEF_AW_CHAN_T(axi_aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(axi_w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(axi_b_chan_t, id_t, user_t) - - `AXI_TYPEDEF_AR_CHAN_T(axi_ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(axi_r_chan_t, data_t, id_t, user_t) - - `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_chan_t, axi_w_chan_t, axi_ar_chan_t) - `AXI_TYPEDEF_RESP_T(axi_rsp_t, axi_b_chan_t, axi_r_chan_t) - - /// AXI Stream typedefs - `IDMA_AXI_STREAM_TYPEDEF_S_CHAN_T(axis_t_chan_t, data_t, strb_t, strb_t, id_t, id_t, user_t) - `IDMA_AXI_STREAM_TYPEDEF_REQ_T(axi_stream_req_t, axis_t_chan_t) - `IDMA_AXI_STREAM_TYPEDEF_RSP_T(axi_stream_rsp_t) - - /// Meta Channel Widths - localparam int unsigned axi_aw_chan_width = axi_pkg::aw_width(AddrWidth, AxiIdWidth, UserWidth); - localparam int unsigned axi_ar_chan_width = axi_pkg::ar_width(AddrWidth, AxiIdWidth, UserWidth); - localparam int unsigned axis_t_chan_width = $bits(axis_t_chan_t); - - `IDMA_TYPEDEF_OPTIONS_T(options_t, id_t) - `IDMA_TYPEDEF_REQ_T(idma_req_t, tf_len_t, addr_t, options_t) - `IDMA_TYPEDEF_ERR_PAYLOAD_T(err_payload_t, addr_t) - `IDMA_TYPEDEF_RSP_T(idma_rsp_t, err_payload_t) - - function int unsigned max_width(input int unsigned a, b); - return (a > b) ? a : b; - endfunction - -typedef struct packed { - axi_ar_chan_t ar_chan; - logic[max_width(axi_ar_chan_width, axis_t_chan_width)-axi_ar_chan_width:0] padding; -} axi_read_ar_chan_padded_t; - -typedef struct packed { - axis_t_chan_t t_chan; - logic[max_width(axi_ar_chan_width, axis_t_chan_width)-axis_t_chan_width:0] padding; -} axis_read_t_chan_padded_t; - -typedef union packed { - axi_read_ar_chan_padded_t axi; - axis_read_t_chan_padded_t axis; -} read_meta_channel_t; - -typedef struct packed { - axi_aw_chan_t aw_chan; - logic[max_width(axi_aw_chan_width, axis_t_chan_width)-axi_aw_chan_width:0] padding; -} axi_write_aw_chan_padded_t; - -typedef struct packed { - axis_t_chan_t t_chan; - logic[max_width(axi_aw_chan_width, axis_t_chan_width)-axis_t_chan_width:0] padding; -} axis_write_t_chan_padded_t; - -typedef union packed { - axi_write_aw_chan_padded_t axi; - axis_write_t_chan_padded_t axis; -} write_meta_channel_t; + /// AXI4+ATOP typedefs + `AXI_TYPEDEF_AW_CHAN_T(axi_aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(axi_w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(axi_b_chan_t, id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(axi_ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(axi_r_chan_t, data_t, id_t, user_t) + + `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_chan_t, axi_w_chan_t, axi_ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_rsp_t, axi_b_chan_t, axi_r_chan_t) + + /// AXI Stream typedefs + `IDMA_AXI_STREAM_TYPEDEF_S_CHAN_T(axis_t_chan_t, data_t, strb_t, strb_t, id_t, id_t, user_t) + `IDMA_AXI_STREAM_TYPEDEF_REQ_T(axi_stream_req_t, axis_t_chan_t) + `IDMA_AXI_STREAM_TYPEDEF_RSP_T(axi_stream_rsp_t) + + /// Meta Channel Widths + localparam int unsigned axi_aw_chan_width = axi_pkg::aw_width(AddrWidth, AxiIdWidth, UserWidth); + localparam int unsigned axi_ar_chan_width = axi_pkg::ar_width(AddrWidth, AxiIdWidth, UserWidth); + localparam int unsigned axis_t_chan_width = $bits(axis_t_chan_t); + + `IDMA_TYPEDEF_OPTIONS_T(options_t, id_t) + `IDMA_TYPEDEF_REQ_T(idma_req_t, tf_len_t, addr_t, options_t) + `IDMA_TYPEDEF_ERR_PAYLOAD_T(err_payload_t, addr_t) + `IDMA_TYPEDEF_RSP_T(idma_rsp_t, err_payload_t) + + function automatic int unsigned max_width(input int unsigned a, b); + return (a > b) ? a : b; + endfunction + + typedef struct packed { + axi_ar_chan_t ar_chan; + logic[max_width(axi_ar_chan_width, axis_t_chan_width)-axi_ar_chan_width:0] padding; + } axi_read_ar_chan_padded_t; + + typedef struct packed { + axis_t_chan_t t_chan; + logic[max_width(axi_ar_chan_width, axis_t_chan_width)-axis_t_chan_width:0] padding; + } axis_read_t_chan_padded_t; + + typedef union packed { + axi_read_ar_chan_padded_t axi; + axis_read_t_chan_padded_t axis; + } read_meta_channel_t; + + typedef struct packed { + axi_aw_chan_t aw_chan; + logic[max_width(axi_aw_chan_width, axis_t_chan_width)-axi_aw_chan_width:0] padding; + } axi_write_aw_chan_padded_t; + + typedef struct packed { + axis_t_chan_t t_chan; + logic[max_width(axi_aw_chan_width, axis_t_chan_width)-axis_t_chan_width:0] padding; + } axis_write_t_chan_padded_t; + + typedef union packed { + axi_write_aw_chan_padded_t axi; + axis_write_t_chan_padded_t axis; + } write_meta_channel_t; endpackage : eth_idma_pkg diff --git a/rtl/eth_idma_wrap.sv b/rtl/eth_idma_wrap.sv index 3db60a0..acd8a4c 100644 --- a/rtl/eth_idma_wrap.sv +++ b/rtl/eth_idma_wrap.sv @@ -15,13 +15,13 @@ module eth_idma_wrap #( /// Data width - parameter int unsigned DataWidth = 32'd32, + parameter int unsigned DataWidth = 32'd64, /// Address width parameter int unsigned AddrWidth = 32'd32, /// AXI User width parameter int unsigned UserWidth = 32'd1, /// AXI ID width - parameter int unsigned AxiIdWidth = 32'd1, + parameter int unsigned AxiIdWidth = 32'd5, /// Number of transaction that can be in-flight concurrently parameter int unsigned NumAxInFlight = 32'd3, /// The depth of the internal reorder buffer diff --git a/target/synth/eth_idma_wrap_synth.sv b/target/synth/eth_idma_wrap_synth.sv index ad01bbd..4433c27 100644 --- a/target/synth/eth_idma_wrap_synth.sv +++ b/target/synth/eth_idma_wrap_synth.sv @@ -14,13 +14,13 @@ module eth_idma_wrap_synth #( /// Data width - parameter int unsigned DataWidth = 32'd32, + parameter int unsigned DataWidth = 32'd64, /// Address width parameter int unsigned AddrWidth = 32'd32, /// AXI User width parameter int unsigned UserWidth = 32'd1, /// AXI ID width - parameter int unsigned AxiIdWidth = 32'd1, + parameter int unsigned AxiIdWidth = 32'd5, /// Number of transaction that can be in-flight concurrently parameter int unsigned NumAxInFlight = 32'd3, /// The depth of the internal reorder buffer From 92174e3c1f4625e498008149f6c073779f48f546 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Fri, 16 Feb 2024 16:17:22 +0100 Subject: [PATCH 03/12] eth.mk: Update nonfree pointer --- eth.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/eth.mk b/eth.mk index 81e1c11..b8bc7a6 100644 --- a/eth.mk +++ b/eth.mk @@ -52,7 +52,7 @@ include $(IDMA_ROOT)/idma.mk ###################### ETH_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-ethernet-nonfree.git -ETH_NONFREE_COMMIT ?= 5633df7 +ETH_NONFREE_COMMIT ?= 6c5e566 eth-nonfree-init: git clone $(ETH_NONFREE_REMOTE) $(ETH_ROOT)/nonfree From 56737fb11f0058c71f939ca09ff7a2aabbcb8cf1 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Fri, 16 Feb 2024 16:19:51 +0100 Subject: [PATCH 04/12] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 0e4d402..664a739 100644 --- a/README.md +++ b/README.md @@ -20,7 +20,7 @@ used. ## Generate iDMA with AXIS support (Terminal) ``` -make eth-gen +make eth-idma-gen ``` ## Compile (Questa) From a319bb6db325694d96fa94aadca5c0fbcf2e4419 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Fri, 16 Feb 2024 16:21:36 +0100 Subject: [PATCH 05/12] eth.mk: Update nonfree pointer --- eth.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/eth.mk b/eth.mk index b8bc7a6..c6ce7be 100644 --- a/eth.mk +++ b/eth.mk @@ -52,7 +52,7 @@ include $(IDMA_ROOT)/idma.mk ###################### ETH_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-ethernet-nonfree.git -ETH_NONFREE_COMMIT ?= 6c5e566 +ETH_NONFREE_COMMIT ?= 0f2f998 eth-nonfree-init: git clone $(ETH_NONFREE_REMOTE) $(ETH_ROOT)/nonfree From f345e76ca1e46d6f36f5be496677ec07cb7430be Mon Sep 17 00:00:00 2001 From: aottaviano Date: Fri, 16 Feb 2024 16:23:31 +0100 Subject: [PATCH 06/12] Bender.yml: Use same IP commit lenght --- Bender.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.yml b/Bender.yml index b1e67d8..dd71ab5 100644 --- a/Bender.yml +++ b/Bender.yml @@ -21,7 +21,7 @@ dependencies: common_verification : { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 } register_interface : { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 } - idma: { git: "git@github.com:pulp-platform/iDMA.git", rev: "a80fcace" } # branch: cl/idma-eth + idma: { git: "git@github.com:pulp-platform/iDMA.git", rev: "a80fcac" } # branch: cl/idma-eth sources: # Source files grouped in levels. Files in level 0 have no dependencies on files in this From 07bde7999b43dd1af924603714a0cc233f8aca48 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Fri, 16 Feb 2024 16:25:25 +0100 Subject: [PATCH 07/12] eth.mk: Update nonfree pointer --- eth.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/eth.mk b/eth.mk index c6ce7be..bb04020 100644 --- a/eth.mk +++ b/eth.mk @@ -52,7 +52,7 @@ include $(IDMA_ROOT)/idma.mk ###################### ETH_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-ethernet-nonfree.git -ETH_NONFREE_COMMIT ?= 0f2f998 +ETH_NONFREE_COMMIT ?= 9a45a7c eth-nonfree-init: git clone $(ETH_NONFREE_REMOTE) $(ETH_ROOT)/nonfree From 0d15e4219d64e324da6ba92fa5758d31f532f8e3 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Fri, 16 Feb 2024 16:33:08 +0100 Subject: [PATCH 08/12] target: Update keyword for succeeded test --- target/sim/src/eth_tb.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sim/src/eth_tb.sv b/target/sim/src/eth_tb.sv index a0eedc2..1b2d5d4 100644 --- a/target/sim/src/eth_tb.sv +++ b/target/sim/src/eth_tb.sv @@ -367,7 +367,7 @@ module eth_tb end if (!error_found) begin - $display("Test PASS"); + $display("SUCCESS"); end $finish; From e91ed1f3f1f74c3ed92687824ad31e8d7784ca5a Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Tue, 20 Feb 2024 11:11:22 +0100 Subject: [PATCH 09/12] restore external clk gen --- Bender.yml | 3 -- rtl/clk_gen_hyper.sv | 61 ------------------------------ rtl/eth_clk_gen.sv | 49 ------------------------ rtl/eth_idma_pkg.sv | 2 +- rtl/eth_idma_wrap.sv | 21 ++++------- rtl/eth_top.sv | 73 ++++++++++++++++++------------------ rtl/fll_dummy.sv | 89 -------------------------------------------- 7 files changed, 46 insertions(+), 252 deletions(-) delete mode 100644 rtl/clk_gen_hyper.sv delete mode 100644 rtl/eth_clk_gen.sv delete mode 100644 rtl/fll_dummy.sv diff --git a/Bender.yml b/Bender.yml index dd71ab5..8be528d 100644 --- a/Bender.yml +++ b/Bender.yml @@ -32,8 +32,6 @@ sources: - gen/eth_idma_reg_top.sv - rtl/axis_gmii_rx.sv - rtl/axis_gmii_tx.sv - - rtl/fll_dummy.sv - - rtl/clk_gen_hyper.sv # Level 1 - rtl/eth_mac_1g_rgmii_fifo.sv - rtl/eth_mac_1g_rgmii.sv @@ -49,7 +47,6 @@ sources: - rtl/framing_top.sv - rtl/eth_idma_pkg.sv - rtl/eth_top.sv - - rtl/eth_clk_gen.sv - rtl/eth_idma_wrap.sv - target: any(synthesis, asic) diff --git a/rtl/clk_gen_hyper.sv b/rtl/clk_gen_hyper.sv deleted file mode 100644 index adf9c8b..0000000 --- a/rtl/clk_gen_hyper.sv +++ /dev/null @@ -1,61 +0,0 @@ -// Copyright 2018-2021 ETH Zurich and University of Bologna. -// -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -//// Hayate Okuhara - -// Description: Generates 4 phase shifted clocks out of one faster clock -module clk_gen_hyper ( - input logic clk_i, // input clock - input logic rst_ni, - output logic clk0_o, // have the input clock - 0deg phase shift - output logic clk90_o, // have the input clock - 90deg phase shift - output logic clk180_o, // have the input clock - 180deg phase shift - output logic clk270_o // have the input clock - 270deg phase shift -); - -//`ifndef PULP_FPGA_EMUL - logic r_clk0_o; - logic r_clk90_o; - logic r_clk180_o; - logic r_clk270_o; - - assign clk0_o = r_clk0_o; - assign clk90_o = r_clk90_o; - assign clk180_o = r_clk180_o; - assign clk270_o = r_clk270_o; - - always_ff @(posedge clk_i or negedge rst_ni) begin - if(~rst_ni) begin - r_clk0_o <= 0; - r_clk180_o <= 1; - end else begin - r_clk0_o <= ~r_clk0_o; - r_clk180_o <= r_clk90_o; - end - end - - always_ff @(negedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - r_clk90_o <= 0; - r_clk270_o <= 1; - end else begin - r_clk90_o <= r_clk0_o; - r_clk270_o <= r_clk180_o; - end - end -/*`else - assign clk0_o = clk_i; - assign clk90_o = clk_i; - assign clk180_o = clk_i; - assign clk270_o = clk_i; -`endif*/ -endmodule - diff --git a/rtl/eth_clk_gen.sv b/rtl/eth_clk_gen.sv deleted file mode 100644 index 86063c6..0000000 --- a/rtl/eth_clk_gen.sv +++ /dev/null @@ -1,49 +0,0 @@ -// Copyright 2024 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// -// Chaoqun Liang - -module eth_clk_gen ( - input logic ref_clk_i, - input logic rst_ni, - output logic clk_eth_125_o, - output logic clk_eth_125_90_o -); - -logic clk_eth_125; -assign clk_eth_125 = clk_eth_125_o; - -fll_dummy #( - .NB_FLL (1) -) i_gf12_fll ( // Clock & reset - .OUTCLK ( clk_eth_125_o ), // FLL clock outputs - .REFCLK ( ref_clk_i ), // Reference clock input - .RSTB ( rst_ni ), // Asynchronous reset (active low) - .CFGREQ ( ), // CFG I/F access request (active high) - .CFGACK ( ), // CFG I/F access granted (active high) - .CFGAD ( ), // CFG I/F address bus - .CFGD ( ), // CFG I/F input data bus (write) - .CFGQ ( ), // CFG I/F output data bus (read) - .CFGWEB ( ), // CFG I/F write enable (active low) - .PWD ( 1'b0 ), // Asynchronous power down (active high) - .RET ( 1'b0 ), // Asynchronous retention/isolation control (active high) - .TM ( 1'b0 ), // Test mode (active high) - .TE ( 1'b0 ), // Scan enable (active high) - .TD ( '0 ), // Scan data input for chain 1:4 - .TQ ( ), // Scan data output for chain 1:4 - .JTD ( 1'b0 ), // Scan data in 5 - .JTQ ( ) // Scan data out 5 -); - -clk_gen_hyper i_clk_gen_ethernet ( - .clk_i ( clk_eth_125 ), - .rst_ni ( rst_ni ), - .clk0_o ( ), - .clk90_o ( clk_eth_125_90_o ), - .clk180_o ( ), - .clk270_o ( ) -); - -endmodule : eth_clk_gen diff --git a/rtl/eth_idma_pkg.sv b/rtl/eth_idma_pkg.sv index 3aff68a..1dc0011 100644 --- a/rtl/eth_idma_pkg.sv +++ b/rtl/eth_idma_pkg.sv @@ -99,4 +99,4 @@ package eth_idma_pkg; axis_write_t_chan_padded_t axis; } write_meta_channel_t; -endpackage : eth_idma_pkg +endpackage : eth_idma_pkg \ No newline at end of file diff --git a/rtl/eth_idma_wrap.sv b/rtl/eth_idma_wrap.sv index acd8a4c..d25285f 100644 --- a/rtl/eth_idma_wrap.sv +++ b/rtl/eth_idma_wrap.sv @@ -50,6 +50,9 @@ module eth_idma_wrap #( )( input logic clk_i, input logic rst_ni, + /// Etherent Internal clocks + input logic eth_clk_i, + input logic eth_clk90_i, /// Ethernet: 1000BASE-T RGMII input logic phy_rx_clk_i, input logic [3:0] phy_rxd_i, @@ -84,7 +87,6 @@ module eth_idma_wrap #( import eth_idma_reg_pkg::*; import idma_pkg::*; - logic eth_clk, eth_clk90; logic idma_req_valid, req_ready, idma_rsp_ready, rsp_valid; localparam idma_pkg::error_cap_e ErrorCap = ErrorHandling ? ERROR_HANDLING : NO_ERROR_HANDLING; @@ -204,13 +206,6 @@ module eth_idma_wrap #( .busy_o ( idma_busy_o ) ); - eth_clk_gen i_eth_clk_gen( - .ref_clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clk_eth_125_o ( eth_clk ), - .clk_eth_125_90_o ( eth_clk90 ) - ); - eth_top #( .axi_stream_req_t ( axi_stream_req_t ), .axi_stream_rsp_t ( axi_stream_rsp_t ), @@ -223,8 +218,8 @@ module eth_idma_wrap #( .hw2reg_itf_t ( eth_idma_hw2reg_t ) ) i_eth_top ( .rst_ni ( rst_ni ), - .clk_i ( eth_clk ), - .clk90_int ( eth_clk90 ), + .clk_i ( eth_clk_i ), + .clk90_int ( eth_clk90_i ), .phy_rx_clk ( phy_rx_clk_i ), .phy_rxd ( phy_rxd_i ), .phy_rx_ctl ( phy_rx_ctl_i ), @@ -259,7 +254,7 @@ module eth_idma_wrap #( .src_valid_i ( idma_axis_write_req.tvalid ), .src_ready_o ( idma_axis_write_rsp.tready ), .dst_rst_ni ( rst_ni ), - .dst_clk_i ( eth_clk ), + .dst_clk_i ( eth_clk_i ), .dst_data_o ( eth_axis_tx_req.t ), .dst_valid_o ( eth_axis_tx_req.tvalid ), .dst_ready_i ( eth_axis_tx_rsp.tready ) @@ -271,7 +266,7 @@ module eth_idma_wrap #( .LOG_DEPTH ( RxFifoLogDepth ) ) i_cdc_fifo_rx ( .src_rst_ni ( rst_ni ), - .src_clk_i ( eth_clk ), + .src_clk_i ( eth_clk_i ), .src_data_i ( eth_axis_rx_rsp.t ), .src_valid_i ( eth_axis_rx_rsp.tvalid ), .src_ready_o ( eth_axis_rx_req.tready ), @@ -296,4 +291,4 @@ module eth_idma_wrap #( .mst_resp_i ( axi_rsp_i ) ); -endmodule : eth_idma_wrap +endmodule : eth_idma_wrap \ No newline at end of file diff --git a/rtl/eth_top.sv b/rtl/eth_top.sv index d908768..b3a91cd 100644 --- a/rtl/eth_top.sv +++ b/rtl/eth_top.sv @@ -11,55 +11,56 @@ `include "register_interface/assign.svh" module eth_top #( - /// AXI Stream in request struct - parameter type axi_stream_req_t = eth_idma_pkg::axi_stream_req_t, - /// AXI Stream in response struct - parameter type axi_stream_rsp_t = eth_idma_pkg::axi_stream_rsp_t, + /// AXI Stream Data Width - parameter int unsigned DataWidth = 64, + parameter int unsigned DataWidth = 64, /// AXI Stream Id Width - parameter int unsigned IdWidth = 0, + parameter int unsigned IdWidth = 0, /// AXI Stream Dest Width = 0 - parameter int unsigned DestWidth = 0, + parameter int unsigned DestWidth = 0, /// AXI Stream User Width - parameter int unsigned UserWidth = 1, + parameter int unsigned UserWidth = 1, + /// Register address width + parameter int unsigned RegAddrWidth = 4, + /// AXI Stream in request struct + parameter type axi_stream_req_t = logic, + /// AXI Stream in response struct + parameter type axi_stream_rsp_t = logic, /// REGBUS - //parameter type reg2hw_itf_t = eth_idma_reg_pkg::eth_idma_reg2hw_t, - //parameter type hw2reg_itf_t = eth_idma_reg_pkg::eth_idma_hw2reg_t, - parameter type reg2hw_itf_t = logic, - parameter type hw2reg_itf_t = logic, - parameter int AW_REGBUS = 4 + parameter type reg2hw_itf_t = logic, + parameter type hw2reg_itf_t = logic + ) ( // Internal 125 MHz clock - input wire clk_i, - input wire rst_ni, - input wire clk90_int, + input wire clk_i , + input wire rst_ni , + input wire clk90_int , // Ethernet: 1000BASE-T RGMII - input wire phy_rx_clk, - input wire [3:0] phy_rxd, - input wire phy_rx_ctl, - output wire phy_tx_clk, - output wire [3:0] phy_txd, - output wire phy_tx_ctl, - output wire phy_reset_n, - input wire phy_int_n, - input wire phy_pme_n, + input wire phy_rx_clk , + input wire [3:0] phy_rxd , + input wire phy_rx_ctl , + output wire phy_tx_clk , + output wire [3:0] phy_txd , + output wire phy_tx_ctl , + output wire phy_reset_n , + input wire phy_int_n , + input wire phy_pme_n , // MDIO - input wire phy_mdio_i, - output reg phy_mdio_o, - output reg phy_mdio_oe, - output wire phy_mdc, + input wire phy_mdio_i , + output reg phy_mdio_o , + output reg phy_mdio_oe , + output wire phy_mdc , // AXIS TX/RX input axi_stream_req_t tx_axis_req_i, output axi_stream_rsp_t tx_axis_rsp_o, output axi_stream_req_t rx_axis_req_o, input axi_stream_rsp_t rx_axis_rsp_i, - - input logic idma_req_ready, - input logic idma_rsp_valid, + + input logic idma_req_ready, + input logic idma_rsp_valid, // Reg configs - input reg2hw_itf_t reg2hw_i, - output hw2reg_itf_t hw2reg_o + input reg2hw_itf_t reg2hw_i , + output hw2reg_itf_t hw2reg_o ); // ---------------- axis streams for the framing module ---------------------- @@ -89,7 +90,7 @@ module eth_top #( .axi_stream_rsp_t ( s_framing_rsp_t ), .reg2hw_itf_t ( reg2hw_itf_t ), .hw2reg_itf_t ( hw2reg_itf_t ), - .AW_REGBUS ( AW_REGBUS ) + .AW_REGBUS ( RegAddrWidth ) ) i_framing_top ( .rst_ni ( rst_ni ), .clk_i ( clk_i ), @@ -164,4 +165,4 @@ module eth_top #( .out_rsp_i ( rx_axis_rsp_i ) ); -endmodule : eth_top +endmodule : eth_top \ No newline at end of file diff --git a/rtl/fll_dummy.sv b/rtl/fll_dummy.sv deleted file mode 100644 index 04fd06f..0000000 --- a/rtl/fll_dummy.sv +++ /dev/null @@ -1,89 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -`ifndef TEST_CLOCK_BYPASS - `timescale 1ns/1ns - `endif - -module fll_dummy #( - parameter int unsigned NB_FLL = 4, - parameter int unsigned CFG_ADDR_WIDTH = 4, - parameter int unsigned CFG_DATA_WIDTH = 32, - parameter int unsigned NB_SCAN_CHAIN = 1 -) ( - // Clock & reset - output logic [NB_FLL-1:0] OUTCLK, // FLL clock outputs - input logic REFCLK, // Reference clock input - input logic RSTB, // Asynchronous reset (active low) - - // Configuration I/F - input logic CFGREQ, // CFG I/F access request (active high) - output logic CFGACK, // CFG I/F access granted (active high) - input logic [CFG_ADDR_WIDTH-1:0] CFGAD, // CFG I/F address bus - input logic [CFG_DATA_WIDTH-1:0] CFGD, // CFG I/F input data bus (write) - output logic [CFG_DATA_WIDTH-1:0] CFGQ, // CFG I/F output data bus (read) - input logic CFGWEB, // CFG I/F write enable (active low) - - // Power management - input logic PWD, // Asynchronous power down (active high) - input logic RET, // Asynchronous retention/isolation control (active high) - - // Test I/F - input logic TM, // Test mode (active high) - input logic TE, // Scan enable (active high) - input logic [NB_SCAN_CHAIN-1:0] TD, // Scan data input for chain 1:4 - output logic [NB_SCAN_CHAIN-1:0] TQ, // Scan data output for chain 1:4 - input logic JTD, // Scan data in 5 - output logic JTQ // Scan data out 5 -); - - `ifdef TARGET_ASIC - `ifdef TARGET_TOP_POST_SYNTH_SIM - `define GENERATE_CLOCK - `endif - `else - `define GENERATE_CLOCK - `endif - - `ifdef GENERATE_CLOCK - logic clk; - parameter time ClkPeriod = 8ns; - - - assign CFGACK = 1'b1; - assign CFGQ = 32'hdeadbeef; - - assign TQ = 1'b0; - assign JTQ = 1'b0; - - `ifndef TEST_CLOCK_BYPASS - initial begin - clk = 1'b0; - end - always begin - // Emit rising clock edge. - clk = 1'b1; - // Wait for at most half the clock period before emitting falling clock edge. Due to integer - // division, this is not always exactly half the clock period but as close as we can get. - #(ClkPeriod/2); - // Emit falling clock edge. - clk = 1'b0; - // Wait for remainder of clock period before continuing with next cycle. - #(ClkPeriod/2); - end // always - - for (genvar i=0;i Date: Tue, 20 Feb 2024 11:15:20 +0100 Subject: [PATCH 10/12] restore eth_top, tb update --- rtl/eth_top.sv | 73 ++++++++++++++++++++-------------------- target/sim/src/eth_tb.sv | 30 ++++++++++++++++- 2 files changed, 65 insertions(+), 38 deletions(-) diff --git a/rtl/eth_top.sv b/rtl/eth_top.sv index b3a91cd..fe15777 100644 --- a/rtl/eth_top.sv +++ b/rtl/eth_top.sv @@ -1,4 +1,4 @@ -// Copyright 2023 ETH Zurich and University of Bologna. +/// Copyright 2023 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 // @@ -11,56 +11,55 @@ `include "register_interface/assign.svh" module eth_top #( - + /// AXI Stream in request struct + parameter type axi_stream_req_t = eth_idma_pkg::axi_stream_req_t, + /// AXI Stream in response struct + parameter type axi_stream_rsp_t = eth_idma_pkg::axi_stream_rsp_t, /// AXI Stream Data Width - parameter int unsigned DataWidth = 64, + parameter int unsigned DataWidth = 64, /// AXI Stream Id Width - parameter int unsigned IdWidth = 0, + parameter int unsigned IdWidth = 0, /// AXI Stream Dest Width = 0 - parameter int unsigned DestWidth = 0, + parameter int unsigned DestWidth = 0, /// AXI Stream User Width - parameter int unsigned UserWidth = 1, - /// Register address width - parameter int unsigned RegAddrWidth = 4, - /// AXI Stream in request struct - parameter type axi_stream_req_t = logic, - /// AXI Stream in response struct - parameter type axi_stream_rsp_t = logic, + parameter int unsigned UserWidth = 1, /// REGBUS - parameter type reg2hw_itf_t = logic, - parameter type hw2reg_itf_t = logic - + //parameter type reg2hw_itf_t = eth_idma_reg_pkg::eth_idma_reg2hw_t, + //parameter type hw2reg_itf_t = eth_idma_reg_pkg::eth_idma_hw2reg_t, + parameter type reg2hw_itf_t = logic, + parameter type hw2reg_itf_t = logic, + parameter int AW_REGBUS = 4 ) ( // Internal 125 MHz clock - input wire clk_i , - input wire rst_ni , - input wire clk90_int , + input wire clk_i, + input wire rst_ni, + input wire clk90_int, // Ethernet: 1000BASE-T RGMII - input wire phy_rx_clk , - input wire [3:0] phy_rxd , - input wire phy_rx_ctl , - output wire phy_tx_clk , - output wire [3:0] phy_txd , - output wire phy_tx_ctl , - output wire phy_reset_n , - input wire phy_int_n , - input wire phy_pme_n , + input wire phy_rx_clk, + input wire [3:0] phy_rxd, + input wire phy_rx_ctl, + output wire phy_tx_clk, + output wire [3:0] phy_txd, + output wire phy_tx_ctl, + output wire phy_reset_n, + input wire phy_int_n, + input wire phy_pme_n, // MDIO - input wire phy_mdio_i , - output reg phy_mdio_o , - output reg phy_mdio_oe , - output wire phy_mdc , + input wire phy_mdio_i, + output reg phy_mdio_o, + output reg phy_mdio_oe, + output wire phy_mdc, // AXIS TX/RX input axi_stream_req_t tx_axis_req_i, output axi_stream_rsp_t tx_axis_rsp_o, output axi_stream_req_t rx_axis_req_o, input axi_stream_rsp_t rx_axis_rsp_i, - - input logic idma_req_ready, - input logic idma_rsp_valid, + + input logic idma_req_ready, + input logic idma_rsp_valid, // Reg configs - input reg2hw_itf_t reg2hw_i , - output hw2reg_itf_t hw2reg_o + input reg2hw_itf_t reg2hw_i, + output hw2reg_itf_t hw2reg_o ); // ---------------- axis streams for the framing module ---------------------- @@ -90,7 +89,7 @@ module eth_top #( .axi_stream_rsp_t ( s_framing_rsp_t ), .reg2hw_itf_t ( reg2hw_itf_t ), .hw2reg_itf_t ( hw2reg_itf_t ), - .AW_REGBUS ( RegAddrWidth ) + .AW_REGBUS ( AW_REGBUS ) ) i_framing_top ( .rst_ni ( rst_ni ), .clk_i ( clk_i ), diff --git a/target/sim/src/eth_tb.sv b/target/sim/src/eth_tb.sv index 1b2d5d4..a2c396d 100644 --- a/target/sim/src/eth_tb.sv +++ b/target/sim/src/eth_tb.sv @@ -38,6 +38,7 @@ module eth_tb /// timing parameters localparam time SYS_TCK = 8ns; + localparam time TCK125 = 8ns; localparam time SYS_TA = 2ns; localparam time SYS_TT = 6ns; @@ -50,6 +51,8 @@ module eth_tb /// ethernet pads logic s_clk; + logic s_clk_125MHz_0; + logic s_clk_125MHz_90; logic s_rst_n; logic done = 0; logic error_found = 0; @@ -206,7 +209,8 @@ module eth_tb ) i_tx_eth_idma_wrap ( .clk_i ( s_clk ), .rst_ni ( s_rst_n ), - /// Etherent Internal clocks + .eth_clk_i ( s_clk_125MHz_0 ), // 125MHz in-phase + .eth_clk90_i ( s_clk_125MHz_90 ), // 125 MHz with 90 phase shift .phy_rx_clk_i ( eth_rxck ), .phy_rxd_i ( eth_rxd ), .phy_rx_ctl_i ( eth_rxctl ), @@ -249,6 +253,8 @@ module eth_tb )i_rx_eth_idma_wrap ( .clk_i ( s_clk ), .rst_ni ( s_rst_n ), + .eth_clk_i ( s_clk_125MHz_0 ), // 125MHz in-phase + .eth_clk90_i ( s_clk_125MHz_90 ), // 125 MHz with 90 phase shift .phy_rx_clk_i ( eth_txck ), .phy_rxd_i ( eth_txd ), .phy_rx_ctl_i ( eth_txctl ), @@ -274,6 +280,26 @@ module eth_tb ); // ------------------------ BEGINNING OF SIMULATION ------------------------ + + initial begin + while (!done) begin + s_clk_125MHz_0 <= 1; + #(TCK125/2); + s_clk_125MHz_0 <= 0; + #(TCK125/2); + end + end + + initial begin + while (!done) begin + s_clk_125MHz_90 <= 0; + #(TCK125/4); + s_clk_125MHz_90 <= 1; + #(TCK125/2); + s_clk_125MHz_90 <= 0; + #(TCK125/4); + end + end initial begin @@ -283,6 +309,8 @@ module eth_tb $readmemh("../stimuli/rx_mem_init.vmem", i_rx_axi_sim_mem.mem); $readmemh("../stimuli/eth_frame.vmem", i_tx_axi_sim_mem.mem); + + /// TX eth configs reg_drv_tx.send_write( 'h00, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address @(posedge s_clk); From b7cef2ff5caf3b56dacd020a123706bf9d7fe259 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Mon, 26 Feb 2024 17:47:36 +0100 Subject: [PATCH 11/12] multiple fixes --- Bender.lock | 9 +------- Bender.yml | 3 +-- README.md | 6 +++--- rtl/eth_idma_pkg.sv | 21 +++++++++--------- rtl/eth_idma_wrap.sv | 2 +- rtl/eth_top.sv | 2 +- rtl/framing_top.sv | 10 +++++++-- target/sim/src/eth_tb.sv | 46 ++++++++++++++++++---------------------- 8 files changed, 47 insertions(+), 52 deletions(-) diff --git a/Bender.lock b/Bender.lock index 7b37788..4958f3a 100644 --- a/Bender.lock +++ b/Bender.lock @@ -15,13 +15,6 @@ packages: - common_cells - common_verification - tech_cells_generic - axi_mem_if: - revision: 3567273b4f67bd57a81a2a503394a49641bae53a - version: 0.2.1 - source: - Git: git@github.com:pulp-platform/axi_mem_if.git - dependencies: - - axi axi_stream: revision: 54891ff40455ca94a37641b9da4604647878cc07 version: 0.1.1 @@ -45,7 +38,7 @@ packages: dependencies: [] idma: revision: a80fcace92b1562e7cd76c8615298b5623ba74d2 - version: null + version: 0.6.0-beta source: Git: git@github.com:pulp-platform/iDMA.git dependencies: diff --git a/Bender.yml b/Bender.yml index 8be528d..145ddc8 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,12 +16,11 @@ package: dependencies: axi : { git: "git@github.com:pulp-platform/axi.git", version: 0.39.1 } - axi_mem_if : { git: git@github.com:pulp-platform/axi_mem_if.git, version: 0.2.1 } axi_stream: { git: "git@github.com:pulp-platform/axi_stream.git", rev: "54891ff" } # branch: main common_verification : { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 } register_interface : { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 } - idma: { git: "git@github.com:pulp-platform/iDMA.git", rev: "a80fcac" } # branch: cl/idma-eth + idma: { git: "git@github.com:pulp-platform/iDMA.git", rev: "a80fcac" } # branch: main sources: # Source files grouped in levels. Files in level 0 have no dependencies on files in this diff --git a/README.md b/README.md index 664a739..c82004e 100644 --- a/README.md +++ b/README.md @@ -17,7 +17,7 @@ used. `pulp-ethernet` is intended for use with https://github.com/pulp-platform/ariane (a RISCV Linux-capable soft core). -## Generate iDMA with AXIS support (Terminal) +## Generate iDMA ``` make eth-idma-gen @@ -26,12 +26,12 @@ make eth-idma-gen ## Compile (Questa) ``` -make eth-hw-build +make eth-sim-build ``` ## Simulate (Questa) ``` -make eth-hw-sim +make eth-vsim-sim-run ``` ### Debugging diff --git a/rtl/eth_idma_pkg.sv b/rtl/eth_idma_pkg.sv index 1dc0011..85d61b6 100644 --- a/rtl/eth_idma_pkg.sv +++ b/rtl/eth_idma_pkg.sv @@ -1,7 +1,8 @@ -// Copyright 2023 ETH Zurich and University of Bologna. +// Copyright 2024 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 - +// +// Chaoqun Liang `include "axi_stream/assign.svh" `include "axi_stream/typedef.svh" @@ -13,13 +14,13 @@ package eth_idma_pkg; /// Ethernet reg typedefs - parameter int AW_REGBUS = 32; - localparam int DW_REGBUS = 32; - localparam int unsigned STRB_WIDTH = DW_REGBUS/8; + parameter int unsigned AwRegbus = 32; + localparam int unsigned DwRegbus = 32; + localparam int unsigned StrbWidth = DwRegbus/8; - typedef logic [AW_REGBUS-1:0] reg_bus_addr_t; - typedef logic [DW_REGBUS-1:0] reg_bus_data_t; - typedef logic [STRB_WIDTH-1:0] reg_bus_strb_t; + typedef logic [AwRegbus-1:0] reg_bus_addr_t; + typedef logic [DwRegbus-1:0] reg_bus_data_t; + typedef logic [StrbWidth-1:0] reg_bus_strb_t; `REG_BUS_TYPEDEF_ALL(reg_bus, reg_bus_addr_t, reg_bus_data_t, reg_bus_strb_t) @@ -29,13 +30,13 @@ package eth_idma_pkg; parameter int unsigned AxiIdWidth = 5; parameter int unsigned TFLenWidth = 32; - localparam int unsigned StrbWidth = DataWidth / 8; + localparam int unsigned AxiStrbWidth = DataWidth / 8; localparam int unsigned OffsetWidth = $clog2(StrbWidth); typedef logic [AddrWidth-1:0] addr_t; typedef logic [AxiIdWidth-1:0] id_t; typedef logic [UserWidth-1:0] user_t; - typedef logic [StrbWidth-1:0] strb_t; + typedef logic [AxiStrbWidth-1:0] strb_t; typedef logic [DataWidth-1:0] data_t; typedef logic [TFLenWidth-1:0] tf_len_t; diff --git a/rtl/eth_idma_wrap.sv b/rtl/eth_idma_wrap.sv index d25285f..0fe7271 100644 --- a/rtl/eth_idma_wrap.sv +++ b/rtl/eth_idma_wrap.sv @@ -50,7 +50,7 @@ module eth_idma_wrap #( )( input logic clk_i, input logic rst_ni, - /// Etherent Internal clocks + /// Ethernet Internal clocks input logic eth_clk_i, input logic eth_clk90_i, /// Ethernet: 1000BASE-T RGMII diff --git a/rtl/eth_top.sv b/rtl/eth_top.sv index fe15777..7a4c5ae 100644 --- a/rtl/eth_top.sv +++ b/rtl/eth_top.sv @@ -1,4 +1,4 @@ -/// Copyright 2023 ETH Zurich and University of Bologna. +// Copyright 2024 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 // diff --git a/rtl/framing_top.sv b/rtl/framing_top.sv index d4de620..21690d0 100644 --- a/rtl/framing_top.sv +++ b/rtl/framing_top.sv @@ -1,5 +1,11 @@ -// See LICENSE for license details. - +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Authors: +// - Jonathan Kimmitt +// - Thiemo Zaugg +// - chaoqun Liang module framing_top #( /// AXI Stream in request struct diff --git a/target/sim/src/eth_tb.sv b/target/sim/src/eth_tb.sv index a2c396d..878f550 100644 --- a/target/sim/src/eth_tb.sv +++ b/target/sim/src/eth_tb.sv @@ -37,14 +37,14 @@ module eth_tb import reg_test::*; /// timing parameters - localparam time SYS_TCK = 8ns; - localparam time TCK125 = 8ns; - localparam time SYS_TA = 2ns; - localparam time SYS_TT = 6ns; + localparam time SYS_TCK = 8ns; + localparam time TCK125 = 8ns; + localparam time SYS_TA = 2ns; + localparam time SYS_TT = 6ns; /// regbus - localparam int unsigned REG_BUS_DW = 32; - localparam int unsigned REG_BUS_AW = 32; + localparam int unsigned RegBusDw = 32; + localparam int unsigned RegBusAw = 32; /// parse error handling caps localparam error_cap_e ErrorCap = ErrorHandling ? ERROR_HANDLING : NO_ERROR_HANDLING; @@ -54,11 +54,10 @@ module eth_tb logic s_clk_125MHz_0; logic s_clk_125MHz_90; logic s_rst_n; - logic done = 0; logic error_found = 0; - logic [REG_BUS_DW-1:0] tx_req_ready, tx_rsp_valid; - logic [REG_BUS_DW-1:0] rx_req_ready, rx_rsp_valid; + logic [RegBusDw-1:0] tx_req_ready, tx_rsp_valid; + logic [RegBusAw-1:0] rx_req_ready, rx_rsp_valid; logic eth_rxck; logic eth_rxctl; @@ -85,22 +84,22 @@ module eth_tb /// -------------------- REG Drivers ----------------------- typedef reg_test::reg_driver #( - .AW(REG_BUS_AW), - .DW(REG_BUS_DW), + .AW(RegBusAw), + .DW(RegBusDw), .TT(SYS_TT), .TA(SYS_TA) ) reg_bus_drv_t; REG_BUS #( - .DATA_WIDTH(REG_BUS_DW), - .ADDR_WIDTH(REG_BUS_AW) + .DATA_WIDTH(RegBusDw), + .ADDR_WIDTH(RegBusAw) ) reg_bus_tx ( .clk_i(s_clk) ); REG_BUS #( - .DATA_WIDTH(REG_BUS_DW), - .ADDR_WIDTH(REG_BUS_AW) + .DATA_WIDTH(RegBusDw), + .ADDR_WIDTH(RegBusAw) ) reg_bus_rx ( .clk_i(s_clk) ); @@ -281,24 +280,21 @@ module eth_tb // ------------------------ BEGINNING OF SIMULATION ------------------------ - initial begin - while (!done) begin - s_clk_125MHz_0 <= 1; - #(TCK125/2); - s_clk_125MHz_0 <= 0; - #(TCK125/2); - end - end + clk_rst_gen #( + .ClkPeriod ( TCK125 ), + .RstClkCycles ( 5 ) + ) i_clk_rst_125_gen ( + .clk_o ( s_clk_125MHz_0 ), + .rst_no ( ) + ); initial begin - while (!done) begin s_clk_125MHz_90 <= 0; #(TCK125/4); s_clk_125MHz_90 <= 1; #(TCK125/2); s_clk_125MHz_90 <= 0; #(TCK125/4); - end end initial begin From 7b6bf10c8f71fae7251e60d20762b0802ee1f88b Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Mon, 26 Feb 2024 18:37:16 +0100 Subject: [PATCH 12/12] clean up --- Bender.yml | 3 +- rtl/eth_idma_pkg.sv | 103 ----------------- rtl/eth_idma_wrap.sv | 231 +++++++++++++++++++++++---------------- rtl/eth_top.sv | 28 ++--- rtl/rgmii_soc.sv | 113 +------------------ target/sim/src/eth_tb.sv | 87 +++++++++------ 6 files changed, 204 insertions(+), 361 deletions(-) delete mode 100644 rtl/eth_idma_pkg.sv diff --git a/Bender.yml b/Bender.yml index 145ddc8..9126914 100644 --- a/Bender.yml +++ b/Bender.yml @@ -20,7 +20,7 @@ dependencies: common_verification : { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 } register_interface : { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 } - idma: { git: "git@github.com:pulp-platform/iDMA.git", rev: "a80fcac" } # branch: main + idma: { git: "git@github.com:pulp-platform/iDMA.git", rev: "v0.6.0-beta" } sources: # Source files grouped in levels. Files in level 0 have no dependencies on files in this @@ -44,7 +44,6 @@ sources: - rtl/ssio_ddr_in.sv # Level 2 - rtl/framing_top.sv - - rtl/eth_idma_pkg.sv - rtl/eth_top.sv - rtl/eth_idma_wrap.sv diff --git a/rtl/eth_idma_pkg.sv b/rtl/eth_idma_pkg.sv deleted file mode 100644 index 85d61b6..0000000 --- a/rtl/eth_idma_pkg.sv +++ /dev/null @@ -1,103 +0,0 @@ -// Copyright 2024 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Chaoqun Liang - -`include "axi_stream/assign.svh" -`include "axi_stream/typedef.svh" -`include "axi/typedef.svh" -`include "idma/typedef.svh" -`include "register_interface/typedef.svh" -`include "register_interface/assign.svh" - -package eth_idma_pkg; - - /// Ethernet reg typedefs - parameter int unsigned AwRegbus = 32; - localparam int unsigned DwRegbus = 32; - localparam int unsigned StrbWidth = DwRegbus/8; - - typedef logic [AwRegbus-1:0] reg_bus_addr_t; - typedef logic [DwRegbus-1:0] reg_bus_data_t; - typedef logic [StrbWidth-1:0] reg_bus_strb_t; - - `REG_BUS_TYPEDEF_ALL(reg_bus, reg_bus_addr_t, reg_bus_data_t, reg_bus_strb_t) - - parameter int unsigned DataWidth = 64; - parameter int unsigned AddrWidth = 32; - parameter int unsigned UserWidth = 1; - parameter int unsigned AxiIdWidth = 5; - parameter int unsigned TFLenWidth = 32; - - localparam int unsigned AxiStrbWidth = DataWidth / 8; - localparam int unsigned OffsetWidth = $clog2(StrbWidth); - - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [AxiIdWidth-1:0] id_t; - typedef logic [UserWidth-1:0] user_t; - typedef logic [AxiStrbWidth-1:0] strb_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [TFLenWidth-1:0] tf_len_t; - - /// AXI4+ATOP typedefs - `AXI_TYPEDEF_AW_CHAN_T(axi_aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(axi_w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(axi_b_chan_t, id_t, user_t) - - `AXI_TYPEDEF_AR_CHAN_T(axi_ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(axi_r_chan_t, data_t, id_t, user_t) - - `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_chan_t, axi_w_chan_t, axi_ar_chan_t) - `AXI_TYPEDEF_RESP_T(axi_rsp_t, axi_b_chan_t, axi_r_chan_t) - - /// AXI Stream typedefs - `IDMA_AXI_STREAM_TYPEDEF_S_CHAN_T(axis_t_chan_t, data_t, strb_t, strb_t, id_t, id_t, user_t) - `IDMA_AXI_STREAM_TYPEDEF_REQ_T(axi_stream_req_t, axis_t_chan_t) - `IDMA_AXI_STREAM_TYPEDEF_RSP_T(axi_stream_rsp_t) - - /// Meta Channel Widths - localparam int unsigned axi_aw_chan_width = axi_pkg::aw_width(AddrWidth, AxiIdWidth, UserWidth); - localparam int unsigned axi_ar_chan_width = axi_pkg::ar_width(AddrWidth, AxiIdWidth, UserWidth); - localparam int unsigned axis_t_chan_width = $bits(axis_t_chan_t); - - `IDMA_TYPEDEF_OPTIONS_T(options_t, id_t) - `IDMA_TYPEDEF_REQ_T(idma_req_t, tf_len_t, addr_t, options_t) - `IDMA_TYPEDEF_ERR_PAYLOAD_T(err_payload_t, addr_t) - `IDMA_TYPEDEF_RSP_T(idma_rsp_t, err_payload_t) - - function automatic int unsigned max_width(input int unsigned a, b); - return (a > b) ? a : b; - endfunction - - typedef struct packed { - axi_ar_chan_t ar_chan; - logic[max_width(axi_ar_chan_width, axis_t_chan_width)-axi_ar_chan_width:0] padding; - } axi_read_ar_chan_padded_t; - - typedef struct packed { - axis_t_chan_t t_chan; - logic[max_width(axi_ar_chan_width, axis_t_chan_width)-axis_t_chan_width:0] padding; - } axis_read_t_chan_padded_t; - - typedef union packed { - axi_read_ar_chan_padded_t axi; - axis_read_t_chan_padded_t axis; - } read_meta_channel_t; - - typedef struct packed { - axi_aw_chan_t aw_chan; - logic[max_width(axi_aw_chan_width, axis_t_chan_width)-axi_aw_chan_width:0] padding; - } axi_write_aw_chan_padded_t; - - typedef struct packed { - axis_t_chan_t t_chan; - logic[max_width(axi_aw_chan_width, axis_t_chan_width)-axis_t_chan_width:0] padding; - } axis_write_t_chan_padded_t; - - typedef union packed { - axi_write_aw_chan_padded_t axi; - axis_write_t_chan_padded_t axis; - } write_meta_channel_t; - -endpackage : eth_idma_pkg \ No newline at end of file diff --git a/rtl/eth_idma_wrap.sv b/rtl/eth_idma_wrap.sv index 0fe7271..e4f14b0 100644 --- a/rtl/eth_idma_wrap.sv +++ b/rtl/eth_idma_wrap.sv @@ -4,24 +4,21 @@ // // Chaoqun Liang -`include "axi/assign.svh" `include "axi/typedef.svh" -`include "axi_stream/assign.svh" -`include "axi_stream/typedef.svh" `include "idma/typedef.svh" -`include "register_interface/typedef.svh" -`include "register_interface/assign.svh" -`include "common_cells/registers.svh" -module eth_idma_wrap #( +module eth_idma_wrap + import eth_idma_reg_pkg::*; + import idma_pkg::*; + #( /// Data width - parameter int unsigned DataWidth = 32'd64, + parameter int unsigned DataWidth = 32'd32, /// Address width parameter int unsigned AddrWidth = 32'd32, - /// AXI User width + /// AXI User width parameter int unsigned UserWidth = 32'd1, - /// AXI ID width - parameter int unsigned AxiIdWidth = 32'd5, + /// AXI ID width + parameter int unsigned AxiIdWidth = 32'd1, /// Number of transaction that can be in-flight concurrently parameter int unsigned NumAxInFlight = 32'd3, /// The depth of the internal reorder buffer @@ -30,75 +27,62 @@ module eth_idma_wrap #( parameter int unsigned TFLenWidth = 32'd32, /// The depth of the memory system the backend is attached to parameter int unsigned MemSysDepth = 32'd0, - /// Should the `R`-`AW` coupling hardware be present? (recommended) - parameter bit RAWCouplingAvail = 1'b0, - /// Mask invalid data on the manager interface - parameter bit MaskInvalidData = 1'b1, - parameter bit CombinedShifter = 1'b1, + parameter bit CombinedShifter = 1'b1, /// hardware legalization present - parameter bit HardwareLegalizer = 1'b1, + parameter bit HardwareLegalizer = 1'b1, /// Reject zero-length transfers - parameter bit RejectZeroTransfers = 1'b1, - /// Enable error handling - parameter bit ErrorHandling = 1'b0, + parameter bit RejectZeroTransfers = 1'b1, /// CDC FIFO parameter int unsigned TxFifoLogDepth = 32'd8, parameter int unsigned RxFifoLogDepth = 32'd8, - /// Register bus - parameter type reg_req_t = eth_idma_pkg::reg_bus_req_t, - parameter type reg_rsp_t = eth_idma_pkg::reg_bus_rsp_t + /// AXI4+ATOP Request and Response channel type + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic, + /// Register Request and Response type + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic )( - input logic clk_i, - input logic rst_ni, - /// Ethernet Internal clocks - input logic eth_clk_i, - input logic eth_clk90_i, + input logic clk_i, + input logic rst_ni, + /// Etherent Internal clocks + input logic eth_clk_i, + input logic eth_clk90_i, /// Ethernet: 1000BASE-T RGMII - input logic phy_rx_clk_i, - input logic [3:0] phy_rxd_i, - input logic phy_rx_ctl_i, - output logic phy_tx_clk_o, - output logic [3:0] phy_txd_o, - output logic phy_tx_ctl_o, - output logic phy_resetn_o, - input logic phy_intn_i, - input logic phy_pme_i, + input logic phy_rx_clk_i, + input logic [3:0] phy_rxd_i, + input logic phy_rx_ctl_i, + output logic phy_tx_clk_o, + output logic [3:0] phy_txd_o, + output logic phy_tx_ctl_o, + output logic phy_resetn_o, + input logic phy_intn_i, + input logic phy_pme_i, /// Ethernet MDIO - input logic phy_mdio_i, - output logic phy_mdio_o, - output logic phy_mdio_oe, - output wire phy_mdc_o, + input logic phy_mdio_i, + output logic phy_mdio_o, + output logic phy_mdio_oe, + output logic phy_mdc_o, /// iDMA testmode - input logic testmode_i, - /// Error handler request - input idma_pkg::idma_eh_req_t idma_eh_req_i, - input logic eh_req_valid_i, - output logic eh_req_ready_o, - output eth_idma_pkg::axi_req_t axi_req_o, - input eth_idma_pkg::axi_rsp_t axi_rsp_i, - /// iDMA busy flags - output idma_pkg::idma_busy_t idma_busy_o, - /// REGBUS Configuration Interface - input reg_req_t reg_req_i, - output reg_rsp_t reg_rsp_o + input logic testmode_i, + /// iDMA AXI Interface + output axi_req_t axi_req_o, + input axi_rsp_t axi_rsp_i, + /// iDMA Busy Signal + output idma_busy_t idma_busy_o, + /// Register Configuration Interface + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o ); + localparam int unsigned RegAddrWidth = 8; + localparam int unsigned StrbWidth = DataWidth / 8; - import eth_idma_pkg::*; - import eth_idma_reg_pkg::*; - import idma_pkg::*; - - logic idma_req_valid, req_ready, idma_rsp_ready, rsp_valid; - - localparam idma_pkg::error_cap_e ErrorCap = ErrorHandling ? ERROR_HANDLING : NO_ERROR_HANDLING; - localparam int unsigned AW_REGBUS = 8; - - eth_idma_reg_pkg::eth_idma_reg2hw_t reg2hw; // Write - eth_idma_reg_pkg::eth_idma_hw2reg_t hw2reg; // Read + eth_idma_reg2hw_t reg2hw; // Write + eth_idma_hw2reg_t hw2reg; // Read eth_idma_reg_top #( .reg_req_t(reg_req_t), .reg_rsp_t(reg_rsp_t), - .AW(AW_REGBUS) + .AW(RegAddrWidth) ) i_regs ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -109,17 +93,80 @@ module eth_idma_wrap #( .devmode_i(1'b1) ); + /// Address type + typedef logic [AddrWidth-1:0] addr_t; + typedef logic [DataWidth-1:0] data_t; + typedef logic [StrbWidth-1:0] strb_t; + typedef logic [UserWidth-1:0] user_t; + typedef logic [AxiIdWidth-1:0] id_t; + typedef logic [TFLenWidth-1:0] tf_len_t; + + /// AXI typedefs + `AXI_TYPEDEF_AW_CHAN_T(axi_aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(axi_ar_chan_t, addr_t, id_t, user_t) + + /// AXI Stream typedefs + `IDMA_AXI_STREAM_TYPEDEF_S_CHAN_T(axis_t_chan_t, data_t, strb_t, strb_t, id_t, id_t, user_t) + `IDMA_AXI_STREAM_TYPEDEF_REQ_T(axi_stream_req_t, axis_t_chan_t) + `IDMA_AXI_STREAM_TYPEDEF_RSP_T(axi_stream_rsp_t) + + /// Meta Channel Widths + localparam int unsigned axi_aw_chan_width = axi_pkg::aw_width(AddrWidth, AxiIdWidth, UserWidth); + localparam int unsigned axi_ar_chan_width = axi_pkg::ar_width(AddrWidth, AxiIdWidth, UserWidth); + localparam int unsigned axis_t_chan_width = $bits(axis_t_chan_t); + + /// iDMA req and rsp typedefs + `IDMA_TYPEDEF_OPTIONS_T(options_t, id_t) + `IDMA_TYPEDEF_REQ_T(idma_req_t, tf_len_t, addr_t, options_t) + `IDMA_TYPEDEF_ERR_PAYLOAD_T(err_payload_t, addr_t) + `IDMA_TYPEDEF_RSP_T(idma_rsp_t, err_payload_t) + function int unsigned max_width(input int unsigned a, b); + return (a > b) ? a : b; + endfunction + + typedef struct packed { + axi_ar_chan_t ar_chan; + logic[max_width(axi_ar_chan_width, axis_t_chan_width)-axi_ar_chan_width:0] padding; + } axi_read_ar_chan_padded_t; + + typedef struct packed { + axis_t_chan_t t_chan; + logic[max_width(axi_ar_chan_width, axis_t_chan_width)-axis_t_chan_width:0] padding; + } axis_read_t_chan_padded_t; + + typedef union packed { + axi_read_ar_chan_padded_t axi; + axis_read_t_chan_padded_t axis; + } read_meta_channel_t; + + typedef struct packed { + axi_aw_chan_t aw_chan; + logic[max_width(axi_aw_chan_width, axis_t_chan_width)-axi_aw_chan_width:0] padding; + } axi_write_aw_chan_padded_t; + + typedef struct packed { + axis_t_chan_t t_chan; + logic[max_width(axi_aw_chan_width, axis_t_chan_width)-axis_t_chan_width:0] padding; + } axis_write_t_chan_padded_t; + + typedef union packed { + axi_write_aw_chan_padded_t axi; + axis_write_t_chan_padded_t axis; + } write_meta_channel_t; + + logic idma_req_valid, idma_req_ready, idma_rsp_ready, idma_rsp_valid; + /// AXI request and response - eth_idma_pkg::axi_req_t axi_read_req,axi_write_req; - eth_idma_pkg::axi_rsp_t axi_read_rsp,axi_write_rsp; + axi_req_t axi_read_req,axi_write_req; + axi_rsp_t axi_read_rsp,axi_write_rsp; /// AXI Stream request and response - axi_stream_rsp_t idma_axis_read_rsp, eth_axis_tx_rsp; + axi_stream_rsp_t idma_axis_read_rsp, eth_axis_tx_rsp; axi_stream_req_t idma_axis_read_req, eth_axis_tx_req; - axi_stream_req_t idma_axis_write_req, eth_axis_rx_rsp; axi_stream_rsp_t idma_axis_write_rsp, eth_axis_rx_req; + /// iDMA request and response idma_req_t idma_reg_req; idma_rsp_t idma_reg_rsp; @@ -127,9 +174,9 @@ module eth_idma_wrap #( assign idma_reg_req.src_addr = reg2hw.src_addr.q; assign idma_reg_req.dst_addr = reg2hw.dst_addr.q; - assign idma_reg_req.opt.src_protocol = protocol_e'(reg2hw.src_protocol.q); - assign idma_reg_req.opt.dst_protocol = protocol_e'(reg2hw.dst_protocol.q); - + assign idma_reg_req.opt.src_protocol = idma_pkg::protocol_e'(reg2hw.src_protocol.q); + assign idma_reg_req.opt.dst_protocol = idma_pkg::protocol_e'(reg2hw.dst_protocol.q); + assign idma_reg_req.opt.axi_id = reg2hw.axi_id.q; assign idma_reg_req.opt.src.burst = reg2hw.opt_src.burst.q; @@ -154,7 +201,7 @@ module eth_idma_wrap #( assign idma_reg_req.opt.beo.dst_reduce_len = reg2hw.beo.dst_reduce_len.q; assign idma_reg_req.opt.last = reg2hw.last.q; - /// idma start signals + assign idma_req_valid = reg2hw.req_valid.q; assign idma_rsp_ready = reg2hw.rsp_ready.q; @@ -167,14 +214,10 @@ module eth_idma_wrap #( .BufferDepth ( BufferDepth ), .NumAxInFlight ( NumAxInFlight ), .MemSysDepth ( MemSysDepth ), - .RAWCouplingAvail ( RAWCouplingAvail ), - .MaskInvalidData ( MaskInvalidData ), .HardwareLegalizer ( HardwareLegalizer ), .RejectZeroTransfers ( RejectZeroTransfers ), - .ErrorCap ( ErrorCap ), - .idma_req_t ( idma_req_t ), + .idma_req_t ( idma_req_t ), .idma_rsp_t ( idma_rsp_t ), - .idma_eh_req_t ( idma_eh_req_t ), .idma_busy_t ( idma_busy_t ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ), @@ -187,33 +230,27 @@ module eth_idma_wrap #( .rst_ni ( rst_ni ), .testmode_i ( testmode_i ), .idma_req_i ( idma_reg_req ), - .req_valid_i ( idma_req_valid ), - .req_ready_o ( req_ready ), + .req_valid_i ( idma_req_valid ), + .req_ready_o ( idma_req_ready ), .idma_rsp_o ( idma_reg_rsp ), - .rsp_valid_o ( rsp_valid ), + .rsp_valid_o ( idma_rsp_valid ), .rsp_ready_i ( idma_rsp_ready ), - .idma_eh_req_i ( idma_eh_req_i ), - .eh_req_valid_i ( eh_req_valid_i ), - .eh_req_ready_o ( eh_req_ready_o ), .axi_write_req_o ( axi_write_req ), .axi_write_rsp_i ( axi_write_rsp ), .axi_read_req_o ( axi_read_req ), .axi_read_rsp_i ( axi_read_rsp ), .axis_read_req_i ( idma_axis_read_req ), - .axis_read_rsp_o ( idma_axis_read_rsp ), - .axis_write_req_o ( idma_axis_write_req ), + .axis_read_rsp_o ( idma_axis_read_rsp ), + .axis_write_req_o ( idma_axis_write_req ), .axis_write_rsp_i ( idma_axis_write_rsp ), .busy_o ( idma_busy_o ) ); eth_top #( + .DataWidth ( DataWidth ), + .RegAddrWidth ( RegAddrWidth ), .axi_stream_req_t ( axi_stream_req_t ), .axi_stream_rsp_t ( axi_stream_rsp_t ), - .DataWidth ( DataWidth ), - .IdWidth ( 32'd0 ), - .DestWidth ( 32'd0 ), - .UserWidth ( 32'd1 ), - .AW_REGBUS ( AW_REGBUS ), .reg2hw_itf_t ( eth_idma_reg2hw_t ), .hw2reg_itf_t ( eth_idma_hw2reg_t ) ) i_eth_top ( @@ -232,13 +269,13 @@ module eth_idma_wrap #( .phy_mdio_i ( phy_mdio_i ), .phy_mdio_o ( phy_mdio_o ), .phy_mdio_oe ( phy_mdio_oe ), - .phy_mdc ( phy_mdc ), - .tx_axis_req_i ( eth_axis_tx_req ), + .phy_mdc ( phy_mdc ), + .tx_axis_req_i ( eth_axis_tx_req ), .tx_axis_rsp_o ( eth_axis_tx_rsp ), .rx_axis_req_o ( eth_axis_rx_rsp ), .rx_axis_rsp_i ( eth_axis_rx_req ), - .idma_req_ready ( req_ready ), - .idma_rsp_valid ( rsp_valid ), + .idma_req_ready ( idma_req_ready ), + .idma_rsp_valid ( idma_rsp_valid ), .reg2hw_i ( reg2hw ), .hw2reg_o ( hw2reg ) ); @@ -278,8 +315,8 @@ module eth_idma_wrap #( ); axi_rw_join #( - .axi_req_t ( eth_idma_pkg::axi_req_t ), - .axi_resp_t ( eth_idma_pkg::axi_rsp_t ) + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_rsp_t ) ) i_axi_tx_rw_join ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), diff --git a/rtl/eth_top.sv b/rtl/eth_top.sv index 7a4c5ae..991c3b6 100644 --- a/rtl/eth_top.sv +++ b/rtl/eth_top.sv @@ -4,6 +4,7 @@ // // Authors: // - Thiemo Zaugg +// - chaoqun Liang `include "axi_stream/assign.svh" `include "axi_stream/typedef.svh" @@ -11,24 +12,23 @@ `include "register_interface/assign.svh" module eth_top #( - /// AXI Stream in request struct - parameter type axi_stream_req_t = eth_idma_pkg::axi_stream_req_t, - /// AXI Stream in response struct - parameter type axi_stream_rsp_t = eth_idma_pkg::axi_stream_rsp_t, /// AXI Stream Data Width - parameter int unsigned DataWidth = 64, + parameter int unsigned DataWidth = 64, /// AXI Stream Id Width - parameter int unsigned IdWidth = 0, + parameter int unsigned IdWidth = 0, /// AXI Stream Dest Width = 0 - parameter int unsigned DestWidth = 0, + parameter int unsigned DestWidth = 0, /// AXI Stream User Width - parameter int unsigned UserWidth = 1, + parameter int unsigned UserWidth = 1, + /// Register address width + parameter int unsigned RegAddrWidth = 4, + /// AXI Stream in request struct + parameter type axi_stream_req_t = logic, + /// AXI Stream in response struct + parameter type axi_stream_rsp_t = logic, /// REGBUS - //parameter type reg2hw_itf_t = eth_idma_reg_pkg::eth_idma_reg2hw_t, - //parameter type hw2reg_itf_t = eth_idma_reg_pkg::eth_idma_hw2reg_t, - parameter type reg2hw_itf_t = logic, - parameter type hw2reg_itf_t = logic, - parameter int AW_REGBUS = 4 + parameter type reg2hw_itf_t = logic, + parameter type hw2reg_itf_t = logic ) ( // Internal 125 MHz clock input wire clk_i, @@ -89,7 +89,7 @@ module eth_top #( .axi_stream_rsp_t ( s_framing_rsp_t ), .reg2hw_itf_t ( reg2hw_itf_t ), .hw2reg_itf_t ( hw2reg_itf_t ), - .AW_REGBUS ( AW_REGBUS ) + .AW_REGBUS ( RegAddrWidth ) ) i_framing_top ( .rst_ni ( rst_ni ), .clk_i ( clk_i ), diff --git a/rtl/rgmii_soc.sv b/rtl/rgmii_soc.sv index 01e74f1..8c9688a 100644 --- a/rtl/rgmii_soc.sv +++ b/rtl/rgmii_soc.sv @@ -35,8 +35,6 @@ module rgmii_soc ( input clk_int, input rst_int, input clk90_int, - input clk_200_int, - /* * Ethernet: 1000BASE-T RGMII */ @@ -81,116 +79,9 @@ module rgmii_soc ( wire [3:0] phy_rxd_delay; wire phy_rx_ctl_delay; -`ifdef GENESYSII - -IDELAYCTRL -idelayctrl_inst -( - .REFCLK(clk_200_int), - .RST(rst_int), - .RDY() -); - -IDELAYE2 #( - .IDELAY_TYPE("FIXED") -) -phy_rxd_idelay_0 -( - .IDATAIN(phy_rxd[0]), - .DATAOUT(phy_rxd_delay[0]), - .DATAIN(1'b0), - .C(1'b0), - .CE(1'b0), - .INC(1'b0), - .CINVCTRL(1'b0), - .CNTVALUEIN(5'd0), - .CNTVALUEOUT(), - .LD(1'b0), - .LDPIPEEN(1'b0), - .REGRST(1'b0) -); - -IDELAYE2 #( - .IDELAY_TYPE("FIXED") -) -phy_rxd_idelay_1 -( - .IDATAIN(phy_rxd[1]), - .DATAOUT(phy_rxd_delay[1]), - .DATAIN(1'b0), - .C(1'b0), - .CE(1'b0), - .INC(1'b0), - .CINVCTRL(1'b0), - .CNTVALUEIN(5'd0), - .CNTVALUEOUT(), - .LD(1'b0), - .LDPIPEEN(1'b0), - .REGRST(1'b0) -); - -IDELAYE2 #( - .IDELAY_TYPE("FIXED") -) -phy_rxd_idelay_2 -( - .IDATAIN(phy_rxd[2]), - .DATAOUT(phy_rxd_delay[2]), - .DATAIN(1'b0), - .C(1'b0), - .CE(1'b0), - .INC(1'b0), - .CINVCTRL(1'b0), - .CNTVALUEIN(5'd0), - .CNTVALUEOUT(), - .LD(1'b0), - .LDPIPEEN(1'b0), - .REGRST(1'b0) -); - -IDELAYE2 #( - .IDELAY_TYPE("FIXED") -) -phy_rxd_idelay_3 -( - .IDATAIN(phy_rxd[3]), - .DATAOUT(phy_rxd_delay[3]), - .DATAIN(1'b0), - .C(1'b0), - .CE(1'b0), - .INC(1'b0), - .CINVCTRL(1'b0), - .CNTVALUEIN(5'd0), - .CNTVALUEOUT(), - .LD(1'b0), - .LDPIPEEN(1'b0), - .REGRST(1'b0) -); - -IDELAYE2 #( - .IDELAY_VALUE(0), - .IDELAY_TYPE("FIXED") -) -phy_rx_ctl_idelay -( - .IDATAIN(phy_rx_ctl), - .DATAOUT(phy_rx_ctl_delay), - .DATAIN(1'b0), - .C(1'b0), - .CE(1'b0), - .INC(1'b0), - .CINVCTRL(1'b0), - .CNTVALUEIN(5'd0), - .CNTVALUEOUT(), - .LD(1'b0), - .LDPIPEEN(1'b0), - .REGRST(1'b0) -); +assign phy_rx_ctl_delay = phy_rx_ctl; +assign phy_rxd_delay = phy_rxd; -`else // !`ifdef GENESYSII - assign phy_rx_ctl_delay = phy_rx_ctl; - assign phy_rxd_delay = phy_rxd; -`endif rgmii_core core_inst ( diff --git a/target/sim/src/eth_tb.sv b/target/sim/src/eth_tb.sv index 878f550..4536384 100644 --- a/target/sim/src/eth_tb.sv +++ b/target/sim/src/eth_tb.sv @@ -33,7 +33,6 @@ module eth_tb ); import idma_pkg::*; - import eth_idma_pkg::*; import reg_test::*; /// timing parameters @@ -42,23 +41,46 @@ module eth_tb localparam time SYS_TA = 2ns; localparam time SYS_TT = 6ns; - /// regbus - localparam int unsigned RegBusDw = 32; - localparam int unsigned RegBusAw = 32; + /// Dependent parameters + localparam int unsigned StrbWidth = DataWidth / 8; + localparam int unsigned OffsetWidth = $clog2(StrbWidth); + + /// AXI4+ATOP typedefs + typedef logic [AddrWidth-1:0] addr_t; + typedef logic [AxiIdWidth-1:0] id_t; + typedef logic [UserWidth-1:0] user_t; + typedef logic [StrbWidth-1:0] strb_t; + typedef logic [DataWidth-1:0] data_t; + typedef logic [TFLenWidth-1:0] tf_len_t; + + `AXI_TYPEDEF_AW_CHAN_T(axi_aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(axi_w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(axi_b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(axi_ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(axi_r_chan_t, data_t, id_t, user_t) - /// parse error handling caps - localparam error_cap_e ErrorCap = ErrorHandling ? ERROR_HANDLING : NO_ERROR_HANDLING; + `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_chan_t, axi_w_chan_t, axi_ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_rsp_t, axi_b_chan_t, axi_r_chan_t) + + /// Register interface parameters + localparam int unsigned RegBusDw = 32; + localparam int unsigned RegBusAw = 32; + localparam int unsigned RegBusStrb = RegBusDw/8; + + /// Regsiter bus typedefs + typedef logic [RegBusAw-1:0] reg_bus_addr_t; + typedef logic [RegBusDw-1:0] reg_bus_data_t; + typedef logic [RegBusStrb-1:0] reg_bus_strb_t; + + `REG_BUS_TYPEDEF_ALL(reg_bus, reg_bus_addr_t, reg_bus_data_t, reg_bus_strb_t) - /// ethernet pads logic s_clk; logic s_clk_125MHz_0; logic s_clk_125MHz_90; logic s_rst_n; logic error_found = 0; - logic [RegBusDw-1:0] tx_req_ready, tx_rsp_valid; - logic [RegBusAw-1:0] rx_req_ready, rx_rsp_valid; - + /// ethernet pads logic eth_rxck; logic eth_rxctl; logic [3:0] eth_rxd; @@ -67,6 +89,9 @@ module eth_tb logic [3:0] eth_txd; logic eth_tx_rstn, eth_rx_rstn; + logic [RegBusDw-1:0] tx_req_ready, tx_rsp_valid; + logic [RegBusAw-1:0] rx_req_ready, rx_rsp_valid; + logic tx_idma_req_valid, tx_idma_req_ready, tx_idma_rsp_valid, tx_idma_rsp_ready; logic rx_idma_req_valid, rx_idma_req_ready, rx_idma_rsp_valid, rx_idma_rsp_ready; @@ -74,11 +99,6 @@ module eth_tb axi_req_t axi_tx_req_mem, axi_rx_req_mem; axi_rsp_t axi_tx_rsp_mem, axi_rx_rsp_mem; - /// error handler - idma_eh_req_t idma_eh_req; - logic eh_req_valid; - logic eh_req_ready; - /// busy signal idma_busy_t tx_busy, rx_busy; @@ -194,7 +214,7 @@ module eth_tb ); eth_idma_wrap#( - .DataWidth ( DataWidth ), + .DataWidth ( DataWidth ), .AddrWidth ( AddrWidth ), .UserWidth ( UserWidth ), .AxiIdWidth ( AxiIdWidth ), @@ -202,12 +222,15 @@ module eth_tb .BufferDepth ( BufferDepth ), .TFLenWidth ( TFLenWidth ), .MemSysDepth ( MemSysDepth ), - .RAWCouplingAvail ( RAWCouplingAvail ), - .HardwareLegalizer ( HardwareLegalizer ), - .RejectZeroTransfers ( RejectZeroTransfers ) + .RejectZeroTransfers ( RejectZeroTransfers ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ), + .reg_req_t ( reg_bus_req_t ), + .reg_rsp_t ( reg_bus_rsp_t ) ) i_tx_eth_idma_wrap ( .clk_i ( s_clk ), .rst_ni ( s_rst_n ), + /// Ethernet Internal clocks .eth_clk_i ( s_clk_125MHz_0 ), // 125MHz in-phase .eth_clk90_i ( s_clk_125MHz_90 ), // 125 MHz with 90 phase shift .phy_rx_clk_i ( eth_rxck ), @@ -216,7 +239,7 @@ module eth_tb .phy_tx_clk_o ( eth_txck ), .phy_txd_o ( eth_txd ), .phy_tx_ctl_o ( eth_txctl ), - .phy_resetn_o ( eth_tx_rstn ), + .phy_resetn_o ( eth_tx_rstn ), .phy_intn_i ( 1'b1 ), .phy_pme_i ( 1'b1 ), .phy_mdio_i ( 1'b0 ), @@ -226,9 +249,6 @@ module eth_tb .reg_req_i ( reg_bus_tx_req ), .reg_rsp_o ( reg_bus_tx_rsp ), .testmode_i ( 1'b0 ), - .idma_eh_req_i ( idma_eh_req ), // error handling disabled now - .eh_req_valid_i ( eh_req_valid ), - .eh_req_ready_o ( eh_req_ready ), .axi_req_o ( axi_tx_req_mem ), .axi_rsp_i ( axi_tx_rsp_mem ), .idma_busy_o ( tx_busy ) @@ -238,7 +258,7 @@ module eth_tb reg_bus_rsp_t rx_reg_idma_rsp, tx_reg_idma_rsp; eth_idma_wrap #( - .DataWidth ( DataWidth ), + .DataWidth ( DataWidth ), .AddrWidth ( AddrWidth ), .UserWidth ( UserWidth ), .AxiIdWidth ( AxiIdWidth ), @@ -246,9 +266,11 @@ module eth_tb .BufferDepth ( BufferDepth ), .TFLenWidth ( TFLenWidth ), .MemSysDepth ( MemSysDepth ), - .RAWCouplingAvail ( RAWCouplingAvail ), - .HardwareLegalizer ( HardwareLegalizer ), - .RejectZeroTransfers ( RejectZeroTransfers ) + .RejectZeroTransfers ( RejectZeroTransfers ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ), + .reg_req_t ( reg_bus_req_t ), + .reg_rsp_t ( reg_bus_rsp_t ) )i_rx_eth_idma_wrap ( .clk_i ( s_clk ), .rst_ni ( s_rst_n ), @@ -260,19 +282,16 @@ module eth_tb .phy_tx_clk_o ( eth_rxck ), .phy_txd_o ( eth_rxd ), .phy_tx_ctl_o ( eth_rxctl ), - .phy_resetn_o ( eth_rx_rstn ), + .phy_resetn_o ( eth_rx_rstn ), .phy_intn_i ( 1'b1 ), .phy_pme_i ( 1'b1 ), .phy_mdio_i ( 1'b0 ), - .phy_mdio_o ( ), - .phy_mdio_oe ( ), - .phy_mdc_o ( ), + .phy_mdio_o ( ), + .phy_mdio_oe ( ), + .phy_mdc_o ( ), .reg_req_i ( reg_bus_rx_req ), .reg_rsp_o ( reg_bus_rx_rsp ), .testmode_i ( 1'b0 ), - .idma_eh_req_i ( ), // error handling disabled now - .eh_req_valid_i ( ), - .eh_req_ready_o ( ), .axi_req_o ( axi_rx_req_mem ), .axi_rsp_i ( axi_rx_rsp_mem ), .idma_busy_o ( rx_busy )