[HW]: Add mem_multibanked_pwrgate for correct power management #296
reviewdog [verible-verilog-lint] report
reported by reviewdog 🐶
Findings (7)
src/mem_multibank_pwrgate.sv|24 col 101| Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
src/mem_multibank_pwrgate.sv|26 col 28| Explicitly define a storage type for every parameter and localparam, (SimInit). [Style: constants] [explicit-parameter-storage-type]
src/mem_multibank_pwrgate.sv|28 col 28| Explicitly define a storage type for every parameter and localparam, (ImplKey). [Style: constants] [explicit-parameter-storage-type]
src/mem_multibank_pwrgate.sv|133 col 19| Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
src/mem_multibank_pwrgate.sv|136 col 22| Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
src/mem_multibank_pwrgate.sv|146 col 66| All generate block statements must have a label [Style: generate-statements] [generate-label]
src/mem_multibank_pwrgate.sv|151 col 101| Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]
Filtered Findings (0)
Annotations
Check warning on line 24 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L24
Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:24 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 26 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L26
Explicitly define a storage type for every parameter and localparam, (SimInit). [Style: constants] [explicit-parameter-storage-type]
Raw output
message:"Explicitly define a storage type for every parameter and localparam, (SimInit). [Style: constants] [explicit-parameter-storage-type]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:26 column:28}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 28 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L28
Explicitly define a storage type for every parameter and localparam, (ImplKey). [Style: constants] [explicit-parameter-storage-type]
Raw output
message:"Explicitly define a storage type for every parameter and localparam, (ImplKey). [Style: constants] [explicit-parameter-storage-type]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:28 column:28}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 133 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L133
Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
Raw output
message:"Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:133 column:19}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 136 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L136
Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
Raw output
message:"Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:136 column:22}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 146 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L146
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:146 column:66}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 151 in src/mem_multibank_pwrgate.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L151
Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]" location:{path:"./src/mem_multibank_pwrgate.sv" range:{start:{line:151 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}