diff --git a/src/cdc_2phase.sv b/src/cdc_2phase.sv
index e1a67b44..cf020567 100644
--- a/src/cdc_2phase.sv
+++ b/src/cdc_2phase.sv
@@ -111,7 +111,7 @@ module cdc_2phase_src #(
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       req_src_q  <= 0;
-      data_src_q <= '0;
+      data_src_q <= T'('0);
     end else if (valid_i && ready_o) begin
       req_src_q  <= ~req_src_q;
       data_src_q <= data_i;
@@ -171,7 +171,7 @@ module cdc_2phase_dst #(
   // indicated by the async_req line changing levels.
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
-      data_dst_q <= '0;
+      data_dst_q <= T'('0);
     end else if (req_q0 != req_q1 && !valid_o) begin
       data_dst_q <= async_data_i;
     end
diff --git a/src/cdc_fifo_2phase.sv b/src/cdc_fifo_2phase.sv
index 87332d1f..d482283a 100644
--- a/src/cdc_fifo_2phase.sv
+++ b/src/cdc_fifo_2phase.sv
@@ -90,7 +90,7 @@ module cdc_fifo_2phase #(
   for (genvar i = 0; i < 2**LOG_DEPTH; i++) begin : g_word
     always_ff @(posedge src_clk_i, negedge src_rst_ni) begin
       if (!src_rst_ni)
-        fifo_data_q[i] <= '0;
+        fifo_data_q[i] <= T'('0);
       else if (fifo_write && fifo_widx == i)
         fifo_data_q[i] <= fifo_wdata;
     end
diff --git a/src/fifo_v3.sv b/src/fifo_v3.sv
index a1b61180..83df3b23 100644
--- a/src/fifo_v3.sv
+++ b/src/fifo_v3.sv
@@ -131,7 +131,7 @@ module fifo_v3 #(
 
     always_ff @(posedge clk_i or negedge rst_ni) begin
         if(~rst_ni) begin
-            mem_q <= '0;
+            mem_q <= {FifoDepth{dtype'('0)}};
         end else if (!gate_clock) begin
             mem_q <= mem_n;
         end
diff --git a/src/lossy_valid_to_stream.sv b/src/lossy_valid_to_stream.sv
index 68dad552..8e172dd7 100644
--- a/src/lossy_valid_to_stream.sv
+++ b/src/lossy_valid_to_stream.sv
@@ -125,7 +125,7 @@ module lossy_valid_to_stream #(
       read_ptr_q           <= '0;
       write_ptr_q          <= '0;
       pending_tx_counter_q <= '0;
-      mem_q                <= '0;
+      mem_q                <= {2{T'('0)}};
     end else begin
       read_ptr_q           <= read_ptr_d;
       write_ptr_q          <= write_ptr_d;
diff --git a/src/shift_reg_gated.sv b/src/shift_reg_gated.sv
index 6a9657f1..0037f8b7 100644
--- a/src/shift_reg_gated.sv
+++ b/src/shift_reg_gated.sv
@@ -53,7 +53,7 @@ module shift_reg_gated #(
 
       // Gate each shift register with a valid flag to enable the synthsis tools to insert ICG for
       // better power comsumption.
-      `FFL(data_q[i], data_d[i], valid_d[i], '0, clk_i, rst_ni)
+      `FFL(data_q[i], data_d[i], valid_d[i], T'('0), clk_i, rst_ni)
     end
 
     // Output the shifted result.
diff --git a/src/spill_register_flushable.sv b/src/spill_register_flushable.sv
index 8588a43a..cea3fc88 100644
--- a/src/spill_register_flushable.sv
+++ b/src/spill_register_flushable.sv
@@ -41,7 +41,7 @@ module spill_register_flushable #(
 
     always_ff @(posedge clk_i or negedge rst_ni) begin : ps_a_data
       if (!rst_ni)
-        a_data_q <= '0;
+        a_data_q <= T'('0);
       else if (a_fill)
         a_data_q <= data_i;
     end
@@ -60,7 +60,7 @@ module spill_register_flushable #(
 
     always_ff @(posedge clk_i or negedge rst_ni) begin : ps_b_data
       if (!rst_ni)
-        b_data_q <= '0;
+        b_data_q <= T'('0);
       else if (b_fill)
         b_data_q <= a_data_q;
     end
diff --git a/src/stream_register.sv b/src/stream_register.sv
index d2c1571f..247ef34c 100644
--- a/src/stream_register.sv
+++ b/src/stream_register.sv
@@ -34,7 +34,7 @@ module stream_register #(
     assign ready_o = ready_i | ~valid_o;
     assign reg_ena = valid_i & ready_o;
     // Load-enable FFs with synch clear
-    `FFLARNC(valid_o, valid_i, ready_o, clr_i, 1'b0, clk_i, rst_ni)
-    `FFLARNC(data_o,   data_i, reg_ena, clr_i,   '0, clk_i, rst_ni)
+    `FFLARNC(valid_o, valid_i, ready_o, clr_i, 1'b0  , clk_i, rst_ni)
+    `FFLARNC(data_o,   data_i, reg_ena, clr_i, T'('0), clk_i, rst_ni)
 
 endmodule