diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 21b7a01..a086edc 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -55,6 +55,9 @@ tests:
         PARAM1: [-GN=1, -GN=2, -GN=3, -GN=4, -GN=8, -GN=16]
       - TOPLEVEL: fifo_tb
         PARAM1: [-GDEPTH=1, -GDEPTH=13, -GDEPTH=32 -GFALL_THROUGH=1]
+      - TOPLEVEL: mem_multibank_pwrgate_tb
+        PARAM1: [-gNumLogicBanks=1, -gNumLogicBanks=2, -gNumLogicBanks=4, -gNumLogicBanks=8]
+        PARAM2: [-gLatency=0, -gLatency=1, -gLatency=2]
       # - TOPLEVEL: [cdc_2phase_tb, cdc_2phase_clearable_tb]
       #   PARAM1: -GUNTIL=1000000
       # - TOPLEVEL: cdc_fifo_tb
diff --git a/test/mem_multibank_pwrgate_tb.sv b/test/mem_multibank_pwrgate_tb.sv
index f48ef6e..5266e7b 100644
--- a/test/mem_multibank_pwrgate_tb.sv
+++ b/test/mem_multibank_pwrgate_tb.sv
@@ -14,7 +14,7 @@
 //    Test to address the multibanked powergated SRAM and checlk correct address handling.
 
 module mem_multibank_pwrgate_tb #(
-    parameter int unsigned NumPorts      = 32'd2,
+    parameter int unsigned NumPorts      = 32'd1,
     parameter int unsigned Latency       = 32'd1,
     parameter int unsigned NumWords      = 32'd1024,
     parameter int unsigned DataWidth     = 32'd64,