[TB] Fast Preload of binary for fast debug #57
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In the existing testbench the binary preload takes a lot of time due to JTAG load. A fast preload of binary is done by forcing the relevant signals in the narrow interconnect of the memory island. The method still relies on JTAG to halt and unhalt the core whereas the preload(significant portion) is done through forcing the relevant memory signals.
Scheremo
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Dec 12, 2024
target/sim/src/tb_chimera_soc.sv
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| static doub_bt write_address; | ||
| static doub_bt write_data; | ||
| write_address = addr; | ||
| write_data = data; |
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Could this be automatic or not decorated instead of static
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Using automatic variable leads to compilation error that it is not allowed in the force statement.
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Scheremo
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Dec 12, 2024
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In the existing testbench the binary preload takes a lot of time due to JTAG load. A fast preload of binary is done by forcing the relevant signals in the narrow interconnect of the memory island. The method still relies on JTAG to halt and unhalt the core whereas the preload(significant portion) is done through forcing the relevant memory signals.