Reduce idle_cyles to speed up simulation time

pulp-platform · Nov 6, 2024 · 9e3ccae · 9e3ccae
1 parent 5f5a5a5
commit 9e3ccae
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/target/sim/src/vip_chimera_soc.sv b/target/sim/src/vip_chimera_soc.sv
@@ -22,7 +22,7 @@ module vip_chimera_soc
   // Timing
   parameter time         ClkPeriodClu           = 2ns,
   parameter time         ClkPeriodSys           = 5ns,
-  parameter time         ClkPeriodJtag          = 100ns,
+  parameter time         ClkPeriodJtag          = 20ns,
   parameter time         ClkPeriodRtc           = 30518ns,
   parameter int unsigned RstCycles              = 5,
   parameter real         TAppl                  = 0.1,
@@ -329,7 +329,7 @@ module vip_chimera_soc
 
   // Wait for termination signal and get return code
   task automatic jtag_wait_for_eoc(output word_bt exit_code);
-    jtag_poll_bit0(AmRegs + cheshire_reg_pkg::CHESHIRE_SCRATCH_2_OFFSET, exit_code, 8000);
+    jtag_poll_bit0(AmRegs + cheshire_reg_pkg::CHESHIRE_SCRATCH_2_OFFSET, exit_code, 4000);
     exit_code >>= 1;
     if (exit_code) $error("[JTAG] FAILED: return code %0d", exit_code);
     else $display("[JTAG] SUCCESS");