update ethernet deps

pulp-platform · Dec 9, 2024 · fbdd67d · fbdd67d
1 parent fd98482
commit fbdd67d
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Showing 5 changed files with 31 additions and 18 deletions.
diff --git a/Bender.lock b/Bender.lock
@@ -15,8 +15,8 @@ packages:
     - apb
     - register_interface
   axi:
-    revision: 853ede23b2a9837951b74dbdc6d18c3eef5bac7d
-    version: 0.39.5
+    revision: 39f5f2d51c5e524f6fc5cf8b6e901f7dcc5622d7
+    version: 0.39.6
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
@@ -93,8 +93,8 @@ packages:
     - common_verification
     - tech_cells_generic
   common_verification:
-    revision: 9c07fa860593b2caabd9b5681740c25fac04b878
-    version: 0.2.3
+    revision: fa2630f61666f61d9d78451c4d8b4d1ea403944e
+    version: 0.2.4
     source:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
@@ -162,7 +162,7 @@ packages:
     - register_interface
     - tech_cells_generic
   pulp-ethernet:
-    revision: e6e4c8eb7a1dc739492818e45b7ef8196e345b0c
+    revision: a80c246da972dabd7cd4fb6ec5ac8c83e613f0a3
     version: null
     source:
       Git: https://github.com/pulp-platform/pulp-ethernet.git

diff --git a/Bender.yml b/Bender.yml
@@ -30,7 +30,7 @@ dependencies:
   riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              version: 0.8.1  }
   serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.1  }
   unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.6  }
-  pulp-ethernet:            { git: "https://github.com/pulp-platform/pulp-ethernet.git",          rev: "e6e4c8e"  } # branch: chs-hs
+  pulp-ethernet:            { git: "https://github.com/pulp-platform/pulp-ethernet.git",          rev: "a80c246"  } # branch: chs-hs
 
 export_include_dirs:
   - hw/include

diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
@@ -1301,6 +1301,7 @@ module cheshire_soc import cheshire_pkg::*; #(
   //  ETHERNET  //
   ////////////////
   if (Cfg.Ethernet) begin : gen_ethernet
+    logic eth_rx_irq, eth_rx_irq_o;
     eth_idma_wrap#(
       .DataWidth           ( Cfg.AxiDataWidth  ),
       .AddrWidth           ( Cfg.AddrWidth     ),
@@ -1340,9 +1341,22 @@ module cheshire_soc import cheshire_pkg::*; #(
       .axi_rsp_i           ( axi_in_rsp[AxiIn.eth]        ),
       .reg_req_i           ( reg_out_req[RegOut.ethernet] ),
       .reg_rsp_o           ( reg_out_rsp[RegOut.ethernet] ),
-      .eth_rx_irq_o        ( intr.intn.ethernet           )
+      .eth_rx_irq_o        ( eth_rx_irq                   )
     );
 
+    // interrupt sync
+    sync #(
+      .STAGES     ( 32'd3      ),
+      .ResetValue ( 1'b0       )
+    ) i_rx_irq_sync (
+      .clk_i,
+      .rst_ni   ( rst_ni        ),
+      .serial_i ( eth_rx_irq    ),
+      .serial_o ( eth_rx_irq_o  )
+    );
+
+    assign intr.intn.ethernet = eth_rx_irq_o;
+
   end else begin : gen_no_ethernet
       assign intr.intn.ethernet = 1'b0;
       assign eth_txck_o  = 1'b0;

diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c
@@ -8,7 +8,7 @@
 
 #define MACLO_OFFSET                 0x0
 #define MACHI_OFFSET                 0x4
-#define IRQ_OFFSET                   0x18
+#define ETH_IDMA_RSR_OFFSET          0x18
 #define IDMA_SRC_ADDR_OFFSET         0x1c
 #define IDMA_DST_ADDR_OFFSET         0x20
 #define IDMA_LENGTH_OFFSET           0x24
@@ -18,7 +18,6 @@
 #define IDMA_REQ_READY_OFFSET        0x48
 #define IDMA_RSP_READY_OFFSET        0x4c
 #define IDMA_RSP_VALID_OFFSET        0x50
-#define IDMA_RX_EN_OFFSET            0x54
 #define ETH_MDIO_OFFSET              0x8
 
 #define PLIC_BASE                    0x04000000
@@ -91,8 +90,10 @@ int main(void) {
   *reg32(ETH_BASE, MACHI_OFFSET)          = 0x00800207;
   // rx irq
   while (!((*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ));
-  // dma length ready, dma can be configured now
-  while (!(*reg32(ETH_BASE,IDMA_RX_EN_OFFSET)));
+
+  uint32_t *rx_length;
+  rx_length = 0x0300c024;
+  printf("rx length value: 0x%08X\n", *rx_length);
 
   *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET)  = 0x0;
   *reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET)  = RX_BASE;
@@ -105,6 +106,8 @@ int main(void) {
   // wait until DMA moves all data
   while (!(*reg32(ETH_BASE, IDMA_RSP_VALID_OFFSET)));
 
+  *reg32(ETH_BASE, ETH_IDMA_RSR_OFFSET)  = 0x2;
+
   volatile uint32_t error = 0;
 
   for (int i = 0; i < DATA_CHUNK; ++i) {

diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv
@@ -736,13 +736,6 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
 
     @(posedge eth_rx_irq);
 
-    while(1) begin
-      reg_drv_rx.send_read( 'h0300c054, dma_en, reg_error);   // req ready with packet length
-      if( dma_en )
-        break;
-      @(posedge clk);
-    end
-
     reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR
     @(posedge clk);
 
@@ -770,6 +763,9 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
       @(posedge clk);
     end
 
+    reg_drv_rx.send_write( 'h0300c018, 32'h2, 'hf, reg_error ); // to clear rx_complete, thus to clear rx_irq once all data is processed.
+    @(posedge clk)
+
     // Tx test starts here: external back to core
     reg_drv_rx.send_write( 'h0300c000, 32'h89000123, 'hf, reg_error); //lower 32bits of MAC address
     @(posedge clk);