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add testbench check memory format
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@fhaus1
fhaus1 committed Dec 11, 2024
1 parent cfab0ae commit 67b099f
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Showing 3 changed files with 16 additions and 12 deletions.
6 changes: 3 additions & 3 deletions hw/newusb_tb/tb_new_usb.mem
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Expand Up @@ -6,13 +6,13 @@
//
/// Address memory map for the testbench. The system has byte-addressable memory.
/// All descriptors are 16-byte aligned, except isochronous TDs are 32-byte aligned.
/// All values are in hexadecimal and will be stored LsB first.
/// All values are in hexadecimal and will be stored LsB first by the testbench.
/// Isochrounous TDs need to be loaded in two separate lines.
/// Use the python script to generate connected EDs and TDs linked lists
/// and insert them down below.
///
/// Format: @Address dword0 dword1 dword2 dword3
/// Size: (Address AxiAddrWidth) (dword 32bit)

@0000A000 0000000A 0000000B 0000000C 0000000D
@0000ABCD 00000001 00000002 00000003 00000004
@0000A000 0000000D 0000000C 0000000B 0000000A
@0000ABC0 00000004 00000003 00000002 00000001
16 changes: 9 additions & 7 deletions hw/newusb_tb/tb_new_usb.sv
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Expand Up @@ -40,7 +40,7 @@ module tb_new_usb #(
logic [31:0] dword [3:0];

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/newusb_tb/tb_new_usb.sv#L40 

Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]
Raw output 
message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]"  location:{path:"hw/newusb_tb/tb_new_usb.sv"  range:{start:{line:40  column:23}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
reg [7:0] mem [logic [AxiAddrWidth-1:0]];
integer file, status, i, j;
string line;
string line, rest;

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[verible-verilog-lint] hw/newusb_tb/tb_new_usb.sv#L44 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/newusb_tb/tb_new_usb.sv"  range:{start:{line:44  column:1}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:44  column:1}  end:{line:46}}  text:"\n\n"}
initial begin

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[verible-verilog-lint] hw/newusb_tb/tb_new_usb.sv#L46 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/newusb_tb/tb_new_usb.sv"  range:{start:{line:46  column:1}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
Expand All @@ -60,29 +60,31 @@ module tb_new_usb #(
continue;
end
// Try to parse the address and data
status = $sscanf(line, "@%h %h %h %h %h", address, dword[0], dword[1], dword[2], dword[3]);

if (status == 5) begin // Successfully read 5 values
status = $sscanf(line, "@%h %h %h %h %h%s", address, dword[0], dword[1], dword[2], dword[3], rest);

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/newusb_tb/tb_new_usb.sv#L63 

Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]"  location:{path:"hw/newusb_tb/tb_new_usb.sv"  range:{start:{line:63  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

if (status == 5) begin // Successfully read exactly 5 values
if ((address & 4'hF) != 0) begin
$display("Not 16 Byte aligned address in line: %s", line);
$stop;
end
for (i = 0; i < 4; i++) begin
mem[address + i * 4 + 0] = dword[i][7:0]; // LSB to lowest address
mem[address + i * 4 + 1] = dword[i][15:8];

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/newusb_tb/tb_new_usb.sv#L72 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/newusb_tb/tb_new_usb.sv"  range:{start:{line:72  column:61}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:72  column:61}  end:{line:74}}  text:"                  mem[address + i * 4 + 1] = dword[i][15:8];\n                  mem[address + i * 4 + 2] = dword[i][23:16];\n"}
mem[address + i * 4 + 2] = dword[i][23:16];

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/newusb_tb/tb_new_usb.sv#L73 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/newusb_tb/tb_new_usb.sv"  range:{start:{line:73  column:62}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
mem[address + i * 4 + 3] = dword[i][31:24]; // MSB to highest address
$display("Written into mem: @%h %h", address + i*4, dword[i]);
end
end
end
else begin
$display("Invalid data format in line: %s", line);
end

if ($feof(file)) begin
break;
end
end

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[verible-verilog-lint] hw/newusb_tb/tb_new_usb.sv#L85 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/newusb_tb/tb_new_usb.sv"  range:{start:{line:85  column:1}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:85  column:1}  end:{line:86}}  text:"\n"}
$fclose(file);
#1000;
$finish;
end

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/newusb_tb/tb_new_usb.sv#L89 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/newusb_tb/tb_new_usb.sv"  range:{start:{line:89  column:1}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:89  column:1}  end:{line:90}}  text:"\n"}
//axi_lite_to_axi #(
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6 changes: 4 additions & 2 deletions target/sim/vsim/start.newusb.tcl
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Expand Up @@ -6,7 +6,9 @@

set TESTBENCH tb_new_usb

set StdArithNoWarnings 1
set NumericStdNoWarnings 1

eval vsim -c ${TESTBENCH} -t 1ps -vopt -voptargs="+acc"

set StdArithNoWarnings 1
set NumericStdNoWarnings 1
run 1us

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