diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
index 29022c51..7fe9f342 100644
--- a/hw/cheshire_soc.sv
+++ b/hw/cheshire_soc.sv
@@ -1336,7 +1336,7 @@ module cheshire_soc import cheshire_pkg::*; #(
       .phy_mdio_o          ( eth_mdio_o   ),
       .phy_mdio_oe         ( eth_mdio_oe  ),
       .phy_mdc_o           ( eth_mdc_o    ),
-      .testmode_i          ( testmode_i   ),
+      .testmode_i          ( test_mode_i  ),
       .axi_req_o           ( axi_in_req[AxiIn.eth]        ),
       .axi_rsp_i           ( axi_in_rsp[AxiIn.eth]        ),
       .reg_req_i           ( reg_out_req[RegOut.ethernet] ),
diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c
index 5eeb75a2..018cb58b 100644
--- a/sw/tests/ethernet.c
+++ b/sw/tests/ethernet.c
@@ -91,6 +91,11 @@ int main(void) {
   // rx irq
   while (!((*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ));
 
+
+  uint32_t *rsr;
+  rsr = 0x0300c018;
+  printf("rsr value: 0x%08X\n", *rsr);
+
   uint32_t *rx_length;
   rx_length = 0x0300c024;
   printf("rx length value: 0x%08X\n", *rx_length);
diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv
index e51ede10..54573cd1 100644
--- a/target/sim/src/vip_cheshire_soc.sv
+++ b/target/sim/src/vip_cheshire_soc.sv
@@ -18,7 +18,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
   parameter type          axi_ext_mst_req_t = logic,
   parameter type          axi_ext_mst_rsp_t = logic,
   // Timing
-  parameter time          ClkPeriodSys      = 5ns,
+  parameter time          ClkPeriodSys      = 20ns,
   parameter time          ClkPeriodJtag     = 20ns,
   parameter time          ClkPeriodRtc      = 30518ns,
   parameter time          ClkPeriodEth      = 8ns,
@@ -762,10 +762,12 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
       end
       @(posedge clk);
     end
+    repeat (300) @(posedge clk);
 
     reg_drv_rx.send_write( 'h0300c018, 32'h2, 'hf, reg_error ); // to clear rx_complete, thus to clear rx_irq once all data is processed.
     @(posedge clk)
 
+
     // Tx test starts here: external back to core
     reg_drv_rx.send_write( 'h0300c000, 32'h89000123, 'hf, reg_error); //lower 32bits of MAC address
     @(posedge clk);