Skip to content

Commit

Permalink
rx complete debug
Browse files Browse the repository at this point in the history
  • Loading branch information
chaoqun-liang committed Dec 13, 2024
1 parent dd317d8 commit 4794c7e
Show file tree
Hide file tree
Showing 3 changed files with 9 additions and 2 deletions.
2 changes: 1 addition & 1 deletion hw/cheshire_soc.sv
Original file line number Diff line number Diff line change
Expand Up @@ -1336,7 +1336,7 @@ module cheshire_soc import cheshire_pkg::*; #(
.phy_mdio_o ( eth_mdio_o ),
.phy_mdio_oe ( eth_mdio_oe ),
.phy_mdc_o ( eth_mdc_o ),
.testmode_i ( testmode_i ),
.testmode_i ( test_mode_i ),
.axi_req_o ( axi_in_req[AxiIn.eth] ),
.axi_rsp_i ( axi_in_rsp[AxiIn.eth] ),
.reg_req_i ( reg_out_req[RegOut.ethernet] ),
Expand Down
5 changes: 5 additions & 0 deletions sw/tests/ethernet.c
Original file line number Diff line number Diff line change
Expand Up @@ -91,6 +91,11 @@ int main(void) {
// rx irq
while (!((*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ));


uint32_t *rsr;
rsr = 0x0300c018;
printf("rsr value: 0x%08X\n", *rsr);

uint32_t *rx_length;
rx_length = 0x0300c024;
printf("rx length value: 0x%08X\n", *rx_length);
Expand Down
4 changes: 3 additions & 1 deletion target/sim/src/vip_cheshire_soc.sv
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
parameter type axi_ext_mst_req_t = logic,
parameter type axi_ext_mst_rsp_t = logic,
// Timing
parameter time ClkPeriodSys = 5ns,
parameter time ClkPeriodSys = 20ns,
parameter time ClkPeriodJtag = 20ns,
parameter time ClkPeriodRtc = 30518ns,
parameter time ClkPeriodEth = 8ns,
Expand Down Expand Up @@ -762,10 +762,12 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
end
@(posedge clk);
end
repeat (300) @(posedge clk);

reg_drv_rx.send_write( 'h0300c018, 32'h2, 'hf, reg_error ); // to clear rx_complete, thus to clear rx_irq once all data is processed.
@(posedge clk)


// Tx test starts here: external back to core
reg_drv_rx.send_write( 'h0300c000, 32'h89000123, 'hf, reg_error); //lower 32bits of MAC address
@(posedge clk);
Expand Down

0 comments on commit 4794c7e

Please sign in to comment.