diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index ee199735..7db655b5 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -42,6 +42,7 @@ jobs: uses: chipsalliance/verible-linter-action@main with: paths: hw + exclude_paths: hw/configs extra_args: "--waiver_files .github/verible.waiver" github_token: ${{ secrets.GITHUB_TOKEN }} fail_on_error: true diff --git a/Bender.yml b/Bender.yml index 01f6ef29..8292cc85 100644 --- a/Bender.yml +++ b/Bender.yml @@ -8,6 +8,7 @@ package: - "Luca Valente " - "Alessandro Ottaviano " - "Robert Balas " + - "Yvan Tortorella " dependencies: register_interface: { git: https://github.com/pulp-platform/register_interface.git, version: 0.4.2 } @@ -37,6 +38,39 @@ workspace: pulp_cluster: pulp_cluster sources: + # Configurations + - target: carfield_l2dual_safe_secure_pulp_spatz_periph_can + files: + - hw/configs/carfield_l2dual_safe_secure_pulp_spatz_periph_can.sv + + - target: carfield_l2dual_periph + files: + - hw/configs/carfield_l2dual_periph.sv + + - target: carfield_l2dual_safe_pulp_periph + files: + - hw/configs/carfield_l2dual_safe_pulp_periph.sv + + - target: carfield_l2dual_pulp_periph + files: + - hw/configs/carfield_l2dual_pulp_periph.sv + + - target: carfield_l2dual_safe_periph + files: + - hw/configs/carfield_l2dual_safe_periph.sv + + - target: carfield_l2dual_spatz_periph + files: + - hw/configs/carfield_l2dual_spatz_periph.sv + + - target: carfield_l2dual_secure_periph + files: + - hw/configs/carfield_l2dual_secure_periph.sv + + - target: carfield_l2dual_safe_pulp_spatz_periph + files: + - hw/configs/carfield_l2dual_safe_pulp_spatz_periph.sv + # Source files grouped in levels. Files in level 0 have no dependencies on files in this # package. Files in level 1 only depend on files in level 0, files in level 2 on files in # levels 1 and 0, etc. Files within a level are ordered alphabetically. @@ -48,6 +82,7 @@ sources: - hw/cheshire_wrap.sv - hw/hyperbus_wrap.sv - hw/l2_wrap.sv + - hw/spatz_cluster_wrapper.sv - hw/carfield_rstgen.sv # Level 2 - hw/carfield.sv @@ -70,16 +105,16 @@ sources: - target: all(xilinx, fpga, xilinx_vanilla) files: - target/xilinx/src/cdc_dst_axi_err.sv - - target/xilinx/src/overrides/tc_clk_xilinx.sv - target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv - target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv + - target/xilinx/src/overrides/tc_clk_xilinx.sv - target: all(xilinx, fpga, xilinx_bd) files: - target/xilinx/src/cdc_dst_axi_err.sv - - target/xilinx/src/overrides/tc_clk_xilinx.sv - target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv - target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx_ip.v + - target/xilinx/src/overrides/tc_clk_xilinx.sv - target: intel16_elab_only files: diff --git a/bender-common.mk b/bender-common.mk index ac9e5aec..4e5ba36f 100644 --- a/bender-common.mk +++ b/bender-common.mk @@ -5,6 +5,9 @@ # Author: Yvan Tortorella # Author: Matteo Perotti +# Runtime-selectable Carfield configuration +CARFIELD_CONFIG ?= carfield_l2dual_safe_secure_pulp_spatz_periph_can + # bender targets common_targs += -t cva6 common_targs += -t mchan @@ -14,6 +17,8 @@ common_targs += -t cv32e40p_use_ff_regfile common_targs += -t scm_use_fpga_scm common_targs += -t cv64a6_imafdcsclic_sv39 common_targs += -t rtl +# Carfield config target. +common_targs += -t $(CARFIELD_CONFIG) # bender defines common_defs += -D FEATURE_ICACHE_STAT diff --git a/bender-xilinx.mk b/bender-xilinx.mk index 4e8f151b..16f682e7 100644 --- a/bender-xilinx.mk +++ b/bender-xilinx.mk @@ -17,10 +17,6 @@ xilinx_defs_common += -D$(1)=1 endif endef -$(eval $(call check_enable_island,GEN_PULP_CLUSTER)) -$(eval $(call check_enable_island,GEN_SAFETY_ISLAND)) -$(eval $(call check_enable_island,GEN_SPATZ_CLUSTER)) -$(eval $(call check_enable_island,GEN_OPEN_TITAN)) $(eval $(call check_enable_island,GEN_NO_HYPERBUS)) $(eval $(call check_enable_island,GEN_EXT_JTAG)) diff --git a/carfield.mk b/carfield.mk index dee3134a..715f8128 100644 --- a/carfield.mk +++ b/carfield.mk @@ -44,7 +44,7 @@ include $(CAR_ROOT)/bender-safed.mk ###################### CAR_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:carfield/carfield-nonfree.git -CAR_NONFREE_COMMIT ?= acda49f +CAR_NONFREE_COMMIT ?= 54ce7e49 ## @section Carfield platform nonfree components ## Clone the non-free verification IP for Carfield. Some components such as CI scripts and ASIC diff --git a/docs/tg/xilinx.md b/docs/tg/xilinx.md index 43ce371b..243fc248 100644 --- a/docs/tg/xilinx.md +++ b/docs/tg/xilinx.md @@ -41,30 +41,29 @@ Generate the bitstream in `target/xilinx/out/` by running: ```bash make car-xil-all XILINX_FLAVOR=vanilla [VIVADO=version] -[VIVADO_MODE={batch,gui}] [XILINX_BOARD={vcu128}] [NO_HYPERBUS={0,1}] -[GEN_EXT_JTAG={0,1}] [GEN_PULP_CLUSTER={0,1}] [GEN_SAFETY_ISLAND={0,1}] -[GEN_SPATZ_CLUSTER={0,1}] [GEN_OPEN_TITAN={0,1}] +[VIVADO_MODE={batch,gui}] [XILINX_BOARD={vcu128}] [GEN_NO_HYPERBUS={0,1}] +[GEN_EXT_JTAG={0,1}] [CARFIELD_CONFIG=carfield_l2dual_{safe,spatz}_periph] ``` See the argument list below: -| Argument | Relevance | Description | -|----------------|-----------|---------------------------------------------------------------------------------------------------------------------------------------| -| VIVADO | all | Vivado command to use | -| XILINX_BOARD | all | `vcu128` | -| NO_HYPERBUS | all | `0` Use the hyperram controller inside `carfield.sv`
`1` Use the Xilinx DDR controller | -| GEN_EXT_JTAG | vcu128 | `0` Connect the JTAG debugger to the board's JTAG (see [vcu128](#xilinx-vcu128))
`1` Connect the JTAG debugger to an external JTAG chain | -| GEN_*[IP]* | all | `0` Replace the IP with an AXI error slave
`1` Instanciate the IP | -| VIVADO_MODE | all | `batch` Compile in Vivado shell
`gui` Compile in Vivado gui | +| Argument | Relevance | Description | +|-----------------|-----------|---------------------------------------------------------------------------------------------------------------------------------------| +| VIVADO | all | Vivado command to use | +| XILINX_BOARD | all | `vcu128` | +| GEN_NO_HYPERBUS | all | `0` Use the hyperram controller inside `carfield.sv`
`1` Use the Xilinx DDR controller | +| GEN_EXT_JTAG | vcu128 | `0` Connect the JTAG debugger to the board's JTAG (see [vcu128](#xilinx-vcu128))
`1` Connect the JTAG debugger to an external JTAG chain | +| CARFIELD_CONFIG | all | Select the Carfield configuration to implement. See below for supported configs. | +| VIVADO_MODE | all | `batch` Compile in Vivado shell
`gui` Compile in Vivado gui | See below some typical building time for reference: -| IPs | Board | Duration | -|-------------------|--------|------------| -| PULP | vcu128 | xxhxxmin | -| SAFETY | vcu128 | xxhxxmin | -| SPATZ | vcu128 | xxhxxmin | -| PULP + SAFETY | vcu128 | xxhxxmin | +| Config | Board | Duration | +|----------------------------------------|--------|------------| +| carfield_l2dual_pulp_periph | vcu128 | __ISSUE__ | +| carfield_l2dual_safe_periph | vcu128 | 6h01min | +| carfield_l2dual_spatz_periph | vcu128 | 3h31min | +| carfield_l2dual_secure_periph | vcu128 | __ISSUE__ | You can find which sources are used by looking at `Bender.yml` (target `all(xilinx, fpga, xilinx_vanilla)`). This file is used by bender to generate @@ -91,30 +90,29 @@ Generate the bitstream in `target/xilinx/out/` by running: ```bash make car-xil-all XILINX_FLAVOR=bd [VIVADO=version] [VIVADO_MODE={batch,gui}] -[XILINX_BOARD={vcu128}] [NO_HYPERBUS={0,1}] [GEN_EXT_JTAG={0,1}] -[GEN_PULP_CLUSTER={0,1}] [GEN_SAFETY_ISLAND={0,1}] [GEN_SPATZ_CLUSTER={0,1}] -[GEN_OPEN_TITAN={0,1}] +[XILINX_BOARD={vcu128}] [GEN_NO_HYPERBUS={0,1}] [GEN_EXT_JTAG={0,1}] +[CARFIELD_CONFIG=carfield_l2dual_{safe,spatz}_periph] ``` See the argument list below: -| Argument | Relevance | Description | -|----------------|-----------|---------------------------------------------------------------------------------------------------------------------------------------| -| VIVADO | all | Vivado command to use | -| XILINX_BOARD | all | `vcu128` | -| NO_HYPERBUS | all | `0` Use the hyperram controller inside `carfield.sv`
`1` Use the Xilinx DDR controller | -| GEN_EXT_JTAG | vcu128 | `0` Connect the JTAG debugger to the board's JTAG (see [vcu128](#xilinx-vcu128))
`1` Connect the JTAG debugger to an external JTAG chain | -| GEN_*[IP]* | all | `0` Replace the IP with an AXI error slave
`1` Instanciate the IP | -| VIVADO_MODE | all | `batch` Compile in Vivado shell
`gui` Compile in Vivado gui | +| Argument | Relevance | Description | +|---------------- |-----------|---------------------------------------------------------------------------------------------------------------------------------------| +| VIVADO | all | Vivado command to use | +| XILINX_BOARD | all | `vcu128` | +| GEN_NO_HYPERBUS | all | `0` Use the hyperram controller inside `carfield.sv`
`1` Use the Xilinx DDR controller | +| GEN_EXT_JTAG | vcu128 | `0` Connect the JTAG debugger to the board's JTAG (see [vcu128](#xilinx-vcu128))
`1` Connect the JTAG debugger to an external JTAG chain | +| CARFIELD_CONFIG | all | Select the Carfield configuration to implement. See below for supported configs. | +| VIVADO_MODE | all | `batch` Compile in Vivado shell
`gui` Compile in Vivado gui | See below some typical building time for reference: -| IPs | Board | Duration | -|-------------------|--------|------------| -| PULP | vcu128 | xxhxxmin | -| SAFETY | vcu128 | xxhxxmin | -| SPATZ | vcu128 | xxhxxmin | -| PULP + SAFETY | vcu128 | xxhxxmin | +| Config | Board | Duration | +|----------------------------------------|--------|------------| +| carfield_l2dual_pulp_periph | vcu128 | __ISSUE__ | +| carfield_l2dual_safe_periph | vcu128 | 3h49min | +| carfield_l2dual_spatz_periph | vcu128 | 5h40min | +| carfield_l2dual_secure_periph | vcu128 | __ISSUE__ | You can find which sources are used by looking at `Bender.yml` (target `all(xilinx, fpga, xilinx_bd)`). This file is used by bender to generate diff --git a/hw/carfield.sv b/hw/carfield.sv index 2ebbb111..79a5c106 100644 --- a/hw/carfield.sv +++ b/hw/carfield.sv @@ -22,7 +22,6 @@ module carfield import spatz_cluster_pkg::*; #( parameter cheshire_cfg_t Cfg = carfield_pkg::CarfieldCfgDefault, - parameter islands_cfg_t IslandsCfg = carfield_pkg::IslandsCfgDefault, parameter int unsigned HypNumPhys = 2, parameter int unsigned HypNumChips = 2, `ifdef GEN_NO_HYPERBUS // bender-xilinx.mk @@ -34,7 +33,13 @@ module carfield parameter int unsigned LlcWWidth, `endif parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic + parameter type reg_rsp_t = logic, + localparam int unsigned NumExcludedSlaves = CarfieldIslandsCfg.pulp.enable ? 2 : 1, + localparam int unsigned NumSlaveCDCs = Cfg.AxiExtNumSlv - NumExcludedSlaves, + localparam int unsigned NumExcludedIsolate = CarfieldIslandsCfg.pulp.enable ? 1 : 0, + localparam int unsigned NumIsolate = Cfg.AxiExtNumSlv - NumExcludedIsolate, + localparam int unsigned NumExcludedMasters = CarfieldIslandsCfg.pulp.enable ? 1 : 0, + localparam int unsigned NumMasterCDCs = Cfg.AxiExtNumMst - NumExcludedMasters ) ( // host clock input logic host_clk_i, @@ -472,42 +477,42 @@ logic [ LogDepth:0] llc_w_rptr; logic hyper_isolate_req, hyper_isolated_rsp; logic security_island_isolate_req; -logic [iomsb(Cfg.AxiExtNumSlv-1):0] slave_isolate_req, slave_isolated_rsp, slave_isolated; +logic [iomsb(NumIsolate):0] slave_isolate_req, slave_isolated_rsp, slave_isolated; logic [iomsb(Cfg.AxiExtNumMst):0] master_isolated_rsp; // All AXI Slaves (except the Integer Cluster and the Mailbox) -logic [iomsb(Cfg.AxiExtNumSlv-2):0][CarfieldAxiSlvAwWidth-1:0] axi_slv_ext_aw_data; -logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_aw_wptr; -logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_aw_rptr; -logic [iomsb(Cfg.AxiExtNumSlv-2):0][ CarfieldAxiSlvWWidth-1:0] axi_slv_ext_w_data ; -logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_w_wptr ; -logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_w_rptr ; -logic [iomsb(Cfg.AxiExtNumSlv-2):0][ CarfieldAxiSlvBWidth-1:0] axi_slv_ext_b_data ; -logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_b_wptr ; -logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_b_rptr ; -logic [iomsb(Cfg.AxiExtNumSlv-2):0][CarfieldAxiSlvArWidth-1:0] axi_slv_ext_ar_data; -logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_ar_wptr; -logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_ar_rptr; -logic [iomsb(Cfg.AxiExtNumSlv-2):0][ CarfieldAxiSlvRWidth-1:0] axi_slv_ext_r_data ; -logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_r_wptr ; -logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_r_rptr ; +logic [iomsb(NumSlaveCDCs):0][CarfieldAxiSlvAwWidth-1:0] axi_slv_ext_aw_data; +logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_aw_wptr; +logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_aw_rptr; +logic [iomsb(NumSlaveCDCs):0][ CarfieldAxiSlvWWidth-1:0] axi_slv_ext_w_data ; +logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_w_wptr ; +logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_w_rptr ; +logic [iomsb(NumSlaveCDCs):0][ CarfieldAxiSlvBWidth-1:0] axi_slv_ext_b_data ; +logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_b_wptr ; +logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_b_rptr ; +logic [iomsb(NumSlaveCDCs):0][CarfieldAxiSlvArWidth-1:0] axi_slv_ext_ar_data; +logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_ar_wptr; +logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_ar_rptr; +logic [iomsb(NumSlaveCDCs):0][ CarfieldAxiSlvRWidth-1:0] axi_slv_ext_r_data ; +logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_r_wptr ; +logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_r_rptr ; // All AXI Masters (except the Integer Cluster) -logic [iomsb(Cfg.AxiExtNumMst-1):0][CarfieldAxiMstAwWidth-1:0] axi_mst_ext_aw_data; -logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_aw_wptr; -logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_aw_rptr; -logic [iomsb(Cfg.AxiExtNumMst-1):0][ CarfieldAxiMstWWidth-1:0] axi_mst_ext_w_data ; -logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_w_wptr ; -logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_w_rptr ; -logic [iomsb(Cfg.AxiExtNumMst-1):0][ CarfieldAxiMstBWidth-1:0] axi_mst_ext_b_data ; -logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_b_wptr ; -logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_b_rptr ; -logic [iomsb(Cfg.AxiExtNumMst-1):0][CarfieldAxiMstArWidth-1:0] axi_mst_ext_ar_data; -logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_ar_wptr; -logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_ar_rptr; -logic [iomsb(Cfg.AxiExtNumMst-1):0][ CarfieldAxiMstRWidth-1:0] axi_mst_ext_r_data ; -logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_r_wptr ; -logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_r_rptr ; +logic [iomsb(NumMasterCDCs):0][CarfieldAxiMstAwWidth-1:0] axi_mst_ext_aw_data; +logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_aw_wptr; +logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_aw_rptr; +logic [iomsb(NumMasterCDCs):0][ CarfieldAxiMstWWidth-1:0] axi_mst_ext_w_data ; +logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_w_wptr ; +logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_w_rptr ; +logic [iomsb(NumMasterCDCs):0][ CarfieldAxiMstBWidth-1:0] axi_mst_ext_b_data ; +logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_b_wptr ; +logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_b_rptr ; +logic [iomsb(NumMasterCDCs):0][CarfieldAxiMstArWidth-1:0] axi_mst_ext_ar_data; +logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_ar_wptr; +logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_ar_rptr; +logic [iomsb(NumMasterCDCs):0][ CarfieldAxiMstRWidth-1:0] axi_mst_ext_r_data ; +logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_r_wptr ; +logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_r_rptr ; // Integer Cluster Slave Bus logic [IntClusterAxiSlvAwWidth-1:0] axi_slv_intcluster_aw_data; @@ -613,13 +618,6 @@ logic [NumDomains-1:0] rsts_n; // every target domain to use different clock frequencies. // 3. The internal clock gate of the clock divider is used to provide clock gating for the domain. -localparam int unsigned DomainClkDivValue[NumDomains] = '{PeriphDomainClkDivValue , - SafedDomainClkDivValue , - SecdDomainClkDivValue , - IntClusterDomainClkDivValue , - FPClusterDomainClkDivValue , - L2DomainClkDivValue }; - for (genvar i = 0; i < NumDomains; i++) begin : gen_domain_clock_mux clk_mux_glitch_free #( .NUM_INPUTS(3) @@ -672,7 +670,7 @@ for (genvar i = 0; i < NumDomains; i++) begin : gen_domain_clock_mux clk_int_div #( .DIV_VALUE_WIDTH(DomainClkDivValueWidth), - .DEFAULT_DIV_VALUE(DomainClkDivValue[i]), + .DEFAULT_DIV_VALUE(CarfieldClkDivValue.clock_div_value[i]), .ENABLE_CLOCK_IN_RESET(1) ) i_clk_div ( .clk_i ( domain_clk[i] ), @@ -688,8 +686,6 @@ for (genvar i = 0; i < NumDomains; i++) begin : gen_domain_clock_mux ); end - - // Reset generation for power-on reset for host domain. For the other domain we // get this from carfield_rstgen rstgen i_host_rstgen ( @@ -704,18 +700,14 @@ rstgen i_host_rstgen ( // Reset generation combining software and power-on reset. These are software // controllable resets. The matching of clock and reset domain is according to // the description above +logic [NumDomains-1:0] reset_vector; carfield_rstgen #( .NumRstDomains (NumDomains) ) i_carfield_rstgen ( .clks_i(domain_clk), .pwr_on_rst_ni, - .sw_rsts_ni(~{car_regs_reg2hw.l2_rst.q, - car_regs_reg2hw.spatz_cluster_rst.q, - car_regs_reg2hw.pulp_cluster_rst.q, - car_regs_reg2hw.security_island_rst.q, - car_regs_reg2hw.safety_island_rst.q, - car_regs_reg2hw.periph_rst.q}), + .sw_rsts_ni(~reset_vector), .test_mode_i, .rsts_no(rsts_n), .pwr_on_rsts_no(pwr_on_rsts_n), @@ -725,56 +717,19 @@ carfield_rstgen #( // Assign vectorized reset and clock signals to friendly-named domain signals and registers // verilog_lint: waive-start line-length -assign periph_rst_n = rsts_n[PeriphDomainIdx]; -assign safety_rst_n = rsts_n[SafedDomainIdx]; -assign security_rst_n = rsts_n[SecdDomainIdx]; -assign pulp_rst_n = rsts_n[IntClusterDomainIdx]; -assign spatz_rst_n = rsts_n[FPClusterDomainIdx]; -assign l2_rst_n = rsts_n[L2DomainIdx]; - -assign periph_pwr_on_rst_n = pwr_on_rsts_n[PeriphDomainIdx]; -assign safety_pwr_on_rst_n = pwr_on_rsts_n[SafedDomainIdx]; -assign security_pwr_on_rst_n = pwr_on_rsts_n[SecdDomainIdx]; -assign pulp_pwr_on_rst_n = pwr_on_rsts_n[IntClusterDomainIdx]; -assign spatz_pwr_on_rst_n = pwr_on_rsts_n[FPClusterDomainIdx]; -assign l2_pwr_on_rst_n = pwr_on_rsts_n[L2DomainIdx]; - -assign periph_clk = domain_clk_gated[PeriphDomainIdx]; -assign safety_clk = domain_clk_gated[SafedDomainIdx]; -assign security_clk = domain_clk_gated[SecdDomainIdx]; -assign pulp_clk = domain_clk_gated[IntClusterDomainIdx]; -assign spatz_clk = domain_clk_gated[FPClusterDomainIdx]; -assign l2_clk = domain_clk_gated[L2DomainIdx]; - -assign domain_clk_sel[PeriphDomainIdx] = car_regs_reg2hw.periph_clk_sel.q; -assign domain_clk_sel[SafedDomainIdx] = car_regs_reg2hw.safety_island_clk_sel.q; -assign domain_clk_sel[SecdDomainIdx] = car_regs_reg2hw.security_island_clk_sel.q; -assign domain_clk_sel[IntClusterDomainIdx] = car_regs_reg2hw.pulp_cluster_clk_sel.q; -assign domain_clk_sel[FPClusterDomainIdx] = car_regs_reg2hw.spatz_cluster_clk_sel.q; -assign domain_clk_sel[L2DomainIdx] = car_regs_reg2hw.l2_clk_sel.q; - -assign domain_clk_div_value[PeriphDomainIdx] = car_regs_reg2hw.periph_clk_div_value.q; -assign domain_clk_div_value[SafedDomainIdx] = car_regs_reg2hw.safety_island_clk_div_value.q; -assign domain_clk_div_value[SecdDomainIdx] = car_regs_reg2hw.security_island_clk_div_value.q; -assign domain_clk_div_value[IntClusterDomainIdx] = car_regs_reg2hw.pulp_cluster_clk_div_value.q; -assign domain_clk_div_value[FPClusterDomainIdx] = car_regs_reg2hw.spatz_cluster_clk_div_value.q; -assign domain_clk_div_value[L2DomainIdx] = car_regs_reg2hw.l2_clk_div_value.q; - -assign domain_clk_div_changed[PeriphDomainIdx] = car_regs_reg2hw.periph_clk_div_value.qe; -assign domain_clk_div_changed[SafedDomainIdx] = car_regs_reg2hw.safety_island_clk_div_value.qe; -assign domain_clk_div_changed[SecdDomainIdx] = car_regs_reg2hw.security_island_clk_div_value.qe; -assign domain_clk_div_changed[IntClusterDomainIdx] = car_regs_reg2hw.pulp_cluster_clk_div_value.qe; -assign domain_clk_div_changed[FPClusterDomainIdx] = car_regs_reg2hw.spatz_cluster_clk_div_value.qe; -assign domain_clk_div_changed[L2DomainIdx] = car_regs_reg2hw.l2_clk_div_value.qe; - -assign domain_clk_en[PeriphDomainIdx] = car_regs_reg2hw.periph_clk_en.q; -assign domain_clk_en[SafedDomainIdx] = car_regs_reg2hw.safety_island_clk_en.q; -// secure boot mode forces security island to come up concurrently with host domain. Furthermore, it -// cannot be disabled by design -assign domain_clk_en[SecdDomainIdx] = car_regs_reg2hw.security_island_clk_en.q | secure_boot_i; -assign domain_clk_en[IntClusterDomainIdx] = car_regs_reg2hw.pulp_cluster_clk_en.q; -assign domain_clk_en[FPClusterDomainIdx] = car_regs_reg2hw.spatz_cluster_clk_en.q; -assign domain_clk_en[L2DomainIdx] = car_regs_reg2hw.l2_clk_en.q; +assign periph_rst_n = rsts_n[CarfieldDomainIdx.periph]; + +assign periph_pwr_on_rst_n = pwr_on_rsts_n[CarfieldDomainIdx.periph]; + +assign periph_clk = domain_clk_gated[CarfieldDomainIdx.periph]; + +assign domain_clk_sel[CarfieldDomainIdx.periph] = car_regs_reg2hw.periph_clk_sel.q; + +assign domain_clk_div_value[CarfieldDomainIdx.periph] = car_regs_reg2hw.periph_clk_div_value.q; + +assign domain_clk_div_changed[CarfieldDomainIdx.periph] = car_regs_reg2hw.periph_clk_div_value.qe; + +assign domain_clk_en[CarfieldDomainIdx.periph] = car_regs_reg2hw.periph_clk_en.q; // Assign debug signals assign debug_signals_o.domain_clk = domain_clk_gated; @@ -807,81 +762,13 @@ carfield_reg_top #( ) i_carfield_reg_top ( .clk_i (host_clk_i), .rst_ni (host_pwr_on_rst_n), - .reg_req_i(ext_reg_req_cut[CarRegsIdx]), - .reg_rsp_o(ext_reg_rsp_cut[CarRegsIdx]), + .reg_req_i(ext_reg_req_cut[int'(CarfieldRegBusSlvIdx.pcrs)]), + .reg_rsp_o(ext_reg_rsp_cut[int'(CarfieldRegBusSlvIdx.pcrs)]), .reg2hw (car_regs_reg2hw), .hw2reg (car_regs_hw2reg), .devmode_i (1'b1) ); -// Isolate and Isolate status - -// For islands that connect to Cheshire with a master and a slave AXI port (Safety Island, Integer -// Cluster, FP cluster), we consider the island isolated when the isolation status signals for both -// ports are asserted. - -// For islands that connect to Cheshire with a slave port only (L2 port0, L2 port1, Ethernet, -// Carfield peripherals, Hyperbus), we consider the island isolated when the unique isolation status -// signal is asserted. - -// For islands that connect to Cheshire with a master port only (Security Island), we consider the -// island isolated when the unique isolation status signal is asserted. - -assign slave_isolate_req[SafetyIslandSlvIdx] = car_regs_reg2hw.safety_island_isolate.q; -assign slave_isolate_req[IntClusterSlvIdx] = car_regs_reg2hw.pulp_cluster_isolate.q; -assign slave_isolate_req[FPClusterSlvIdx] = car_regs_reg2hw.spatz_cluster_isolate.q; -// We isolate both L2 AXI ports with a single write to the isolate register in `carfield_reg_top` -assign slave_isolate_req[L2Port0SlvIdx] = car_regs_reg2hw.l2_isolate.q; -assign slave_isolate_req[L2Port1SlvIdx] = car_regs_reg2hw.l2_isolate.q; -// Ethernet isolation follows writes to the peripheral isolate registers in `carfield_reg_top` -assign slave_isolate_req[EthernetSlvIdx] = car_regs_reg2hw.periph_isolate.q; -// Hyperbus isolation follows writes to the peripheral isolate registers in `carfield_reg_top` -assign hyper_isolate_req = car_regs_reg2hw.periph_isolate.q; -assign slave_isolate_req[PeriphsSlvIdx] = car_regs_reg2hw.periph_isolate.q; -assign security_island_isolate_req = car_regs_reg2hw.security_island_isolate.q - && !secure_boot_i; - -always_comb begin : gen_assign_isolated_responses - slave_isolated = '0; - for (int i = 0; i < Cfg.AxiExtNumSlv; i++) begin - if (i == SafetyIslandSlvIdx) - slave_isolated[i] = slave_isolated_rsp[i] & master_isolated_rsp[SafetyIslandMstIdx]; - else if (i == IntClusterSlvIdx) - slave_isolated[i] = slave_isolated_rsp[i] & master_isolated_rsp[IntClusterMstIdx]; - else if (i == FPClusterSlvIdx) - slave_isolated[i] = slave_isolated_rsp[i] & master_isolated_rsp[FPClusterMstIdx]; - else - slave_isolated[i] = slave_isolated_rsp[i]; - end -end - -// Safety Island, Integer cluster, FP cluster: master and slave AXI ports -assign car_regs_hw2reg.safety_island_isolate_status.d = slave_isolated[SafetyIslandSlvIdx]; -assign car_regs_hw2reg.safety_island_isolate_status.de = 1'b1; - -assign car_regs_hw2reg.pulp_cluster_isolate_status.d = slave_isolated[IntClusterSlvIdx]; -assign car_regs_hw2reg.pulp_cluster_isolate_status.de = 1'b1; - -assign car_regs_hw2reg.spatz_cluster_isolate_status.d = slave_isolated[FPClusterSlvIdx]; -assign car_regs_hw2reg.spatz_cluster_isolate_status.de = 1'b1; - -// L2 port0, L2 port1, Carfield peripherals -// L2 requires both ports to be isolated before asserting the isolated status -assign car_regs_hw2reg.l2_isolate_status.d = slave_isolated[L2Port0SlvIdx] & - slave_isolated[L2Port1SlvIdx]; -assign car_regs_hw2reg.l2_isolate_status.de = 1'b1; - -// Peripheral isolate status is asserted when peripherals or the hyperbus or ethernet assert their -// isolated status -assign car_regs_hw2reg.periph_isolate_status.d = slave_isolated[PeriphsSlvIdx] | - hyper_isolated_rsp | - slave_isolated[EthernetSlvIdx]; -assign car_regs_hw2reg.periph_isolate_status.de = 1'b1; - -// security island only has a master port -assign car_regs_hw2reg.security_island_isolate_status.d = master_isolated_rsp[SecurityIslandMstIdx]; -assign car_regs_hw2reg.security_island_isolate_status.de = 1'b1; - // hyperbus reg req/rsp carfield_a32_d32_reg_req_t reg_hyper_req; carfield_a32_d32_reg_rsp_t reg_hyper_rsp; @@ -1138,6 +1025,8 @@ cheshire i_cheshire_wrap ( .vga_blue_o ( ) ); +assign hyper_isolate_req = car_regs_reg2hw.periph_isolate.q; + `ifndef GEN_NO_HYPERBUS // bender-xilinx.mk // Hyperbus hyperbus_wrap #( @@ -1212,62 +1101,108 @@ hyperbus_wrap #( ); `endif // GEN_NO_HYPERBUS +// Temporary Mailbox parameters (evaluate if we can move everything here). +// The best approach would be to move all these parameters to the package. +localparam int unsigned HostdMboxOffset = (spatz_cluster_pkg::NumCores + + (spatz_cluster_pkg::NumCores * + CheshireNumIntHarts ) + ); + +localparam int unsigned SpatzMboxOffset = HostdMboxOffset + + 3*CheshireNumIntHarts; + +localparam int unsigned PulpclMboxOffset = SpatzMboxOffset + + CheshireNumIntHarts + 1; + +localparam int unsigned SecdMboxOffset = PulpclMboxOffset + + CheshireNumIntHarts + 1; + +localparam int unsigned SafedMboxOffset = SecdMboxOffset + + CheshireNumIntHarts + 1; + // Reconfigurable L2 Memory // Host Clock Domain -`ifndef L2_WRAP_NETLIST -l2_wrap #( - .Cfg ( Cfg ), - .NumPort ( NumL2Ports ), - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiIdWidth ( AxiSlvIdWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiMaxTrans ( Cfg.AxiMaxSlvTrans ), - .LogDepth ( LogDepth ), - .CdcSyncStages( SyncStages ), - .NumRules ( L2NumRules ), - .L2MemSize ( L2MemSize ), - // Atomics - .L2MaxReadTxns ( Cfg.LlcMaxReadTxns ), // TODO: AMO parameters are default - // from the LLC (Cheshire), at the - // moment - .L2MaxWriteTxns ( Cfg.LlcMaxWriteTxns ), - .AxiUserAmoMsb ( Cfg.AxiUserAmoMsb ), - .AxiUserAmoLsb ( Cfg.AxiUserAmoLsb ), - .L2AmoNumCuts ( Cfg.LlcAmoNumCuts ), - .l2_ecc_reg_req_t ( carfield_reg_req_t ), - .l2_ecc_reg_rsp_t ( carfield_reg_rsp_t ) -) i_reconfigurable_l2 ( -`else -l2_wrap i_reconfigurable_l2 ( -`endif - .clk_i ( l2_clk ), - .rst_ni ( l2_rst_n ), - .pwr_on_rst_ni ( l2_pwr_on_rst_n ), - .slvport_ar_data_i ( axi_slv_ext_ar_data [NumL2Ports-1:0] ), - .slvport_ar_wptr_i ( axi_slv_ext_ar_wptr [NumL2Ports-1:0] ), - .slvport_ar_rptr_o ( axi_slv_ext_ar_rptr [NumL2Ports-1:0] ), - .slvport_aw_data_i ( axi_slv_ext_aw_data [NumL2Ports-1:0] ), - .slvport_aw_wptr_i ( axi_slv_ext_aw_wptr [NumL2Ports-1:0] ), - .slvport_aw_rptr_o ( axi_slv_ext_aw_rptr [NumL2Ports-1:0] ), - .slvport_b_data_o ( axi_slv_ext_b_data [NumL2Ports-1:0] ), - .slvport_b_wptr_o ( axi_slv_ext_b_wptr [NumL2Ports-1:0] ), - .slvport_b_rptr_i ( axi_slv_ext_b_rptr [NumL2Ports-1:0] ), - .slvport_r_data_o ( axi_slv_ext_r_data [NumL2Ports-1:0] ), - .slvport_r_wptr_o ( axi_slv_ext_r_wptr [NumL2Ports-1:0] ), - .slvport_r_rptr_i ( axi_slv_ext_r_rptr [NumL2Ports-1:0] ), - .slvport_w_data_i ( axi_slv_ext_w_data [NumL2Ports-1:0] ), - .slvport_w_wptr_i ( axi_slv_ext_w_wptr [NumL2Ports-1:0] ), - .slvport_w_rptr_o ( axi_slv_ext_w_rptr [NumL2Ports-1:0] ), - .l2_ecc_reg_async_mst_req_i ( ext_reg_async_slv_req_out [L2EccIdx-NumSyncRegSlv] ), - .l2_ecc_reg_async_mst_ack_o ( ext_reg_async_slv_ack_in [L2EccIdx-NumSyncRegSlv] ), - .l2_ecc_reg_async_mst_data_i ( ext_reg_async_slv_data_out[L2EccIdx-NumSyncRegSlv] ), - .l2_ecc_reg_async_mst_req_o ( ext_reg_async_slv_req_in [L2EccIdx-NumSyncRegSlv] ), - .l2_ecc_reg_async_mst_ack_i ( ext_reg_async_slv_ack_out [L2EccIdx-NumSyncRegSlv] ), - .l2_ecc_reg_async_mst_data_o ( ext_reg_async_slv_data_in [L2EccIdx-NumSyncRegSlv] ), - .ecc_error_o ( l2_ecc_err ) -); +if (CarfieldIslandsCfg.l2_port0.enable) begin: gen_l2 + assign l2_rst_n = rsts_n[CarfieldDomainIdx.l2]; + assign l2_pwr_on_rst_n = pwr_on_rsts_n[CarfieldDomainIdx.l2]; + assign l2_clk = domain_clk_gated[CarfieldDomainIdx.l2]; + assign domain_clk_sel[CarfieldDomainIdx.l2] = car_regs_reg2hw.l2_clk_sel.q; + assign domain_clk_div_value[CarfieldDomainIdx.l2] = car_regs_reg2hw.l2_clk_div_value.q; + assign domain_clk_div_changed[CarfieldDomainIdx.l2] = car_regs_reg2hw.l2_clk_div_value.qe; + assign domain_clk_en[CarfieldDomainIdx.l2] = car_regs_reg2hw.l2_clk_en.q; + assign reset_vector[CarfieldDomainIdx.l2] = car_regs_reg2hw.l2_rst.q; + assign slave_isolate_req[L2Port0SlvIdx] = car_regs_reg2hw.l2_isolate.q; + assign slave_isolate_req[L2Port1SlvIdx] = car_regs_reg2hw.l2_isolate.q; + assign slave_isolated[L2Port0SlvIdx] = slave_isolated_rsp[L2Port0SlvIdx]; + assign slave_isolated[L2Port1SlvIdx] = slave_isolated_rsp[L2Port1SlvIdx]; + assign car_regs_hw2reg.l2_isolate_status.d = slave_isolated[L2Port0SlvIdx] & + slave_isolated[L2Port1SlvIdx]; + assign car_regs_hw2reg.l2_isolate_status.de = 1'b1; + + `ifndef L2_WRAP_NETLIST + l2_wrap #( + .Cfg ( Cfg ), + .NumPort ( NumL2Ports ), + .AxiAddrWidth ( Cfg.AddrWidth ), + .AxiDataWidth ( Cfg.AxiDataWidth ), + .AxiIdWidth ( AxiSlvIdWidth ), + .AxiUserWidth ( Cfg.AxiUserWidth ), + .AxiMaxTrans ( Cfg.AxiMaxSlvTrans ), + .LogDepth ( LogDepth ), + .CdcSyncStages( SyncStages ), + .NumRules ( L2NumRules ), + .L2MemSize ( L2MemSize ), + // Atomics + .L2MaxReadTxns ( Cfg.LlcMaxReadTxns ), // TODO: AMO parameters are default + // from the LLC (Cheshire), at the + // moment + .L2MaxWriteTxns ( Cfg.LlcMaxWriteTxns ), + .AxiUserAmoMsb ( Cfg.AxiUserAmoMsb ), + .AxiUserAmoLsb ( Cfg.AxiUserAmoLsb ), + .L2AmoNumCuts ( Cfg.LlcAmoNumCuts ), + .l2_ecc_reg_req_t ( carfield_reg_req_t ), + .l2_ecc_reg_rsp_t ( carfield_reg_rsp_t ) + ) i_reconfigurable_l2 ( + `else + l2_wrap i_reconfigurable_l2 ( + `endif + .clk_i ( l2_clk ), + .rst_ni ( l2_rst_n ), + .pwr_on_rst_ni ( l2_pwr_on_rst_n ), + .slvport_ar_data_i ( axi_slv_ext_ar_data [NumL2Ports-1:0] ), + .slvport_ar_wptr_i ( axi_slv_ext_ar_wptr [NumL2Ports-1:0] ), + .slvport_ar_rptr_o ( axi_slv_ext_ar_rptr [NumL2Ports-1:0] ), + .slvport_aw_data_i ( axi_slv_ext_aw_data [NumL2Ports-1:0] ), + .slvport_aw_wptr_i ( axi_slv_ext_aw_wptr [NumL2Ports-1:0] ), + .slvport_aw_rptr_o ( axi_slv_ext_aw_rptr [NumL2Ports-1:0] ), + .slvport_b_data_o ( axi_slv_ext_b_data [NumL2Ports-1:0] ), + .slvport_b_wptr_o ( axi_slv_ext_b_wptr [NumL2Ports-1:0] ), + .slvport_b_rptr_i ( axi_slv_ext_b_rptr [NumL2Ports-1:0] ), + .slvport_r_data_o ( axi_slv_ext_r_data [NumL2Ports-1:0] ), + .slvport_r_wptr_o ( axi_slv_ext_r_wptr [NumL2Ports-1:0] ), + .slvport_r_rptr_i ( axi_slv_ext_r_rptr [NumL2Ports-1:0] ), + .slvport_w_data_i ( axi_slv_ext_w_data [NumL2Ports-1:0] ), + .slvport_w_wptr_i ( axi_slv_ext_w_wptr [NumL2Ports-1:0] ), + .slvport_w_rptr_o ( axi_slv_ext_w_rptr [NumL2Ports-1:0] ), + // verilog_lint: waive-start line-length + .l2_ecc_reg_async_mst_req_i ( ext_reg_async_slv_req_out [CarfieldRegBusSlvIdx.l2ecc-NumSyncRegSlv] ), + .l2_ecc_reg_async_mst_ack_o ( ext_reg_async_slv_ack_in [CarfieldRegBusSlvIdx.l2ecc-NumSyncRegSlv] ), + .l2_ecc_reg_async_mst_data_i ( ext_reg_async_slv_data_out[CarfieldRegBusSlvIdx.l2ecc-NumSyncRegSlv] ), + .l2_ecc_reg_async_mst_req_o ( ext_reg_async_slv_req_in [CarfieldRegBusSlvIdx.l2ecc-NumSyncRegSlv] ), + .l2_ecc_reg_async_mst_ack_i ( ext_reg_async_slv_ack_out [CarfieldRegBusSlvIdx.l2ecc-NumSyncRegSlv] ), + .l2_ecc_reg_async_mst_data_o ( ext_reg_async_slv_data_in [CarfieldRegBusSlvIdx.l2ecc-NumSyncRegSlv] ), + // verilog_lint: waive-stop line-length + .ecc_error_o ( l2_ecc_err ) + ); +end else begin: gen_no_l2 + assign l2_rst_n = '0; + assign l2_pwr_on_rst_n = '0; + assign l2_clk = '0; + assign car_regs_hw2reg.l2_isolate_status.d = '0; + assign car_regs_hw2reg.l2_isolate_status.de = '0; + assign l2_ecc_err = '0; +end // Safety Island logic [SafetyIslandCfg.NumInterrupts-1:0] safed_intrs; @@ -1302,7 +1237,6 @@ end // Collect interrupts for the safety island: private interrupts from mailboxes, shared interrupts // from the interrupt router. -// verilog_lint: waive-start line-length assign safed_intrs = { {(SafetyIslandCfg.NumInterrupts-(NumIntIntrs+CarfieldNumExtIntrs+NumMailboxesSafed)){1'b0}}, // Pad remaining interrupts // Shared interrupts (cheshire and carfield's peripherals interrupts) @@ -1318,156 +1252,159 @@ assign safed_intrs = { }; // verilog_lint: waive-stop line-length -if (IslandsCfg.EnSafetyIsland) begin : gen_safety_island -`ifndef SAFED_NETLIST - safety_island_synth_wrapper #( - .SafetyIslandCfg ( SafetyIslandCfg ), - - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiInIdWidth ( AxiSlvIdWidth ), - .AxiOutIdWidth ( Cfg.AxiMstIdWidth ), - - .AxiUserAtop ( 1'b1 ), - .AxiUserAtopMsb ( Cfg.AxiUserAmoMsb ), - .AxiUserAtopLsb ( Cfg.AxiUserAmoLsb ), - .AxiUserEccErr ( Cfg.AxiUserErrBits ), - .AxiUserEccErrBit ( Cfg.AxiUserErrLsb ), - - .DefaultUser ( 10'b00000_0_0101 ), - .LogDepth ( LogDepth ), - .CdcSyncStages ( SyncStages ), - .SyncStages ( SyncStages ), - - .SafetyIslandBaseAddr ( SafetyIslandBase ), - .SafetyIslandAddrRange ( SafetyIslandSize ), - .SafetyIslandMemOffset ( SafetyIslandMemOffset ), - .SafetyIslandPeriphOffset ( SafetyIslandPerOffset ), - - .NumDebug ( MaxHartId+1 ), - .SelectableHarts ( SafetyIslandExtHarts ), - .HartInfo ( SafetyIslandExtHartinfo ), +if (CarfieldIslandsCfg.safed.enable) begin : gen_safety_island + assign reset_vector[CarfieldDomainIdx.safed] = car_regs_reg2hw.safety_island_rst.q; + assign safety_rst_n = rsts_n[CarfieldDomainIdx.safed]; + assign safety_pwr_on_rst_n = pwr_on_rsts_n[CarfieldDomainIdx.safed]; + assign safety_clk = domain_clk_gated[CarfieldDomainIdx.safed]; + assign domain_clk_sel[CarfieldDomainIdx.safed] = car_regs_reg2hw.safety_island_clk_sel.q; + assign domain_clk_div_value[CarfieldDomainIdx.safed] = + car_regs_reg2hw.safety_island_clk_div_value.q; + assign domain_clk_div_changed[CarfieldDomainIdx.safed] = + car_regs_reg2hw.safety_island_clk_div_value.qe; + assign domain_clk_en[CarfieldDomainIdx.safed] = car_regs_reg2hw.safety_island_clk_en.q; + + assign slave_isolate_req[SafetyIslandSlvIdx] = car_regs_reg2hw.safety_island_isolate.q; + assign car_regs_hw2reg.safety_island_isolate_status.d = slave_isolated[SafetyIslandSlvIdx]; + assign car_regs_hw2reg.safety_island_isolate_status.de = 1'b1; + assign slave_isolated[SafetyIslandSlvIdx] = slave_isolated_rsp[SafetyIslandSlvIdx] & + master_isolated_rsp[SafetyIslandMstIdx]; + + for (genvar i = 0; i < CheshireNumIntHarts; i++ ) begin : gen_hostd_mbox_intrs + assign hostd_safed_mbox_intr [i] = snd_mbox_intrs[HostdMboxOffset + 2*CheshireNumIntHarts + i]; + end + + for (genvar i = 0; i < CheshireNumIntHarts; i++ ) begin : gen_safed_mbox_intr + assign safed_hostd_mbox_intr [i] = snd_mbox_intrs[SafedMboxOffset + CheshireNumIntHarts + 1]; + end + assign safed_secd_mbox_intr = snd_mbox_intrs[SafedMboxOffset + CheshireNumIntHarts + 0]; + + + `ifndef SAFED_NETLIST + safety_island_synth_wrapper #( + .SafetyIslandCfg ( SafetyIslandCfg ), + + .AxiAddrWidth ( Cfg.AddrWidth ), + .AxiDataWidth ( Cfg.AxiDataWidth ), + .AxiUserWidth ( Cfg.AxiUserWidth ), + .AxiInIdWidth ( AxiSlvIdWidth ), + .AxiOutIdWidth ( Cfg.AxiMstIdWidth ), + + .AxiUserAtop ( 1'b1 ), + .AxiUserAtopMsb ( Cfg.AxiUserAmoMsb ), + .AxiUserAtopLsb ( Cfg.AxiUserAmoLsb ), + .AxiUserEccErr ( Cfg.AxiUserErrBits ), + .AxiUserEccErrBit ( Cfg.AxiUserErrLsb ), + + .DefaultUser ( 10'b00000_0_0101 ), + .LogDepth ( LogDepth ), + .CdcSyncStages ( SyncStages ), + .SyncStages ( SyncStages ), + + .SafetyIslandBaseAddr ( CarfieldIslandsCfg.safed.base ), + .SafetyIslandAddrRange ( CarfieldIslandsCfg.safed.size ), + .SafetyIslandMemOffset ( SafetyIslandMemOffset ), + .SafetyIslandPeriphOffset ( SafetyIslandPerOffset ), + + .NumDebug ( MaxHartId+1 ), + .SelectableHarts ( SafetyIslandExtHarts ), + .HartInfo ( SafetyIslandExtHartinfo ), + + .axi_in_aw_chan_t ( carfield_axi_slv_aw_chan_t ), + .axi_in_w_chan_t ( carfield_axi_slv_w_chan_t ), + .axi_in_b_chan_t ( carfield_axi_slv_b_chan_t ), + .axi_in_ar_chan_t ( carfield_axi_slv_ar_chan_t ), + .axi_in_r_chan_t ( carfield_axi_slv_r_chan_t ), + .axi_in_req_t ( carfield_axi_slv_req_t ), + .axi_in_resp_t ( carfield_axi_slv_rsp_t ), + + .axi_out_aw_chan_t ( carfield_axi_mst_aw_chan_t ), + .axi_out_w_chan_t ( carfield_axi_mst_w_chan_t ), + .axi_out_b_chan_t ( carfield_axi_mst_b_chan_t ), + .axi_out_ar_chan_t ( carfield_axi_mst_ar_chan_t ), + .axi_out_r_chan_t ( carfield_axi_mst_r_chan_t ), + .axi_out_req_t ( carfield_axi_mst_req_t ), + .axi_out_resp_t ( carfield_axi_mst_rsp_t ), + + .AsyncAxiInAwWidth ( CarfieldAxiSlvAwWidth ), + .AsyncAxiInWWidth ( CarfieldAxiSlvWWidth ), + .AsyncAxiInBWidth ( CarfieldAxiSlvBWidth ), + .AsyncAxiInArWidth ( CarfieldAxiSlvArWidth ), + .AsyncAxiInRWidth ( CarfieldAxiSlvRWidth ), + + .AsyncAxiOutAwWidth ( CarfieldAxiMstAwWidth ), + .AsyncAxiOutWWidth ( CarfieldAxiMstWWidth ), + .AsyncAxiOutBWidth ( CarfieldAxiMstBWidth ), + .AsyncAxiOutArWidth ( CarfieldAxiMstArWidth ), + .AsyncAxiOutRWidth ( CarfieldAxiMstRWidth ) + ) i_safety_island_wrap ( + `else + safety_island i_safety_island_wrap ( + `endif + .clk_i ( safety_clk ), + .ref_clk_i ( rt_clk_i ), + .rst_ni ( safety_rst_n ), + .pwr_on_rst_ni ( safety_pwr_on_rst_n ), + .test_enable_i ( test_mode_i ), + .bootmode_i ( bootmode_safe_isln_i ), + .fetch_en_i ( car_regs_reg2hw.safety_island_fetch_enable ), // To SoC Bus + .axi_isolate_i ( slave_isolate_req [SafetyIslandSlvIdx] ), // To SoC Bus + .axi_isolated_o ( master_isolated_rsp [SafetyIslandMstIdx] ), + .irqs_i ( safed_intrs ), + .debug_req_o ( safed_dbg_reqs ), + .jtag_tck_i ( jtag_safety_island_tck_i ), + .jtag_trst_ni ( jtag_safety_island_trst_ni ), + .jtag_tms_i ( jtag_safety_island_tms_i ), + .jtag_tdi_i ( jtag_safety_island_tdi_i ), + .jtag_tdo_o ( jtag_safety_island_tdo_o ), + // Slave port + .async_axi_in_aw_data_i ( axi_slv_ext_aw_data [SafetyIslandSlvIdx] ), + .async_axi_in_aw_wptr_i ( axi_slv_ext_aw_wptr [SafetyIslandSlvIdx] ), + .async_axi_in_aw_rptr_o ( axi_slv_ext_aw_rptr [SafetyIslandSlvIdx] ), + .async_axi_in_w_data_i ( axi_slv_ext_w_data [SafetyIslandSlvIdx] ), + .async_axi_in_w_wptr_i ( axi_slv_ext_w_wptr [SafetyIslandSlvIdx] ), + .async_axi_in_w_rptr_o ( axi_slv_ext_w_rptr [SafetyIslandSlvIdx] ), + .async_axi_in_b_data_o ( axi_slv_ext_b_data [SafetyIslandSlvIdx] ), + .async_axi_in_b_wptr_o ( axi_slv_ext_b_wptr [SafetyIslandSlvIdx] ), + .async_axi_in_b_rptr_i ( axi_slv_ext_b_rptr [SafetyIslandSlvIdx] ), + .async_axi_in_ar_data_i ( axi_slv_ext_ar_data [SafetyIslandSlvIdx] ), + .async_axi_in_ar_wptr_i ( axi_slv_ext_ar_wptr [SafetyIslandSlvIdx] ), + .async_axi_in_ar_rptr_o ( axi_slv_ext_ar_rptr [SafetyIslandSlvIdx] ), + .async_axi_in_r_data_o ( axi_slv_ext_r_data [SafetyIslandSlvIdx] ), + .async_axi_in_r_wptr_o ( axi_slv_ext_r_wptr [SafetyIslandSlvIdx] ), + .async_axi_in_r_rptr_i ( axi_slv_ext_r_rptr [SafetyIslandSlvIdx] ), + // Master port + .async_axi_out_aw_data_o ( axi_mst_ext_aw_data [SafetyIslandMstIdx] ), + .async_axi_out_aw_wptr_o ( axi_mst_ext_aw_wptr [SafetyIslandMstIdx] ), + .async_axi_out_aw_rptr_i ( axi_mst_ext_aw_rptr [SafetyIslandMstIdx] ), + .async_axi_out_w_data_o ( axi_mst_ext_w_data [SafetyIslandMstIdx] ), + .async_axi_out_w_wptr_o ( axi_mst_ext_w_wptr [SafetyIslandMstIdx] ), + .async_axi_out_w_rptr_i ( axi_mst_ext_w_rptr [SafetyIslandMstIdx] ), + .async_axi_out_b_data_i ( axi_mst_ext_b_data [SafetyIslandMstIdx] ), + .async_axi_out_b_wptr_i ( axi_mst_ext_b_wptr [SafetyIslandMstIdx] ), + .async_axi_out_b_rptr_o ( axi_mst_ext_b_rptr [SafetyIslandMstIdx] ), + .async_axi_out_ar_data_o ( axi_mst_ext_ar_data [SafetyIslandMstIdx] ), + .async_axi_out_ar_wptr_o ( axi_mst_ext_ar_wptr [SafetyIslandMstIdx] ), + .async_axi_out_ar_rptr_i ( axi_mst_ext_ar_rptr [SafetyIslandMstIdx] ), + .async_axi_out_r_data_i ( axi_mst_ext_r_data [SafetyIslandMstIdx] ), + .async_axi_out_r_wptr_i ( axi_mst_ext_r_wptr [SafetyIslandMstIdx] ), + .async_axi_out_r_rptr_o ( axi_mst_ext_r_rptr [SafetyIslandMstIdx] ) + ); + end +else begin : gen_no_safety_island + assign safety_rst_n = '0; + assign safety_pwr_on_rst_n = '0; + assign safety_clk = '0; - .axi_in_aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .axi_in_w_chan_t ( carfield_axi_slv_w_chan_t ), - .axi_in_b_chan_t ( carfield_axi_slv_b_chan_t ), - .axi_in_ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .axi_in_r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_in_req_t ( carfield_axi_slv_req_t ), - .axi_in_resp_t ( carfield_axi_slv_rsp_t ), + assign car_regs_hw2reg.safety_island_isolate_status.d = '0; + assign car_regs_hw2reg.safety_island_isolate_status.de = '0; - .axi_out_aw_chan_t ( carfield_axi_mst_aw_chan_t ), - .axi_out_w_chan_t ( carfield_axi_mst_w_chan_t ), - .axi_out_b_chan_t ( carfield_axi_mst_b_chan_t ), - .axi_out_ar_chan_t ( carfield_axi_mst_ar_chan_t ), - .axi_out_r_chan_t ( carfield_axi_mst_r_chan_t ), - .axi_out_req_t ( carfield_axi_mst_req_t ), - .axi_out_resp_t ( carfield_axi_mst_rsp_t ), + assign hostd_safed_mbox_intr = '0; + assign safed_hostd_mbox_intr = '0; + assign safed_secd_mbox_intr = '0; - .AsyncAxiInAwWidth ( CarfieldAxiSlvAwWidth ), - .AsyncAxiInWWidth ( CarfieldAxiSlvWWidth ), - .AsyncAxiInBWidth ( CarfieldAxiSlvBWidth ), - .AsyncAxiInArWidth ( CarfieldAxiSlvArWidth ), - .AsyncAxiInRWidth ( CarfieldAxiSlvRWidth ), - - .AsyncAxiOutAwWidth ( CarfieldAxiMstAwWidth ), - .AsyncAxiOutWWidth ( CarfieldAxiMstWWidth ), - .AsyncAxiOutBWidth ( CarfieldAxiMstBWidth ), - .AsyncAxiOutArWidth ( CarfieldAxiMstArWidth ), - .AsyncAxiOutRWidth ( CarfieldAxiMstRWidth ) - ) i_safety_island_wrap ( -`else - safety_island i_safety_island_wrap ( -`endif - .clk_i ( safety_clk ), - .ref_clk_i ( rt_clk_i ), - .rst_ni ( safety_rst_n ), - .pwr_on_rst_ni ( safety_pwr_on_rst_n ), - .test_enable_i ( test_mode_i ), - .bootmode_i ( bootmode_safe_isln_i ), - .fetch_en_i ( car_regs_reg2hw.safety_island_fetch_enable ), // To SoC Bus - .axi_isolate_i ( slave_isolate_req [SafetyIslandSlvIdx] ), // To SoC Bus - .axi_isolated_o ( master_isolated_rsp [SafetyIslandMstIdx] ), - .irqs_i ( safed_intrs ), - .debug_req_o ( safed_dbg_reqs ), - .jtag_tck_i ( jtag_safety_island_tck_i ), - .jtag_trst_ni ( jtag_safety_island_trst_ni ), - .jtag_tms_i ( jtag_safety_island_tms_i ), - .jtag_tdi_i ( jtag_safety_island_tdi_i ), - .jtag_tdo_o ( jtag_safety_island_tdo_o ), - // Slave port - .async_axi_in_aw_data_i ( axi_slv_ext_aw_data [SafetyIslandSlvIdx] ), - .async_axi_in_aw_wptr_i ( axi_slv_ext_aw_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_aw_rptr_o ( axi_slv_ext_aw_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_w_data_i ( axi_slv_ext_w_data [SafetyIslandSlvIdx] ), - .async_axi_in_w_wptr_i ( axi_slv_ext_w_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_w_rptr_o ( axi_slv_ext_w_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_b_data_o ( axi_slv_ext_b_data [SafetyIslandSlvIdx] ), - .async_axi_in_b_wptr_o ( axi_slv_ext_b_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_b_rptr_i ( axi_slv_ext_b_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_ar_data_i ( axi_slv_ext_ar_data [SafetyIslandSlvIdx] ), - .async_axi_in_ar_wptr_i ( axi_slv_ext_ar_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_ar_rptr_o ( axi_slv_ext_ar_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_r_data_o ( axi_slv_ext_r_data [SafetyIslandSlvIdx] ), - .async_axi_in_r_wptr_o ( axi_slv_ext_r_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_r_rptr_i ( axi_slv_ext_r_rptr [SafetyIslandSlvIdx] ), - // Master port - .async_axi_out_aw_data_o ( axi_mst_ext_aw_data [SafetyIslandMstIdx] ), - .async_axi_out_aw_wptr_o ( axi_mst_ext_aw_wptr [SafetyIslandMstIdx] ), - .async_axi_out_aw_rptr_i ( axi_mst_ext_aw_rptr [SafetyIslandMstIdx] ), - .async_axi_out_w_data_o ( axi_mst_ext_w_data [SafetyIslandMstIdx] ), - .async_axi_out_w_wptr_o ( axi_mst_ext_w_wptr [SafetyIslandMstIdx] ), - .async_axi_out_w_rptr_i ( axi_mst_ext_w_rptr [SafetyIslandMstIdx] ), - .async_axi_out_b_data_i ( axi_mst_ext_b_data [SafetyIslandMstIdx] ), - .async_axi_out_b_wptr_i ( axi_mst_ext_b_wptr [SafetyIslandMstIdx] ), - .async_axi_out_b_rptr_o ( axi_mst_ext_b_rptr [SafetyIslandMstIdx] ), - .async_axi_out_ar_data_o ( axi_mst_ext_ar_data [SafetyIslandMstIdx] ), - .async_axi_out_ar_wptr_o ( axi_mst_ext_ar_wptr [SafetyIslandMstIdx] ), - .async_axi_out_ar_rptr_i ( axi_mst_ext_ar_rptr [SafetyIslandMstIdx] ), - .async_axi_out_r_data_i ( axi_mst_ext_r_data [SafetyIslandMstIdx] ), - .async_axi_out_r_wptr_i ( axi_mst_ext_r_wptr [SafetyIslandMstIdx] ), - .async_axi_out_r_rptr_o ( axi_mst_ext_r_rptr [SafetyIslandMstIdx] ) - ); -end -else begin : gen_no_safety_island - assign jtag_safety_island_tdo_o = jtag_safety_island_tdi_i; - cdc_dst_axi_err #( - .AxiInIdWidth ( AxiSlvIdWidth ), - .LogDepth ( LogDepth ), - .CdcSyncStages ( SyncStages ), - .axi_in_aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .axi_in_w_chan_t ( carfield_axi_slv_w_chan_t ), - .axi_in_b_chan_t ( carfield_axi_slv_b_chan_t ), - .axi_in_ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .axi_in_r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_in_resp_t ( carfield_axi_slv_rsp_t ), - .axi_in_req_t ( carfield_axi_slv_req_t ), - .AsyncAxiInAwWidth ( CarfieldAxiSlvAwWidth ), - .AsyncAxiInWWidth ( CarfieldAxiSlvWWidth ), - .AsyncAxiInBWidth ( CarfieldAxiSlvBWidth ), - .AsyncAxiInArWidth ( CarfieldAxiSlvArWidth ), - .AsyncAxiInRWidth ( CarfieldAxiSlvRWidth ) - ) i_safety_island_axi_err ( - .clk_i ( safety_clk ), - .rst_ni ( safety_rst_n ), - .pwr_on_rst_ni ( safety_pwr_on_rst_n ), - .async_axi_in_aw_data_i ( axi_slv_ext_aw_data [SafetyIslandSlvIdx] ), - .async_axi_in_aw_wptr_i ( axi_slv_ext_aw_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_aw_rptr_o ( axi_slv_ext_aw_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_ar_data_i ( axi_slv_ext_ar_data [SafetyIslandSlvIdx] ), - .async_axi_in_ar_wptr_i ( axi_slv_ext_ar_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_ar_rptr_o ( axi_slv_ext_ar_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_w_data_i ( axi_slv_ext_w_data [SafetyIslandSlvIdx] ), - .async_axi_in_w_wptr_i ( axi_slv_ext_w_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_w_rptr_o ( axi_slv_ext_w_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_r_data_o ( axi_slv_ext_r_data [SafetyIslandSlvIdx] ), - .async_axi_in_r_wptr_o ( axi_slv_ext_r_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_r_rptr_i ( axi_slv_ext_r_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_b_data_o ( axi_slv_ext_b_data [SafetyIslandSlvIdx] ), - .async_axi_in_b_wptr_o ( axi_slv_ext_b_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_b_rptr_i ( axi_slv_ext_b_rptr [SafetyIslandSlvIdx] ) - ); + assign safed_dbg_reqs = '0; + assign jtag_safety_island_tdo_o = '0; end // PULP integer cluster @@ -1477,191 +1414,235 @@ assign car_regs_hw2reg.pulp_cluster_eoc.de = 1'b1; assign car_regs_hw2reg.pulp_cluster_busy.de = 1'b1; assign car_regs_hw2reg.pulp_cluster_eoc.d = pulpcl_eoc; -if (IslandsCfg.EnPulpCluster) begin : gen_pulp_cluster +if (CarfieldIslandsCfg.pulp.enable) begin : gen_pulp_cluster + assign pulp_rst_n = rsts_n[CarfieldDomainIdx.pulp]; + assign pulp_pwr_on_rst_n = pwr_on_rsts_n[CarfieldDomainIdx.pulp]; + assign pulp_clk = domain_clk_gated[CarfieldDomainIdx.pulp]; + assign reset_vector[CarfieldDomainIdx.pulp] = car_regs_reg2hw.pulp_cluster_rst.q; + + assign domain_clk_sel[CarfieldDomainIdx.pulp] = + car_regs_reg2hw.pulp_cluster_clk_sel.q; + assign domain_clk_div_value[CarfieldDomainIdx.pulp] = + car_regs_reg2hw.pulp_cluster_clk_div_value.q; + assign domain_clk_div_changed[CarfieldDomainIdx.pulp] = + car_regs_reg2hw.pulp_cluster_clk_div_value.qe; + assign domain_clk_en[CarfieldDomainIdx.pulp] = + car_regs_reg2hw.pulp_cluster_clk_en.q; + + assign slave_isolate_req[IntClusterSlvIdx] = car_regs_reg2hw.pulp_cluster_isolate.q; + assign car_regs_hw2reg.pulp_cluster_isolate_status.d = slave_isolated[IntClusterSlvIdx]; + assign car_regs_hw2reg.pulp_cluster_isolate_status.de = 1'b1; + + assign slave_isolated[IntClusterSlvIdx] = slave_isolated_rsp[IntClusterSlvIdx] & + master_isolated_rsp[IntClusterMstIdx]; + `ifndef INT_CLUSTER_NETLIST -pulp_cluster #( - .NB_CORES ( IntClusterNumCores ), - .NB_HWPE_PORTS ( IntClusterNumHwpePorts ), - .NB_DMAS ( IntClusterNumDmas ), - .NB_MPERIPHS ( IntClusterNumMstPer ), - .NB_SPERIPHS ( IntClusterNumSlvPer ), - .SynchStages ( SyncStages ), - .TCDM_SIZE ( IntClusterTcdmSize ), - .NB_TCDM_BANKS ( IntClusterTcdmBanks ), - .HWPE_PRESENT ( IntClusterHwpePresent ), - .USE_HETEROGENEOUS_INTERCONNECT ( IntClusterUseHci ), - .SET_ASSOCIATIVE ( IntClusterSetAssociative ), - .NB_CACHE_BANKS ( IntClusterNumCacheBanks ), - .CACHE_LINE ( IntClusterNumCacheLines ), - .CACHE_SIZE ( IntClusterCacheSize ), - .L0_BUFFER_FEATURE ( "DISABLED" ), - .MULTICAST_FEATURE ( "DISABLED" ), - .SHARED_ICACHE ( "ENABLED" ), - .DIRECT_MAPPED_FEATURE ( "DISABLED" ), - .L2_SIZE ( L2MemSize ), - .USE_REDUCED_TAG ( "TRUE" ), - .DEBUG_START_ADDR ( IntClusterDbgStart ), - .ROM_BOOT_ADDR ( IntClusterBootAddr ), - .BOOT_ADDR ( IntClusterBootAddr ), - .INSTR_RDATA_WIDTH ( IntClusterInstrRdataWidth ), - .CLUST_FPU ( IntClusterFpu ), - .CLUST_FP_DIVSQRT ( IntClusterFpuDivSqrt ), - .CLUST_SHARED_FP ( IntClusterFpu ), - .CLUST_SHARED_FP_DIVSQRT ( IntClusterFpuDivSqrt ), - .NumAxiMst ( IntClusterNumAxiMst ), - .NumAxiSlv ( IntClusterNumAxiSlv ), - .AXI_ADDR_WIDTH ( Cfg.AddrWidth ), - .AXI_DATA_C2S_WIDTH ( Cfg.AxiDataWidth ), - .AXI_DATA_S2C_WIDTH ( Cfg.AxiDataWidth ), - .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), - .AXI_ID_IN_WIDTH ( IntClusterAxiIdInWidth ), - .AXI_ID_OUT_WIDTH ( IntClusterAxiIdOutWidth ), - .LOG_DEPTH ( LogDepth ), - .BaseAddr ( IntClusterBase ), - .CdcSynchStages ( SyncStages ) -) i_integer_cluster ( + pulp_cluster #( + .NB_CORES ( IntClusterNumCores ), + .NB_HWPE_PORTS ( IntClusterNumHwpePorts ), + .NB_DMAS ( IntClusterNumDmas ), + .NB_MPERIPHS ( IntClusterNumMstPer ), + .NB_SPERIPHS ( IntClusterNumSlvPer ), + .SynchStages ( SyncStages ), + .TCDM_SIZE ( IntClusterTcdmSize ), + .NB_TCDM_BANKS ( IntClusterTcdmBanks ), + .HWPE_PRESENT ( IntClusterHwpePresent ), + .USE_HETEROGENEOUS_INTERCONNECT ( IntClusterUseHci ), + .SET_ASSOCIATIVE ( IntClusterSetAssociative ), + .NB_CACHE_BANKS ( IntClusterNumCacheBanks ), + .CACHE_LINE ( IntClusterNumCacheLines ), + .CACHE_SIZE ( IntClusterCacheSize ), + .L0_BUFFER_FEATURE ( "DISABLED" ), + .MULTICAST_FEATURE ( "DISABLED" ), + .SHARED_ICACHE ( "ENABLED" ), + .DIRECT_MAPPED_FEATURE ( "DISABLED" ), + .L2_SIZE ( L2MemSize ), + .USE_REDUCED_TAG ( "TRUE" ), + .DEBUG_START_ADDR ( IntClusterDbgStart ), + .ROM_BOOT_ADDR ( IntClusterBootAddr ), + .BOOT_ADDR ( IntClusterBootAddr ), + .INSTR_RDATA_WIDTH ( IntClusterInstrRdataWidth ), + .CLUST_FPU ( IntClusterFpu ), + .CLUST_FP_DIVSQRT ( IntClusterFpuDivSqrt ), + .CLUST_SHARED_FP ( IntClusterFpu ), + .CLUST_SHARED_FP_DIVSQRT ( IntClusterFpuDivSqrt ), + .NumAxiMst ( IntClusterNumAxiMst ), + .NumAxiSlv ( IntClusterNumAxiSlv ), + .AXI_ADDR_WIDTH ( Cfg.AddrWidth ), + .AXI_DATA_C2S_WIDTH ( Cfg.AxiDataWidth ), + .AXI_DATA_S2C_WIDTH ( Cfg.AxiDataWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), + .AXI_ID_IN_WIDTH ( IntClusterAxiIdInWidth ), + .AXI_ID_OUT_WIDTH ( IntClusterAxiIdOutWidth ), + .LOG_DEPTH ( LogDepth ), + .BaseAddr ( CarfieldIslandsCfg.pulp.base ), + .CdcSynchStages ( SyncStages ) + ) i_integer_cluster ( `else -int_cluster i_integer_cluster ( + int_cluster i_integer_cluster ( `endif - .clk_i ( pulp_clk ), - .rst_ni ( pulp_rst_n ), - .pwr_on_rst_ni ( pulp_pwr_on_rst_n ), - .ref_clk_i ( rt_clk_i ), - .pmu_mem_pwdn_i ( '0 ), - .base_addr_i ( IntClusterBase[31:28] ), - .test_mode_i ( test_mode_i ), - .cluster_id_i ( IntClusterIndex ), - .en_sa_boot_i ( car_regs_reg2hw.pulp_cluster_boot_enable ), - .fetch_en_i ( car_regs_reg2hw.pulp_cluster_fetch_enable ), - .eoc_o ( pulpcl_eoc ), - .busy_o ( car_regs_hw2reg.pulp_cluster_busy.d ), - .axi_isolate_i ( slave_isolate_req [IntClusterSlvIdx] ), - .axi_isolated_o ( master_isolated_rsp [IntClusterMstIdx] ), - .dma_pe_evt_ack_i ( '0 ), - .dma_pe_evt_valid_o ( ), - .dma_pe_irq_ack_i ( '1 ), - .dma_pe_irq_valid_o ( ), - .dbg_irq_valid_i ( pulpcl_dbg_reqs ), - .mbox_irq_i ( pulpcl_mbox_intr ), - .pf_evt_ack_i ( '1 ), - .pf_evt_valid_o ( ), - .async_cluster_events_wptr_i ( '0 ), - .async_cluster_events_rptr_o ( ), - .async_cluster_events_data_i ( '0 ), - // AXI4 Slave port - .async_data_slave_aw_data_i ( axi_slv_intcluster_aw_data ), - .async_data_slave_aw_wptr_i ( axi_slv_intcluster_aw_wptr ), - .async_data_slave_aw_rptr_o ( axi_slv_intcluster_aw_rptr ), - .async_data_slave_ar_data_i ( axi_slv_intcluster_ar_data ), - .async_data_slave_ar_wptr_i ( axi_slv_intcluster_ar_wptr ), - .async_data_slave_ar_rptr_o ( axi_slv_intcluster_ar_rptr ), - .async_data_slave_w_data_i ( axi_slv_intcluster_w_data ), - .async_data_slave_w_wptr_i ( axi_slv_intcluster_w_wptr ), - .async_data_slave_w_rptr_o ( axi_slv_intcluster_w_rptr ), - .async_data_slave_r_data_o ( axi_slv_intcluster_r_data ), - .async_data_slave_r_wptr_o ( axi_slv_intcluster_r_wptr ), - .async_data_slave_r_rptr_i ( axi_slv_intcluster_r_rptr ), - .async_data_slave_b_data_o ( axi_slv_intcluster_b_data ), - .async_data_slave_b_wptr_o ( axi_slv_intcluster_b_wptr ), - .async_data_slave_b_rptr_i ( axi_slv_intcluster_b_rptr ), - // AXI4 Master Port - .async_data_master_aw_data_o ( axi_mst_intcluster_aw_data ), - .async_data_master_aw_wptr_o ( axi_mst_intcluster_aw_wptr ), - .async_data_master_aw_rptr_i ( axi_mst_intcluster_aw_rptr ), - .async_data_master_ar_data_o ( axi_mst_intcluster_ar_data ), - .async_data_master_ar_wptr_o ( axi_mst_intcluster_ar_wptr ), - .async_data_master_ar_rptr_i ( axi_mst_intcluster_ar_rptr ), - .async_data_master_w_data_o ( axi_mst_intcluster_w_data ), - .async_data_master_w_wptr_o ( axi_mst_intcluster_w_wptr ), - .async_data_master_w_rptr_i ( axi_mst_intcluster_w_rptr ), - .async_data_master_r_data_i ( axi_mst_intcluster_r_data ), - .async_data_master_r_wptr_i ( axi_mst_intcluster_r_wptr ), - .async_data_master_r_rptr_o ( axi_mst_intcluster_r_rptr ), - .async_data_master_b_data_i ( axi_mst_intcluster_b_data ), - .async_data_master_b_wptr_i ( axi_mst_intcluster_b_wptr ), - .async_data_master_b_rptr_o ( axi_mst_intcluster_b_rptr ) -); -end -else begin : gen_no_pulp_cluster - cdc_dst_axi_err #( - .AxiInIdWidth ( IntClusterAxiIdInWidth ), - .LogDepth ( LogDepth ), - .CdcSyncStages ( SyncStages ), - .axi_in_aw_chan_t ( axi_intcluster_slv_aw_chan_t ), - .axi_in_w_chan_t ( axi_intcluster_slv_w_chan_t ), - .axi_in_b_chan_t ( axi_intcluster_slv_b_chan_t ), - .axi_in_ar_chan_t ( axi_intcluster_slv_ar_chan_t ), - .axi_in_r_chan_t ( axi_intcluster_slv_r_chan_t ), - .axi_in_resp_t ( axi_intcluster_slv_rsp_t ), - .axi_in_req_t ( axi_intcluster_slv_req_t ), - .AsyncAxiInAwWidth ( (2**LogDepth)*axi_pkg::aw_width(Cfg.AddrWidth,IntClusterAxiIdInWidth, - Cfg.AxiUserWidth)), - .AsyncAxiInWWidth ( (2**LogDepth)*axi_pkg::w_width(Cfg.AxiDataWidth,Cfg.AxiUserWidth) ), - .AsyncAxiInBWidth ( (2**LogDepth)*axi_pkg::b_width(IntClusterAxiIdInWidth,Cfg.AxiUserWidth) ), - .AsyncAxiInArWidth ( (2**LogDepth)*axi_pkg::ar_width(Cfg.AddrWidth,IntClusterAxiIdInWidth, - Cfg.AxiUserWidth)), - .AsyncAxiInRWidth ( (2**LogDepth)*axi_pkg::r_width(Cfg.AxiDataWidth,IntClusterAxiIdInWidth, - Cfg.AxiUserWidth)) - ) i_pulp_cluster_axi_err ( - .clk_i ( pulp_clk ), - .rst_ni ( pulp_rst_n ), - .pwr_on_rst_ni ( pulp_pwr_on_rst_n ), - .async_axi_in_aw_data_i ( axi_slv_intcluster_aw_data ), - .async_axi_in_aw_wptr_i ( axi_slv_intcluster_aw_wptr ), - .async_axi_in_aw_rptr_o ( axi_slv_intcluster_aw_rptr ), - .async_axi_in_ar_data_i ( axi_slv_intcluster_ar_data ), - .async_axi_in_ar_wptr_i ( axi_slv_intcluster_ar_wptr ), - .async_axi_in_ar_rptr_o ( axi_slv_intcluster_ar_rptr ), - .async_axi_in_w_data_i ( axi_slv_intcluster_w_data ), - .async_axi_in_w_wptr_i ( axi_slv_intcluster_w_wptr ), - .async_axi_in_w_rptr_o ( axi_slv_intcluster_w_rptr ), - .async_axi_in_r_data_o ( axi_slv_intcluster_r_data ), - .async_axi_in_r_wptr_o ( axi_slv_intcluster_r_wptr ), - .async_axi_in_r_rptr_i ( axi_slv_intcluster_r_rptr ), - .async_axi_in_b_data_o ( axi_slv_intcluster_b_data ), - .async_axi_in_b_wptr_o ( axi_slv_intcluster_b_wptr ), - .async_axi_in_b_rptr_i ( axi_slv_intcluster_b_rptr ) + .clk_i ( pulp_clk ), + .rst_ni ( pulp_rst_n ), + .pwr_on_rst_ni ( pulp_pwr_on_rst_n ), + .ref_clk_i ( rt_clk_i ), + .pmu_mem_pwdn_i ( '0 ), + .base_addr_i ( CarfieldIslandsCfg.pulp.base[31:28] ), + .test_mode_i ( test_mode_i ), + .cluster_id_i ( IntClusterIndex ), + .en_sa_boot_i ( car_regs_reg2hw.pulp_cluster_boot_enable ), + .fetch_en_i ( car_regs_reg2hw.pulp_cluster_fetch_enable ), + .eoc_o ( pulpcl_eoc ), + .busy_o ( car_regs_hw2reg.pulp_cluster_busy.d ), + .axi_isolate_i ( slave_isolate_req [IntClusterSlvIdx] ), + .axi_isolated_o ( master_isolated_rsp [IntClusterMstIdx] ), + .dma_pe_evt_ack_i ( '0 ), + .dma_pe_evt_valid_o ( ), + .dma_pe_irq_ack_i ( '1 ), + .dma_pe_irq_valid_o ( ), + .dbg_irq_valid_i ( pulpcl_dbg_reqs ), + .mbox_irq_i ( pulpcl_mbox_intr ), + .pf_evt_ack_i ( '1 ), + .pf_evt_valid_o ( ), + .async_cluster_events_wptr_i ( '0 ), + .async_cluster_events_rptr_o ( ), + .async_cluster_events_data_i ( '0 ), + // AXI4 Slave port + .async_data_slave_aw_data_i ( axi_slv_intcluster_aw_data ), + .async_data_slave_aw_wptr_i ( axi_slv_intcluster_aw_wptr ), + .async_data_slave_aw_rptr_o ( axi_slv_intcluster_aw_rptr ), + .async_data_slave_ar_data_i ( axi_slv_intcluster_ar_data ), + .async_data_slave_ar_wptr_i ( axi_slv_intcluster_ar_wptr ), + .async_data_slave_ar_rptr_o ( axi_slv_intcluster_ar_rptr ), + .async_data_slave_w_data_i ( axi_slv_intcluster_w_data ), + .async_data_slave_w_wptr_i ( axi_slv_intcluster_w_wptr ), + .async_data_slave_w_rptr_o ( axi_slv_intcluster_w_rptr ), + .async_data_slave_r_data_o ( axi_slv_intcluster_r_data ), + .async_data_slave_r_wptr_o ( axi_slv_intcluster_r_wptr ), + .async_data_slave_r_rptr_i ( axi_slv_intcluster_r_rptr ), + .async_data_slave_b_data_o ( axi_slv_intcluster_b_data ), + .async_data_slave_b_wptr_o ( axi_slv_intcluster_b_wptr ), + .async_data_slave_b_rptr_i ( axi_slv_intcluster_b_rptr ), + // AXI4 Master Port + .async_data_master_aw_data_o ( axi_mst_intcluster_aw_data ), + .async_data_master_aw_wptr_o ( axi_mst_intcluster_aw_wptr ), + .async_data_master_aw_rptr_i ( axi_mst_intcluster_aw_rptr ), + .async_data_master_ar_data_o ( axi_mst_intcluster_ar_data ), + .async_data_master_ar_wptr_o ( axi_mst_intcluster_ar_wptr ), + .async_data_master_ar_rptr_i ( axi_mst_intcluster_ar_rptr ), + .async_data_master_w_data_o ( axi_mst_intcluster_w_data ), + .async_data_master_w_wptr_o ( axi_mst_intcluster_w_wptr ), + .async_data_master_w_rptr_i ( axi_mst_intcluster_w_rptr ), + .async_data_master_r_data_i ( axi_mst_intcluster_r_data ), + .async_data_master_r_wptr_i ( axi_mst_intcluster_r_wptr ), + .async_data_master_r_rptr_o ( axi_mst_intcluster_r_rptr ), + .async_data_master_b_data_i ( axi_mst_intcluster_b_data ), + .async_data_master_b_wptr_i ( axi_mst_intcluster_b_wptr ), + .async_data_master_b_rptr_o ( axi_mst_intcluster_b_rptr ) ); + + for (genvar i = 0; i < CheshireNumIntHarts; i++ ) begin : gen_pulpcl_mbox_intrs + assign pulpcl_hostd_mbox_intr [i] = snd_mbox_intrs[PulpclMboxOffset + i]; + end + assign pulpcl_safed_mbox_intr = snd_mbox_intrs[PulpclMboxOffset + CheshireNumIntHarts]; + + for (genvar i = 0; i < CheshireNumIntHarts; i++ ) begin : gen_hostd_pulpcl_mbox_intrs + assign hostd_pulpcl_mbox_intr [i] = snd_mbox_intrs[HostdMboxOffset + 0*CheshireNumIntHarts + i]; + end + + // Integer cluster + logic hostd_pulpcl_mbox_intr_ored; + assign hostd_pulpcl_mbox_intr_ored = |hostd_pulpcl_mbox_intr ; + assign pulpcl_mbox_intr = hostd_pulpcl_mbox_intr_ored | safed_pulpcl_mbox_intr; + + assign safed_pulpcl_mbox_intr = snd_mbox_intrs[SafedMboxOffset + CheshireNumIntHarts + 1]; +end else begin : gen_no_pulp_cluster + assign pulp_rst_n = '0; + assign pulp_pwr_on_rst_n = '0; + assign pulp_clk = '0; + assign pulpcl_safed_mbox_intr = '0; + assign pulpcl_hostd_mbox_intr = '0; + + assign hostd_pulpcl_mbox_intr = '0; + assign hostd_pulpcl_mbox_intr_ored = '0; + assign pulpcl_mbox_intr = '0; + + assign safed_pulpcl_mbox_intr = '0; + + assign pulpcl_eoc = '0; + assign car_regs_hw2reg.pulp_cluster_busy.d = '0; + + assign car_regs_hw2reg.pulp_cluster_isolate_status.d = '0; + assign car_regs_hw2reg.pulp_cluster_isolate_status.de = '0; + + assign axi_slv_intcluster_aw_rptr = '0; + assign axi_slv_intcluster_ar_rptr = '0; + assign axi_slv_intcluster_w_rptr = '0; + assign axi_slv_intcluster_r_data = '0; + assign axi_slv_intcluster_r_wptr = '0; + assign axi_slv_intcluster_b_data = '0; + assign axi_slv_intcluster_b_wptr = '0; + + assign axi_mst_intcluster_aw_data = '0; + assign axi_mst_intcluster_aw_wptr = '0; + assign axi_mst_intcluster_ar_data = '0; + assign axi_mst_intcluster_ar_wptr = '0; + assign axi_mst_intcluster_w_data = '0; + assign axi_mst_intcluster_w_wptr = '0; + assign axi_mst_intcluster_r_rptr = '0; + assign axi_mst_intcluster_b_rptr = '0; end // Floating Point Spatz Cluster - // Spatz cluster interrupts // msi (machine software interrupt): hostd, safed logic [spatz_cluster_pkg::NumCores-1:0] spatzcl_mbox_intr; // mti (machine timer interrupt) : hostd (RISC-V clint) // verilog_lint: waive-start line-length logic [spatz_cluster_pkg::NumCores-1:0] spatzcl_timer_intr; -// verilog_lint: waive-stop line-length +if (CarfieldIslandsCfg.spatz.enable) begin : gen_spatz_cluster + + assign reset_vector[CarfieldDomainIdx.spatz] = car_regs_reg2hw.spatz_cluster_rst.q; + + assign domain_clk_sel[CarfieldDomainIdx.spatz] = car_regs_reg2hw.spatz_cluster_clk_sel.q; + assign spatz_rst_n = rsts_n[CarfieldDomainIdx.spatz]; + assign spatz_pwr_on_rst_n = pwr_on_rsts_n[CarfieldDomainIdx.spatz]; + assign spatz_clk = domain_clk_gated[CarfieldDomainIdx.spatz]; + assign domain_clk_div_value[CarfieldDomainIdx.spatz] = car_regs_reg2hw.spatz_cluster_clk_div_value.q; + assign domain_clk_div_changed[CarfieldDomainIdx.spatz] = car_regs_reg2hw.spatz_cluster_clk_div_value.qe; + assign domain_clk_en[CarfieldDomainIdx.spatz] = car_regs_reg2hw.spatz_cluster_clk_en.q; -assign spatzcl_timer_intr = { chs_mti[FPClusterIntrHart1Idx], chs_mti[FPClusterIntrHart0Idx] }; + assign spatzcl_timer_intr = { chs_mti[FPClusterIntrHart1Idx], chs_mti[FPClusterIntrHart0Idx] }; + + assign slave_isolate_req[FPClusterSlvIdx] = car_regs_reg2hw.spatz_cluster_isolate.q; + assign car_regs_hw2reg.spatz_cluster_isolate_status.d = slave_isolated[FPClusterSlvIdx]; + assign car_regs_hw2reg.spatz_cluster_isolate_status.de = 1'b1; + + assign slave_isolated[FPClusterSlvIdx] = slave_isolated_rsp[FPClusterSlvIdx] & + master_isolated_rsp[FPClusterMstIdx]; -if (IslandsCfg.EnSpatzCluster) begin : gen_spatz_cluster `ifndef FP_CLUSTER_NETLIST spatz_cluster_wrapper #( - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiInIdWidth ( AxiSlvIdWidth ), - .AxiOutIdWidth ( Cfg.AxiMstIdWidth ), - .LogDepth ( LogDepth ), - .CdcSyncStages ( SyncStages ), - .SyncStages ( SyncStages ), - + .AxiAddrWidth ( Cfg.AddrWidth ), + .AxiDataWidth ( Cfg.AxiDataWidth ), + .AxiUserWidth ( Cfg.AxiUserWidth ), + .AxiInIdWidth ( AxiSlvIdWidth ), + .AxiOutIdWidth ( Cfg.AxiMstIdWidth ), + .IwcAxiIdOutWidth ( FpClustIwcAxiIdOutWidth ), + .LogDepth ( LogDepth ), + .CdcSyncStages ( SyncStages ), + .SyncStages ( SyncStages ), + .AxiMaxOutTrans ( FpClustAxiMaxOutTrans ), // AXI type IN .axi_in_resp_t ( carfield_axi_slv_rsp_t ), .axi_in_req_t ( carfield_axi_slv_req_t ), - .axi_in_aw_chan_t ( carfield_axi_slv_aw_chan_t ), .axi_in_w_chan_t ( carfield_axi_slv_w_chan_t ), .axi_in_b_chan_t ( carfield_axi_slv_b_chan_t ), .axi_in_ar_chan_t ( carfield_axi_slv_ar_chan_t ), .axi_in_r_chan_t ( carfield_axi_slv_r_chan_t ), - // AXI type OUT .axi_out_resp_t ( carfield_axi_mst_rsp_t ), .axi_out_req_t ( carfield_axi_mst_req_t ), - .axi_out_aw_chan_t ( carfield_axi_mst_aw_chan_t ), .axi_out_w_chan_t ( carfield_axi_mst_w_chan_t ), .axi_out_b_chan_t ( carfield_axi_mst_b_chan_t ), @@ -1695,166 +1676,211 @@ if (IslandsCfg.EnSpatzCluster) begin : gen_spatz_cluster .axi_isolated_o ( master_isolated_rsp [FPClusterMstIdx] ), //AXI FP Cluster Slave Port <- Carfield Master Port - .async_axi_in_aw_data_i ( axi_slv_ext_aw_data [FPClusterSlvIdx] ), - .async_axi_in_aw_wptr_i ( axi_slv_ext_aw_wptr [FPClusterSlvIdx] ), - .async_axi_in_aw_rptr_o ( axi_slv_ext_aw_rptr [FPClusterSlvIdx] ), - .async_axi_in_w_data_i ( axi_slv_ext_w_data [FPClusterSlvIdx] ), - .async_axi_in_w_wptr_i ( axi_slv_ext_w_wptr [FPClusterSlvIdx] ), - .async_axi_in_w_rptr_o ( axi_slv_ext_w_rptr [FPClusterSlvIdx] ), - .async_axi_in_b_data_o ( axi_slv_ext_b_data [FPClusterSlvIdx] ), - .async_axi_in_b_wptr_o ( axi_slv_ext_b_wptr [FPClusterSlvIdx] ), - .async_axi_in_b_rptr_i ( axi_slv_ext_b_rptr [FPClusterSlvIdx] ), - .async_axi_in_ar_data_i ( axi_slv_ext_ar_data [FPClusterSlvIdx] ), - .async_axi_in_ar_wptr_i ( axi_slv_ext_ar_wptr [FPClusterSlvIdx] ), - .async_axi_in_ar_rptr_o ( axi_slv_ext_ar_rptr [FPClusterSlvIdx] ), - .async_axi_in_r_data_o ( axi_slv_ext_r_data [FPClusterSlvIdx] ), - .async_axi_in_r_wptr_o ( axi_slv_ext_r_wptr [FPClusterSlvIdx] ), - .async_axi_in_r_rptr_i ( axi_slv_ext_r_rptr [FPClusterSlvIdx] ), - //AXI FP Cluster Master Port -> Carfield Slave Port - .async_axi_out_aw_data_o ( axi_mst_ext_aw_data [FPClusterMstIdx] ), - .async_axi_out_aw_wptr_o ( axi_mst_ext_aw_wptr [FPClusterMstIdx] ), - .async_axi_out_aw_rptr_i ( axi_mst_ext_aw_rptr [FPClusterMstIdx] ), - .async_axi_out_w_data_o ( axi_mst_ext_w_data [FPClusterMstIdx] ), - .async_axi_out_w_wptr_o ( axi_mst_ext_w_wptr [FPClusterMstIdx] ), - .async_axi_out_w_rptr_i ( axi_mst_ext_w_rptr [FPClusterMstIdx] ), - .async_axi_out_b_data_i ( axi_mst_ext_b_data [FPClusterMstIdx] ), - .async_axi_out_b_wptr_i ( axi_mst_ext_b_wptr [FPClusterMstIdx] ), - .async_axi_out_b_rptr_o ( axi_mst_ext_b_rptr [FPClusterMstIdx] ), - .async_axi_out_ar_data_o ( axi_mst_ext_ar_data [FPClusterMstIdx] ), - .async_axi_out_ar_wptr_o ( axi_mst_ext_ar_wptr [FPClusterMstIdx] ), - .async_axi_out_ar_rptr_i ( axi_mst_ext_ar_rptr [FPClusterMstIdx] ), - .async_axi_out_r_data_i ( axi_mst_ext_r_data [FPClusterMstIdx] ), - .async_axi_out_r_wptr_i ( axi_mst_ext_r_wptr [FPClusterMstIdx] ), - .async_axi_out_r_rptr_o ( axi_mst_ext_r_rptr [FPClusterMstIdx] ), - .cluster_probe_o ( car_regs_hw2reg.spatz_cluster_busy.d ) - ); -end -else begin : gen_no_spatz_cluster - cdc_dst_axi_err #( - .AxiInIdWidth ( AxiSlvIdWidth ), - .LogDepth ( LogDepth ), - .CdcSyncStages ( SyncStages ), - .axi_in_aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .axi_in_w_chan_t ( carfield_axi_slv_w_chan_t ), - .axi_in_b_chan_t ( carfield_axi_slv_b_chan_t ), - .axi_in_ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .axi_in_r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_in_resp_t ( carfield_axi_slv_rsp_t ), - .axi_in_req_t ( carfield_axi_slv_req_t ), - .AsyncAxiInAwWidth ( CarfieldAxiSlvAwWidth ), - .AsyncAxiInWWidth ( CarfieldAxiSlvWWidth ), - .AsyncAxiInBWidth ( CarfieldAxiSlvBWidth ), - .AsyncAxiInArWidth ( CarfieldAxiSlvArWidth ), - .AsyncAxiInRWidth ( CarfieldAxiSlvRWidth ) - ) i_spatz_cluster_axi_err ( - .clk_i ( spatz_clk ), - .rst_ni ( spatz_rst_n ), - .pwr_on_rst_ni ( spatz_pwr_on_rst_n ), - .async_axi_in_aw_data_i ( axi_slv_ext_aw_data [FPClusterSlvIdx] ), - .async_axi_in_aw_wptr_i ( axi_slv_ext_aw_wptr [FPClusterSlvIdx] ), - .async_axi_in_aw_rptr_o ( axi_slv_ext_aw_rptr [FPClusterSlvIdx] ), - .async_axi_in_ar_data_i ( axi_slv_ext_ar_data [FPClusterSlvIdx] ), - .async_axi_in_ar_wptr_i ( axi_slv_ext_ar_wptr [FPClusterSlvIdx] ), - .async_axi_in_ar_rptr_o ( axi_slv_ext_ar_rptr [FPClusterSlvIdx] ), - .async_axi_in_w_data_i ( axi_slv_ext_w_data [FPClusterSlvIdx] ), - .async_axi_in_w_wptr_i ( axi_slv_ext_w_wptr [FPClusterSlvIdx] ), - .async_axi_in_w_rptr_o ( axi_slv_ext_w_rptr [FPClusterSlvIdx] ), - .async_axi_in_r_data_o ( axi_slv_ext_r_data [FPClusterSlvIdx] ), - .async_axi_in_r_wptr_o ( axi_slv_ext_r_wptr [FPClusterSlvIdx] ), - .async_axi_in_r_rptr_i ( axi_slv_ext_r_rptr [FPClusterSlvIdx] ), - .async_axi_in_b_data_o ( axi_slv_ext_b_data [FPClusterSlvIdx] ), - .async_axi_in_b_wptr_o ( axi_slv_ext_b_wptr [FPClusterSlvIdx] ), - .async_axi_in_b_rptr_i ( axi_slv_ext_b_rptr [FPClusterSlvIdx] ) + .async_axi_in_aw_data_i ( axi_slv_ext_aw_data [FPClusterSlvIdx] ), + .async_axi_in_aw_wptr_i ( axi_slv_ext_aw_wptr [FPClusterSlvIdx] ), + .async_axi_in_aw_rptr_o ( axi_slv_ext_aw_rptr [FPClusterSlvIdx] ), + .async_axi_in_w_data_i ( axi_slv_ext_w_data [FPClusterSlvIdx] ), + .async_axi_in_w_wptr_i ( axi_slv_ext_w_wptr [FPClusterSlvIdx] ), + .async_axi_in_w_rptr_o ( axi_slv_ext_w_rptr [FPClusterSlvIdx] ), + .async_axi_in_b_data_o ( axi_slv_ext_b_data [FPClusterSlvIdx] ), + .async_axi_in_b_wptr_o ( axi_slv_ext_b_wptr [FPClusterSlvIdx] ), + .async_axi_in_b_rptr_i ( axi_slv_ext_b_rptr [FPClusterSlvIdx] ), + .async_axi_in_ar_data_i ( axi_slv_ext_ar_data [FPClusterSlvIdx] ), + .async_axi_in_ar_wptr_i ( axi_slv_ext_ar_wptr [FPClusterSlvIdx] ), + .async_axi_in_ar_rptr_o ( axi_slv_ext_ar_rptr [FPClusterSlvIdx] ), + .async_axi_in_r_data_o ( axi_slv_ext_r_data [FPClusterSlvIdx] ), + .async_axi_in_r_wptr_o ( axi_slv_ext_r_wptr [FPClusterSlvIdx] ), + .async_axi_in_r_rptr_i ( axi_slv_ext_r_rptr [FPClusterSlvIdx] ), + //AXI FP Cluster Master Port -> Carfield Slave Port + .async_axi_out_aw_data_o ( axi_mst_ext_aw_data [FPClusterMstIdx] ), + .async_axi_out_aw_wptr_o ( axi_mst_ext_aw_wptr [FPClusterMstIdx] ), + .async_axi_out_aw_rptr_i ( axi_mst_ext_aw_rptr [FPClusterMstIdx] ), + .async_axi_out_w_data_o ( axi_mst_ext_w_data [FPClusterMstIdx] ), + .async_axi_out_w_wptr_o ( axi_mst_ext_w_wptr [FPClusterMstIdx] ), + .async_axi_out_w_rptr_i ( axi_mst_ext_w_rptr [FPClusterMstIdx] ), + .async_axi_out_b_data_i ( axi_mst_ext_b_data [FPClusterMstIdx] ), + .async_axi_out_b_wptr_i ( axi_mst_ext_b_wptr [FPClusterMstIdx] ), + .async_axi_out_b_rptr_o ( axi_mst_ext_b_rptr [FPClusterMstIdx] ), + .async_axi_out_ar_data_o ( axi_mst_ext_ar_data [FPClusterMstIdx] ), + .async_axi_out_ar_wptr_o ( axi_mst_ext_ar_wptr [FPClusterMstIdx] ), + .async_axi_out_ar_rptr_i ( axi_mst_ext_ar_rptr [FPClusterMstIdx] ), + .async_axi_out_r_data_i ( axi_mst_ext_r_data [FPClusterMstIdx] ), + .async_axi_out_r_wptr_i ( axi_mst_ext_r_wptr [FPClusterMstIdx] ), + .async_axi_out_r_rptr_o ( axi_mst_ext_r_rptr [FPClusterMstIdx] ), + .cluster_probe_o ( car_regs_hw2reg.spatz_cluster_busy.d ) ); + + for (genvar i = 0; i < spatz_cluster_pkg::NumCores; i++ ) begin : gen_spatzcl_mbox_intrs_spatz_harts + assign safed_spatzcl_mbox_intr[i] = snd_mbox_intrs[i]; + for (genvar j = 0; j < CheshireNumIntHarts; j++ ) begin : gen_spatzcl_mbox_intrs_host_harts + assign hostd_spatzcl_mbox_intr[i][j] = snd_mbox_intrs[spatz_cluster_pkg::NumCores + (spatz_cluster_pkg::NumCores * j) + i]; + end + end + + for (genvar i = 0; i < CheshireNumIntHarts; i++ ) begin : gen_spatzcl_mbox_intrs + assign spatzcl_hostd_mbox_intr[i] = snd_mbox_intrs[SpatzMboxOffset + i]; + end + assign spatzcl_safed_mbox_intr = snd_mbox_intrs[SpatzMboxOffset + CheshireNumIntHarts]; + + logic [spatz_cluster_pkg::NumCores-1:0] hostd_spatzcl_mbox_intr_ored; + // Floating point cluster + for (genvar i = 0; i < spatz_cluster_pkg::NumCores; i++ ) begin : gen_spatzcl_mbox_intrs_or + assign hostd_spatzcl_mbox_intr_ored[i] = |hostd_spatzcl_mbox_intr[i]; + end + // For the spatz FP cluster SW interrupt in machine mode (msi), OR together interrupts coming from the + // host domain and the safe domain + assign spatzcl_mbox_intr = hostd_spatzcl_mbox_intr_ored | safed_spatzcl_mbox_intr; + // verilog_lint: waive-stop line-length +end else begin : gen_no_spatz_cluster + assign spatzcl_mbox_intr = '0; + assign spatzcl_timer_intr = '0; + assign car_regs_hw2reg.spatz_cluster_busy.d = '0; + assign safed_spatzcl_mbox_intr = '0; + assign hostd_spatzcl_mbox_intr = '0; + assign spatzcl_hostd_mbox_intr = '0; + assign spatzcl_safed_mbox_intr = '0; + assign spatz_rst_n = '0; + assign spatz_pwr_on_rst_n = '0; + assign spatz_clk = '0; end // Security Island logic secd_mbox_intr; -if (IslandsCfg.EnOpenTitan) begin : gen_secure_subsystem -`ifndef SECD_NETLIST -secure_subsystem_synth_wrap #( - .HartIdOffs ( OpnTitHartIdOffs ), - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiOutIdWidth ( Cfg.AxiMstIdWidth ), - .AxiOtAddrWidth ( Cfg.AddrWidth ), - .AxiOtDataWidth ( AxiNarrowDataWidth ), // TODO: why is this exposed? - .AxiOtUserWidth ( Cfg.AxiUserWidth ), - .AxiOtOutIdWidth ( Cfg.AxiMstIdWidth ), - .AsyncAxiOutAwWidth ( CarfieldAxiMstAwWidth ), - .AsyncAxiOutWWidth ( CarfieldAxiMstWWidth ), - .AsyncAxiOutBWidth ( CarfieldAxiMstBWidth ), - .AsyncAxiOutArWidth ( CarfieldAxiMstArWidth ), - .AsyncAxiOutRWidth ( CarfieldAxiMstRWidth ), - .axi_out_aw_chan_t ( carfield_axi_mst_aw_chan_t ), - .axi_out_w_chan_t ( carfield_axi_mst_w_chan_t ), - .axi_out_b_chan_t ( carfield_axi_mst_b_chan_t ), - .axi_out_ar_chan_t ( carfield_axi_mst_ar_chan_t ), - .axi_out_r_chan_t ( carfield_axi_mst_r_chan_t ), - .axi_out_req_t ( carfield_axi_mst_req_t ), - .axi_out_resp_t ( carfield_axi_mst_rsp_t ), - .axi_ot_out_aw_chan_t ( carfield_axi_mst_aw_chan_t ), - .axi_ot_out_w_chan_t ( carfield_axi_mst_w_chan_t ), - .axi_ot_out_b_chan_t ( carfield_axi_mst_b_chan_t ), - .axi_ot_out_ar_chan_t ( carfield_axi_mst_ar_chan_t ), - .axi_ot_out_r_chan_t ( carfield_axi_mst_r_chan_t ), - .axi_ot_out_req_t ( carfield_axi_mst_req_t ), - .axi_ot_out_resp_t ( carfield_axi_mst_rsp_t ), - .CdcSyncStages ( SyncStages ), - .SyncStages ( SyncStages ) -) i_security_island ( -`else -security_island i_security_island ( -`endif - .clk_i ( security_clk ), - .clk_ref_i ( rt_clk_i ), - .rst_ni ( security_rst_n ), - .pwr_on_rst_ni ( security_pwr_on_rst_n ), - .fetch_en_i ( car_regs_reg2hw.security_island_fetch_enable ), - .bootmode_i ( bootmode_ot_i ), - .test_enable_i ( test_mode_i ), - .irq_ibex_i ( secd_mbox_intr ), // from hostd or safed - // JTAG port - .jtag_tck_i ( jtag_ot_tck_i ), - .jtag_tms_i ( jtag_ot_tms_i ), - .jtag_trst_n_i ( jtag_ot_trst_ni ), - .jtag_tdi_i ( jtag_ot_tdi_i ), - .jtag_tdo_o ( jtag_ot_tdo_o ), - .jtag_tdo_oe_o ( jtag_ot_tdo_oe_o), - // Asynch axi port - .async_axi_out_aw_data_o ( axi_mst_ext_aw_data [SecurityIslandMstIdx] ), - .async_axi_out_aw_wptr_o ( axi_mst_ext_aw_wptr [SecurityIslandMstIdx] ), - .async_axi_out_aw_rptr_i ( axi_mst_ext_aw_rptr [SecurityIslandMstIdx] ), - .async_axi_out_w_data_o ( axi_mst_ext_w_data [SecurityIslandMstIdx] ), - .async_axi_out_w_wptr_o ( axi_mst_ext_w_wptr [SecurityIslandMstIdx] ), - .async_axi_out_w_rptr_i ( axi_mst_ext_w_rptr [SecurityIslandMstIdx] ), - .async_axi_out_b_data_i ( axi_mst_ext_b_data [SecurityIslandMstIdx] ), - .async_axi_out_b_wptr_i ( axi_mst_ext_b_wptr [SecurityIslandMstIdx] ), - .async_axi_out_b_rptr_o ( axi_mst_ext_b_rptr [SecurityIslandMstIdx] ), - .async_axi_out_ar_data_o ( axi_mst_ext_ar_data [SecurityIslandMstIdx] ), - .async_axi_out_ar_wptr_o ( axi_mst_ext_ar_wptr [SecurityIslandMstIdx] ), - .async_axi_out_ar_rptr_i ( axi_mst_ext_ar_rptr [SecurityIslandMstIdx] ), - .async_axi_out_r_data_i ( axi_mst_ext_r_data [SecurityIslandMstIdx] ), - .async_axi_out_r_wptr_i ( axi_mst_ext_r_wptr [SecurityIslandMstIdx] ), - .async_axi_out_r_rptr_o ( axi_mst_ext_r_rptr [SecurityIslandMstIdx] ), - .axi_isolate_i ( security_island_isolate_req ), - .axi_isolated_o ( master_isolated_rsp[SecurityIslandMstIdx] ), - // Uart - .ibex_uart_rx_i ( uart_ot_rx_i ), - .ibex_uart_tx_o ( uart_ot_tx_o ), - // SPI host - .spi_host_SCK_o ( spih_ot_sck_o ), - .spi_host_SCK_en_o( spih_ot_sck_en_o ), - .spi_host_CSB_o ( spih_ot_csb_o ), - .spi_host_CSB_en_o( spih_ot_csb_en_o ), - .spi_host_SD_o ( spih_ot_sd_o ), - .spi_host_SD_i ( spih_ot_sd_i ), - .spi_host_SD_en_o ( spih_ot_sd_en_o ) -); -end -else begin : gen_no_secure_subsystem - assign jtag_ot_tdo_o = jtag_ot_tdi_i; +// Logic `or` on interrupts coming from different harts of the host domain +logic hostd_secd_mbox_intr_ored; +if (CarfieldIslandsCfg.secured.enable) begin : gen_secure_subsystem + + assign reset_vector[CarfieldDomainIdx.secured] = car_regs_reg2hw.security_island_rst.q; + + for (genvar i = 0; i < CheshireNumIntHarts; i++ ) begin : gen_hostd_mbox_intrs + // hostd sender + assign hostd_secd_mbox_intr [i] = snd_mbox_intrs[HostdMboxOffset + 1*CheshireNumIntHarts + i]; + end + + for (genvar i = 0; i < CheshireNumIntHarts; i++ ) begin : gen_secd_mbox_intrs + assign secd_hostd_mbox_intr [i] = snd_mbox_intrs[SecdMboxOffset + i]; + end + assign secd_safed_mbox_intr = snd_mbox_intrs[SecdMboxOffset + CheshireNumIntHarts]; + + // Security island + assign hostd_secd_mbox_intr_ored = |hostd_secd_mbox_intr ; + + // For the security island. OR together interrupts coming from the host domain and the safe domain + assign secd_mbox_intr = hostd_secd_mbox_intr_ored | safed_secd_mbox_intr; + + assign security_rst_n = rsts_n[CarfieldDomainIdx.secured]; + assign security_pwr_on_rst_n = pwr_on_rsts_n[CarfieldDomainIdx.secured]; + assign security_clk = domain_clk_gated[CarfieldDomainIdx.secured]; + assign domain_clk_sel[CarfieldDomainIdx.secured] = + car_regs_reg2hw.security_island_clk_sel.q; + assign domain_clk_div_value[CarfieldDomainIdx.secured] = + car_regs_reg2hw.security_island_clk_div_value.q; + assign domain_clk_div_changed[CarfieldDomainIdx.secured] = + car_regs_reg2hw.security_island_clk_div_value.qe; + assign domain_clk_en[CarfieldDomainIdx.secured] = car_regs_reg2hw.security_island_clk_en.q | + secure_boot_i; + assign security_island_isolate_req = car_regs_reg2hw.security_island_isolate.q && + !secure_boot_i; + assign car_regs_hw2reg.security_island_isolate_status.d = + master_isolated_rsp[SecurityIslandMstIdx]; + assign car_regs_hw2reg.security_island_isolate_status.de = 1'b1; + + `ifndef SECD_NETLIST + secure_subsystem_synth_wrap #( + .HartIdOffs ( OpnTitHartIdOffs ), + .AxiAddrWidth ( Cfg.AddrWidth ), + .AxiDataWidth ( Cfg.AxiDataWidth ), + .AxiUserWidth ( Cfg.AxiUserWidth ), + .AxiOutIdWidth ( Cfg.AxiMstIdWidth ), + .AxiOtAddrWidth ( Cfg.AddrWidth ), + .AxiOtDataWidth ( AxiNarrowDataWidth ), // TODO: why is this exposed? + .AxiOtUserWidth ( Cfg.AxiUserWidth ), + .AxiOtOutIdWidth ( Cfg.AxiMstIdWidth ), + .AsyncAxiOutAwWidth ( CarfieldAxiMstAwWidth ), + .AsyncAxiOutWWidth ( CarfieldAxiMstWWidth ), + .AsyncAxiOutBWidth ( CarfieldAxiMstBWidth ), + .AsyncAxiOutArWidth ( CarfieldAxiMstArWidth ), + .AsyncAxiOutRWidth ( CarfieldAxiMstRWidth ), + .axi_out_aw_chan_t ( carfield_axi_mst_aw_chan_t ), + .axi_out_w_chan_t ( carfield_axi_mst_w_chan_t ), + .axi_out_b_chan_t ( carfield_axi_mst_b_chan_t ), + .axi_out_ar_chan_t ( carfield_axi_mst_ar_chan_t ), + .axi_out_r_chan_t ( carfield_axi_mst_r_chan_t ), + .axi_out_req_t ( carfield_axi_mst_req_t ), + .axi_out_resp_t ( carfield_axi_mst_rsp_t ), + .axi_ot_out_aw_chan_t ( carfield_axi_mst_aw_chan_t ), + .axi_ot_out_w_chan_t ( carfield_axi_mst_w_chan_t ), + .axi_ot_out_b_chan_t ( carfield_axi_mst_b_chan_t ), + .axi_ot_out_ar_chan_t ( carfield_axi_mst_ar_chan_t ), + .axi_ot_out_r_chan_t ( carfield_axi_mst_r_chan_t ), + .axi_ot_out_req_t ( carfield_axi_mst_req_t ), + .axi_ot_out_resp_t ( carfield_axi_mst_rsp_t ), + .CdcSyncStages ( SyncStages ), + .SyncStages ( SyncStages ) + ) i_security_island ( + `else + security_island i_security_island ( + `endif + .clk_i ( security_clk ), + .clk_ref_i ( rt_clk_i ), + .rst_ni ( security_rst_n ), + .pwr_on_rst_ni ( security_pwr_on_rst_n ), + .fetch_en_i ( car_regs_reg2hw.security_island_fetch_enable ), + .bootmode_i ( bootmode_ot_i ), + .test_enable_i ( test_mode_i ), + .irq_ibex_i ( secd_mbox_intr ), // from hostd or safed + // JTAG port + .jtag_tck_i ( jtag_ot_tck_i ), + .jtag_tms_i ( jtag_ot_tms_i ), + .jtag_trst_n_i ( jtag_ot_trst_ni ), + .jtag_tdi_i ( jtag_ot_tdi_i ), + .jtag_tdo_o ( jtag_ot_tdo_o ), + .jtag_tdo_oe_o ( jtag_ot_tdo_oe_o), + // Asynch axi port + .async_axi_out_aw_data_o ( axi_mst_ext_aw_data [SecurityIslandMstIdx] ), + .async_axi_out_aw_wptr_o ( axi_mst_ext_aw_wptr [SecurityIslandMstIdx] ), + .async_axi_out_aw_rptr_i ( axi_mst_ext_aw_rptr [SecurityIslandMstIdx] ), + .async_axi_out_w_data_o ( axi_mst_ext_w_data [SecurityIslandMstIdx] ), + .async_axi_out_w_wptr_o ( axi_mst_ext_w_wptr [SecurityIslandMstIdx] ), + .async_axi_out_w_rptr_i ( axi_mst_ext_w_rptr [SecurityIslandMstIdx] ), + .async_axi_out_b_data_i ( axi_mst_ext_b_data [SecurityIslandMstIdx] ), + .async_axi_out_b_wptr_i ( axi_mst_ext_b_wptr [SecurityIslandMstIdx] ), + .async_axi_out_b_rptr_o ( axi_mst_ext_b_rptr [SecurityIslandMstIdx] ), + .async_axi_out_ar_data_o ( axi_mst_ext_ar_data [SecurityIslandMstIdx] ), + .async_axi_out_ar_wptr_o ( axi_mst_ext_ar_wptr [SecurityIslandMstIdx] ), + .async_axi_out_ar_rptr_i ( axi_mst_ext_ar_rptr [SecurityIslandMstIdx] ), + .async_axi_out_r_data_i ( axi_mst_ext_r_data [SecurityIslandMstIdx] ), + .async_axi_out_r_wptr_i ( axi_mst_ext_r_wptr [SecurityIslandMstIdx] ), + .async_axi_out_r_rptr_o ( axi_mst_ext_r_rptr [SecurityIslandMstIdx] ), + .axi_isolate_i ( security_island_isolate_req ), + .axi_isolated_o ( master_isolated_rsp[SecurityIslandMstIdx] ), + // Uart + .ibex_uart_rx_i ( uart_ot_rx_i ), + .ibex_uart_tx_o ( uart_ot_tx_o ), + // SPI host + .spi_host_SCK_o ( spih_ot_sck_o ), + .spi_host_SCK_en_o( spih_ot_sck_en_o ), + .spi_host_CSB_o ( spih_ot_csb_o ), + .spi_host_CSB_en_o( spih_ot_csb_en_o ), + .spi_host_SD_o ( spih_ot_sd_o ), + .spi_host_SD_i ( spih_ot_sd_i ), + .spi_host_SD_en_o ( spih_ot_sd_en_o ) + ); +end else begin : gen_no_secure_subsystem + assign hostd_secd_mbox_intr = '0; + assign secd_hostd_mbox_intr = '0; + assign secd_safed_mbox_intr = '0; + assign hostd_secd_mbox_intr_ored = '0; + assign secd_mbox_intr = '0; + + assign security_rst_n = '0; + assign security_pwr_on_rst_n = '0; + assign security_clk = '0; + assign security_island_isolate_req = '0; + assign car_regs_hw2reg.security_island_isolate_status.d = '0; + assign car_regs_hw2reg.security_island_isolate_status.de = '0; + + assign jtag_ot_tdo_o = '0; end // Mailbox unit @@ -1947,89 +1973,6 @@ axi_to_reg_v2 #( .busy_o ( ) ); -// Interrupts assignment for mailbox unit - -// verilog_lint: waive-start line-length - -// -// hostd mailboxes -// -for (genvar i = 0; i < spatz_cluster_pkg::NumCores; i++ ) begin : gen_spatzcl_mbox_intrs_spatz_harts - assign safed_spatzcl_mbox_intr[i] = snd_mbox_intrs[i]; - for (genvar j = 0; j < CheshireNumIntHarts; j++ ) begin : gen_spatzcl_mbox_intrs_host_harts - assign hostd_spatzcl_mbox_intr[i][j] = snd_mbox_intrs[spatz_cluster_pkg::NumCores + (spatz_cluster_pkg::NumCores * j) + i]; - end -end - -localparam int unsigned HostdMboxOffset = (spatz_cluster_pkg::NumCores + spatz_cluster_pkg::NumCores * CheshireNumIntHarts); -for (genvar i = 0; i < CheshireNumIntHarts; i++ ) begin : gen_hostd_mbox_intrs - // hostd sender - assign hostd_pulpcl_mbox_intr [i] = snd_mbox_intrs[HostdMboxOffset + 0*CheshireNumIntHarts + i]; - assign hostd_secd_mbox_intr [i] = snd_mbox_intrs[HostdMboxOffset + 1*CheshireNumIntHarts + i]; - assign hostd_safed_mbox_intr [i] = snd_mbox_intrs[HostdMboxOffset + 2*CheshireNumIntHarts + i]; -end - -// -// Spatzcl -// -localparam int unsigned SpatzMboxOffset = HostdMboxOffset + 3*CheshireNumIntHarts; -for (genvar i = 0; i < CheshireNumIntHarts; i++ ) begin : gen_spatzcl_mbox_intrs - assign spatzcl_hostd_mbox_intr[i] = snd_mbox_intrs[SpatzMboxOffset + i]; -end -assign spatzcl_safed_mbox_intr = snd_mbox_intrs[SpatzMboxOffset + CheshireNumIntHarts]; - -// -// Pulpcl -// -localparam int unsigned PulpclMboxOffset = SpatzMboxOffset + CheshireNumIntHarts + 1; -for (genvar i = 0; i < CheshireNumIntHarts; i++ ) begin : gen_pulpcl_mbox_intrs - assign pulpcl_hostd_mbox_intr [i] = snd_mbox_intrs[PulpclMboxOffset + i]; -end -assign pulpcl_safed_mbox_intr = snd_mbox_intrs[PulpclMboxOffset + CheshireNumIntHarts]; - -// -// Secd -// -localparam int unsigned SecdMboxOffset = PulpclMboxOffset + CheshireNumIntHarts + 1; -for (genvar i = 0; i < CheshireNumIntHarts; i++ ) begin : gen_secd_mbox_intrs - assign secd_hostd_mbox_intr [i] = snd_mbox_intrs[SecdMboxOffset + i]; -end -assign secd_safed_mbox_intr = snd_mbox_intrs[SecdMboxOffset + CheshireNumIntHarts]; - -// -// Safed -// -localparam int unsigned SafedMboxOffset = SecdMboxOffset + CheshireNumIntHarts + 1; -for (genvar i = 0; i < CheshireNumIntHarts; i++ ) begin : gen_safed_mbox_intr - assign safed_hostd_mbox_intr [i] = snd_mbox_intrs[SafedMboxOffset + CheshireNumIntHarts + 1]; -end -assign safed_secd_mbox_intr = snd_mbox_intrs[SafedMboxOffset + CheshireNumIntHarts + 0]; -assign safed_pulpcl_mbox_intr = snd_mbox_intrs[SafedMboxOffset + CheshireNumIntHarts + 1]; - -// verilog_lint: waive-stop line-length - -// Logic `or` on interrupts coming from different harts of the host domain -logic [spatz_cluster_pkg::NumCores-1:0] hostd_spatzcl_mbox_intr_ored; -logic hostd_pulpcl_mbox_intr_ored; -logic hostd_secd_mbox_intr_ored; - -// Floating point cluster -for (genvar i = 0; i < spatz_cluster_pkg::NumCores; i++ ) begin : gen_spatzcl_mbox_intrs_or - assign hostd_spatzcl_mbox_intr_ored[i] = |hostd_spatzcl_mbox_intr[i]; -end -// Integer cluster -assign hostd_pulpcl_mbox_intr_ored = |hostd_pulpcl_mbox_intr ; -// Security island -assign hostd_secd_mbox_intr_ored = |hostd_secd_mbox_intr ; - -// For the spatz FP cluster SW interrupt in machine mode (msi), OR together interrupts coming from the -// host domain and the safe domain -assign spatzcl_mbox_intr = hostd_spatzcl_mbox_intr_ored | safed_spatzcl_mbox_intr; -// For the integer cluster. OR together interrupts coming from the host domain and the safe domain -assign pulpcl_mbox_intr = hostd_pulpcl_mbox_intr_ored | safed_pulpcl_mbox_intr; -// For the security island. OR together interrupts coming from the host domain and the safe domain -assign secd_mbox_intr = hostd_secd_mbox_intr_ored | safed_secd_mbox_intr; - mailbox_unit #( .reg_req_t( carfield_reg_req_t ), .reg_rsp_t( carfield_reg_rsp_t ), @@ -2046,645 +1989,601 @@ mailbox_unit #( // Carfield peripherals // Ethernet // Peripheral Clock Domain +logic ethernet_slave_isolated; carfield_axi_slv_req_t axi_ethernet_req; carfield_axi_slv_rsp_t axi_ethernet_rsp; -if (IslandsCfg.EnEthernet) begin : gen_ethernet -axi_cdc_dst #( - .LogDepth ( LogDepth ), - .SyncStages ( SyncStages ), - .aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .w_chan_t ( carfield_axi_slv_w_chan_t ), - .b_chan_t ( carfield_axi_slv_b_chan_t ), - .ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_resp_t ( carfield_axi_slv_rsp_t ) -) i_ethernet_cdc_dst ( - .async_data_slave_aw_data_i ( axi_slv_ext_aw_data [EthernetSlvIdx] ), - .async_data_slave_aw_wptr_i ( axi_slv_ext_aw_wptr [EthernetSlvIdx] ), - .async_data_slave_aw_rptr_o ( axi_slv_ext_aw_rptr [EthernetSlvIdx] ), - .async_data_slave_w_data_i ( axi_slv_ext_w_data [EthernetSlvIdx] ), - .async_data_slave_w_wptr_i ( axi_slv_ext_w_wptr [EthernetSlvIdx] ), - .async_data_slave_w_rptr_o ( axi_slv_ext_w_rptr [EthernetSlvIdx] ), - .async_data_slave_b_data_o ( axi_slv_ext_b_data [EthernetSlvIdx] ), - .async_data_slave_b_wptr_o ( axi_slv_ext_b_wptr [EthernetSlvIdx] ), - .async_data_slave_b_rptr_i ( axi_slv_ext_b_rptr [EthernetSlvIdx] ), - .async_data_slave_ar_data_i ( axi_slv_ext_ar_data [EthernetSlvIdx] ), - .async_data_slave_ar_wptr_i ( axi_slv_ext_ar_wptr [EthernetSlvIdx] ), - .async_data_slave_ar_rptr_o ( axi_slv_ext_ar_rptr [EthernetSlvIdx] ), - .async_data_slave_r_data_o ( axi_slv_ext_r_data [EthernetSlvIdx] ), - .async_data_slave_r_wptr_o ( axi_slv_ext_r_wptr [EthernetSlvIdx] ), - .async_data_slave_r_rptr_i ( axi_slv_ext_r_rptr [EthernetSlvIdx] ), - .dst_clk_i ( periph_clk ), - .dst_rst_ni ( periph_rst_n ), - .dst_req_o ( axi_ethernet_req ), - .dst_resp_i ( axi_ethernet_rsp ) -); +if (CarfieldIslandsCfg.ethernet.enable) begin : gen_ethernet + assign ethernet_slave_isolated = slave_isolated[EthernetSlvIdx]; + assign slave_isolated[EthernetSlvIdx] = slave_isolated_rsp[EthernetSlvIdx]; + assign slave_isolate_req[EthernetSlvIdx] = car_regs_reg2hw.periph_isolate.q; + axi_cdc_dst #( + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ), + .aw_chan_t ( carfield_axi_slv_aw_chan_t ), + .w_chan_t ( carfield_axi_slv_w_chan_t ), + .b_chan_t ( carfield_axi_slv_b_chan_t ), + .ar_chan_t ( carfield_axi_slv_ar_chan_t ), + .r_chan_t ( carfield_axi_slv_r_chan_t ), + .axi_req_t ( carfield_axi_slv_req_t ), + .axi_resp_t ( carfield_axi_slv_rsp_t ) + ) i_ethernet_cdc_dst ( + .async_data_slave_aw_data_i ( axi_slv_ext_aw_data [EthernetSlvIdx] ), + .async_data_slave_aw_wptr_i ( axi_slv_ext_aw_wptr [EthernetSlvIdx] ), + .async_data_slave_aw_rptr_o ( axi_slv_ext_aw_rptr [EthernetSlvIdx] ), + .async_data_slave_w_data_i ( axi_slv_ext_w_data [EthernetSlvIdx] ), + .async_data_slave_w_wptr_i ( axi_slv_ext_w_wptr [EthernetSlvIdx] ), + .async_data_slave_w_rptr_o ( axi_slv_ext_w_rptr [EthernetSlvIdx] ), + .async_data_slave_b_data_o ( axi_slv_ext_b_data [EthernetSlvIdx] ), + .async_data_slave_b_wptr_o ( axi_slv_ext_b_wptr [EthernetSlvIdx] ), + .async_data_slave_b_rptr_i ( axi_slv_ext_b_rptr [EthernetSlvIdx] ), + .async_data_slave_ar_data_i ( axi_slv_ext_ar_data [EthernetSlvIdx] ), + .async_data_slave_ar_wptr_i ( axi_slv_ext_ar_wptr [EthernetSlvIdx] ), + .async_data_slave_ar_rptr_o ( axi_slv_ext_ar_rptr [EthernetSlvIdx] ), + .async_data_slave_r_data_o ( axi_slv_ext_r_data [EthernetSlvIdx] ), + .async_data_slave_r_wptr_o ( axi_slv_ext_r_wptr [EthernetSlvIdx] ), + .async_data_slave_r_rptr_i ( axi_slv_ext_r_rptr [EthernetSlvIdx] ), + .dst_clk_i ( periph_clk ), + .dst_rst_ni ( periph_rst_n ), + .dst_req_o ( axi_ethernet_req ), + .dst_resp_i ( axi_ethernet_rsp ) + ); -AXI_BUS #( - .AXI_ADDR_WIDTH( Cfg.AddrWidth ), - .AXI_DATA_WIDTH( Cfg.AxiDataWidth ), - .AXI_ID_WIDTH ( AxiSlvIdWidth ), - .AXI_USER_WIDTH( Cfg.AxiUserWidth ) -) axi_ethernet (); - -`AXI_ASSIGN_FROM_REQ(axi_ethernet, axi_ethernet_req); -`AXI_ASSIGN_TO_RESP(axi_ethernet_rsp, axi_ethernet); - -// The Ethernet RGMII interfaces mandates a clock of 125MHz (in 1GBit mode) for both TX and RX -// clocks. We generate a 125MHz clock starting from the `periph_clk`. The (integer) division value -// is SW-programmable. -localparam int unsigned EthRgmiiPhyClkDivWidth = 20; -// We assume a peripheral clock of 250MHz to get the 125MHz clock for the RGMII interface. Hence, -// the default division value after PoR is 250/125. -localparam int unsigned EthRgmiiPhyClkDivDefaultValue = 2; -logic [EthRgmiiPhyClkDivWidth-1:0] eth_rgmii_phy_clk_div_value; -logic eth_rgmii_phy_clk_div_value_valid; -logic eth_rgmii_phy_clk_div_value_ready; -logic eth_rgmii_phy_clk0; - -// The register file does not support back pressure directly. I.e the hardware side cannot tell -// the regfile that a reg value cannot be written at the moment. This is a problem since the clk -// divider input of the clk_int_div module will stall the transaction until it is safe to change -// the clock division factor. The stream_deposit module converts between these two protocols -// (write-pulse only protocol <-> ready-valid protocol). See the documentation in the header of -// the module for more details. -lossy_valid_to_stream #( - .DATA_WIDTH(EthRgmiiPhyClkDivWidth) -) i_eth_rgmii_phy_clk_div_config_decouple ( - .clk_i ( periph_clk ), - .rst_ni ( periph_rst_n ), - .valid_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_value.qe ), - .data_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_value.q ), - .valid_o ( eth_rgmii_phy_clk_div_value_valid ), - .ready_i ( eth_rgmii_phy_clk_div_value_ready ), - .data_o ( eth_rgmii_phy_clk_div_value ), - .busy_o ( ) -); + AXI_BUS #( + .AXI_ADDR_WIDTH( Cfg.AddrWidth ), + .AXI_DATA_WIDTH( Cfg.AxiDataWidth ), + .AXI_ID_WIDTH ( AxiSlvIdWidth ), + .AXI_USER_WIDTH( Cfg.AxiUserWidth ) + ) axi_ethernet (); + + `AXI_ASSIGN_FROM_REQ(axi_ethernet, axi_ethernet_req); + `AXI_ASSIGN_TO_RESP(axi_ethernet_rsp, axi_ethernet); + + // The Ethernet RGMII interfaces mandates a clock of 125MHz (in 1GBit mode) for both TX and RX + // clocks. We generate a 125MHz clock starting from the `periph_clk`. The (integer) division value + // is SW-programmable. + localparam int unsigned EthRgmiiPhyClkDivWidth = 20; + // We assume a peripheral clock of 250MHz to get the 125MHz clock for the RGMII interface. Hence, + // the default division value after PoR is 250/125. + localparam int unsigned EthRgmiiPhyClkDivDefaultValue = 2; + logic [EthRgmiiPhyClkDivWidth-1:0] eth_rgmii_phy_clk_div_value; + logic eth_rgmii_phy_clk_div_value_valid; + logic eth_rgmii_phy_clk_div_value_ready; + logic eth_rgmii_phy_clk0; -(* no_ungroup *) -(* no_boundary_optimization *) -clk_int_div #( - .DIV_VALUE_WIDTH ( EthRgmiiPhyClkDivWidth ), - .DEFAULT_DIV_VALUE ( EthRgmiiPhyClkDivDefaultValue ), - .ENABLE_CLOCK_IN_RESET ( 0 ) -) i_eth_rgmii_phy_clk_int_div ( - .clk_i ( periph_clk ), - .rst_ni ( periph_rst_n ), - .en_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_en.q ), - .test_mode_en_i ( test_mode_i ), - .div_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_value.q ), - .div_valid_i ( eth_rgmii_phy_clk_div_value_valid ), - .div_ready_o ( eth_rgmii_phy_clk_div_value_ready ), - .clk_o ( eth_rgmii_phy_clk0 ), - .cycl_count_o ( ) -); + // The register file does not support back pressure directly. I.e the hardware side cannot tell + // the regfile that a reg value cannot be written at the moment. This is a problem since the clk + // divider input of the clk_int_div module will stall the transaction until it is safe to change + // the clock division factor. The stream_deposit module converts between these two protocols + // (write-pulse only protocol <-> ready-valid protocol). See the documentation in the header of + // the module for more details. + lossy_valid_to_stream #( + .DATA_WIDTH(EthRgmiiPhyClkDivWidth) + ) i_eth_rgmii_phy_clk_div_config_decouple ( + .clk_i ( periph_clk ), + .rst_ni ( periph_rst_n ), + .valid_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_value.qe ), + .data_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_value.q ), + .valid_o ( eth_rgmii_phy_clk_div_value_valid ), + .ready_i ( eth_rgmii_phy_clk_div_value_ready ), + .data_o ( eth_rgmii_phy_clk_div_value ), + .busy_o ( ) + ); + (* no_ungroup *) + (* no_boundary_optimization *) + clk_int_div #( + .DIV_VALUE_WIDTH ( EthRgmiiPhyClkDivWidth ), + .DEFAULT_DIV_VALUE ( EthRgmiiPhyClkDivDefaultValue ), + .ENABLE_CLOCK_IN_RESET ( 0 ) + ) i_eth_rgmii_phy_clk_int_div ( + .clk_i ( periph_clk ), + .rst_ni ( periph_rst_n ), + .en_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_en.q ), + .test_mode_en_i ( test_mode_i ), + .div_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_value.q ), + .div_valid_i ( eth_rgmii_phy_clk_div_value_valid ), + .div_ready_o ( eth_rgmii_phy_clk_div_value_ready ), + .clk_o ( eth_rgmii_phy_clk0 ), + .cycl_count_o ( ) + ); -// The Ethernet MDIO interfaces mandates a clock of 2.5MHz. We generate a 2.5MHz clock starting from -// the `periph_clk`. The (integer) division value is SW-programmable. -localparam int unsigned EthMdioClkDivWidth = 20; -// We assume a default peripheral clock of 250 MHz to get the 2.5MHz required for the MDIO -// interface. Hence, the default division value after PoR is 250/2.5 -localparam int unsigned EthMdioClkDivDefaultValue = 100; -logic [EthRgmiiPhyClkDivWidth-1:0] eth_mdio_clk_div_value; -logic eth_mdio_clk_div_value_valid; -logic eth_mdio_clk_div_value_ready; -logic eth_mdio_clk; - -lossy_valid_to_stream #( - .DATA_WIDTH(EthMdioClkDivWidth) -) i_eth_mdio_clk_div_config_decouple ( - .clk_i ( periph_clk ), - .rst_ni ( periph_rst_n ), - .valid_i ( car_regs_reg2hw.eth_mdio_clk_div_value.qe ), - .data_i ( car_regs_reg2hw.eth_mdio_clk_div_value.q ), - .valid_o ( eth_mdio_clk_div_value_valid ), - .ready_i ( eth_mdio_clk_div_value_ready ), - .data_o ( eth_mdio_clk_div_value ), - .busy_o ( ) -); -(* no_ungroup *) -(* no_boundary_optimization *) -clk_int_div #( - .DIV_VALUE_WIDTH ( EthMdioClkDivWidth ), - .DEFAULT_DIV_VALUE ( EthMdioClkDivDefaultValue ), - .ENABLE_CLOCK_IN_RESET ( 0 ) -) i_eth_mdio_clk_int_div ( - .clk_i ( periph_clk ), - .rst_ni ( periph_rst_n ), - .en_i ( car_regs_reg2hw.eth_mdio_clk_div_en.q ), - .test_mode_en_i ( test_mode_i ), - .div_i ( car_regs_reg2hw.eth_mdio_clk_div_value.q ), - .div_valid_i ( eth_mdio_clk_div_value_valid ), - .div_ready_o ( eth_mdio_clk_div_value_ready ), - .clk_o ( eth_mdio_clk ), - .cycl_count_o ( ) -); + // The Ethernet MDIO interfaces mandates a clock of 2.5MHz. We generate a 2.5MHz clock starting from + // the `periph_clk`. The (integer) division value is SW-programmable. + localparam int unsigned EthMdioClkDivWidth = 20; + // We assume a default peripheral clock of 250 MHz to get the 2.5MHz required for the MDIO + // interface. Hence, the default division value after PoR is 250/2.5 + localparam int unsigned EthMdioClkDivDefaultValue = 100; + logic [EthRgmiiPhyClkDivWidth-1:0] eth_mdio_clk_div_value; + logic eth_mdio_clk_div_value_valid; + logic eth_mdio_clk_div_value_ready; + logic eth_mdio_clk; -// Ethernet IP -eth_rgmii #( - .AXI_ADDR_WIDTH ( Cfg.AddrWidth ), - .AXI_DATA_WIDTH ( Cfg.AxiDataWidth ), - .AXI_ID_WIDTH ( AxiSlvIdWidth ), - .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) -) i_eth_rgmii ( - .clk_i ( eth_mdio_clk ), - .clk_200MHz_i ( '0 ), // Only used with FPGA mapping for genesysII in IDELAYCTRL cell's - // ref clk (see IP) - .rst_ni ( periph_rst_n ), - .eth_clk_i ( '0 ), // quadrature (90deg) clk to `phy_tx_clk_i` -> disabled when `USE_CLK90 == - // FALSE` in ethernet IP. See `eth_mac_1g_rgmii_fifo`. In carfieldv1, - // USE_CLK90 == 0, hence changing the clock phase is left to PHY chips on - // the PCB. - - .ethernet ( axi_ethernet ), - - .eth_rxck ( eth_rxck_i ), - .eth_rxctl ( eth_rxctl_i ), - .eth_rxd ( eth_rxd_i ), - - .eth_txck ( eth_txck_o ), - .eth_txctl ( eth_txctl_o ), - .eth_txd ( eth_txd_o ), - - .eth_rst_n ( eth_rst_n_o ), - .phy_tx_clk_i ( eth_rgmii_phy_clk0 ), // in phase (0deg) clk - - // MDIO - .eth_mdio_i ( eth_md_i ), - .eth_mdio_o ( eth_md_o ), - .eth_mdio_oe_o ( eth_md_oe ), - .eth_mdc_o ( eth_mdc_o ), - - .eth_irq ( car_eth_intr ) -); + lossy_valid_to_stream #( + .DATA_WIDTH(EthMdioClkDivWidth) + ) i_eth_mdio_clk_div_config_decouple ( + .clk_i ( periph_clk ), + .rst_ni ( periph_rst_n ), + .valid_i ( car_regs_reg2hw.eth_mdio_clk_div_value.qe ), + .data_i ( car_regs_reg2hw.eth_mdio_clk_div_value.q ), + .valid_o ( eth_mdio_clk_div_value_valid ), + .ready_i ( eth_mdio_clk_div_value_ready ), + .data_o ( eth_mdio_clk_div_value ), + .busy_o ( ) + ); -end else begin : gen_no_ethernet + (* no_ungroup *) + (* no_boundary_optimization *) + clk_int_div #( + .DIV_VALUE_WIDTH ( EthMdioClkDivWidth ), + .DEFAULT_DIV_VALUE ( EthMdioClkDivDefaultValue ), + .ENABLE_CLOCK_IN_RESET ( 0 ) + ) i_eth_mdio_clk_int_div ( + .clk_i ( periph_clk ), + .rst_ni ( periph_rst_n ), + .en_i ( car_regs_reg2hw.eth_mdio_clk_div_en.q ), + .test_mode_en_i ( test_mode_i ), + .div_i ( car_regs_reg2hw.eth_mdio_clk_div_value.q ), + .div_valid_i ( eth_mdio_clk_div_value_valid ), + .div_ready_o ( eth_mdio_clk_div_value_ready ), + .clk_o ( eth_mdio_clk ), + .cycl_count_o ( ) + ); -axi_cdc_dst #( - .LogDepth ( LogDepth ), - .SyncStages ( SyncStages ), - .aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .w_chan_t ( carfield_axi_slv_w_chan_t ), - .b_chan_t ( carfield_axi_slv_b_chan_t ), - .ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_resp_t ( carfield_axi_slv_rsp_t ) -) i_ethernet_cdc_dst ( - .async_data_slave_aw_data_i ( axi_slv_ext_aw_data [EthernetSlvIdx] ), - .async_data_slave_aw_wptr_i ( axi_slv_ext_aw_wptr [EthernetSlvIdx] ), - .async_data_slave_aw_rptr_o ( axi_slv_ext_aw_rptr [EthernetSlvIdx] ), - .async_data_slave_w_data_i ( axi_slv_ext_w_data [EthernetSlvIdx] ), - .async_data_slave_w_wptr_i ( axi_slv_ext_w_wptr [EthernetSlvIdx] ), - .async_data_slave_w_rptr_o ( axi_slv_ext_w_rptr [EthernetSlvIdx] ), - .async_data_slave_b_data_o ( axi_slv_ext_b_data [EthernetSlvIdx] ), - .async_data_slave_b_wptr_o ( axi_slv_ext_b_wptr [EthernetSlvIdx] ), - .async_data_slave_b_rptr_i ( axi_slv_ext_b_rptr [EthernetSlvIdx] ), - .async_data_slave_ar_data_i ( axi_slv_ext_ar_data [EthernetSlvIdx] ), - .async_data_slave_ar_wptr_i ( axi_slv_ext_ar_wptr [EthernetSlvIdx] ), - .async_data_slave_ar_rptr_o ( axi_slv_ext_ar_rptr [EthernetSlvIdx] ), - .async_data_slave_r_data_o ( axi_slv_ext_r_data [EthernetSlvIdx] ), - .async_data_slave_r_wptr_o ( axi_slv_ext_r_wptr [EthernetSlvIdx] ), - .async_data_slave_r_rptr_i ( axi_slv_ext_r_rptr [EthernetSlvIdx] ), - .dst_clk_i ( periph_clk ), - .dst_rst_ni ( periph_rst_n ), - .dst_req_o ( axi_ethernet_req ), - .dst_resp_i ( axi_ethernet_rsp ) -); + // Ethernet IP + eth_rgmii #( + .AXI_ADDR_WIDTH ( Cfg.AddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataWidth ), + .AXI_ID_WIDTH ( AxiSlvIdWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) + ) i_eth_rgmii ( + .clk_i ( eth_mdio_clk ), + /* Clock 200MHz */ + // Only used with FPGA mapping for genesysII + // in IDELAYCTRL cell's ref clk (see IP) + .clk_200MHz_i ( '0 ), + .rst_ni ( periph_rst_n ), + /* Ethernet Clock */ + // Quadrature (90deg) clk to `phy_tx_clk_i` -> disabled when + // `USE_CLK90 == FALSE` in ethernet IP. See `eth_mac_1g_rgmii_fifo`. + // In carfieldv1, USE_CLK90 == 0, hence changing the clock phase + // is left to PHY chips on the PCB. + .eth_clk_i ( '0 ), + + .ethernet ( axi_ethernet ), + + .eth_rxck ( eth_rxck_i ), + .eth_rxctl ( eth_rxctl_i ), + .eth_rxd ( eth_rxd_i ), + + .eth_txck ( eth_txck_o ), + .eth_txctl ( eth_txctl_o ), + .eth_txd ( eth_txd_o ), + + .eth_rst_n ( eth_rst_n_o ), + .phy_tx_clk_i ( eth_rgmii_phy_clk0 ), // in phase (0deg) clk + + // MDIO + .eth_mdio_i ( eth_md_i ), + .eth_mdio_o ( eth_md_o ), + .eth_mdio_oe_o ( eth_md_oe ), + .eth_mdc_o ( eth_mdc_o ), + + .eth_irq ( car_eth_intr ) + ); -axi_err_slv #( - .AxiIdWidth ( AxiSlvIdWidth ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_resp_t ( carfield_axi_slv_rsp_t ), - .Resp ( axi_pkg::RESP_DECERR ), - .ATOPs ( 1'b0 ), - .MaxTrans ( 4 ) -) i_axi_err_slv_ethernet ( - .clk_i ( periph_clk ), - .rst_ni ( periph_pwr_on_rst_n ), - .test_i ( test_mode_i ), - // slave port - .slv_req_i ( axi_ethernet_req ), - .slv_resp_o ( axi_ethernet_rsp ) -); +end else begin : gen_no_ethernet -assign car_eth_intr = '0; -assign eth_md_o = '0; -assign eth_md_oe = '0; -assign eth_mdc_o = '0; -assign eth_rst_n_o = '0; -assign eth_txck_o = '0; -assign eth_txctl_o = '0; -assign eth_txd_o = '0; + assign ethernet_slave_isolated = '0; + assign car_eth_intr = '0; + assign eth_md_o = '0; + assign eth_md_oe = '0; + assign eth_mdc_o = '0; + assign eth_rst_n_o = '0; + assign eth_txck_o = '0; + assign eth_txctl_o = '0; + assign eth_txd_o = '0; end // APB peripherals // Periph Clock Domain // axi_cdc -> axi_amos -> axi_cut -> axi_to_axilite -> axilite_to_apb -> periph devices -carfield_axi_slv_req_t axi_d64_a48_peripherals_req; -carfield_axi_slv_rsp_t axi_d64_a48_peripherals_rsp; - -axi_cdc_dst #( - .LogDepth ( LogDepth ), - .SyncStages ( SyncStages ), - .aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .w_chan_t ( carfield_axi_slv_w_chan_t ), - .b_chan_t ( carfield_axi_slv_b_chan_t ), - .ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_resp_t ( carfield_axi_slv_rsp_t ) -) i_cdc_dst_peripherals ( - // asynchronous slave port - .async_data_slave_aw_data_i ( axi_slv_ext_aw_data [PeriphsSlvIdx] ), - .async_data_slave_aw_wptr_i ( axi_slv_ext_aw_wptr [PeriphsSlvIdx] ), - .async_data_slave_aw_rptr_o ( axi_slv_ext_aw_rptr [PeriphsSlvIdx] ), - .async_data_slave_w_data_i ( axi_slv_ext_w_data [PeriphsSlvIdx] ), - .async_data_slave_w_wptr_i ( axi_slv_ext_w_wptr [PeriphsSlvIdx] ), - .async_data_slave_w_rptr_o ( axi_slv_ext_w_rptr [PeriphsSlvIdx] ), - .async_data_slave_b_data_o ( axi_slv_ext_b_data [PeriphsSlvIdx] ), - .async_data_slave_b_wptr_o ( axi_slv_ext_b_wptr [PeriphsSlvIdx] ), - .async_data_slave_b_rptr_i ( axi_slv_ext_b_rptr [PeriphsSlvIdx] ), - .async_data_slave_ar_data_i ( axi_slv_ext_ar_data [PeriphsSlvIdx] ), - .async_data_slave_ar_wptr_i ( axi_slv_ext_ar_wptr [PeriphsSlvIdx] ), - .async_data_slave_ar_rptr_o ( axi_slv_ext_ar_rptr [PeriphsSlvIdx] ), - .async_data_slave_r_data_o ( axi_slv_ext_r_data [PeriphsSlvIdx] ), - .async_data_slave_r_wptr_o ( axi_slv_ext_r_wptr [PeriphsSlvIdx] ), - .async_data_slave_r_rptr_i ( axi_slv_ext_r_rptr [PeriphsSlvIdx] ), - // synchronous master port - .dst_clk_i ( periph_clk ), - .dst_rst_ni ( periph_pwr_on_rst_n ), - .dst_req_o ( axi_d64_a48_peripherals_req ), - .dst_resp_i ( axi_d64_a48_peripherals_rsp ) -); - -carfield_axi_slv_req_t axi_d64_a48_amo_peripherals_req; -carfield_axi_slv_rsp_t axi_d64_a48_amo_peripherals_rsp; - -// Shim atomics, which are not supported in reg -// TODO: should we use a filter instead here? -axi_riscv_atomics_structs #( - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiIdWidth ( AxiSlvIdWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiMaxReadTxns ( Cfg.RegMaxReadTxns ), - .AxiMaxWriteTxns ( Cfg.RegMaxWriteTxns ), - .AxiUserAsId ( 1 ), - .AxiUserIdMsb ( Cfg.AxiUserAmoMsb ), - .AxiUserIdLsb ( Cfg.AxiUserAmoLsb ), - .RiscvWordWidth ( 64 ), - .NAxiCuts ( Cfg.RegAmoNumCuts ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_rsp_t ( carfield_axi_slv_rsp_t ) -) i_atomics_peripherals ( - .clk_i ( periph_clk ), - .rst_ni ( periph_pwr_on_rst_n ), - .axi_slv_req_i ( axi_d64_a48_peripherals_req ), - .axi_slv_rsp_o ( axi_d64_a48_peripherals_rsp ), - .axi_mst_req_o ( axi_d64_a48_amo_peripherals_req ), - .axi_mst_rsp_i ( axi_d64_a48_amo_peripherals_rsp ) -); - -carfield_axi_slv_req_t axi_d64_a48_amo_cut_peripherals_req; -carfield_axi_slv_rsp_t axi_d64_a48_amo_cut_peripherals_rsp; - -axi_cut #( - .Bypass ( ~Cfg.RegAmoPostCut ), - .aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .w_chan_t ( carfield_axi_slv_w_chan_t ), - .b_chan_t ( carfield_axi_slv_b_chan_t ), - .ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_resp_t ( carfield_axi_slv_rsp_t ) -) i_atomics_cut_peripherals ( - .clk_i ( periph_clk ), - .rst_ni ( periph_pwr_on_rst_n ), - .slv_req_i ( axi_d64_a48_amo_peripherals_req ), - .slv_resp_o ( axi_d64_a48_amo_peripherals_rsp ), - .mst_req_o ( axi_d64_a48_amo_cut_peripherals_req ), - .mst_resp_i ( axi_d64_a48_amo_cut_peripherals_rsp ) -); - -// Convert to d32 a48 -// verilog_lint: waive-start line-length -`AXI_TYPEDEF_ALL_CT(carfield_axi_d32_a48_slv, carfield_axi_d32_a48_slv_req_t, carfield_axi_d32_a48_slv_rsp_t, car_addrw_t, car_slv_id_t, car_nar_dataw_t, car_nar_strb_t, car_usr_t) -// verilog_lint: waive-stop line-length - -carfield_axi_d32_a48_slv_req_t axi_d32_a48_peripherals_req; -carfield_axi_d32_a48_slv_rsp_t axi_d32_a48_peripherals_rsp; - -axi_dw_converter #( - .AxiSlvPortDataWidth ( Cfg.AxiDataWidth ), - .AxiMstPortDataWidth ( AxiNarrowDataWidth ), - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiIdWidth ( AxiSlvIdWidth ), - .aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .mst_w_chan_t ( carfield_axi_d32_a48_slv_w_chan_t ), - .slv_w_chan_t ( carfield_axi_slv_w_chan_t ), - .b_chan_t ( carfield_axi_slv_b_chan_t ), - .ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .mst_r_chan_t ( carfield_axi_d32_a48_slv_r_chan_t ), - .slv_r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_mst_req_t ( carfield_axi_d32_a48_slv_req_t ), - .axi_mst_resp_t ( carfield_axi_d32_a48_slv_rsp_t ), - .axi_slv_req_t ( carfield_axi_slv_req_t ), - .axi_slv_resp_t ( carfield_axi_slv_rsp_t ) -) i_axi_dw_converter_peripherals ( - .clk_i ( periph_clk ), - .rst_ni ( periph_pwr_on_rst_n ), - .slv_req_i ( axi_d64_a48_amo_cut_peripherals_req ), - .slv_resp_o ( axi_d64_a48_amo_cut_peripherals_rsp ), - .mst_req_o ( axi_d32_a48_peripherals_req ), - .mst_resp_i ( axi_d32_a48_peripherals_rsp ) -); +if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... + assign reset_vector[CarfieldDomainIdx.periph] = car_regs_reg2hw.periph_rst.q; + + assign slave_isolate_req[PeriphsSlvIdx] = car_regs_reg2hw.periph_isolate.q; + assign slave_isolated[PeriphsSlvIdx] = slave_isolated_rsp[PeriphsSlvIdx]; + assign car_regs_hw2reg.periph_isolate_status.d = slave_isolated[PeriphsSlvIdx] | + hyper_isolated_rsp | + ethernet_slave_isolated; + assign car_regs_hw2reg.periph_isolate_status.de = 1'b1; + + carfield_axi_slv_req_t axi_d64_a48_peripherals_req; + carfield_axi_slv_rsp_t axi_d64_a48_peripherals_rsp; + + axi_cdc_dst #( + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ), + .aw_chan_t ( carfield_axi_slv_aw_chan_t ), + .w_chan_t ( carfield_axi_slv_w_chan_t ), + .b_chan_t ( carfield_axi_slv_b_chan_t ), + .ar_chan_t ( carfield_axi_slv_ar_chan_t ), + .r_chan_t ( carfield_axi_slv_r_chan_t ), + .axi_req_t ( carfield_axi_slv_req_t ), + .axi_resp_t ( carfield_axi_slv_rsp_t ) + ) i_cdc_dst_peripherals ( + // asynchronous slave port + .async_data_slave_aw_data_i ( axi_slv_ext_aw_data [PeriphsSlvIdx] ), + .async_data_slave_aw_wptr_i ( axi_slv_ext_aw_wptr [PeriphsSlvIdx] ), + .async_data_slave_aw_rptr_o ( axi_slv_ext_aw_rptr [PeriphsSlvIdx] ), + .async_data_slave_w_data_i ( axi_slv_ext_w_data [PeriphsSlvIdx] ), + .async_data_slave_w_wptr_i ( axi_slv_ext_w_wptr [PeriphsSlvIdx] ), + .async_data_slave_w_rptr_o ( axi_slv_ext_w_rptr [PeriphsSlvIdx] ), + .async_data_slave_b_data_o ( axi_slv_ext_b_data [PeriphsSlvIdx] ), + .async_data_slave_b_wptr_o ( axi_slv_ext_b_wptr [PeriphsSlvIdx] ), + .async_data_slave_b_rptr_i ( axi_slv_ext_b_rptr [PeriphsSlvIdx] ), + .async_data_slave_ar_data_i ( axi_slv_ext_ar_data [PeriphsSlvIdx] ), + .async_data_slave_ar_wptr_i ( axi_slv_ext_ar_wptr [PeriphsSlvIdx] ), + .async_data_slave_ar_rptr_o ( axi_slv_ext_ar_rptr [PeriphsSlvIdx] ), + .async_data_slave_r_data_o ( axi_slv_ext_r_data [PeriphsSlvIdx] ), + .async_data_slave_r_wptr_o ( axi_slv_ext_r_wptr [PeriphsSlvIdx] ), + .async_data_slave_r_rptr_i ( axi_slv_ext_r_rptr [PeriphsSlvIdx] ), + // synchronous master port + .dst_clk_i ( periph_clk ), + .dst_rst_ni ( periph_pwr_on_rst_n ), + .dst_req_o ( axi_d64_a48_peripherals_req ), + .dst_resp_i ( axi_d64_a48_peripherals_rsp ) + ); -// Convert to d32_a32 -// verilog_lint: waive-start line-length -`AXI_TYPEDEF_ALL_CT(carfield_axi_d32_a32_slv, carfield_axi_d32_a32_slv_req_t, carfield_axi_d32_a32_slv_rsp_t, car_nar_addrw_t, car_slv_id_t, car_nar_dataw_t, car_nar_strb_t, car_usr_t) -// verilog_lint: waive-stop line-length + carfield_axi_slv_req_t axi_d64_a48_amo_peripherals_req; + carfield_axi_slv_rsp_t axi_d64_a48_amo_peripherals_rsp; + + // Shim atomics, which are not supported in reg + // TODO: should we use a filter instead here? + axi_riscv_atomics_structs #( + .AxiAddrWidth ( Cfg.AddrWidth ), + .AxiDataWidth ( Cfg.AxiDataWidth ), + .AxiIdWidth ( AxiSlvIdWidth ), + .AxiUserWidth ( Cfg.AxiUserWidth ), + .AxiMaxReadTxns ( Cfg.RegMaxReadTxns ), + .AxiMaxWriteTxns ( Cfg.RegMaxWriteTxns ), + .AxiUserAsId ( 1 ), + .AxiUserIdMsb ( Cfg.AxiUserAmoMsb ), + .AxiUserIdLsb ( Cfg.AxiUserAmoLsb ), + .RiscvWordWidth ( 64 ), + .NAxiCuts ( Cfg.RegAmoNumCuts ), + .axi_req_t ( carfield_axi_slv_req_t ), + .axi_rsp_t ( carfield_axi_slv_rsp_t ) + ) i_atomics_peripherals ( + .clk_i ( periph_clk ), + .rst_ni ( periph_pwr_on_rst_n ), + .axi_slv_req_i ( axi_d64_a48_peripherals_req ), + .axi_slv_rsp_o ( axi_d64_a48_peripherals_rsp ), + .axi_mst_req_o ( axi_d64_a48_amo_peripherals_req ), + .axi_mst_rsp_i ( axi_d64_a48_amo_peripherals_rsp ) + ); -carfield_axi_d32_a32_slv_req_t axi_d32_a32_peripherals_req; -carfield_axi_d32_a32_slv_rsp_t axi_d32_a32_peripherals_rsp; - -axi_modify_address #( - .slv_req_t ( carfield_axi_d32_a48_slv_req_t ), - .mst_addr_t ( car_nar_addrw_t ), - .mst_req_t ( carfield_axi_d32_a32_slv_req_t ), - .axi_resp_t ( carfield_axi_d32_a32_slv_rsp_t ) -) i_axi_modify_addr_peripherals ( - .slv_req_i ( axi_d32_a48_peripherals_req ), - .slv_resp_o ( axi_d32_a48_peripherals_rsp ), - .mst_req_o ( axi_d32_a32_peripherals_req ), - .mst_resp_i ( axi_d32_a32_peripherals_rsp ), - .mst_aw_addr_i ( axi_d32_a48_peripherals_req.aw.addr[31:0] ), - .mst_ar_addr_i ( axi_d32_a48_peripherals_req.ar.addr[31:0] ) -); + carfield_axi_slv_req_t axi_d64_a48_amo_cut_peripherals_req; + carfield_axi_slv_rsp_t axi_d64_a48_amo_cut_peripherals_rsp; + + axi_cut #( + .Bypass ( ~Cfg.RegAmoPostCut ), + .aw_chan_t ( carfield_axi_slv_aw_chan_t ), + .w_chan_t ( carfield_axi_slv_w_chan_t ), + .b_chan_t ( carfield_axi_slv_b_chan_t ), + .ar_chan_t ( carfield_axi_slv_ar_chan_t ), + .r_chan_t ( carfield_axi_slv_r_chan_t ), + .axi_req_t ( carfield_axi_slv_req_t ), + .axi_resp_t ( carfield_axi_slv_rsp_t ) + ) i_atomics_cut_peripherals ( + .clk_i ( periph_clk ), + .rst_ni ( periph_pwr_on_rst_n ), + .slv_req_i ( axi_d64_a48_amo_peripherals_req ), + .slv_resp_o ( axi_d64_a48_amo_peripherals_rsp ), + .mst_req_o ( axi_d64_a48_amo_cut_peripherals_req ), + .mst_resp_i ( axi_d64_a48_amo_cut_peripherals_rsp ) + ); -// AXI to AXI lite conversion -// verilog_lint: waive-start line-length -`AXI_LITE_TYPEDEF_ALL_CT(carfield_axi_lite_d32_a32, carfield_axi_lite_d32_a32_slv_req_t, carfield_axi_lite_d32_a32_slv_rsp_t, car_nar_addrw_t, car_nar_dataw_t, car_nar_strb_t) -// verilog_lint: waive-stop line-length + // Convert to d32 a48 + // verilog_lint: waive-start line-length + `AXI_TYPEDEF_ALL_CT(carfield_axi_d32_a48_slv, carfield_axi_d32_a48_slv_req_t, carfield_axi_d32_a48_slv_rsp_t, car_addrw_t, car_slv_id_t, car_nar_dataw_t, car_nar_strb_t, car_usr_t) + // verilog_lint: waive-stop line-length + + carfield_axi_d32_a48_slv_req_t axi_d32_a48_peripherals_req; + carfield_axi_d32_a48_slv_rsp_t axi_d32_a48_peripherals_rsp; + + axi_dw_converter #( + .AxiSlvPortDataWidth ( Cfg.AxiDataWidth ), + .AxiMstPortDataWidth ( AxiNarrowDataWidth ), + .AxiAddrWidth ( Cfg.AddrWidth ), + .AxiIdWidth ( AxiSlvIdWidth ), + .aw_chan_t ( carfield_axi_slv_aw_chan_t ), + .mst_w_chan_t ( carfield_axi_d32_a48_slv_w_chan_t ), + .slv_w_chan_t ( carfield_axi_slv_w_chan_t ), + .b_chan_t ( carfield_axi_slv_b_chan_t ), + .ar_chan_t ( carfield_axi_slv_ar_chan_t ), + .mst_r_chan_t ( carfield_axi_d32_a48_slv_r_chan_t ), + .slv_r_chan_t ( carfield_axi_slv_r_chan_t ), + .axi_mst_req_t ( carfield_axi_d32_a48_slv_req_t ), + .axi_mst_resp_t ( carfield_axi_d32_a48_slv_rsp_t ), + .axi_slv_req_t ( carfield_axi_slv_req_t ), + .axi_slv_resp_t ( carfield_axi_slv_rsp_t ) + ) i_axi_dw_converter_peripherals ( + .clk_i ( periph_clk ), + .rst_ni ( periph_pwr_on_rst_n ), + .slv_req_i ( axi_d64_a48_amo_cut_peripherals_req ), + .slv_resp_o ( axi_d64_a48_amo_cut_peripherals_rsp ), + .mst_req_o ( axi_d32_a48_peripherals_req ), + .mst_resp_i ( axi_d32_a48_peripherals_rsp ) + ); -carfield_axi_lite_d32_a32_slv_req_t axi_lite_d32_a32_peripherals_req; -carfield_axi_lite_d32_a32_slv_rsp_t axi_lite_d32_a32_peripherals_rsp; - -axi_to_axi_lite #( - .AxiAddrWidth ( AxiNarrowAddrWidth ), - .AxiDataWidth ( AxiNarrowDataWidth ), - .AxiIdWidth ( AxiSlvIdWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiMaxWriteTxns( 1 ), - .AxiMaxReadTxns ( 1 ), - .FallThrough ( 1 ), - .full_req_t ( carfield_axi_d32_a32_slv_req_t ), - .full_resp_t ( carfield_axi_d32_a32_slv_rsp_t ), - .lite_req_t ( carfield_axi_lite_d32_a32_slv_req_t ), - .lite_resp_t ( carfield_axi_lite_d32_a32_slv_rsp_t ) -) i_axi_to_axi_lite_peripherals ( - .clk_i ( periph_clk ), - .rst_ni ( periph_pwr_on_rst_n ), - .test_i ( test_mode_i ), - .slv_req_i ( axi_d32_a32_peripherals_req ), - .slv_resp_o( axi_d32_a32_peripherals_rsp ), - .mst_req_o ( axi_lite_d32_a32_peripherals_req ), - .mst_resp_i( axi_lite_d32_a32_peripherals_rsp ) -); + // Convert to d32_a32 + // verilog_lint: waive-start line-length + `AXI_TYPEDEF_ALL_CT(carfield_axi_d32_a32_slv, carfield_axi_d32_a32_slv_req_t, carfield_axi_d32_a32_slv_rsp_t, car_nar_addrw_t, car_slv_id_t, car_nar_dataw_t, car_nar_strb_t, car_usr_t) + // verilog_lint: waive-stop line-length + + carfield_axi_d32_a32_slv_req_t axi_d32_a32_peripherals_req; + carfield_axi_d32_a32_slv_rsp_t axi_d32_a32_peripherals_rsp; + + axi_modify_address #( + .slv_req_t ( carfield_axi_d32_a48_slv_req_t ), + .mst_addr_t ( car_nar_addrw_t ), + .mst_req_t ( carfield_axi_d32_a32_slv_req_t ), + .axi_resp_t ( carfield_axi_d32_a32_slv_rsp_t ) + ) i_axi_modify_addr_peripherals ( + .slv_req_i ( axi_d32_a48_peripherals_req ), + .slv_resp_o ( axi_d32_a48_peripherals_rsp ), + .mst_req_o ( axi_d32_a32_peripherals_req ), + .mst_resp_i ( axi_d32_a32_peripherals_rsp ), + .mst_aw_addr_i ( axi_d32_a48_peripherals_req.aw.addr[31:0] ), + .mst_ar_addr_i ( axi_d32_a48_peripherals_req.ar.addr[31:0] ) + ); -// Address map rules for peripherals - -// Address map of peripheral system -typedef struct packed { - logic [31:0] idx; - car_nar_addrw_t start_addr; - car_nar_addrw_t end_addr; -} carfield_addr_map_rule_t; - -localparam carfield_addr_map_rule_t [NumApbMst-1:0] PeriphApbAddrMapRule = '{ - '{ idx: SystemTimerIdx, start_addr: SystemTimerBase, - end_addr: SystemTimerEnd }, // 0: System Timer - '{ idx: AdvancedTimerIdx, start_addr: AdvancedTimerBase, - end_addr: AdvancedTimerEnd }, // 1: Advanced Timer - '{ idx: SystemWdtIdx, start_addr: SystemWdtBase, - end_addr: SystemWdtEnd }, // 2: WDT - '{ idx: CanIdx, start_addr: CanBase, - end_addr: CanEnd }, // 3: Can - '{ idx: HyperBusIdx, start_addr: HyperBusBase, - end_addr: HyperBusEnd } // 4: Hyperbus -}; + // AXI to AXI lite conversion + // verilog_lint: waive-start line-length + `AXI_LITE_TYPEDEF_ALL_CT(carfield_axi_lite_d32_a32, carfield_axi_lite_d32_a32_slv_req_t, carfield_axi_lite_d32_a32_slv_rsp_t, car_nar_addrw_t, car_nar_dataw_t, car_nar_strb_t) + // verilog_lint: waive-stop line-length + + carfield_axi_lite_d32_a32_slv_req_t axi_lite_d32_a32_peripherals_req; + carfield_axi_lite_d32_a32_slv_rsp_t axi_lite_d32_a32_peripherals_rsp; + + axi_to_axi_lite #( + .AxiAddrWidth ( AxiNarrowAddrWidth ), + .AxiDataWidth ( AxiNarrowDataWidth ), + .AxiIdWidth ( AxiSlvIdWidth ), + .AxiUserWidth ( Cfg.AxiUserWidth ), + .AxiMaxWriteTxns( 1 ), + .AxiMaxReadTxns ( 1 ), + .FallThrough ( 1 ), + .full_req_t ( carfield_axi_d32_a32_slv_req_t ), + .full_resp_t ( carfield_axi_d32_a32_slv_rsp_t ), + .lite_req_t ( carfield_axi_lite_d32_a32_slv_req_t ), + .lite_resp_t ( carfield_axi_lite_d32_a32_slv_rsp_t ) + ) i_axi_to_axi_lite_peripherals ( + .clk_i ( periph_clk ), + .rst_ni ( periph_pwr_on_rst_n ), + .test_i ( test_mode_i ), + .slv_req_i ( axi_d32_a32_peripherals_req ), + .slv_resp_o( axi_d32_a32_peripherals_rsp ), + .mst_req_o ( axi_lite_d32_a32_peripherals_req ), + .mst_resp_i( axi_lite_d32_a32_peripherals_rsp ) + ); -// APB req/rsp -`APB_TYPEDEF_REQ_T(carfield_apb_req_t, car_nar_addrw_t, car_nar_dataw_t, car_nar_strb_t) -`APB_TYPEDEF_RESP_T(carfield_apb_rsp_t, car_nar_dataw_t) - -// APB masters -carfield_apb_req_t [NumApbMst-1:0] apb_mst_req; -carfield_apb_rsp_t [NumApbMst-1:0] apb_mst_rsp; - -axi_lite_to_apb #( - .NoApbSlaves ( NumApbMst ), - .NoRules ( NumApbMst ), - .AddrWidth ( AxiNarrowAddrWidth ), - .DataWidth ( AxiNarrowDataWidth ), - .PipelineRequest ( '0 ), - .PipelineResponse( '0 ), - .axi_lite_req_t ( carfield_axi_lite_d32_a32_slv_req_t ), - .axi_lite_resp_t ( carfield_axi_lite_d32_a32_slv_rsp_t ), - .apb_req_t ( carfield_apb_req_t ), - .apb_resp_t ( carfield_apb_rsp_t ), - .rule_t ( carfield_addr_map_rule_t ) -) i_axi_lite_to_apb_peripherals ( - .clk_i ( periph_clk ), - .rst_ni ( periph_pwr_on_rst_n ), - .axi_lite_req_i ( axi_lite_d32_a32_peripherals_req ), - .axi_lite_resp_o( axi_lite_d32_a32_peripherals_rsp ), - .apb_req_o ( apb_mst_req ), - .apb_resp_i ( apb_mst_rsp ), - .addr_map_i ( PeriphApbAddrMapRule ) -); + // APB req/rsp + `APB_TYPEDEF_REQ_T(carfield_apb_req_t, car_nar_addrw_t, car_nar_dataw_t, car_nar_strb_t) + `APB_TYPEDEF_RESP_T(carfield_apb_rsp_t, car_nar_dataw_t) + + // APB masters + carfield_apb_req_t [NumApbMst-1:0] apb_mst_req; + carfield_apb_rsp_t [NumApbMst-1:0] apb_mst_rsp; + + axi_lite_to_apb #( + .NoApbSlaves ( NumApbMst ), + .NoRules ( NumApbMst ), + .AddrWidth ( AxiNarrowAddrWidth ), + .DataWidth ( AxiNarrowDataWidth ), + .PipelineRequest ( '0 ), + .PipelineResponse( '0 ), + .axi_lite_req_t ( carfield_axi_lite_d32_a32_slv_req_t ), + .axi_lite_resp_t ( carfield_axi_lite_d32_a32_slv_rsp_t ), + .apb_req_t ( carfield_apb_req_t ), + .apb_resp_t ( carfield_apb_rsp_t ), + .rule_t ( carfield_addr_map_rule_t ) + ) i_axi_lite_to_apb_peripherals ( + .clk_i ( periph_clk ), + .rst_ni ( periph_pwr_on_rst_n ), + .axi_lite_req_i ( axi_lite_d32_a32_peripherals_req ), + .axi_lite_resp_o( axi_lite_d32_a32_peripherals_rsp ), + .apb_req_o ( apb_mst_req ), + .apb_resp_i ( apb_mst_rsp ), + .addr_map_i ( PeriphApbAddrMapRule ) + ); -// System timer -apb_timer_unit #( - .APB_ADDR_WIDTH ( AxiNarrowAddrWidth ) -) i_system_timer ( - .HCLK ( periph_clk ), - .HRESETn ( periph_pwr_on_rst_n ), - .PADDR ( apb_mst_req[SystemTimerIdx].paddr ), - .PWDATA ( apb_mst_req[SystemTimerIdx].pwdata ), - .PWRITE ( apb_mst_req[SystemTimerIdx].pwrite ), - .PSEL ( apb_mst_req[SystemTimerIdx].psel ), - .PENABLE ( apb_mst_req[SystemTimerIdx].penable ), - .PRDATA ( apb_mst_rsp[SystemTimerIdx].prdata ), - .PREADY ( apb_mst_rsp[SystemTimerIdx].pready ), - .PSLVERR ( apb_mst_rsp[SystemTimerIdx].pslverr ), - .ref_clk_i ( rt_clk_i ), - .event_lo_i ( '0 ), - .event_hi_i ( '0 ), - .irq_lo_o ( car_sys_timer_lo_intr ), - .irq_hi_o ( car_sys_timer_hi_intr ), - .busy_o ( /* TODO connect me */ ) -); + // System timer + apb_timer_unit #( + .APB_ADDR_WIDTH ( AxiNarrowAddrWidth ) + ) i_system_timer ( + .HCLK ( periph_clk ), + .HRESETn ( periph_pwr_on_rst_n ), + .PADDR ( apb_mst_req[SystemTimerIdx].paddr ), + .PWDATA ( apb_mst_req[SystemTimerIdx].pwdata ), + .PWRITE ( apb_mst_req[SystemTimerIdx].pwrite ), + .PSEL ( apb_mst_req[SystemTimerIdx].psel ), + .PENABLE ( apb_mst_req[SystemTimerIdx].penable ), + .PRDATA ( apb_mst_rsp[SystemTimerIdx].prdata ), + .PREADY ( apb_mst_rsp[SystemTimerIdx].pready ), + .PSLVERR ( apb_mst_rsp[SystemTimerIdx].pslverr ), + .ref_clk_i ( rt_clk_i ), + .event_lo_i ( '0 ), + .event_hi_i ( '0 ), + .irq_lo_o ( car_sys_timer_lo_intr ), + .irq_hi_o ( car_sys_timer_hi_intr ), + .busy_o ( /* TODO connect me */ ) + ); -// Advanced Timer -apb_adv_timer #( - .APB_ADDR_WIDTH ( AxiNarrowAddrWidth ), - .EXTSIG_NUM ( 64 ) -) i_advanced_timer ( - .HCLK ( periph_clk ), - .HRESETn ( periph_pwr_on_rst_n ), - .dft_cg_enable_i ( 1'b0 ), - .PADDR ( apb_mst_req[AdvancedTimerIdx].paddr ), - .PWDATA ( apb_mst_req[AdvancedTimerIdx].pwdata ), - .PWRITE ( apb_mst_req[AdvancedTimerIdx].pwrite ), - .PSEL ( apb_mst_req[AdvancedTimerIdx].psel ), - .PENABLE ( apb_mst_req[AdvancedTimerIdx].penable ), - .PRDATA ( apb_mst_rsp[AdvancedTimerIdx].prdata ), - .PREADY ( apb_mst_rsp[AdvancedTimerIdx].pready ), - .PSLVERR ( apb_mst_rsp[AdvancedTimerIdx].pslverr ), - .low_speed_clk_i ( rt_clk_i ), - .ext_sig_i ( '0 /* TODO connect me */ ), - .events_o ( car_adv_timer_events ), - .ch_0_o ( car_adv_timer_intrs ), - .ch_1_o ( ), - .ch_2_o ( ), - .ch_3_o ( ) -); + // Advanced Timer + apb_adv_timer #( + .APB_ADDR_WIDTH ( AxiNarrowAddrWidth ), + .EXTSIG_NUM ( 64 ) + ) i_advanced_timer ( + .HCLK ( periph_clk ), + .HRESETn ( periph_pwr_on_rst_n ), + .dft_cg_enable_i ( 1'b0 ), + .PADDR ( apb_mst_req[AdvancedTimerIdx].paddr ), + .PWDATA ( apb_mst_req[AdvancedTimerIdx].pwdata ), + .PWRITE ( apb_mst_req[AdvancedTimerIdx].pwrite ), + .PSEL ( apb_mst_req[AdvancedTimerIdx].psel ), + .PENABLE ( apb_mst_req[AdvancedTimerIdx].penable ), + .PRDATA ( apb_mst_rsp[AdvancedTimerIdx].prdata ), + .PREADY ( apb_mst_rsp[AdvancedTimerIdx].pready ), + .PSLVERR ( apb_mst_rsp[AdvancedTimerIdx].pslverr ), + .low_speed_clk_i ( rt_clk_i ), + .ext_sig_i ( '0 /* TODO connect me */ ), + .events_o ( car_adv_timer_events ), + .ch_0_o ( car_adv_timer_intrs ), + .ch_1_o ( ), + .ch_2_o ( ), + .ch_3_o ( ) + ); -// Watchdog timer -REG_BUS #( - .ADDR_WIDTH ( AxiNarrowAddrWidth ), - .DATA_WIDTH ( AxiNarrowDataWidth ) -) reg_bus_wdt (periph_clk); - -apb_to_reg i_apb_to_reg_wdt ( - .clk_i ( periph_clk ), - .rst_ni ( periph_pwr_on_rst_n ), - .penable_i ( apb_mst_req[SystemWdtIdx].penable ), - .pwrite_i ( apb_mst_req[SystemWdtIdx].pwrite ), - .paddr_i ( apb_mst_req[SystemWdtIdx].paddr ), - .psel_i ( apb_mst_req[SystemWdtIdx].psel ), - .pwdata_i ( apb_mst_req[SystemWdtIdx].pwdata ), - .prdata_o ( apb_mst_rsp[SystemWdtIdx].prdata ), - .pready_o ( apb_mst_rsp[SystemWdtIdx].pready ), - .pslverr_o ( apb_mst_rsp[SystemWdtIdx].pslverr ), - .reg_o ( reg_bus_wdt ) -); + // Watchdog timer + REG_BUS #( + .ADDR_WIDTH ( AxiNarrowAddrWidth ), + .DATA_WIDTH ( AxiNarrowDataWidth ) + ) reg_bus_wdt (periph_clk); + + apb_to_reg i_apb_to_reg_wdt ( + .clk_i ( periph_clk ), + .rst_ni ( periph_pwr_on_rst_n ), + .penable_i ( apb_mst_req[SystemWdtIdx].penable ), + .pwrite_i ( apb_mst_req[SystemWdtIdx].pwrite ), + .paddr_i ( apb_mst_req[SystemWdtIdx].paddr ), + .psel_i ( apb_mst_req[SystemWdtIdx].psel ), + .pwdata_i ( apb_mst_req[SystemWdtIdx].pwdata ), + .prdata_o ( apb_mst_rsp[SystemWdtIdx].prdata ), + .pready_o ( apb_mst_rsp[SystemWdtIdx].pready ), + .pslverr_o ( apb_mst_rsp[SystemWdtIdx].pslverr ), + .reg_o ( reg_bus_wdt ) + ); -// crop the address to 32-bit -assign reg_wdt_req.addr = reg_bus_wdt.addr; -assign reg_wdt_req.write = reg_bus_wdt.write; -assign reg_wdt_req.wdata = reg_bus_wdt.wdata; -assign reg_wdt_req.wstrb = reg_bus_wdt.wstrb; -assign reg_wdt_req.valid = reg_bus_wdt.valid; - -assign reg_bus_wdt.rdata = reg_wdt_rsp.rdata; -assign reg_bus_wdt.error = reg_wdt_rsp.error; -assign reg_bus_wdt.ready = reg_wdt_rsp.ready; - -// reg to tilelink -tlul_ot_pkg::tl_h2d_t tl_wdt_req; -tlul_ot_pkg::tl_d2h_t tl_wdt_rsp; - -reg_to_tlul #( - .req_t ( carfield_a32_d32_reg_req_t ), - .rsp_t ( carfield_a32_d32_reg_rsp_t ), - .tl_h2d_t ( tlul_ot_pkg::tl_h2d_t ), - .tl_d2h_t ( tlul_ot_pkg::tl_d2h_t ), - .tl_a_user_t ( tlul_ot_pkg::tl_a_user_t ), - .tl_a_op_e ( tlul_ot_pkg::tl_a_op_e ), - .TL_A_USER_DEFAULT ( tlul_ot_pkg::TL_A_USER_DEFAULT ), - .PutFullData ( tlul_ot_pkg::PutFullData ), - .Get ( tlul_ot_pkg::Get ) -) i_reg_to_tlul_wdt ( - .tl_o ( tl_wdt_req ), - .tl_i ( tl_wdt_rsp ), - .reg_req_i ( reg_wdt_req ), - .reg_rsp_o ( reg_wdt_rsp ) -); + // crop the address to 32-bit + assign reg_wdt_req.addr = reg_bus_wdt.addr; + assign reg_wdt_req.write = reg_bus_wdt.write; + assign reg_wdt_req.wdata = reg_bus_wdt.wdata; + assign reg_wdt_req.wstrb = reg_bus_wdt.wstrb; + assign reg_wdt_req.valid = reg_bus_wdt.valid; + + assign reg_bus_wdt.rdata = reg_wdt_rsp.rdata; + assign reg_bus_wdt.error = reg_wdt_rsp.error; + assign reg_bus_wdt.ready = reg_wdt_rsp.ready; + + // reg to tilelink + tlul_ot_pkg::tl_h2d_t tl_wdt_req; + tlul_ot_pkg::tl_d2h_t tl_wdt_rsp; + + reg_to_tlul #( + .req_t ( carfield_a32_d32_reg_req_t ), + .rsp_t ( carfield_a32_d32_reg_rsp_t ), + .tl_h2d_t ( tlul_ot_pkg::tl_h2d_t ), + .tl_d2h_t ( tlul_ot_pkg::tl_d2h_t ), + .tl_a_user_t ( tlul_ot_pkg::tl_a_user_t ), + .tl_a_op_e ( tlul_ot_pkg::tl_a_op_e ), + .TL_A_USER_DEFAULT ( tlul_ot_pkg::TL_A_USER_DEFAULT ), + .PutFullData ( tlul_ot_pkg::PutFullData ), + .Get ( tlul_ot_pkg::Get ) + ) i_reg_to_tlul_wdt ( + .tl_o ( tl_wdt_req ), + .tl_i ( tl_wdt_rsp ), + .reg_req_i ( reg_wdt_req ), + .reg_rsp_o ( reg_wdt_rsp ) + ); -// Wdt -aon_timer i_watchdog_timer ( - .clk_i ( periph_clk ), - .rst_ni ( periph_pwr_on_rst_n ), - .clk_aon_i ( rt_clk_i ), - .rst_aon_ni ( periph_pwr_on_rst_n ), - .tl_i ( tl_wdt_req ), - .tl_o ( tl_wdt_rsp ), - .alert_rx_i ( '0 ), // TODO: what are these for? - .alert_tx_o ( /* TODO connect me */ ), - .lc_escalate_en_i ( '0 ), - .intr_wkup_timer_expired_o ( car_wdt_intrs[0] ), - .intr_wdog_timer_bark_o ( car_wdt_intrs[1] ), - .nmi_wdog_timer_bark_o ( car_wdt_intrs[2] ), - .wkup_req_o ( car_wdt_intrs[3] ), - .aon_timer_rst_req_o ( car_wdt_intrs[4] ), - .sleep_mode_i ( '0 ) -); + // Wdt + aon_timer i_watchdog_timer ( + .clk_i ( periph_clk ), + .rst_ni ( periph_pwr_on_rst_n ), + .clk_aon_i ( rt_clk_i ), + .rst_aon_ni ( periph_pwr_on_rst_n ), + .tl_i ( tl_wdt_req ), + .tl_o ( tl_wdt_rsp ), + .alert_rx_i ( '0 ), // TODO: what are these for? + .alert_tx_o ( /* TODO connect me */ ), + .lc_escalate_en_i ( '0 ), + .intr_wkup_timer_expired_o ( car_wdt_intrs[0] ), + .intr_wdog_timer_bark_o ( car_wdt_intrs[1] ), + .nmi_wdog_timer_bark_o ( car_wdt_intrs[2] ), + .wkup_req_o ( car_wdt_intrs[3] ), + .aon_timer_rst_req_o ( car_wdt_intrs[4] ), + .sleep_mode_i ( '0 ) + ); -// Hyperbus -REG_BUS #( - .ADDR_WIDTH ( AxiNarrowAddrWidth ), - .DATA_WIDTH ( AxiNarrowDataWidth ) -) reg_bus_hyper (periph_clk); - -apb_to_reg i_apb_to_reg_hyper ( - .clk_i ( periph_clk ), - .rst_ni ( periph_pwr_on_rst_n ), - .penable_i ( apb_mst_req[HyperBusIdx].penable ), - .pwrite_i ( apb_mst_req[HyperBusIdx].pwrite ), - .paddr_i ( apb_mst_req[HyperBusIdx].paddr ), - .psel_i ( apb_mst_req[HyperBusIdx].psel ), - .pwdata_i ( apb_mst_req[HyperBusIdx].pwdata ), - .prdata_o ( apb_mst_rsp[HyperBusIdx].prdata ), - .pready_o ( apb_mst_rsp[HyperBusIdx].pready ), - .pslverr_o ( apb_mst_rsp[HyperBusIdx].pslverr ), - .reg_o ( reg_bus_hyper ) -); + // Hyperbus + REG_BUS #( + .ADDR_WIDTH ( AxiNarrowAddrWidth ), + .DATA_WIDTH ( AxiNarrowDataWidth ) + ) reg_bus_hyper (periph_clk); + + apb_to_reg i_apb_to_reg_hyper ( + .clk_i ( periph_clk ), + .rst_ni ( periph_pwr_on_rst_n ), + .penable_i ( apb_mst_req[HyperBusIdx].penable ), + .pwrite_i ( apb_mst_req[HyperBusIdx].pwrite ), + .paddr_i ( apb_mst_req[HyperBusIdx].paddr ), + .psel_i ( apb_mst_req[HyperBusIdx].psel ), + .pwdata_i ( apb_mst_req[HyperBusIdx].pwdata ), + .prdata_o ( apb_mst_rsp[HyperBusIdx].prdata ), + .pready_o ( apb_mst_rsp[HyperBusIdx].pready ), + .pslverr_o ( apb_mst_rsp[HyperBusIdx].pslverr ), + .reg_o ( reg_bus_hyper ) + ); -assign reg_hyper_req.addr = reg_bus_hyper.addr; -assign reg_hyper_req.write = reg_bus_hyper.write; -assign reg_hyper_req.wdata = reg_bus_hyper.wdata; -assign reg_hyper_req.wstrb = reg_bus_hyper.wstrb; -assign reg_hyper_req.valid = reg_bus_hyper.valid; - -assign reg_bus_hyper.rdata = reg_hyper_rsp.rdata; -assign reg_bus_hyper.error = reg_hyper_rsp.error; -assign reg_bus_hyper.ready = reg_hyper_rsp.ready; - -// CAN bus -logic [63:0] can_timestamp; -assign can_timestamp = '1; -if (IslandsCfg.EnCan) begin : gen_can -can_top_apb #( - .rx_buffer_size ( 32 ), - .txt_buffer_count ( 2 ), - .target_technology( 0 ) // 0 for ASIC or 1 for FPGA - ) i_apb_to_can ( - .aclk ( periph_clk ), - .arstn ( periph_pwr_on_rst_n ), - .scan_enable ( 1'b0 ), - .res_n_out ( ), - .irq ( car_can_intr ), - .CAN_tx ( can_tx_o ), - .CAN_rx ( can_rx_i ), - .timestamp ( can_timestamp ), - .s_apb_paddr ( apb_mst_req[CanIdx].paddr ), - .s_apb_penable ( apb_mst_req[CanIdx].penable ), - .s_apb_pprot ( 3'b000 ), - .s_apb_prdata ( apb_mst_rsp[CanIdx].prdata ), - .s_apb_pready ( apb_mst_rsp[CanIdx].pready ), - .s_apb_psel ( apb_mst_req[CanIdx].psel ), - .s_apb_pslverr ( apb_mst_rsp[CanIdx].pslverr ), - .s_apb_pstrb ( 4'b1111 ), - .s_apb_pwdata ( apb_mst_req[CanIdx].pwdata ), - .s_apb_pwrite ( apb_mst_req[CanIdx].pwrite ) -); + assign reg_hyper_req.addr = reg_bus_hyper.addr; + assign reg_hyper_req.write = reg_bus_hyper.write; + assign reg_hyper_req.wdata = reg_bus_hyper.wdata; + assign reg_hyper_req.wstrb = reg_bus_hyper.wstrb; + assign reg_hyper_req.valid = reg_bus_hyper.valid; + + assign reg_bus_hyper.rdata = reg_hyper_rsp.rdata; + assign reg_bus_hyper.error = reg_hyper_rsp.error; + assign reg_bus_hyper.ready = reg_hyper_rsp.ready; + + // CAN bus + logic [63:0] can_timestamp; + assign can_timestamp = '1; + if (carfield_configuration::CanEnable) begin: gen_can + can_top_apb #( + .rx_buffer_size ( 32 ), + .txt_buffer_count ( 2 ), + .target_technology( 0 ) // 0 for ASIC or 1 for FPGA + ) i_apb_to_can ( + .aclk ( periph_clk ), + .arstn ( periph_pwr_on_rst_n ), + .scan_enable ( 1'b0 ), + .res_n_out ( ), + .irq ( car_can_intr ), + .CAN_tx ( can_tx_o ), + .CAN_rx ( can_rx_i ), + .timestamp ( can_timestamp ), + .s_apb_paddr ( apb_mst_req[CanIdx].paddr ), + .s_apb_penable ( apb_mst_req[CanIdx].penable ), + .s_apb_pprot ( 3'b000 ), + .s_apb_prdata ( apb_mst_rsp[CanIdx].prdata ), + .s_apb_pready ( apb_mst_rsp[CanIdx].pready ), + .s_apb_psel ( apb_mst_req[CanIdx].psel ), + .s_apb_pslverr ( apb_mst_rsp[CanIdx].pslverr ), + .s_apb_pstrb ( 4'b1111 ), + .s_apb_pwdata ( apb_mst_req[CanIdx].pwdata ), + .s_apb_pwrite ( apb_mst_req[CanIdx].pwrite ) + ); + end else begin: gen_no_can + assign car_can_intr = '0; + assign can_tx_o = '0; + assign apb_mst_rsp[CanIdx] = '0; + end +end else begin: gen_no_periph + assign car_regs_hw2reg.periph_isolate_status.d = '0; + assign car_regs_hw2reg.periph_isolate_status.de = '0; end - endmodule diff --git a/hw/carfield_pkg.sv b/hw/carfield_pkg.sv index 109ad9d9..d3701bdd 100644 --- a/hw/carfield_pkg.sv +++ b/hw/carfield_pkg.sv @@ -13,6 +13,379 @@ package carfield_pkg; import cheshire_pkg::*; +import carfield_configuration::*; + +/*********************************** +* Carfield Configuration functions * +***********************************/ + +// Below there are the functions used to flexibly reconfigure +// Carfield's depending on a `carfield_configuration` file were +// it is possible to enable/disable given islands and adapt the +// SoC's memory map accordingly. The following functions are all +// used within the `carfield_pkg` only. + +typedef struct packed { + bit enable; + doub_bt base; + doub_bt size; +} islands_properties_t; + +typedef struct packed { + islands_properties_t l2_port0; + islands_properties_t l2_port1; + islands_properties_t safed; + islands_properties_t ethernet; + islands_properties_t periph; + islands_properties_t spatz; + islands_properties_t pulp; + islands_properties_t secured; + islands_properties_t mbox; +} islands_cfg_t; + +// Types are obtained from Cheshire package +// Parameter MaxExtAxiSlvWidth is obtained from Cheshire +// Structure used to create the AXI map to be passed to +// the Cheshire configuration parameter to create the +// AXI crossbar. +localparam int unsigned MaxExtAxiSlv = 2**MaxExtAxiSlvWidth; +typedef struct packed { + byte_bt [MaxExtAxiSlv-1:0] AxiIdx; + doub_bt [MaxExtAxiSlv-1:0] AxiStart; + doub_bt [MaxExtAxiSlv-1:0] AxiEnd; +} axi_struct_t; + +typedef struct packed { + byte_bt l2_port0; + byte_bt l2_port1; + byte_bt safed; + byte_bt ethernet; + byte_bt periph; + byte_bt spatz; + byte_bt pulp; + byte_bt mbox; +} carfield_slave_idx_t; + +typedef struct packed { + byte_bt safed; + byte_bt spatz; + byte_bt secured; + byte_bt pulp; +} carfield_master_idx_t; + +// Generate the number of AXI slave devices to be connected to the +// crossbar starting from the islands enable structure. +function automatic int unsigned gen_num_axi_slave(islands_cfg_t island_cfg); + int unsigned ret = 0; // Number of slaves starts from 0 + if (island_cfg.l2_port0.enable) begin + ret++; // If we enable L2, we increase by 1 + if (island_cfg.l2_port1.enable) + ret++; // If the L2 is dualport, increase again + end + if (island_cfg.safed.enable ) begin ret++; end + if (island_cfg.periph.enable ) begin ret++; end + if (island_cfg.ethernet.enable) begin ret++; end + if (island_cfg.spatz.enable ) begin ret++; end + if (island_cfg.pulp.enable ) begin ret++; end + if (island_cfg.mbox.enable ) begin ret++; end + return ret; +endfunction + +// Generate the IDs for each AXI slave device +function automatic carfield_slave_idx_t carfield_gen_axi_slave_idx(islands_cfg_t island_cfg); + carfield_slave_idx_t ret = '{default: '0}; // Initialize struct first + byte_bt i = 0; + byte_bt j = 0; + if (island_cfg.l2_port0.enable) begin ret.l2_port0 = i; i++; + if (island_cfg.l2_port1.enable) begin ret.l2_port1 = i; i++; end + end else begin + ret.l2_port0 = MaxExtAxiSlv + j; j++; + ret.l2_port1 = MaxExtAxiSlv + j; j++; + end + if (island_cfg.safed.enable) begin ret.safed = i; i++; + end else begin ret.safed = MaxExtAxiSlv + j; j++; end + if (island_cfg.ethernet.enable) begin ret.ethernet = i; i++; + end else begin ret.ethernet = MaxExtAxiSlv + j; j++; end + if (island_cfg.periph.enable) begin ret.periph = i; i++; + end else begin ret.periph = MaxExtAxiSlv + j; j++; end + if (island_cfg.spatz.enable) begin ret.spatz = i; i++; + end else begin ret.spatz = MaxExtAxiSlv + j; j++; end + if (island_cfg.pulp.enable) begin ret.pulp = i; i++; + end else begin ret.pulp = MaxExtAxiSlv + j; j++; end + if (island_cfg.mbox.enable) begin ret.mbox = i; i++; + end else begin ret.mbox = MaxExtAxiSlv + j; j++; end + return ret; +endfunction + +// Generate the number of AXI master devices that connect to the +// crossbar starting from the islands enable structure. +function automatic int unsigned gen_num_axi_master(islands_cfg_t island_cfg); + int unsigned ret = 0; // Number of masters starts from 0 + if (island_cfg.safed.enable ) begin ret++; end + if (island_cfg.spatz.enable ) begin ret++; end + if (island_cfg.pulp.enable ) begin ret++; end + if (island_cfg.secured.enable) begin ret++; end + return ret; +endfunction + +// Generate the IDs for each AXI master device +localparam int unsigned MaxExtAxiMst = 2**MaxExtAxiMstWidth; +function automatic carfield_master_idx_t carfield_gen_axi_master_idx(islands_cfg_t island_cfg); + carfield_master_idx_t ret = '{default: '0}; // Initialize struct first + byte_bt i = 0; + byte_bt j = 0; + if (island_cfg.safed.enable) begin ret.safed = i; i++; + end else begin ret.safed = MaxExtAxiMst + j; j++; end + if (island_cfg.secured.enable) begin ret.secured = i; i++; + end else begin ret.secured = MaxExtAxiMst + j; j++; end + if (island_cfg.spatz.enable) begin ret.spatz = i; i++; + end else begin ret.spatz = MaxExtAxiMst + j; j++; end + if (island_cfg.pulp.enable) begin ret.pulp = i; i++; + end else begin ret.pulp = MaxExtAxiMst + j; j++; end + return ret; +endfunction + +// Compute memory map +function automatic axi_struct_t carfield_gen_axi_map(int unsigned NumSlave , + islands_cfg_t island_cfg, + carfield_slave_idx_t idx); + axi_struct_t ret = '0; // Initialize the map first + int unsigned i = 0; + if (island_cfg.l2_port0.enable) begin + ret.AxiIdx[i] = idx.l2_port0; + ret.AxiStart[i] = island_cfg.l2_port0.base; + ret.AxiEnd[i] = island_cfg.l2_port0.base + island_cfg.l2_port0.size; + if (i < NumSlave - 1) i++; + if (island_cfg.l2_port1.enable) begin + ret.AxiIdx[i] = idx.l2_port1; + ret.AxiStart[i] = island_cfg.l2_port1.base; + ret.AxiEnd[i] = island_cfg.l2_port1.base + island_cfg.l2_port1.size; + if (i < NumSlave - 1) i++; + end + end + if (island_cfg.safed.enable) begin + ret.AxiIdx[i] = idx.safed; + ret.AxiStart[i] = island_cfg.safed.base; + ret.AxiEnd[i] = island_cfg.safed.base + island_cfg.safed.size; + if (i < NumSlave - 1) i++; + end + if (island_cfg.ethernet.enable) begin + ret.AxiIdx[i] = idx.ethernet; + ret.AxiStart[i] = island_cfg.ethernet.base; + ret.AxiEnd[i] = island_cfg.ethernet.base + island_cfg.ethernet.size; + if (i < NumSlave - 1) i++; + end + if (island_cfg.periph.enable) begin + ret.AxiIdx[i] = idx.periph; + ret.AxiStart[i] = island_cfg.periph.base; + ret.AxiEnd[i] = island_cfg.periph.base + island_cfg.periph.size; + if (i < NumSlave - 1) i++; + end + if (island_cfg.spatz.enable) begin + ret.AxiIdx[i] = idx.spatz; + ret.AxiStart[i] = island_cfg.spatz.base; + ret.AxiEnd[i] = island_cfg.spatz.base + island_cfg.spatz.size; + if (i < NumSlave - 1) i++; + end + if (island_cfg.pulp.enable) begin + ret.AxiIdx[i] = idx.pulp; + ret.AxiStart[i] = island_cfg.pulp.base; + ret.AxiEnd[i] = island_cfg.pulp.base + island_cfg.pulp.size; + if (i < NumSlave - 1) i++; + end + if (island_cfg.mbox.enable) begin + ret.AxiIdx[i] = idx.mbox; + ret.AxiStart[i] = island_cfg.mbox.base; + ret.AxiEnd[i] = island_cfg.mbox.base + island_cfg.mbox.size; + if (i < NumSlave - 1) i++; + end + return ret; +endfunction + +/******************** + * RegBus functions * + *******************/ +typedef struct packed { + islands_properties_t pcrs; + islands_properties_t pll; + islands_properties_t padframe; + islands_properties_t l2ecc; +} regbus_cfg_t; + +typedef struct packed { + byte_bt pcrs; + byte_bt pll; + byte_bt padframe; + byte_bt l2ecc; +} carfield_regbus_slave_idx_t; + +// Generate the number of AXI slave devices to be connected to the +// crossbar starting from the islands enable structure. +function automatic int unsigned gen_num_regbus_sync_slave(regbus_cfg_t regbus_cfg); + int unsigned ret = 0; // Number of slaves starts from 0 + if (regbus_cfg.pcrs.enable) begin ret++; end + return ret; +endfunction + +function automatic int unsigned gen_num_regbus_async_slave(regbus_cfg_t regbus_cfg); + int unsigned ret = 0; // Number of slaves starts from 0 + if (regbus_cfg.pll.enable ) begin ret++; end + if (regbus_cfg.padframe.enable) begin ret++; end + if (regbus_cfg.l2ecc.enable ) begin ret++; end + return ret; +endfunction + +localparam regbus_cfg_t CarfieldRegBusCfg = '{ + pcrs: '{1, PcrsBase, PcrsSize}, + pll: '{PllCfgEnable, PllCfgBase, PllCfgSize}, + padframe: '{PadframeCfgEnable, PadframeCfgBase, PadframeCfgSize}, + l2ecc: '{L2EccCfgEnable, L2EccCfgBase, L2EccCfgSize} +}; + +localparam int unsigned NumSyncRegSlv = gen_num_regbus_sync_slave(CarfieldRegBusCfg); +localparam int unsigned NumAsyncRegSlv = gen_num_regbus_async_slave(CarfieldRegBusCfg); +localparam int unsigned NumTotalRegSlv = NumSyncRegSlv + NumAsyncRegSlv; + +// Generate the IDs for each AXI slave device +// verilog_lint: waive-start line-length +function automatic carfield_regbus_slave_idx_t carfield_gen_regbus_slave_idx(regbus_cfg_t regbus_cfg); +// verilog_lint: waive-stop line-length + carfield_regbus_slave_idx_t ret = '{default: '0}; // Initialize struct first + byte_bt i = 0; + byte_bt j = 0; + if (regbus_cfg.pcrs.enable) begin ret.pcrs = i; i++; + end else begin ret.pcrs = NumTotalRegSlv + j; j++; end + if (regbus_cfg.pll.enable) begin ret.pll = i; i++; + end else begin ret.pll = NumTotalRegSlv + j; j++; end + if (regbus_cfg.padframe.enable) begin ret.padframe = i; i++; + end else begin ret.padframe = NumTotalRegSlv + j; j++; end + if (regbus_cfg.l2ecc.enable) begin ret.l2ecc = i; i++; + end else begin ret.l2ecc = NumTotalRegSlv + j; j++; end + return ret; +endfunction + +typedef struct packed { + byte_bt [NumTotalRegSlv-1:0] RegBusIdx; + doub_bt [NumTotalRegSlv-1:0] RegBusStart; + doub_bt [NumTotalRegSlv-1:0] RegBusEnd; +} regbus_struct_t; + +// Compute RegBus memory map +function automatic regbus_struct_t carfield_gen_regbus_map(int unsigned NumSlave , + regbus_cfg_t regbus_cfg , + carfield_regbus_slave_idx_t idx); + regbus_struct_t ret = '0; // Initialize the map first + int unsigned i = 0; + if (regbus_cfg.pcrs.enable) begin + ret.RegBusIdx[i] = idx.pcrs; + ret.RegBusStart[i] = regbus_cfg.pcrs.base; + ret.RegBusEnd[i] = regbus_cfg.pcrs.base + regbus_cfg.pcrs.size; + if (i < NumSlave - 1) i++; + end + if (regbus_cfg.pll.enable) begin + ret.RegBusIdx[i] = idx.pll; + ret.RegBusStart[i] = regbus_cfg.pll.base; + ret.RegBusEnd[i] = regbus_cfg.pll.base + regbus_cfg.pll.size; + if (i < NumSlave - 1) i++; + end + if (regbus_cfg.padframe.enable) begin + ret.RegBusIdx[i] = idx.padframe; + ret.RegBusStart[i] = regbus_cfg.padframe.base; + ret.RegBusEnd[i] = regbus_cfg.padframe.base + regbus_cfg.padframe.size; + if (i < NumSlave - 1) i++; + end + if (regbus_cfg.l2ecc.enable) begin + ret.RegBusIdx[i] = idx.l2ecc; + ret.RegBusStart[i] = regbus_cfg.l2ecc.base; + ret.RegBusEnd[i] = regbus_cfg.l2ecc.base + regbus_cfg.l2ecc.size; + if (i < NumSlave - 1) i++; + end + return ret; +endfunction + +// Generate number of existent domains +function automatic int unsigned gen_carfield_domains(islands_cfg_t island_cfg); + int unsigned ret = 0; // Number of availale domains starts from 0 + if (island_cfg.l2_port0.enable) begin ret++; end + if (island_cfg.safed.enable ) begin ret++; end + if (island_cfg.periph.enable ) begin ret++; end + if (island_cfg.spatz.enable ) begin ret++; end + if (island_cfg.pulp.enable ) begin ret++; end + if (island_cfg.secured.enable ) begin ret++; end + return ret; +endfunction + +localparam islands_cfg_t CarfieldIslandsCfg = '{ + l2_port0: '{L2Port0Enable, L2Port0Base, L2Port0Size}, + l2_port1: '{L2Port1Enable, L2Port1Base, L2Port1Size}, + safed: '{SafetyIslandEnable, SafetyIslandBase, SafetyIslandSize}, + ethernet: '{EthernetEnable, EthernetBase, EthernetSize}, + periph: '{PeriphEnable, PeriphBase, PeriphSize}, + spatz: '{SpatzClusterEnable, SpatzClusterBase, SpatzClusterSize}, + pulp: '{PulpClusterEnable, PulpClusterBase, PulpClusterSize}, + secured: '{SecurityIslandEnable, SecurityIslandBase, SecurityIslandSize}, + mbox: '{MailboxEnable, MailboxBase, MailboxSize} +}; + +localparam int unsigned CarfieldAxiNumSlaves = gen_num_axi_slave(CarfieldIslandsCfg); +localparam carfield_slave_idx_t CarfieldAxiSlvIdx = carfield_gen_axi_slave_idx(CarfieldIslandsCfg); +localparam int unsigned CarfieldAxiNumMasters = gen_num_axi_master(CarfieldIslandsCfg); +localparam carfield_master_idx_t CarfieldMstIdx = carfield_gen_axi_master_idx(CarfieldIslandsCfg); + +localparam axi_struct_t CarfieldAxiMap = carfield_gen_axi_map(CarfieldAxiNumSlaves, + CarfieldIslandsCfg , + CarfieldAxiSlvIdx ); +// verilog_lint: waive-start line-length +localparam carfield_regbus_slave_idx_t CarfieldRegBusSlvIdx = carfield_gen_regbus_slave_idx(CarfieldRegBusCfg); +// verilog_lint: waive-stop line-length + +localparam regbus_struct_t CarfieldRegBusMap = carfield_gen_regbus_map(NumTotalRegSlv , + CarfieldRegBusCfg , + CarfieldRegBusSlvIdx); + +localparam int unsigned CarfieldNumDomains = gen_carfield_domains(CarfieldIslandsCfg); + +typedef struct { + int unsigned clock_div_value[CarfieldNumDomains]; +} carfield_clk_div_values_t; + +function automatic carfield_clk_div_values_t gen_carfield_clk_div_value(int unsigned num_domains); + carfield_clk_div_values_t ret = '{default: '0}; + for (int i = 0; i < num_domains; i++) ret.clock_div_value[i] = 1; + return ret; +endfunction + +// verilog_lint: waive-start line-length +localparam carfield_clk_div_values_t CarfieldClkDivValue = gen_carfield_clk_div_value(CarfieldNumDomains); +// verilog_lint: waive-stop line-length + +typedef struct packed { + byte_bt l2; + byte_bt spatz; + byte_bt pulp; + byte_bt secured; + byte_bt safed; + byte_bt periph; +} carfield_domain_idx_t; + +function automatic carfield_domain_idx_t gen_domain_idx(islands_cfg_t island_cfg); + carfield_domain_idx_t ret = '{default: '0}; + int unsigned i = 0; + if (island_cfg.periph.enable ) begin ret.periph = i; i++; end + if (island_cfg.safed.enable ) begin ret.safed = i; i++; end + if (island_cfg.secured.enable ) begin ret.secured = i; i++; end + if (island_cfg.pulp.enable ) begin ret.pulp = i; i++; end + if (island_cfg.spatz.enable ) begin ret.spatz = i; i++; end + if (island_cfg.l2_port0.enable ) begin ret.l2 = i; i++; end + return ret; +endfunction + +localparam carfield_domain_idx_t CarfieldDomainIdx = gen_domain_idx(CarfieldIslandsCfg); + +/******************************* +* Carfield package starts here * +*******************************/ + localparam int unsigned CarfieldNumExtIntrs = 32; // Number of external interrupts localparam int unsigned CarfieldNumInterruptibleHarts = 2; // Spatz (2 Snitch cores) localparam int unsigned CarfieldNumRouterTargets = 1; // Safety Island @@ -23,15 +396,6 @@ typedef enum int { SafedIntrHartIdx = 'd2 } carfield_ext_intr_harts_e; -typedef enum int { - PeriphDomainIdx = 'd0, - SafedDomainIdx = 'd1, - SecdDomainIdx = 'd2, - IntClusterDomainIdx = 'd3, - FPClusterDomainIdx = 'd4, - L2DomainIdx = 'd5 -} carfield_domains_e; - // Clock dividers integer value after PoR localparam int unsigned PeriphDomainClkDivValue = 1; localparam int unsigned SafedDomainClkDivValue = 1; @@ -41,56 +405,24 @@ localparam int unsigned FPClusterDomainClkDivValue = 1; localparam int unsigned L2DomainClkDivValue = 1; typedef enum byte_bt { - L2Port0SlvIdx = 'd0, - L2Port1SlvIdx = 'd1, - SafetyIslandSlvIdx = 'd2, - EthernetSlvIdx = 'd3, - PeriphsSlvIdx = 'd4, - FPClusterSlvIdx = 'd5, - IntClusterSlvIdx = 'd6, - MailboxSlvIdx = 'd7 + L2Port0SlvIdx = CarfieldAxiSlvIdx.l2_port0, + L2Port1SlvIdx = CarfieldAxiSlvIdx.l2_port1, + SafetyIslandSlvIdx = CarfieldAxiSlvIdx.safed, + EthernetSlvIdx = CarfieldAxiSlvIdx.ethernet, + PeriphsSlvIdx = CarfieldAxiSlvIdx.periph, + FPClusterSlvIdx = CarfieldAxiSlvIdx.spatz, + IntClusterSlvIdx = CarfieldAxiSlvIdx.pulp, + MailboxSlvIdx = CarfieldAxiSlvIdx.mbox } axi_slv_idx_t; typedef enum byte_bt { - SafetyIslandMstIdx = 'd0, - SecurityIslandMstIdx = 'd1, - FPClusterMstIdx = 'd2, - IntClusterMstIdx = 'd3 + SafetyIslandMstIdx = CarfieldMstIdx.safed, + SecurityIslandMstIdx = CarfieldMstIdx.secured, + FPClusterMstIdx = CarfieldMstIdx.spatz, + IntClusterMstIdx = CarfieldMstIdx.pulp } axi_mst_idx_t; -typedef enum doub_bt { - L2Port0Base = 'h0000_0000_7800_0000, - L2Port1Base = 'h0000_0000_7820_0000, - SafetyIslandBase = 'h0000_0000_6000_0000, - EthernetBase = 'h0000_0000_2000_0000, - PeriphsBase = 'h0000_0000_2000_1000, - FPClusterBase = 'h0000_0000_5100_0000, - IntClusterBase = 'h0000_0000_5000_0000, - MailboxBase = 'h0000_0000_4000_0000 -} axi_start_t; - -// AXI Slave Sizes -localparam doub_bt L2Size = 'h0000_0000_0020_0000; -localparam doub_bt SafetyIslandSize = 'h0000_0000_0080_0000; -localparam doub_bt EthernetSize = 'h0000_0000_0000_1000; -localparam doub_bt PeriphsSize = 'h0000_0000_0000_9000; -localparam doub_bt IntClusterSize = 'h0000_0000_0080_0000; -localparam doub_bt FPClusterSize = 'h0000_0000_0080_0000; -localparam doub_bt MailboxSize = 'h0000_0000_0000_1000; - -typedef enum doub_bt { - L2Port0End = L2Port0Base + L2Size, - L2Port1End = L2Port1Base + L2Size, - SafetyIslandEnd = SafetyIslandBase + SafetyIslandSize, - EthernetEnd = EthernetBase + EthernetSize, - PeriphsEnd = PeriphsBase + PeriphsSize, - FPClusterEnd = FPClusterBase + FPClusterSize, - IntClusterEnd = IntClusterBase + IntClusterSize, - MailboxEnd = MailboxBase + MailboxSize -} axi_end_t; - // APB peripherals - localparam int unsigned CarfieldNumAdvTimerIntrs = 4; localparam int unsigned CarfieldNumAdvTimerEvents = 4; localparam int unsigned CarfieldNumSysTimerIntrs = 2; @@ -102,80 +434,6 @@ localparam int unsigned CarfieldNumEthIntrs = 1; localparam int unsigned CarfieldNumPeriphsIntrs = CarfieldNumTimerIntrs + CarfieldNumWdtIntrs + CarfieldNumCanIntrs + CarfieldNumEthIntrs; -localparam int unsigned NumApbMst = 5; - -typedef enum int { - SystemTimerIdx = 'd0, - AdvancedTimerIdx = 'd1, - SystemWdtIdx = 'd2, - CanIdx = 'd3, - HyperBusIdx = 'd4 -} carfield_peripherals_e; - -// APB start -typedef enum word_bt { - SystemTimerBase = 'h2000_4000, - AdvancedTimerBase = 'h2000_5000, - SystemWdtBase = 'h2000_7000, - CanBase = 'h2000_1000, - HyperBusBase = 'h2000_9000 -} apb_start_t; - -// APB Sizes -localparam word_bt SystemTimerSize = 'h0000_1000; -localparam word_bt AdvancedTimerSize = 'h0000_1000; -localparam word_bt SystemWdtSize = 'h0000_1000; -localparam word_bt CanSize = 'h0000_1000; -localparam word_bt HyperBusSize = 'h0000_1000; - -typedef enum word_bt { - SystemTimerEnd = SystemTimerBase + SystemTimerSize, - AdvancedTimerEnd = AdvancedTimerBase + AdvancedTimerSize, - SystemWdtEnd = SystemWdtBase + SystemWdtSize, - CanEnd = CanBase + CanSize, - HyperBusEnd = HyperBusBase + HyperBusSize -} apb_end_t; - -// Cheshire regbus out -// For carfield, PllIdx is the first index of the async reg interfaces. Please add async reg -// interfaces indices to the left of PllIdx, and sync reg interface indices to its right. -typedef enum int { - CarRegsIdx = 'd0, // sync - PllIdx = 'd1, // async - PadframeIdx = 'd2, // async - L2EccIdx = 'd3 // async -} cheshire_reg_out_e; -localparam int unsigned NumSyncRegSlv = 1; - // CarRegs -localparam int unsigned NumAsyncRegSlv = 1 + 1 + 1; - // PLL Padframe L2ECC -localparam int unsigned NumTotalRegSlv = NumSyncRegSlv + NumAsyncRegSlv; -localparam int unsigned NumTotalRegRules = NumTotalRegSlv; - -typedef enum doub_bt { - CarRegsBase = 'h0000_0000_2001_0000, - PllBase = 'h0000_0000_2002_0000, - PadframeBase = 'h0000_0000_200a_0000, - L2EccBase = 'h0000_0000_200b_0000 -} reg_start_t; - -localparam doub_bt CarRegsSize = 'h0000_0000_0000_1000; -localparam doub_bt PllSize = 'h0000_0000_0000_1000; -localparam doub_bt PadframeSize = 'h0000_0000_0000_1000; -localparam doub_bt L2EccSize = 'h0000_0000_0000_1000; - -typedef enum doub_bt { - CarRegsEnd = CarRegsBase + CarRegsSize, - PllEnd = PllBase + PllSize, - PadframeEnd = PadframeBase + PadframeSize, - L2EccEnd = L2EccBase + L2EccSize -} reg_end_t; - -// Ext Slaves: L2Ports + Safety Island + Integer Cluster + Security Island Mailbox + Ethernet + Peripherals + Floating Point Cluster -localparam bit [3:0] AxiNumExtSlv = 3'd2 + 3'd1 + 3'd1 + 3'd1 + 3'd1 + 3'd1 + 3'd1; -// Ext Masters: Integer Cluster + Security Island + Safety Island + Floating Point Cluster -localparam bit [2:0] AxiNumExtMst = 3'd1 + 3'd1 + 3'd1 + 3'd1; - // Synchronization stages (for FIFOs read/write pointers and single-bit signals syncronization after // CDCs) localparam int unsigned SyncStages = 3; @@ -294,42 +552,21 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{ RegAmoNumCuts : 1, RegAmoPostCut : 1, // External AXI ports (at most 8 ports and rules) - AxiExtNumMst : AxiNumExtMst, - AxiExtNumSlv : AxiNumExtSlv, - AxiExtNumRules : AxiNumExtSlv, + AxiExtNumMst : CarfieldAxiNumMasters, + AxiExtNumSlv : CarfieldAxiNumSlaves, + AxiExtNumRules : CarfieldAxiNumSlaves, // External AXI region map - AxiExtRegionIdx : '{0, 0, 0, 0, 0, 0, 0, 0, MailboxSlvIdx , - IntClusterSlvIdx , - FPClusterSlvIdx , - PeriphsSlvIdx , - EthernetSlvIdx , - SafetyIslandSlvIdx, - L2Port1SlvIdx , - L2Port0SlvIdx }, - AxiExtRegionStart : '{0, 0, 0, 0, 0, 0, 0, 0, MailboxBase , - IntClusterBase , - FPClusterBase , - PeriphsBase , - EthernetBase , - SafetyIslandBase, - L2Port1Base , - L2Port0Base }, - AxiExtRegionEnd : '{0, 0, 0, 0, 0, 0, 0, 0, MailboxEnd , - IntClusterEnd , - FPClusterEnd , - PeriphsEnd , - EthernetEnd , - SafetyIslandEnd, - L2Port1End , - L2Port0End }, + AxiExtRegionIdx : CarfieldAxiMap.AxiIdx, + AxiExtRegionStart : CarfieldAxiMap.AxiStart, + AxiExtRegionEnd : CarfieldAxiMap.AxiEnd, // External reg slaves (at most 8 ports and rules) RegExtNumSlv : NumTotalRegSlv, - RegExtNumRules : NumTotalRegRules, + RegExtNumRules : NumTotalRegSlv, // For carfield, PllIdx is the first index of the async reg interfaces. Please add async reg // interfaces indices to the left of PllIdx, and sync reg interface indices to its right. - RegExtRegionIdx : '{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, L2EccIdx, PadframeIdx, PllIdx, CarRegsIdx }, - RegExtRegionStart : '{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, L2EccBase, PadframeBase, PllBase, CarRegsBase }, - RegExtRegionEnd : '{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, L2EccEnd, PadframeEnd, PllEnd, CarRegsEnd }, + RegExtRegionIdx : CarfieldRegBusMap.RegBusIdx, + RegExtRegionStart : CarfieldRegBusMap.RegBusStart, + RegExtRegionEnd : CarfieldRegBusMap.RegBusEnd, // RTC RtcFreq : 1000000, // Features @@ -410,39 +647,20 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{ }; // verilog_lint: waive-stop line-length -// Control which island to add -typedef struct packed { - bit EnPulpCluster; - bit EnSafetyIsland; - bit EnSpatzCluster; - bit EnOpenTitan; - bit EnCan; - bit EnEthernet; -} islands_cfg_t; - -// Enable all islands by default -localparam islands_cfg_t IslandsCfgDefault = '{ - EnPulpCluster : 1, - EnSafetyIsland : 1, - EnSpatzCluster : 1, - EnOpenTitan : 1, - EnCan : 1, - EnEthernet : 0, - default : '1 -}; - // CDC FIFO parameters (FIFO depth). localparam int unsigned LogDepth = 3; /*****************/ /* L2 Parameters */ /*****************/ -localparam int unsigned NumL2Ports = 2; -localparam int unsigned L2MemSize = 2**20; +localparam int unsigned NumL2Ports = (CarfieldIslandsCfg.l2_port1.enable) ? 2 : 1; +localparam int unsigned L2MemSize = CarfieldIslandsCfg.l2_port0.size/2; localparam int unsigned L2NumRules = 4; // 2 rules per each access mode // (interleaved, non-interleaved) -localparam doub_bt L2Port0NonInterlBase = L2Port0Base + L2MemSize; -localparam doub_bt L2Port1NonInterlBase = L2Port1Base + L2MemSize; +localparam doub_bt L2Port0InterlBase = CarfieldIslandsCfg.l2_port0.base; +localparam doub_bt L2Port1InterlBase = CarfieldIslandsCfg.l2_port1.base; +localparam doub_bt L2Port0NonInterlBase = CarfieldIslandsCfg.l2_port0.base + L2MemSize; +localparam doub_bt L2Port1NonInterlBase = CarfieldIslandsCfg.l2_port1.base + L2MemSize; /****************************/ /* Safety Island Parameters */ @@ -465,11 +683,12 @@ localparam int unsigned IntClusterSetAssociative = 4; localparam int unsigned IntClusterNumCacheBanks = 2; localparam int unsigned IntClusterNumCacheLines = 1; localparam int unsigned IntClusterCacheSize = 4*1024; -localparam int unsigned IntClusterDbgStart = SafetyIslandBase+ +localparam int unsigned IntClusterDbgStart = CarfieldIslandsCfg.safed.base+ SafetyIslandPerOffset+ safety_island_pkg::DebugAddrOffset; localparam int unsigned IntClusterBootAddrDefaultOffs = 'h8080; -localparam int unsigned IntClusterBootAddr = L2Port0Base + IntClusterBootAddrDefaultOffs; +localparam int unsigned IntClusterBootAddr = CarfieldIslandsCfg.l2_port0.base + + IntClusterBootAddrDefaultOffs; localparam int unsigned IntClusterInstrRdataWidth = 32; localparam int unsigned IntClusterFpu = 0; localparam int unsigned IntClusterFpuDivSqrt = 0; @@ -486,6 +705,12 @@ localparam int unsigned IntClusterNumEoc = 1; localparam logic [ 5:0] IntClusterIndex = (PulpHartIdOffs >> 5); localparam logic [CarfieldCfgDefault.AddrWidth-1:0] IntClusterInternalSize = 'h0040_0000; +/*************************************/ +/* Floating Point Cluster Parameters */ +/*************************************/ +localparam int unsigned FpClustAxiMaxOutTrans = 4; +localparam int unsigned FpClustIwcAxiIdOutWidth = 3; + /*******************************/ /* Narrow Parameters: A32, D32 */ /*******************************/ @@ -500,6 +725,42 @@ typedef logic [ AxiNarrowStrobe-1:0] car_nar_strb_t; typedef logic [ IntClusterAxiIdInWidth-1:0] intclust_idin_t; typedef logic [IntClusterAxiIdOutWidth-1:0] intclust_idout_t; +// APB Mapping +localparam int unsigned NumApbMst = 5; + +typedef enum int { + SystemTimerIdx = 'd0, + AdvancedTimerIdx = 'd1, + SystemWdtIdx = 'd2, + CanIdx = 'd3, + HyperBusIdx = 'd4 +} carfield_peripherals_e; + +// Address map of peripheral system +typedef struct packed { + logic [31:0] idx; + car_nar_addrw_t start_addr; + car_nar_addrw_t end_addr; +} carfield_addr_map_rule_t; + +localparam carfield_addr_map_rule_t [NumApbMst-1:0] PeriphApbAddrMapRule = '{ + // 0: System Timer + '{ idx: SystemTimerIdx, start_addr: SystemTimerBase, + end_addr: SystemTimerBase + SystemTimerSize }, + // 1: Advanced Timer + '{ idx: AdvancedTimerIdx, start_addr: SystemAdvancedTimerBase, + end_addr: SystemAdvancedTimerBase + SystemAdvancedTimerSize }, + // 2: WDT + '{ idx: SystemWdtIdx, start_addr: SystemWatchdogBase, + end_addr: SystemWatchdogBase + SystemWatchdogSize }, + // 3: Can + '{ idx: CanIdx, start_addr: CanBase, + end_addr: CanBase + CanSize }, + // 4: Hyperbus + '{ idx: HyperBusIdx, start_addr: HyperBusBase, + end_addr: HyperBusBase + HyperBusSize } +}; + // Narrow reg types `REG_BUS_TYPEDEF_ALL(carfield_a32_d32_reg, car_nar_addrw_t, car_nar_dataw_t, car_nar_strb_t) @@ -511,8 +772,7 @@ typedef logic [IntClusterAxiIdOutWidth-1:0] intclust_idout_t; // 6 clock gateable Subdomains in Carfield: periph_domain, safety_island, security_isalnd, spatz & // pulp_cluster, L2 shared memory -localparam int unsigned NumDomains = 6; - +localparam int unsigned NumDomains = CarfieldNumDomains; typedef struct packed { logic [NumDomains-1:0] domain_clk; diff --git a/hw/cheshire_wrap.sv b/hw/cheshire_wrap.sv index 9b3e7c44..e0e9329f 100644 --- a/hw/cheshire_wrap.sv +++ b/hw/cheshire_wrap.sv @@ -82,6 +82,10 @@ module cheshire_wrap axi_pkg::w_width(Cfg.AxiDataWidth, Cfg.AxiUserWidth), // External Slaves Parameters + localparam int unsigned NumExcludedSlaves = CarfieldIslandsCfg.pulp.enable ? 2 : 1, + localparam int unsigned NumSlaveCDCs = Cfg.AxiExtNumSlv - NumExcludedSlaves, + localparam int unsigned NumExcludedIsolate = CarfieldIslandsCfg.pulp.enable ? 1 : 0, + localparam int unsigned NumIsolate = Cfg.AxiExtNumSlv - NumExcludedIsolate, localparam int unsigned ExtSlvIdWidth = Cfg.AxiMstIdWidth + $clog2(AxiIn.num_in ), localparam int unsigned ExtSlvArWidth = (2**LogDepth)* @@ -103,6 +107,8 @@ module cheshire_wrap axi_pkg::w_width(Cfg.AxiDataWidth, Cfg.AxiUserWidth), // External Master Parameters + localparam int unsigned NumExcludedMasters = CarfieldIslandsCfg.pulp.enable ? 1 : 0, + localparam int unsigned NumMasterCDCs = Cfg.AxiExtNumMst - NumExcludedMasters, localparam int unsigned ExtMstArWidth = (2**LogDepth)* axi_pkg::ar_width(Cfg.AddrWidth , Cfg.AxiMstIdWidth, @@ -184,40 +190,40 @@ module cheshire_wrap output logic [ LogDepth:0] llc_mst_w_wptr_o , input logic [ LogDepth:0] llc_mst_w_rptr_i , // External AXI isolate slave Ports (except the Mailbox) - input logic [iomsb(Cfg.AxiExtNumSlv-1):0] axi_ext_slv_isolate_i, - output logic [iomsb(Cfg.AxiExtNumSlv-1):0] axi_ext_slv_isolated_o, + input logic [iomsb(NumIsolate):0] axi_ext_slv_isolate_i, + output logic [iomsb(NumIsolate):0] axi_ext_slv_isolated_o, // External async AXI slave Ports (except the Integer Cluster and the Mailbox) - output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ExtSlvArWidth-1:0] axi_ext_slv_ar_data_o, - output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_ar_wptr_o, - input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_ar_rptr_i, - output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ExtSlvAwWidth-1:0] axi_ext_slv_aw_data_o, - output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_aw_wptr_o, - input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_aw_rptr_i, - input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ ExtSlvBWidth-1:0] axi_ext_slv_b_data_i , - input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_b_wptr_i , - output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_b_rptr_o , - input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ ExtSlvRWidth-1:0] axi_ext_slv_r_data_i , - input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_r_wptr_i , - output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_r_rptr_o , - output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ ExtSlvWWidth-1:0] axi_ext_slv_w_data_o , - output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_w_wptr_o , - input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_w_rptr_i , + output logic [iomsb(NumSlaveCDCs):0][ExtSlvArWidth-1:0] axi_ext_slv_ar_data_o, + output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_ar_wptr_o, + input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_ar_rptr_i, + output logic [iomsb(NumSlaveCDCs):0][ExtSlvAwWidth-1:0] axi_ext_slv_aw_data_o, + output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_aw_wptr_o, + input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_aw_rptr_i, + input logic [iomsb(NumSlaveCDCs):0][ ExtSlvBWidth-1:0] axi_ext_slv_b_data_i , + input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_b_wptr_i , + output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_b_rptr_o , + input logic [iomsb(NumSlaveCDCs):0][ ExtSlvRWidth-1:0] axi_ext_slv_r_data_i , + input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_r_wptr_i , + output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_r_rptr_o , + output logic [iomsb(NumSlaveCDCs):0][ ExtSlvWWidth-1:0] axi_ext_slv_w_data_o , + output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_w_wptr_o , + input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_w_rptr_i , // External async AXI master Ports (except the Integer Cluster) - input logic [iomsb(Cfg.AxiExtNumMst-1):0][ExtMstArWidth-1:0] axi_ext_mst_ar_data_i, - input logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_ar_wptr_i, - output logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_ar_rptr_o, - input logic [iomsb(Cfg.AxiExtNumMst-1):0][ExtMstAwWidth-1:0] axi_ext_mst_aw_data_i, - input logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_aw_wptr_i, - output logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_aw_rptr_o, - output logic [iomsb(Cfg.AxiExtNumMst-1):0][ ExtMstBWidth-1:0] axi_ext_mst_b_data_o , - output logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_b_wptr_o , - input logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_b_rptr_i , - output logic [iomsb(Cfg.AxiExtNumMst-1):0][ ExtMstRWidth-1:0] axi_ext_mst_r_data_o , - output logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_r_wptr_o , - input logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_r_rptr_i , - input logic [iomsb(Cfg.AxiExtNumMst-1):0][ ExtMstWWidth-1:0] axi_ext_mst_w_data_i , - input logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_w_wptr_i , - output logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_w_rptr_o , + input logic [iomsb(NumMasterCDCs):0][ExtMstArWidth-1:0] axi_ext_mst_ar_data_i, + input logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_ar_wptr_i, + output logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_ar_rptr_o, + input logic [iomsb(NumMasterCDCs):0][ExtMstAwWidth-1:0] axi_ext_mst_aw_data_i, + input logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_aw_wptr_i, + output logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_aw_rptr_o, + output logic [iomsb(NumMasterCDCs):0][ ExtMstBWidth-1:0] axi_ext_mst_b_data_o , + output logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_b_wptr_o , + input logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_b_rptr_i , + output logic [iomsb(NumMasterCDCs):0][ ExtMstRWidth-1:0] axi_ext_mst_r_data_o , + output logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_r_wptr_o , + input logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_r_rptr_i , + input logic [iomsb(NumMasterCDCs):0][ ExtMstWWidth-1:0] axi_ext_mst_w_data_i , + input logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_w_wptr_i , + output logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_w_rptr_o , // Integer Cluster async Slave Port output logic [IntClusterAxiSlvAwWidth-1:0] axi_slv_intcluster_aw_data_o, output logic [ LogDepth:0] axi_slv_intcluster_aw_wptr_o, @@ -328,8 +334,8 @@ module cheshire_wrap cheshire_axi_ext_slv_req_t [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_req; cheshire_axi_ext_slv_rsp_t [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_rsp; -cheshire_axi_ext_slv_req_t [iomsb(Cfg.AxiExtNumSlv-2):0] axi_ext_slv_isolated_req; -cheshire_axi_ext_slv_rsp_t [iomsb(Cfg.AxiExtNumSlv-2):0] axi_ext_slv_isolated_rsp; +cheshire_axi_ext_slv_req_t [iomsb(NumSlaveCDCs):0] axi_ext_slv_isolated_req; +cheshire_axi_ext_slv_rsp_t [iomsb(NumSlaveCDCs):0] axi_ext_slv_isolated_rsp; // All AXI master buses cheshire_axi_ext_mst_req_t [iomsb(Cfg.AxiExtNumMst):0] axi_ext_mst_req; @@ -442,7 +448,7 @@ cheshire_soc #( // Cheshire's AXI master cdc generation, except for the Integer Cluster (slave 6) and the Mailbox // (slave 7) -for (genvar i = 0; i < Cfg.AxiExtNumSlv - 2; i++) begin: gen_ext_slv_src_cdc +for (genvar i = 0; i < NumSlaveCDCs; i++) begin: gen_ext_slv_src_cdc axi_isolate #( .NumPending ( Cfg.AxiMaxSlvTrans ), .TerminateTransaction ( 1 ), @@ -499,9 +505,8 @@ for (genvar i = 0; i < Cfg.AxiExtNumSlv - 2; i++) begin: gen_ext_slv_src_cdc ); end - // Cheshire's AXI slave cdc and isolate generation, except for the Integer Cluster (slave 7) -for (genvar i = 0; i < Cfg.AxiExtNumMst - 1; i++) begin: gen_ext_mst_dst_cdc +for (genvar i = 0; i < NumMasterCDCs; i++) begin: gen_ext_mst_dst_cdc axi_cdc_dst #( .LogDepth ( LogDepth ), .SyncStages ( CdcSyncStages ), @@ -593,138 +598,157 @@ axi_cdc_src #( .async_data_master_r_rptr_o ( llc_mst_r_rptr_o ) ); -// Integer Cluster slave bus -axi_intcluster_slv_req_t axi_intcluster_ser_slv_req, axi_intcluster_ser_isolated_slv_req; -axi_intcluster_slv_rsp_t axi_intcluster_ser_slv_rsp, axi_intcluster_ser_isolated_slv_rsp; +if (CarfieldIslandsCfg.pulp) begin : gen_pulp_cluster + // Integer Cluster slave bus + axi_intcluster_slv_req_t axi_intcluster_ser_slv_req, axi_intcluster_ser_isolated_slv_req; + axi_intcluster_slv_rsp_t axi_intcluster_ser_slv_rsp, axi_intcluster_ser_isolated_slv_rsp; -axi_id_remap #( - .AxiSlvPortIdWidth ( ExtSlvIdWidth ), - .AxiSlvPortMaxUniqIds ( IntClusterMaxUniqId ), - .AxiMaxTxnsPerId ( Cfg.AxiMaxSlvTrans ), - .AxiMstPortIdWidth ( IntClusterAxiIdInWidth ), - .slv_req_t ( cheshire_axi_ext_slv_req_t ), - .slv_resp_t ( cheshire_axi_ext_slv_rsp_t ), - .mst_req_t ( axi_intcluster_slv_req_t ), - .mst_resp_t ( axi_intcluster_slv_rsp_t ) -) i_integer_cluster_axi_slv_id_remap ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( axi_ext_slv_req[IntClusterSlvIdx] ), - .slv_resp_o ( axi_ext_slv_rsp[IntClusterSlvIdx] ), - .mst_req_o ( axi_intcluster_ser_slv_req ), - .mst_resp_i ( axi_intcluster_ser_slv_rsp ) -); + axi_id_remap #( + .AxiSlvPortIdWidth ( ExtSlvIdWidth ), + .AxiSlvPortMaxUniqIds ( IntClusterMaxUniqId ), + .AxiMaxTxnsPerId ( Cfg.AxiMaxSlvTrans ), + .AxiMstPortIdWidth ( IntClusterAxiIdInWidth ), + .slv_req_t ( cheshire_axi_ext_slv_req_t ), + .slv_resp_t ( cheshire_axi_ext_slv_rsp_t ), + .mst_req_t ( axi_intcluster_slv_req_t ), + .mst_resp_t ( axi_intcluster_slv_rsp_t ) + ) i_integer_cluster_axi_slv_id_remap ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( axi_ext_slv_req[IntClusterSlvIdx] ), + .slv_resp_o ( axi_ext_slv_rsp[IntClusterSlvIdx] ), + .mst_req_o ( axi_intcluster_ser_slv_req ), + .mst_resp_i ( axi_intcluster_ser_slv_rsp ) + ); -axi_isolate #( - .NumPending ( Cfg.AxiMaxSlvTrans ), - .TerminateTransaction ( 1 ), - .AtopSupport ( 1 ), - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiIdWidth ( IntClusterAxiIdInWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .axi_req_t ( axi_intcluster_slv_req_t ), - .axi_resp_t ( axi_intcluster_slv_rsp_t ) -) i_axi_intcluster_isolate ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( axi_intcluster_ser_slv_req ), - .slv_resp_o ( axi_intcluster_ser_slv_rsp ), - .mst_req_o ( axi_intcluster_ser_isolated_slv_req ), - .mst_resp_i ( axi_intcluster_ser_isolated_slv_rsp ), - .isolate_i ( axi_ext_slv_isolate_i [IntClusterSlvIdx] ), - .isolated_o ( axi_ext_slv_isolated_o[IntClusterSlvIdx] ) -); + axi_isolate #( + .NumPending ( Cfg.AxiMaxSlvTrans ), + .TerminateTransaction ( 1 ), + .AtopSupport ( 1 ), + .AxiAddrWidth ( Cfg.AddrWidth ), + .AxiDataWidth ( Cfg.AxiDataWidth ), + .AxiIdWidth ( IntClusterAxiIdInWidth ), + .AxiUserWidth ( Cfg.AxiUserWidth ), + .axi_req_t ( axi_intcluster_slv_req_t ), + .axi_resp_t ( axi_intcluster_slv_rsp_t ) + ) i_axi_intcluster_isolate ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( axi_intcluster_ser_slv_req ), + .slv_resp_o ( axi_intcluster_ser_slv_rsp ), + .mst_req_o ( axi_intcluster_ser_isolated_slv_req ), + .mst_resp_i ( axi_intcluster_ser_isolated_slv_rsp ), + .isolate_i ( axi_ext_slv_isolate_i [IntClusterSlvIdx] ), + .isolated_o ( axi_ext_slv_isolated_o[IntClusterSlvIdx] ) + ); -axi_cdc_src #( - .LogDepth ( LogDepth ), - .SyncStages ( CdcSyncStages ), - .aw_chan_t ( axi_intcluster_slv_aw_chan_t ), - .w_chan_t ( axi_intcluster_slv_w_chan_t ), - .b_chan_t ( axi_intcluster_slv_b_chan_t ), - .ar_chan_t ( axi_intcluster_slv_ar_chan_t ), - .r_chan_t ( axi_intcluster_slv_r_chan_t ), - .axi_req_t ( axi_intcluster_slv_req_t ), - .axi_resp_t ( axi_intcluster_slv_rsp_t ) -) i_intcluster_slv_cdc ( - // synchronous slave port - .src_clk_i ( clk_i ), - .src_rst_ni ( rst_ni ), - .src_req_i ( axi_intcluster_ser_isolated_slv_req ), - .src_resp_o ( axi_intcluster_ser_isolated_slv_rsp ), - // asynchronous master port - .async_data_master_aw_data_o ( axi_slv_intcluster_aw_data_o ), - .async_data_master_aw_wptr_o ( axi_slv_intcluster_aw_wptr_o ), - .async_data_master_aw_rptr_i ( axi_slv_intcluster_aw_rptr_i ), - .async_data_master_w_data_o ( axi_slv_intcluster_w_data_o ), - .async_data_master_w_wptr_o ( axi_slv_intcluster_w_wptr_o ), - .async_data_master_w_rptr_i ( axi_slv_intcluster_w_rptr_i ), - .async_data_master_b_data_i ( axi_slv_intcluster_b_data_i ), - .async_data_master_b_wptr_i ( axi_slv_intcluster_b_wptr_i ), - .async_data_master_b_rptr_o ( axi_slv_intcluster_b_rptr_o ), - .async_data_master_ar_data_o ( axi_slv_intcluster_ar_data_o ), - .async_data_master_ar_wptr_o ( axi_slv_intcluster_ar_wptr_o ), - .async_data_master_ar_rptr_i ( axi_slv_intcluster_ar_rptr_i ), - .async_data_master_r_data_i ( axi_slv_intcluster_r_data_i ), - .async_data_master_r_wptr_i ( axi_slv_intcluster_r_wptr_i ), - .async_data_master_r_rptr_o ( axi_slv_intcluster_r_rptr_o ) -); + axi_cdc_src #( + .LogDepth ( LogDepth ), + .SyncStages ( CdcSyncStages ), + .aw_chan_t ( axi_intcluster_slv_aw_chan_t ), + .w_chan_t ( axi_intcluster_slv_w_chan_t ), + .b_chan_t ( axi_intcluster_slv_b_chan_t ), + .ar_chan_t ( axi_intcluster_slv_ar_chan_t ), + .r_chan_t ( axi_intcluster_slv_r_chan_t ), + .axi_req_t ( axi_intcluster_slv_req_t ), + .axi_resp_t ( axi_intcluster_slv_rsp_t ) + ) i_intcluster_slv_cdc ( + // synchronous slave port + .src_clk_i ( clk_i ), + .src_rst_ni ( rst_ni ), + .src_req_i ( axi_intcluster_ser_isolated_slv_req ), + .src_resp_o ( axi_intcluster_ser_isolated_slv_rsp ), + // asynchronous master port + .async_data_master_aw_data_o ( axi_slv_intcluster_aw_data_o ), + .async_data_master_aw_wptr_o ( axi_slv_intcluster_aw_wptr_o ), + .async_data_master_aw_rptr_i ( axi_slv_intcluster_aw_rptr_i ), + .async_data_master_w_data_o ( axi_slv_intcluster_w_data_o ), + .async_data_master_w_wptr_o ( axi_slv_intcluster_w_wptr_o ), + .async_data_master_w_rptr_i ( axi_slv_intcluster_w_rptr_i ), + .async_data_master_b_data_i ( axi_slv_intcluster_b_data_i ), + .async_data_master_b_wptr_i ( axi_slv_intcluster_b_wptr_i ), + .async_data_master_b_rptr_o ( axi_slv_intcluster_b_rptr_o ), + .async_data_master_ar_data_o ( axi_slv_intcluster_ar_data_o ), + .async_data_master_ar_wptr_o ( axi_slv_intcluster_ar_wptr_o ), + .async_data_master_ar_rptr_i ( axi_slv_intcluster_ar_rptr_i ), + .async_data_master_r_data_i ( axi_slv_intcluster_r_data_i ), + .async_data_master_r_wptr_i ( axi_slv_intcluster_r_wptr_i ), + .async_data_master_r_rptr_o ( axi_slv_intcluster_r_rptr_o ) + ); -// Integer Cluster master bus -axi_intcluster_mst_req_t axi_intcluster_ser_mst_req; -axi_intcluster_mst_rsp_t axi_intcluster_ser_mst_rsp; + // Integer Cluster master bus + axi_intcluster_mst_req_t axi_intcluster_ser_mst_req; + axi_intcluster_mst_rsp_t axi_intcluster_ser_mst_rsp; -axi_cdc_dst #( - .LogDepth ( LogDepth ), - .SyncStages ( CdcSyncStages ), - .aw_chan_t ( axi_intcluster_mst_aw_chan_t ), - .w_chan_t ( axi_intcluster_mst_w_chan_t ), - .b_chan_t ( axi_intcluster_mst_b_chan_t ), - .ar_chan_t ( axi_intcluster_mst_ar_chan_t ), - .r_chan_t ( axi_intcluster_mst_r_chan_t ), - .axi_req_t ( axi_intcluster_mst_req_t ), - .axi_resp_t ( axi_intcluster_mst_rsp_t ) -) i_intcluster_mst_cdc ( - // asynchronous slave port - .async_data_slave_aw_data_i ( axi_mst_intcluster_aw_data_i ), - .async_data_slave_aw_wptr_i ( axi_mst_intcluster_aw_wptr_i ), - .async_data_slave_aw_rptr_o ( axi_mst_intcluster_aw_rptr_o ), - .async_data_slave_w_data_i ( axi_mst_intcluster_w_data_i ), - .async_data_slave_w_wptr_i ( axi_mst_intcluster_w_wptr_i ), - .async_data_slave_w_rptr_o ( axi_mst_intcluster_w_rptr_o ), - .async_data_slave_b_data_o ( axi_mst_intcluster_b_data_o ), - .async_data_slave_b_wptr_o ( axi_mst_intcluster_b_wptr_o ), - .async_data_slave_b_rptr_i ( axi_mst_intcluster_b_rptr_i ), - .async_data_slave_ar_data_i ( axi_mst_intcluster_ar_data_i ), - .async_data_slave_ar_wptr_i ( axi_mst_intcluster_ar_wptr_i ), - .async_data_slave_ar_rptr_o ( axi_mst_intcluster_ar_rptr_o ), - .async_data_slave_r_data_o ( axi_mst_intcluster_r_data_o ), - .async_data_slave_r_wptr_o ( axi_mst_intcluster_r_wptr_o ), - .async_data_slave_r_rptr_i ( axi_mst_intcluster_r_rptr_i ), - // synchronous master port - .dst_clk_i ( clk_i ), - .dst_rst_ni ( rst_ni ), - .dst_req_o ( axi_intcluster_ser_mst_req ), - .dst_resp_i ( axi_intcluster_ser_mst_rsp ) -); + axi_cdc_dst #( + .LogDepth ( LogDepth ), + .SyncStages ( CdcSyncStages ), + .aw_chan_t ( axi_intcluster_mst_aw_chan_t ), + .w_chan_t ( axi_intcluster_mst_w_chan_t ), + .b_chan_t ( axi_intcluster_mst_b_chan_t ), + .ar_chan_t ( axi_intcluster_mst_ar_chan_t ), + .r_chan_t ( axi_intcluster_mst_r_chan_t ), + .axi_req_t ( axi_intcluster_mst_req_t ), + .axi_resp_t ( axi_intcluster_mst_rsp_t ) + ) i_intcluster_mst_cdc ( + // asynchronous slave port + .async_data_slave_aw_data_i ( axi_mst_intcluster_aw_data_i ), + .async_data_slave_aw_wptr_i ( axi_mst_intcluster_aw_wptr_i ), + .async_data_slave_aw_rptr_o ( axi_mst_intcluster_aw_rptr_o ), + .async_data_slave_w_data_i ( axi_mst_intcluster_w_data_i ), + .async_data_slave_w_wptr_i ( axi_mst_intcluster_w_wptr_i ), + .async_data_slave_w_rptr_o ( axi_mst_intcluster_w_rptr_o ), + .async_data_slave_b_data_o ( axi_mst_intcluster_b_data_o ), + .async_data_slave_b_wptr_o ( axi_mst_intcluster_b_wptr_o ), + .async_data_slave_b_rptr_i ( axi_mst_intcluster_b_rptr_i ), + .async_data_slave_ar_data_i ( axi_mst_intcluster_ar_data_i ), + .async_data_slave_ar_wptr_i ( axi_mst_intcluster_ar_wptr_i ), + .async_data_slave_ar_rptr_o ( axi_mst_intcluster_ar_rptr_o ), + .async_data_slave_r_data_o ( axi_mst_intcluster_r_data_o ), + .async_data_slave_r_wptr_o ( axi_mst_intcluster_r_wptr_o ), + .async_data_slave_r_rptr_i ( axi_mst_intcluster_r_rptr_i ), + // synchronous master port + .dst_clk_i ( clk_i ), + .dst_rst_ni ( rst_ni ), + .dst_req_o ( axi_intcluster_ser_mst_req ), + .dst_resp_i ( axi_intcluster_ser_mst_rsp ) + ); -axi_id_remap #( - .AxiSlvPortIdWidth ( IntClusterAxiIdOutWidth ), - .AxiSlvPortMaxUniqIds ( IntClusterMaxUniqId ), - .AxiMaxTxnsPerId ( Cfg.AxiMaxMstTrans ), - .AxiMstPortIdWidth ( Cfg.AxiMstIdWidth ), - .slv_req_t ( axi_intcluster_mst_req_t ), - .slv_resp_t ( axi_intcluster_mst_rsp_t ), - .mst_req_t ( cheshire_axi_ext_mst_req_t ), - .mst_resp_t ( cheshire_axi_ext_mst_rsp_t ) -) i_integer_cluster_axi_mst_id_remap ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( axi_intcluster_ser_mst_req ), - .slv_resp_o ( axi_intcluster_ser_mst_rsp ), - .mst_req_o ( axi_ext_mst_req[IntClusterMstIdx] ), - .mst_resp_i ( axi_ext_mst_rsp[IntClusterMstIdx] ) -); + axi_id_remap #( + .AxiSlvPortIdWidth ( IntClusterAxiIdOutWidth ), + .AxiSlvPortMaxUniqIds ( IntClusterMaxUniqId ), + .AxiMaxTxnsPerId ( Cfg.AxiMaxMstTrans ), + .AxiMstPortIdWidth ( Cfg.AxiMstIdWidth ), + .slv_req_t ( axi_intcluster_mst_req_t ), + .slv_resp_t ( axi_intcluster_mst_rsp_t ), + .mst_req_t ( cheshire_axi_ext_mst_req_t ), + .mst_resp_t ( cheshire_axi_ext_mst_rsp_t ) + ) i_integer_cluster_axi_mst_id_remap ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( axi_intcluster_ser_mst_req ), + .slv_resp_o ( axi_intcluster_ser_mst_rsp ), + .mst_req_o ( axi_ext_mst_req[IntClusterMstIdx] ), + .mst_resp_i ( axi_ext_mst_rsp[IntClusterMstIdx] ) + ); +end else begin: gen_no_pulp_cluster + assign axi_slv_intcluster_aw_data_o = '0; + assign axi_slv_intcluster_aw_wptr_o = '0; + assign axi_slv_intcluster_w_data_o = '0; + assign axi_slv_intcluster_w_wptr_o = '0; + assign axi_slv_intcluster_b_rptr_o = '0; + assign axi_slv_intcluster_ar_data_o = '0; + assign axi_slv_intcluster_ar_wptr_o = '0; + assign axi_slv_intcluster_r_rptr_o = '0; + + assign axi_mst_intcluster_aw_rptr_o = '0; + assign axi_mst_intcluster_w_rptr_o = '0; + assign axi_mst_intcluster_b_data_o = '0; + assign axi_mst_intcluster_b_wptr_o = '0; + assign axi_mst_intcluster_ar_rptr_o = '0; + assign axi_mst_intcluster_r_data_o = '0; + assign axi_mst_intcluster_r_wptr_o = '0; +end // Async reg interface: // See carfield_pkg.sv for indices referring to sync and async reg interfaces. diff --git a/hw/configs/carfield_l2dual_periph.sv b/hw/configs/carfield_l2dual_periph.sv new file mode 100644 index 00000000..6bd6c863 --- /dev/null +++ b/hw/configs/carfield_l2dual_periph.sv @@ -0,0 +1,84 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +package carfield_configuration; + +import cheshire_pkg::*; +/********************* + * AXI Configuration * + ********************/ +//L2, port 0 +localparam bit L2Port0Enable = 1; +localparam doub_bt L2Port0Base = 'h78000000; +localparam doub_bt L2Port0Size = 'h00200000; +// L2, port 1 +localparam bit L2Port1Enable = 1; +localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size; +localparam doub_bt L2Port1Size = L2Port0Size; +// Safety Island +localparam bit SafetyIslandEnable = 0; +localparam doub_bt SafetyIslandBase = 'h60000000; +localparam doub_bt SafetyIslandSize = 'h00800000; +// Ethernet +localparam bit EthernetEnable = 0; +localparam doub_bt EthernetBase = 'h20000000; +localparam doub_bt EthernetSize = 'h00001000; +// Peripherals +localparam bit PeriphEnable = 1; +localparam doub_bt PeriphBase = 'h20001000; +localparam doub_bt PeriphSize = 'h00009000; +// Spatz cluster +localparam bit SpatzClusterEnable = 0; +localparam doub_bt SpatzClusterBase = 'h51000000; +localparam doub_bt SpatzClusterSize = 'h00800000; +// PULP cluster +localparam bit PulpClusterEnable = 0; +localparam doub_bt PulpClusterBase = 'h50000000; +localparam doub_bt PulpClusterSize = 'h00800000; +// Security Island +localparam bit SecurityIslandEnable = 0; +localparam doub_bt SecurityIslandBase = 'h0; +localparam doub_bt SecurityIslandSize = 'h0; +// Mailbox +localparam bit MailboxEnable = 1; +localparam doub_bt MailboxBase = 'h40000000; +localparam doub_bt MailboxSize = 'h00001000; +// Can +localparam bit CanEnable = 0; +localparam doub_bt CanBase = 'h20001000; +localparam doub_bt CanSize = 'h00001000; +// System Timer +localparam doub_bt SystemTimerBase = 'h20004000; +localparam doub_bt SystemTimerSize = 'h00001000; +// System Advanced Timer +localparam doub_bt SystemAdvancedTimerBase = 'h20005000; +localparam doub_bt SystemAdvancedTimerSize = 'h00001000; +// System Watchdog +localparam doub_bt SystemWatchdogBase = 'h20007000; +localparam doub_bt SystemWatchdogSize = 'h00001000; +// Hyperbus Config +localparam doub_bt HyperBusBase = 'h20009000; +localparam doub_bt HyperBusSize = 'h00001000; +/************************ + * RegBus Configuration * + ***********************/ +// Platform control registers +localparam doub_bt PcrsBase = 'h20010000; +localparam doub_bt PcrsSize = 'h00001000; +// PLL +localparam bit PllCfgEnable = 1; +localparam doub_bt PllCfgBase = 'h20020000; +localparam doub_bt PllCfgSize = 'h00001000; +// Padframe +localparam bit PadframeCfgEnable = 1; +localparam doub_bt PadframeCfgBase = 'h200A0000; +localparam doub_bt PadframeCfgSize = 'h00001000; +// L2 ECC +localparam bit L2EccCfgEnable = 1; +localparam doub_bt L2EccCfgBase = 'h200B0000; +localparam doub_bt L2EccCfgSize = 'h00001000; + +endpackage diff --git a/hw/configs/carfield_l2dual_pulp_periph.sv b/hw/configs/carfield_l2dual_pulp_periph.sv new file mode 100644 index 00000000..962b2f00 --- /dev/null +++ b/hw/configs/carfield_l2dual_pulp_periph.sv @@ -0,0 +1,84 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +package carfield_configuration; + +import cheshire_pkg::*; +/********************* + * AXI Configuration * + ********************/ +//L2, port 0 +localparam bit L2Port0Enable = 1; +localparam doub_bt L2Port0Base = 'h78000000; +localparam doub_bt L2Port0Size = 'h00200000; +// L2, port 1 +localparam bit L2Port1Enable = 1; +localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size; +localparam doub_bt L2Port1Size = L2Port0Size; +// Safety Island +localparam bit SafetyIslandEnable = 0; +localparam doub_bt SafetyIslandBase = 'h60000000; +localparam doub_bt SafetyIslandSize = 'h00800000; +// Ethernet +localparam bit EthernetEnable = 0; +localparam doub_bt EthernetBase = 'h20000000; +localparam doub_bt EthernetSize = 'h00001000; +// Peripherals +localparam bit PeriphEnable = 1; +localparam doub_bt PeriphBase = 'h20001000; +localparam doub_bt PeriphSize = 'h00009000; +// Spatz cluster +localparam bit SpatzClusterEnable = 0; +localparam doub_bt SpatzClusterBase = 'h51000000; +localparam doub_bt SpatzClusterSize = 'h00800000; +// PULP cluster +localparam bit PulpClusterEnable = 1; +localparam doub_bt PulpClusterBase = 'h50000000; +localparam doub_bt PulpClusterSize = 'h00800000; +// Security Island +localparam bit SecurityIslandEnable = 0; +localparam doub_bt SecurityIslandBase = 'h0; +localparam doub_bt SecurityIslandSize = 'h0; +// Mailbox +localparam bit MailboxEnable = 1; +localparam doub_bt MailboxBase = 'h40000000; +localparam doub_bt MailboxSize = 'h00001000; +// Can +localparam bit CanEnable = 0; +localparam doub_bt CanBase = 'h20001000; +localparam doub_bt CanSize = 'h00001000; +// System Timer +localparam doub_bt SystemTimerBase = 'h20004000; +localparam doub_bt SystemTimerSize = 'h00001000; +// System Advanced Timer +localparam doub_bt SystemAdvancedTimerBase = 'h20005000; +localparam doub_bt SystemAdvancedTimerSize = 'h00001000; +// System Watchdog +localparam doub_bt SystemWatchdogBase = 'h20007000; +localparam doub_bt SystemWatchdogSize = 'h00001000; +// Hyperbus Config +localparam doub_bt HyperBusBase = 'h20009000; +localparam doub_bt HyperBusSize = 'h00001000; +/************************ + * RegBus Configuration * + ***********************/ +// Platform control registers +localparam doub_bt PcrsBase = 'h20010000; +localparam doub_bt PcrsSize = 'h00001000; +// PLL +localparam bit PllCfgEnable = 1; +localparam doub_bt PllCfgBase = 'h20020000; +localparam doub_bt PllCfgSize = 'h00001000; +// Padframe +localparam bit PadframeCfgEnable = 1; +localparam doub_bt PadframeCfgBase = 'h200A0000; +localparam doub_bt PadframeCfgSize = 'h00001000; +// L2 ECC +localparam bit L2EccCfgEnable = 1; +localparam doub_bt L2EccCfgBase = 'h200B0000; +localparam doub_bt L2EccCfgSize = 'h00001000; + +endpackage diff --git a/hw/configs/carfield_l2dual_safe_periph.sv b/hw/configs/carfield_l2dual_safe_periph.sv new file mode 100644 index 00000000..b8859adb --- /dev/null +++ b/hw/configs/carfield_l2dual_safe_periph.sv @@ -0,0 +1,84 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +package carfield_configuration; + +import cheshire_pkg::*; +/********************* + * AXI Configuration * + ********************/ +//L2, port 0 +localparam bit L2Port0Enable = 1; +localparam doub_bt L2Port0Base = 'h78000000; +localparam doub_bt L2Port0Size = 'h00200000; +// L2, port 1 +localparam bit L2Port1Enable = 1; +localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size; +localparam doub_bt L2Port1Size = L2Port0Size; +// Safety Island +localparam bit SafetyIslandEnable = 1; +localparam doub_bt SafetyIslandBase = 'h60000000; +localparam doub_bt SafetyIslandSize = 'h00800000; +// Ethernet +localparam bit EthernetEnable = 0; +localparam doub_bt EthernetBase = 'h20000000; +localparam doub_bt EthernetSize = 'h00001000; +// Peripherals +localparam bit PeriphEnable = 1; +localparam doub_bt PeriphBase = 'h20001000; +localparam doub_bt PeriphSize = 'h00009000; +// Spatz cluster +localparam bit SpatzClusterEnable = 0; +localparam doub_bt SpatzClusterBase = 'h51000000; +localparam doub_bt SpatzClusterSize = 'h00800000; +// PULP cluster +localparam bit PulpClusterEnable = 0; +localparam doub_bt PulpClusterBase = 'h50000000; +localparam doub_bt PulpClusterSize = 'h00800000; +// Security Island +localparam bit SecurityIslandEnable = 0; +localparam doub_bt SecurityIslandBase = 'h0; +localparam doub_bt SecurityIslandSize = 'h0; +// Mailbox +localparam bit MailboxEnable = 1; +localparam doub_bt MailboxBase = 'h40000000; +localparam doub_bt MailboxSize = 'h00001000; +// Can +localparam bit CanEnable = 0; +localparam doub_bt CanBase = 'h20001000; +localparam doub_bt CanSize = 'h00001000; +// System Timer +localparam doub_bt SystemTimerBase = 'h20004000; +localparam doub_bt SystemTimerSize = 'h00001000; +// System Advanced Timer +localparam doub_bt SystemAdvancedTimerBase = 'h20005000; +localparam doub_bt SystemAdvancedTimerSize = 'h00001000; +// System Watchdog +localparam doub_bt SystemWatchdogBase = 'h20007000; +localparam doub_bt SystemWatchdogSize = 'h00001000; +// Hyperbus Config +localparam doub_bt HyperBusBase = 'h20009000; +localparam doub_bt HyperBusSize = 'h00001000; +/************************ + * RegBus Configuration * + ***********************/ +// Platform control registers +localparam doub_bt PcrsBase = 'h20010000; +localparam doub_bt PcrsSize = 'h00001000; +// PLL +localparam bit PllCfgEnable = 1; +localparam doub_bt PllCfgBase = 'h20020000; +localparam doub_bt PllCfgSize = 'h00001000; +// Padframe +localparam bit PadframeCfgEnable = 1; +localparam doub_bt PadframeCfgBase = 'h200A0000; +localparam doub_bt PadframeCfgSize = 'h00001000; +// L2 ECC +localparam bit L2EccCfgEnable = 1; +localparam doub_bt L2EccCfgBase = 'h200B0000; +localparam doub_bt L2EccCfgSize = 'h00001000; + +endpackage diff --git a/hw/configs/carfield_l2dual_safe_pulp_periph.sv b/hw/configs/carfield_l2dual_safe_pulp_periph.sv new file mode 100644 index 00000000..8db380ac --- /dev/null +++ b/hw/configs/carfield_l2dual_safe_pulp_periph.sv @@ -0,0 +1,84 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +package carfield_configuration; + +import cheshire_pkg::*; +/********************* + * AXI Configuration * + ********************/ +//L2, port 0 +localparam bit L2Port0Enable = 1; +localparam doub_bt L2Port0Base = 'h78000000; +localparam doub_bt L2Port0Size = 'h00200000; +// L2, port 1 +localparam bit L2Port1Enable = 1; +localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size; +localparam doub_bt L2Port1Size = L2Port0Size; +// Safety Island +localparam bit SafetyIslandEnable = 1; +localparam doub_bt SafetyIslandBase = 'h60000000; +localparam doub_bt SafetyIslandSize = 'h00800000; +// Ethernet +localparam bit EthernetEnable = 0; +localparam doub_bt EthernetBase = 'h20000000; +localparam doub_bt EthernetSize = 'h00001000; +// Peripherals +localparam bit PeriphEnable = 1; +localparam doub_bt PeriphBase = 'h20001000; +localparam doub_bt PeriphSize = 'h00009000; +// Spatz cluster +localparam bit SpatzClusterEnable = 0; +localparam doub_bt SpatzClusterBase = 'h51000000; +localparam doub_bt SpatzClusterSize = 'h00800000; +// PULP cluster +localparam bit PulpClusterEnable = 1; +localparam doub_bt PulpClusterBase = 'h50000000; +localparam doub_bt PulpClusterSize = 'h00800000; +// Security Island +localparam bit SecurityIslandEnable = 0; +localparam doub_bt SecurityIslandBase = 'h0; +localparam doub_bt SecurityIslandSize = 'h0; +// Mailbox +localparam bit MailboxEnable = 1; +localparam doub_bt MailboxBase = 'h40000000; +localparam doub_bt MailboxSize = 'h00001000; +// Can +localparam bit CanEnable = 0; +localparam doub_bt CanBase = 'h20001000; +localparam doub_bt CanSize = 'h00001000; +// System Timer +localparam doub_bt SystemTimerBase = 'h20004000; +localparam doub_bt SystemTimerSize = 'h00001000; +// System Advanced Timer +localparam doub_bt SystemAdvancedTimerBase = 'h20005000; +localparam doub_bt SystemAdvancedTimerSize = 'h00001000; +// System Watchdog +localparam doub_bt SystemWatchdogBase = 'h20007000; +localparam doub_bt SystemWatchdogSize = 'h00001000; +// Hyperbus Config +localparam doub_bt HyperBusBase = 'h20009000; +localparam doub_bt HyperBusSize = 'h00001000; +/************************ + * RegBus Configuration * + ***********************/ +// Platform control registers +localparam doub_bt PcrsBase = 'h20010000; +localparam doub_bt PcrsSize = 'h00001000; +// PLL +localparam bit PllCfgEnable = 1; +localparam doub_bt PllCfgBase = 'h20020000; +localparam doub_bt PllCfgSize = 'h00001000; +// Padframe +localparam bit PadframeCfgEnable = 1; +localparam doub_bt PadframeCfgBase = 'h200A0000; +localparam doub_bt PadframeCfgSize = 'h00001000; +// L2 ECC +localparam bit L2EccCfgEnable = 1; +localparam doub_bt L2EccCfgBase = 'h200B0000; +localparam doub_bt L2EccCfgSize = 'h00001000; + +endpackage diff --git a/hw/configs/carfield_l2dual_safe_pulp_spatz_periph.sv b/hw/configs/carfield_l2dual_safe_pulp_spatz_periph.sv new file mode 100644 index 00000000..1c4a178f --- /dev/null +++ b/hw/configs/carfield_l2dual_safe_pulp_spatz_periph.sv @@ -0,0 +1,84 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +package carfield_configuration; + +import cheshire_pkg::*; +/********************* + * AXI Configuration * + ********************/ +//L2, port 0 +localparam bit L2Port0Enable = 1; +localparam doub_bt L2Port0Base = 'h78000000; +localparam doub_bt L2Port0Size = 'h00200000; +// L2, port 1 +localparam bit L2Port1Enable = 1; +localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size; +localparam doub_bt L2Port1Size = L2Port0Size; +// Safety Island +localparam bit SafetyIslandEnable = 1; +localparam doub_bt SafetyIslandBase = 'h60000000; +localparam doub_bt SafetyIslandSize = 'h00800000; +// Ethernet +localparam bit EthernetEnable = 0; +localparam doub_bt EthernetBase = 'h20000000; +localparam doub_bt EthernetSize = 'h00001000; +// Peripherals +localparam bit PeriphEnable = 1; +localparam doub_bt PeriphBase = 'h20001000; +localparam doub_bt PeriphSize = 'h00009000; +// Spatz cluster +localparam bit SpatzClusterEnable = 1; +localparam doub_bt SpatzClusterBase = 'h51000000; +localparam doub_bt SpatzClusterSize = 'h00800000; +// PULP cluster +localparam bit PulpClusterEnable = 1; +localparam doub_bt PulpClusterBase = 'h50000000; +localparam doub_bt PulpClusterSize = 'h00800000; +// Security Island +localparam bit SecurityIslandEnable = 0; +localparam doub_bt SecurityIslandBase = 'h0; +localparam doub_bt SecurityIslandSize = 'h0; +// Mailbox +localparam bit MailboxEnable = 1; +localparam doub_bt MailboxBase = 'h40000000; +localparam doub_bt MailboxSize = 'h00001000; +// Can +localparam bit CanEnable = 0; +localparam doub_bt CanBase = 'h20001000; +localparam doub_bt CanSize = 'h00001000; +// System Timer +localparam doub_bt SystemTimerBase = 'h20004000; +localparam doub_bt SystemTimerSize = 'h00001000; +// System Advanced Timer +localparam doub_bt SystemAdvancedTimerBase = 'h20005000; +localparam doub_bt SystemAdvancedTimerSize = 'h00001000; +// System Watchdog +localparam doub_bt SystemWatchdogBase = 'h20007000; +localparam doub_bt SystemWatchdogSize = 'h00001000; +// Hyperbus Config +localparam doub_bt HyperBusBase = 'h20009000; +localparam doub_bt HyperBusSize = 'h00001000; +/************************ + * RegBus Configuration * + ***********************/ +// Platform control registers +localparam doub_bt PcrsBase = 'h20010000; +localparam doub_bt PcrsSize = 'h00001000; +// PLL +localparam bit PllCfgEnable = 1; +localparam doub_bt PllCfgBase = 'h20020000; +localparam doub_bt PllCfgSize = 'h00001000; +// Padframe +localparam bit PadframeCfgEnable = 1; +localparam doub_bt PadframeCfgBase = 'h200A0000; +localparam doub_bt PadframeCfgSize = 'h00001000; +// L2 ECC +localparam bit L2EccCfgEnable = 1; +localparam doub_bt L2EccCfgBase = 'h200B0000; +localparam doub_bt L2EccCfgSize = 'h00001000; + +endpackage diff --git a/hw/configs/carfield_l2dual_safe_secure_pulp_spatz_periph_can.sv b/hw/configs/carfield_l2dual_safe_secure_pulp_spatz_periph_can.sv new file mode 100644 index 00000000..63592396 --- /dev/null +++ b/hw/configs/carfield_l2dual_safe_secure_pulp_spatz_periph_can.sv @@ -0,0 +1,87 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +package carfield_configuration; + +import cheshire_pkg::*; +/********************* + * AXI Configuration * + ********************/ +//L2, port 0 +localparam bit L2Port0Enable = 1; +localparam doub_bt L2Port0Base = 'h78000000; +localparam doub_bt L2Port0Size = 'h00200000; +// L2, port 1 +localparam bit L2Port1Enable = 1; +localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size; +localparam doub_bt L2Port1Size = L2Port0Size; +// Safety Island +localparam bit SafetyIslandEnable = 1; +localparam doub_bt SafetyIslandBase = 'h60000000; +localparam doub_bt SafetyIslandSize = 'h00800000; +// Ethernet +localparam bit EthernetEnable = 0; +localparam doub_bt EthernetBase = 'h20000000; +localparam doub_bt EthernetSize = 'h00001000; +// Peripherals +localparam bit PeriphEnable = 1; +localparam doub_bt PeriphBase = 'h20001000; +localparam doub_bt PeriphSize = 'h00009000; +// Spatz cluster +localparam bit SpatzClusterEnable = 1; +localparam doub_bt SpatzClusterBase = 'h51000000; +localparam doub_bt SpatzClusterSize = 'h00800000; +// PULP cluster +localparam bit PulpClusterEnable = 1; +localparam doub_bt PulpClusterBase = 'h50000000; +localparam doub_bt PulpClusterSize = 'h00800000; +// Security Island +localparam bit SecurityIslandEnable = 1; +localparam doub_bt SecurityIslandBase = 'h0; +localparam doub_bt SecurityIslandSize = 'h0; +// Mailbox +localparam bit MailboxEnable = 1; +localparam doub_bt MailboxBase = 'h40000000; +localparam doub_bt MailboxSize = 'h00001000; +/********************* + * APB Configuration * + ********************/ +// Can +localparam bit CanEnable = 1; +localparam doub_bt CanBase = 'h20001000; +localparam doub_bt CanSize = 'h00001000; +// System Timer +localparam doub_bt SystemTimerBase = 'h20004000; +localparam doub_bt SystemTimerSize = 'h00001000; +// System Advanced Timer +localparam doub_bt SystemAdvancedTimerBase = 'h20005000; +localparam doub_bt SystemAdvancedTimerSize = 'h00001000; +// System Watchdog +localparam doub_bt SystemWatchdogBase = 'h20007000; +localparam doub_bt SystemWatchdogSize = 'h00001000; +// Hyperbus Config +localparam doub_bt HyperBusBase = 'h20009000; +localparam doub_bt HyperBusSize = 'h00001000; +/************************ + * RegBus Configuration * + ***********************/ +// Platform control registers +localparam doub_bt PcrsBase = 'h20010000; +localparam doub_bt PcrsSize = 'h00001000; +// PLL +localparam bit PllCfgEnable = 1; +localparam doub_bt PllCfgBase = 'h20020000; +localparam doub_bt PllCfgSize = 'h00001000; +// Padframe +localparam bit PadframeCfgEnable = 1; +localparam doub_bt PadframeCfgBase = 'h200A0000; +localparam doub_bt PadframeCfgSize = 'h00001000; +// L2 ECC +localparam bit L2EccCfgEnable = 1; +localparam doub_bt L2EccCfgBase = 'h200B0000; +localparam doub_bt L2EccCfgSize = 'h00001000; + +endpackage diff --git a/hw/configs/carfield_l2dual_secure_periph.sv b/hw/configs/carfield_l2dual_secure_periph.sv new file mode 100644 index 00000000..386f5928 --- /dev/null +++ b/hw/configs/carfield_l2dual_secure_periph.sv @@ -0,0 +1,84 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +package carfield_configuration; + +import cheshire_pkg::*; +/********************* + * AXI Configuration * + ********************/ +//L2, port 0 +localparam bit L2Port0Enable = 1; +localparam doub_bt L2Port0Base = 'h78000000; +localparam doub_bt L2Port0Size = 'h00200000; +// L2, port 1 +localparam bit L2Port1Enable = 1; +localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size; +localparam doub_bt L2Port1Size = L2Port0Size; +// Safety Island +localparam bit SafetyIslandEnable = 0; +localparam doub_bt SafetyIslandBase = 'h60000000; +localparam doub_bt SafetyIslandSize = 'h00800000; +// Ethernet +localparam bit EthernetEnable = 0; +localparam doub_bt EthernetBase = 'h20000000; +localparam doub_bt EthernetSize = 'h00001000; +// Peripherals +localparam bit PeriphEnable = 1; +localparam doub_bt PeriphBase = 'h20001000; +localparam doub_bt PeriphSize = 'h00009000; +// Spatz cluster +localparam bit SpatzClusterEnable = 0; +localparam doub_bt SpatzClusterBase = 'h51000000; +localparam doub_bt SpatzClusterSize = 'h00800000; +// PULP cluster +localparam bit PulpClusterEnable = 0; +localparam doub_bt PulpClusterBase = 'h50000000; +localparam doub_bt PulpClusterSize = 'h00800000; +// Security Island +localparam bit SecurityIslandEnable = 1; +localparam doub_bt SecurityIslandBase = 'h0; +localparam doub_bt SecurityIslandSize = 'h0; +// Mailbox +localparam bit MailboxEnable = 1; +localparam doub_bt MailboxBase = 'h40000000; +localparam doub_bt MailboxSize = 'h00001000; +// Can +localparam bit CanEnable = 0; +localparam doub_bt CanBase = 'h20001000; +localparam doub_bt CanSize = 'h00001000; +// System Timer +localparam doub_bt SystemTimerBase = 'h20004000; +localparam doub_bt SystemTimerSize = 'h00001000; +// System Advanced Timer +localparam doub_bt SystemAdvancedTimerBase = 'h20005000; +localparam doub_bt SystemAdvancedTimerSize = 'h00001000; +// System Watchdog +localparam doub_bt SystemWatchdogBase = 'h20007000; +localparam doub_bt SystemWatchdogSize = 'h00001000; +// Hyperbus Config +localparam doub_bt HyperBusBase = 'h20009000; +localparam doub_bt HyperBusSize = 'h00001000; +/************************ + * RegBus Configuration * + ***********************/ +// Platform control registers +localparam doub_bt PcrsBase = 'h20010000; +localparam doub_bt PcrsSize = 'h00001000; +// PLL +localparam bit PllCfgEnable = 1; +localparam doub_bt PllCfgBase = 'h20020000; +localparam doub_bt PllCfgSize = 'h00001000; +// Padframe +localparam bit PadframeCfgEnable = 1; +localparam doub_bt PadframeCfgBase = 'h200A0000; +localparam doub_bt PadframeCfgSize = 'h00001000; +// L2 ECC +localparam bit L2EccCfgEnable = 1; +localparam doub_bt L2EccCfgBase = 'h200B0000; +localparam doub_bt L2EccCfgSize = 'h00001000; + +endpackage diff --git a/hw/configs/carfield_l2dual_spatz_periph.sv b/hw/configs/carfield_l2dual_spatz_periph.sv new file mode 100644 index 00000000..fa1fbcfe --- /dev/null +++ b/hw/configs/carfield_l2dual_spatz_periph.sv @@ -0,0 +1,84 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +package carfield_configuration; + +import cheshire_pkg::*; +/********************* + * AXI Configuration * + ********************/ +//L2, port 0 +localparam bit L2Port0Enable = 1; +localparam doub_bt L2Port0Base = 'h78000000; +localparam doub_bt L2Port0Size = 'h00200000; +// L2, port 1 +localparam bit L2Port1Enable = 1; +localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size; +localparam doub_bt L2Port1Size = L2Port0Size; +// Safety Island +localparam bit SafetyIslandEnable = 0; +localparam doub_bt SafetyIslandBase = 'h60000000; +localparam doub_bt SafetyIslandSize = 'h00800000; +// Ethernet +localparam bit EthernetEnable = 0; +localparam doub_bt EthernetBase = 'h20000000; +localparam doub_bt EthernetSize = 'h00001000; +// Peripherals +localparam bit PeriphEnable = 1; +localparam doub_bt PeriphBase = 'h20001000; +localparam doub_bt PeriphSize = 'h00009000; +// Spatz cluster +localparam bit SpatzClusterEnable = 1; +localparam doub_bt SpatzClusterBase = 'h51000000; +localparam doub_bt SpatzClusterSize = 'h00800000; +// PULP cluster +localparam bit PulpClusterEnable = 0; +localparam doub_bt PulpClusterBase = 'h50000000; +localparam doub_bt PulpClusterSize = 'h00800000; +// Security Island +localparam bit SecurityIslandEnable = 0; +localparam doub_bt SecurityIslandBase = 'h0; +localparam doub_bt SecurityIslandSize = 'h0; +// Mailbox +localparam bit MailboxEnable = 1; +localparam doub_bt MailboxBase = 'h40000000; +localparam doub_bt MailboxSize = 'h00001000; +// Can +localparam bit CanEnable = 0; +localparam doub_bt CanBase = 'h20001000; +localparam doub_bt CanSize = 'h00001000; +// System Timer +localparam doub_bt SystemTimerBase = 'h20004000; +localparam doub_bt SystemTimerSize = 'h00001000; +// System Advanced Timer +localparam doub_bt SystemAdvancedTimerBase = 'h20005000; +localparam doub_bt SystemAdvancedTimerSize = 'h00001000; +// System Watchdog +localparam doub_bt SystemWatchdogBase = 'h20007000; +localparam doub_bt SystemWatchdogSize = 'h00001000; +// Hyperbus Config +localparam doub_bt HyperBusBase = 'h20009000; +localparam doub_bt HyperBusSize = 'h00001000; +/************************ + * RegBus Configuration * + ***********************/ +// Platform control registers +localparam doub_bt PcrsBase = 'h20010000; +localparam doub_bt PcrsSize = 'h00001000; +// PLL +localparam bit PllCfgEnable = 1; +localparam doub_bt PllCfgBase = 'h20020000; +localparam doub_bt PllCfgSize = 'h00001000; +// Padframe +localparam bit PadframeCfgEnable = 1; +localparam doub_bt PadframeCfgBase = 'h200A0000; +localparam doub_bt PadframeCfgSize = 'h00001000; +// L2 ECC +localparam bit L2EccCfgEnable = 1; +localparam doub_bt L2EccCfgBase = 'h200B0000; +localparam doub_bt L2EccCfgSize = 'h00001000; + +endpackage diff --git a/hw/l2_wrap.sv b/hw/l2_wrap.sv index 9f77606f..85179770 100644 --- a/hw/l2_wrap.sv +++ b/hw/l2_wrap.sv @@ -154,17 +154,17 @@ typedef struct packed { } map_rule_t; localparam map_rule_t [NumRules-1:0] MappingRules = '{ - '{idx : dyn_mem_pkg::INTERLEAVE , - start_addr: L2Port0Base , - end_addr : L2Port0Base + L2MemSize}, - '{idx : dyn_mem_pkg::NONE_INTER , - start_addr: L2Port0NonInterlBase , + '{idx : dyn_mem_pkg::INTERLEAVE, + start_addr: L2Port0InterlBase, + end_addr : L2Port0InterlBase + L2MemSize}, + '{idx : dyn_mem_pkg::NONE_INTER, + start_addr: L2Port0NonInterlBase, end_addr : L2Port0NonInterlBase + L2MemSize}, - '{idx : dyn_mem_pkg::INTERLEAVE , - start_addr: L2Port1Base , - end_addr : L2Port1Base + L2MemSize}, - '{idx : dyn_mem_pkg::NONE_INTER , - start_addr: L2Port1NonInterlBase , + '{idx : dyn_mem_pkg::INTERLEAVE, + start_addr: L2Port1InterlBase, + end_addr : L2Port1InterlBase + L2MemSize}, + '{idx : dyn_mem_pkg::NONE_INTER, + start_addr: L2Port1NonInterlBase, end_addr : L2Port1NonInterlBase + L2MemSize} }; diff --git a/hw/spatz_cluster_wrapper.sv b/hw/spatz_cluster_wrapper.sv new file mode 100644 index 00000000..77a206fd --- /dev/null +++ b/hw/spatz_cluster_wrapper.sv @@ -0,0 +1,477 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +`include "axi/typedef.svh" + +module spatz_cluster_wrapper + import spatz_cluster_pkg::*; + import fpnew_pkg::fpu_implementation_t; + import snitch_pma_pkg::snitch_pma_t; + #( + parameter int unsigned AxiAddrWidth = 48, + parameter int unsigned AxiDataWidth = 64, + parameter int unsigned AxiUserWidth = 10, + parameter int unsigned AxiInIdWidth = 6, + parameter int unsigned AxiOutIdWidth = 2, + parameter int unsigned IwcAxiIdOutWidth = 3, + parameter int unsigned LogDepth = 3, + parameter int unsigned CdcSyncStages = 2, + parameter int unsigned SyncStages = 3, + parameter int unsigned AxiMaxOutTrans = 4, + // In channel + parameter type axi_in_resp_t = logic, + parameter type axi_in_req_t = logic, + parameter type axi_in_aw_chan_t = logic, + parameter type axi_in_w_chan_t = logic, + parameter type axi_in_b_chan_t = logic, + parameter type axi_in_ar_chan_t = logic, + parameter type axi_in_r_chan_t = logic, + // Out channel + parameter type axi_out_resp_t = logic, + parameter type axi_out_req_t = logic, + parameter type axi_out_aw_chan_t = logic, + parameter type axi_out_w_chan_t = logic, + parameter type axi_out_b_chan_t = logic, + parameter type axi_out_ar_chan_t = logic, + parameter type axi_out_r_chan_t = logic, + // AXI Master + parameter int unsigned AsyncAxiOutAwWidth = (2**LogDepth)* + axi_pkg::aw_width(AxiAddrWidth , + AxiOutIdWidth, + AxiUserWidth ), + parameter int unsigned AsyncAxiOutWWidth = (2**LogDepth)* + axi_pkg::w_width(AxiDataWidth, + AxiUserWidth), + parameter int unsigned AsyncAxiOutBWidth = (2**LogDepth)* + axi_pkg::b_width(AxiOutIdWidth, + AxiUserWidth ), + parameter int unsigned AsyncAxiOutArWidth = (2**LogDepth)* + axi_pkg::ar_width(AxiAddrWidth , + AxiOutIdWidth, + AxiUserWidth ), + parameter int unsigned AsyncAxiOutRWidth = (2**LogDepth)* + axi_pkg::r_width(AxiDataWidth , + AxiOutIdWidth, + AxiUserWidth ), + // AXI Slave + parameter int unsigned AsyncAxiInAwWidth = (2**LogDepth)* + axi_pkg::aw_width(AxiAddrWidth, + AxiInIdWidth, + AxiUserWidth), + parameter int unsigned AsyncAxiInWWidth = (2**LogDepth)* + axi_pkg::w_width(AxiDataWidth, + AxiUserWidth), + parameter int unsigned AsyncAxiInBWidth = (2**LogDepth)* + axi_pkg::b_width(AxiInIdWidth, + AxiUserWidth), + parameter int unsigned AsyncAxiInArWidth = (2**LogDepth)* + axi_pkg::ar_width(AxiAddrWidth, + AxiInIdWidth, + AxiUserWidth), + parameter int unsigned AsyncAxiInRWidth = (2**LogDepth)* + axi_pkg::r_width(AxiDataWidth, + AxiInIdWidth, + AxiUserWidth), + // Local parameters + localparam int unsigned AxiStrbWidth = AxiDataWidth / 8 +)( + input logic clk_i, + input logic rst_ni, + input logic [NumCores-1:0] debug_req_i, + + input logic [NumCores-1:0] meip_i, + input logic [NumCores-1:0] mtip_i, + input logic [NumCores-1:0] msip_i, + output logic cluster_probe_o, + input logic axi_isolate_i, + output logic axi_isolated_o, + input logic pwr_on_rst_ni, + + // AXI Master port + output logic [AsyncAxiOutAwWidth-1:0] async_axi_out_aw_data_o, + output logic [LogDepth:0] async_axi_out_aw_wptr_o, + input logic [LogDepth:0] async_axi_out_aw_rptr_i, + output logic [AsyncAxiOutWWidth-1:0] async_axi_out_w_data_o, + output logic [LogDepth:0] async_axi_out_w_wptr_o, + input logic [LogDepth:0] async_axi_out_w_rptr_i, + input logic [AsyncAxiOutBWidth-1:0] async_axi_out_b_data_i, + input logic [LogDepth:0] async_axi_out_b_wptr_i, + output logic [LogDepth:0] async_axi_out_b_rptr_o, + output logic [AsyncAxiOutArWidth-1:0] async_axi_out_ar_data_o, + output logic [LogDepth:0] async_axi_out_ar_wptr_o, + input logic [LogDepth:0] async_axi_out_ar_rptr_i, + input logic [AsyncAxiOutRWidth-1:0] async_axi_out_r_data_i, + input logic [LogDepth:0] async_axi_out_r_wptr_i, + output logic [LogDepth:0] async_axi_out_r_rptr_o, + + // AXI Slave port + input logic [AsyncAxiInArWidth-1:0] async_axi_in_ar_data_i, + input logic [LogDepth:0] async_axi_in_ar_wptr_i, + output logic [LogDepth:0] async_axi_in_ar_rptr_o, + input logic [AsyncAxiInAwWidth-1:0] async_axi_in_aw_data_i, + input logic [LogDepth:0] async_axi_in_aw_wptr_i, + output logic [LogDepth:0] async_axi_in_aw_rptr_o, + output logic [AsyncAxiInBWidth-1:0] async_axi_in_b_data_o, + output logic [LogDepth:0] async_axi_in_b_wptr_o, + input logic [LogDepth:0] async_axi_in_b_rptr_i, + output logic [AsyncAxiInRWidth-1:0] async_axi_in_r_data_o, + output logic [LogDepth:0] async_axi_in_r_wptr_o, + input logic [LogDepth:0] async_axi_in_r_rptr_i, + input logic [AsyncAxiInWWidth-1:0] async_axi_in_w_data_i, + input logic [LogDepth:0] async_axi_in_w_wptr_i, + output logic [LogDepth:0] async_axi_in_w_rptr_o +); + + typedef logic [AxiDataWidth-1:0] axi_data_t; + typedef logic [AxiStrbWidth-1:0] axi_strb_t; + typedef logic [AxiAddrWidth-1:0] axi_addr_t; + typedef logic [AxiInIdWidth-1:0] axi_id_in_t; + typedef logic [AxiOutIdWidth-1:0] axi_id_out_t; + typedef logic [AxiUserWidth-1:0] axi_user_t; + typedef logic [IwcAxiIdOutWidth-1:0] axi_id_out_iwc_t; + `AXI_TYPEDEF_ALL(axi_iwc_out, axi_addr_t, axi_id_out_iwc_t, axi_data_t, axi_strb_t, axi_user_t) + + localparam int unsigned NumIntOutstandingLoads [NumCores] = '{1, 1}; + localparam int unsigned NumIntOutstandingMem [NumCores] = '{4, 4}; + localparam int unsigned NumSpatzOutstandingLoads [NumCores] = '{4, 4}; + + axi_iwc_out_req_t axi_from_cluster_iwc_req; + axi_iwc_out_resp_t axi_from_cluster_iwc_resp; + + axi_out_req_t axi_from_cluster_req; + axi_out_resp_t axi_from_cluster_resp; + + // From AXI Isolate to CDC + axi_out_req_t axi_from_cluster_iso_req; + axi_out_resp_t axi_from_cluster_iso_resp; + logic axi_isolate_sync; + + localparam int unsigned ICacheLineWidth = 128; + localparam int unsigned ICacheLineCount = 128; + localparam int unsigned ICacheSets = 2; + + function automatic snitch_pma_pkg::rule_t [snitch_pma_pkg::NrMaxRules-1:0] get_cached_regions(); + automatic snitch_pma_pkg::rule_t [snitch_pma_pkg::NrMaxRules-1:0] cached_regions; + cached_regions = '{default: '0}; + cached_regions[0] = '{base: 48'h78000000, mask: 48'hffffffc00000}; + return cached_regions; + endfunction + + localparam snitch_pma_pkg::snitch_pma_t SnitchPMACfg = '{ + NrCachedRegionRules: 1, + CachedRegion: get_cached_regions(), + default: 0 + }; + + localparam fpnew_pkg::fpu_implementation_t FPUImplementation [NumCores] = '{ + '{ + PipeRegs: // FMA Block + '{ + '{ 2, // FP32 + 4, // FP64 + 1, // FP16 + 0, // FP8 + 1, // FP16alt + 0 // FP8alt + }, + '{1, 1, 1, 1, 1, 1}, // DIVSQRT + '{1, + 1, + 1, + 1, + 1, + 1}, // NONCOMP + '{2, + 2, + 2, + 2, + 2, + 2}, // CONV + '{4, + 4, + 4, + 4, + 4, + 4} // DOTP + }, + UnitTypes: '{'{fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED}, // FMA + '{fpnew_pkg::DISABLED, + fpnew_pkg::DISABLED, + fpnew_pkg::DISABLED, + fpnew_pkg::DISABLED, + fpnew_pkg::DISABLED, + fpnew_pkg::DISABLED}, // DIVSQRT + '{fpnew_pkg::PARALLEL, + fpnew_pkg::PARALLEL, + fpnew_pkg::PARALLEL, + fpnew_pkg::PARALLEL, + fpnew_pkg::PARALLEL, + fpnew_pkg::PARALLEL}, // NONCOMP + '{fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED}, // CONV + '{fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED}}, // DOTP + PipeConfig: fpnew_pkg::BEFORE + }, + '{ + PipeRegs: // FMA Block + '{ + '{ 2, // FP32 + 4, // FP64 + 1, // FP16 + 0, // FP8 + 1, // FP16alt + 0 // FP8alt + }, + '{1, 1, 1, 1, 1, 1}, // DIVSQRT + '{1, + 1, + 1, + 1, + 1, + 1}, // NONCOMP + '{2, + 2, + 2, + 2, + 2, + 2}, // CONV + '{4, + 4, + 4, + 4, + 4, + 4} // DOTP + }, + UnitTypes: '{'{fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED}, // FMA + '{fpnew_pkg::DISABLED, + fpnew_pkg::DISABLED, + fpnew_pkg::DISABLED, + fpnew_pkg::DISABLED, + fpnew_pkg::DISABLED, + fpnew_pkg::DISABLED}, // DIVSQRT + '{fpnew_pkg::PARALLEL, + fpnew_pkg::PARALLEL, + fpnew_pkg::PARALLEL, + fpnew_pkg::PARALLEL, + fpnew_pkg::PARALLEL, + fpnew_pkg::PARALLEL}, // NONCOMP + '{fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED}, // CONV + '{fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED, + fpnew_pkg::MERGED}}, // DOTP + PipeConfig: fpnew_pkg::BEFORE + } + }; + + sync #( + .STAGES ( SyncStages ), + .ResetValue ( 1'b1 ) + ) i_isolate_sync ( + .clk_i, + .rst_ni ( pwr_on_rst_ni ), + .serial_i ( axi_isolate_i ), + .serial_o ( axi_isolate_sync ) + ); + + axi_isolate #( + .NumPending ( AxiMaxOutTrans ), + .TerminateTransaction ( 1 ), + .AtopSupport ( 1 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiOutIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .axi_req_t ( axi_out_req_t ), + .axi_resp_t ( axi_out_resp_t ) + ) i_axi_out_isolate ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( axi_from_cluster_req ), + .slv_resp_o ( axi_from_cluster_resp ), + .mst_req_o ( axi_from_cluster_iso_req ), + .mst_resp_i ( axi_from_cluster_iso_resp ), + .isolate_i ( axi_isolate_sync ), + .isolated_o ( axi_isolated_o ) + ) ; + + // From CDC to Cluster + axi_in_req_t axi_to_cluster_req; + axi_in_resp_t axi_to_cluster_resp; + + axi_cdc_dst #( + .LogDepth ( LogDepth ), + .SyncStages ( CdcSyncStages ), + .aw_chan_t ( axi_in_aw_chan_t ), + .w_chan_t ( axi_in_w_chan_t ), + .b_chan_t ( axi_in_b_chan_t ), + .ar_chan_t ( axi_in_ar_chan_t ), + .r_chan_t ( axi_in_r_chan_t ), + .axi_req_t ( axi_in_req_t ), + .axi_resp_t ( axi_in_resp_t ) + ) i_spatz_cluster_cdc_dst ( + // Asynchronous slave port + .async_data_slave_aw_data_i ( async_axi_in_aw_data_i ), + .async_data_slave_aw_wptr_i ( async_axi_in_aw_wptr_i ), + .async_data_slave_aw_rptr_o ( async_axi_in_aw_rptr_o ), + .async_data_slave_w_data_i ( async_axi_in_w_data_i ), + .async_data_slave_w_wptr_i ( async_axi_in_w_wptr_i ), + .async_data_slave_w_rptr_o ( async_axi_in_w_rptr_o ), + .async_data_slave_b_data_o ( async_axi_in_b_data_o ), + .async_data_slave_b_wptr_o ( async_axi_in_b_wptr_o ), + .async_data_slave_b_rptr_i ( async_axi_in_b_rptr_i ), + .async_data_slave_ar_data_i ( async_axi_in_ar_data_i ), + .async_data_slave_ar_wptr_i ( async_axi_in_ar_wptr_i ), + .async_data_slave_ar_rptr_o ( async_axi_in_ar_rptr_o ), + .async_data_slave_r_data_o ( async_axi_in_r_data_o ), + .async_data_slave_r_wptr_o ( async_axi_in_r_wptr_o ), + .async_data_slave_r_rptr_i ( async_axi_in_r_rptr_i ), + // Synchronous master port + .dst_clk_i ( clk_i ), + .dst_rst_ni ( pwr_on_rst_ni ), + .dst_req_o ( axi_to_cluster_req ), + .dst_resp_i ( axi_to_cluster_resp ) + ); + + axi_cdc_src #( + .LogDepth ( LogDepth ), + .SyncStages ( CdcSyncStages ), + .aw_chan_t ( axi_out_aw_chan_t ), + .w_chan_t ( axi_out_w_chan_t ), + .b_chan_t ( axi_out_b_chan_t ), + .ar_chan_t ( axi_out_ar_chan_t ), + .r_chan_t ( axi_out_r_chan_t ), + .axi_req_t ( axi_out_req_t ), + .axi_resp_t ( axi_out_resp_t ) + ) i_spatz_cluster_cdc_src ( + // Asynchronous Master port + .async_data_master_aw_data_o( async_axi_out_aw_data_o ), + .async_data_master_aw_wptr_o( async_axi_out_aw_wptr_o ), + .async_data_master_aw_rptr_i( async_axi_out_aw_rptr_i ), + .async_data_master_w_data_o ( async_axi_out_w_data_o ), + .async_data_master_w_wptr_o ( async_axi_out_w_wptr_o ), + .async_data_master_w_rptr_i ( async_axi_out_w_rptr_i ), + .async_data_master_b_data_i ( async_axi_out_b_data_i ), + .async_data_master_b_wptr_i ( async_axi_out_b_wptr_i ), + .async_data_master_b_rptr_o ( async_axi_out_b_rptr_o ), + .async_data_master_ar_data_o( async_axi_out_ar_data_o ), + .async_data_master_ar_wptr_o( async_axi_out_ar_wptr_o ), + .async_data_master_ar_rptr_i( async_axi_out_ar_rptr_i ), + .async_data_master_r_data_i ( async_axi_out_r_data_i ), + .async_data_master_r_wptr_i ( async_axi_out_r_wptr_i ), + .async_data_master_r_rptr_o ( async_axi_out_r_rptr_o ), + // Synchronous slave port + .src_clk_i ( clk_i ), + .src_rst_ni ( pwr_on_rst_ni ), + .src_req_i ( axi_from_cluster_iso_req ), + .src_resp_o ( axi_from_cluster_iso_resp) + ); + + axi_iw_converter #( + .AxiSlvPortIdWidth ( IwcAxiIdOutWidth ), + .AxiMstPortIdWidth ( AxiOutIdWidth ), + .AxiSlvPortMaxUniqIds ( 2 ), + .AxiSlvPortMaxTxnsPerId ( 2 ), + .AxiSlvPortMaxTxns ( 4 ), + .AxiMstPortMaxUniqIds ( 2 ), + .AxiMstPortMaxTxnsPerId ( 4 ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiUserWidth ( AxiUserWidth ), + .slv_req_t ( axi_iwc_out_req_t ), + .slv_resp_t ( axi_iwc_out_resp_t ), + .mst_req_t ( axi_out_req_t ), + .mst_resp_t ( axi_out_resp_t ) + ) iw_converter( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( axi_from_cluster_iwc_req ), + .slv_resp_o ( axi_from_cluster_iwc_resp ), + .mst_req_o ( axi_from_cluster_req ), + .mst_resp_i ( axi_from_cluster_resp ) + ); + + // Spatz cluster under test. + spatz_cluster #( + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidthIn ( AxiInIdWidth ), + .AxiIdWidthOut ( IwcAxiIdOutWidth ), + .AxiUserWidth ( AxiUserWidth ), + .BootAddr ( 32'h1000 ), + .ClusterPeriphSize ( 64 ), + .NrCores ( 2 ), + .TCDMDepth ( 1024 ), + .NrBanks ( 16 ), + .ICacheLineWidth ( ICacheLineWidth ), + .ICacheLineCount ( ICacheLineCount ), + .ICacheSets ( ICacheSets ), + .FPUImplementation ( FPUImplementation ), + .SnitchPMACfg ( SnitchPMACfg ), + .NumIntOutstandingLoads ( NumIntOutstandingLoads ), + .NumIntOutstandingMem ( NumIntOutstandingMem ), + .NumSpatzOutstandingLoads ( NumSpatzOutstandingLoads ), + .axi_in_req_t ( axi_in_req_t ), + .axi_in_resp_t ( axi_in_resp_t ), + .axi_out_req_t ( axi_iwc_out_req_t ), + .axi_out_resp_t ( axi_iwc_out_resp_t ), + .Xdma ( 2'b01 ), + .DMAAxiReqFifoDepth ( 3 ), + .DMAReqFifoDepth ( 3 ), + .RegisterOffloadRsp ( 1 ), + .RegisterCoreReq ( 1 ), + .RegisterCoreRsp ( 1 ), + .RegisterTCDMCuts ( 1 ), + .RegisterExt ( 0 ), + .XbarLatency ( axi_pkg::CUT_ALL_PORTS ), + .MaxMstTrans ( 4 ), + .MaxSlvTrans ( 4 ) + ) i_cluster ( + .clk_i, + .rst_ni, + .debug_req_i, + .meip_i, + .mtip_i, + .msip_i, + .hart_base_id_i ( 10'h10 ), + .cluster_base_addr_i ( 48'h51000000 ), + .axi_core_default_user_i ( 10'h7 ), + .cluster_probe_o, + // AXI Slave Port + .axi_in_req_i ( axi_to_cluster_req ), + .axi_in_resp_o ( axi_to_cluster_resp ), + // AXI Master Port + .axi_out_req_o ( axi_from_cluster_iwc_req ), + .axi_out_resp_i ( axi_from_cluster_iwc_resp ) + ); + +endmodule: spatz_cluster_wrapper diff --git a/target/sim/src/carfield_fix.sv b/target/sim/src/carfield_fix.sv index daf776a0..10b7f543 100644 --- a/target/sim/src/carfield_fix.sv +++ b/target/sim/src/carfield_fix.sv @@ -326,121 +326,136 @@ module carfield_soc_fixture; // Safety island VIP // /////////////////////// - localparam time ClkPeriodSafedJtag = 20ns; - - localparam axi_in_t AxiIn = gen_axi_in(DutCfg); - localparam int unsigned AxiSlvIdWidth = DutCfg.AxiMstIdWidth + $clog2(AxiIn.num_in); - // VIP - vip_safety_island_soc #( - .DutCfg ( SafetyIslandCfg ), - .axi_mst_ext_req_t ( axi_mst_req_t ), - .axi_mst_ext_rsp_t ( axi_mst_rsp_t ), - .axi_slv_ext_req_t ( axi_mst_req_t ), - .axi_slv_ext_rsp_t ( axi_mst_rsp_t ), - .GlobalAddrWidth ( 32 ), - .BaseAddr ( 32'h6000_0000 ), - .AddrRange ( SafetyIslandSize ), - .MemOffset ( SafetyIslandMemOffset ), - .PeriphOffset ( SafetyIslandPerOffset ), - .ClkPeriodSys ( ClkPeriodSys ), - .ClkPeriodJtag ( ClkPeriodSafedJtag ), - .ClkPeriodRtc ( ClkPeriodRtc ), - .RstCycles ( RstCycles ), - .AxiDataWidth ( DutCfg.AxiDataWidth ), - .AxiAddrWidth ( DutCfg.AddrWidth ), - .AxiInputIdWidth ( AxiSlvIdWidth ), - .AxiOutputIdWidth ( DutCfg.AxiMstIdWidth ), - .AxiUserWidth ( DutCfg.AxiUserWidth ), - .AxiDebug ( 0 ), - .ApplFrac ( TAppl ), - .TestFrac ( TTest ) - ) safed_vip ( - // we use the clock generated in cheshire VIP - .clk_vip (), - .ext_clk_vip (), - // we use the reset generated in cheshire VIP - .rst_n_vip (), - .test_mode (), - .boot_mode ( boot_mode_safed ), - // we use the rtc generated in cheshire VIP - .rtc (), - // Not used in carfield - .axi_mst_req ( '0 ), - .axi_mst_rsp ( ), - // Virtual driver to be multiplexed and then serialized through the serial link - .axi_slv_req ( ext_to_vip_req[SafedNumAxiExtMstPorts-1:0] ), - .axi_slv_rsp ( ext_to_vip_rsp[SafedNumAxiExtMstPorts-1:0] ), - // JTAG interface - .jtag_tck ( jtag_safed_tck ), - .jtag_trst_n ( jtag_safed_trst_n ), - .jtag_tms ( jtag_safed_tms ), - .jtag_tdi ( jtag_safed_tdi ), - .jtag_tdo ( jtag_safed_tdo ), - // Exit - .exit_status ( ) - ); + if (CarfieldIslandsCfg.safed.enable) begin : gen_safed_vip + localparam time ClkPeriodSafedJtag = 20ns; + + localparam axi_in_t AxiIn = gen_axi_in(DutCfg); + localparam int unsigned AxiSlvIdWidth = DutCfg.AxiMstIdWidth + $clog2(AxiIn.num_in); + + vip_safety_island_soc #( + .DutCfg ( SafetyIslandCfg ), + .axi_mst_ext_req_t ( axi_mst_req_t ), + .axi_mst_ext_rsp_t ( axi_mst_rsp_t ), + .axi_slv_ext_req_t ( axi_mst_req_t ), + .axi_slv_ext_rsp_t ( axi_mst_rsp_t ), + .GlobalAddrWidth ( 32 ), + .BaseAddr ( 32'h6000_0000 ), + .AddrRange ( CarfieldIslandsCfg.safed.size ), + .MemOffset ( SafetyIslandMemOffset ), + .PeriphOffset ( SafetyIslandPerOffset ), + .ClkPeriodSys ( ClkPeriodSys ), + .ClkPeriodJtag ( ClkPeriodSafedJtag ), + .ClkPeriodRtc ( ClkPeriodRtc ), + .RstCycles ( RstCycles ), + .AxiDataWidth ( DutCfg.AxiDataWidth ), + .AxiAddrWidth ( DutCfg.AddrWidth ), + .AxiInputIdWidth ( AxiSlvIdWidth ), + .AxiOutputIdWidth ( DutCfg.AxiMstIdWidth ), + .AxiUserWidth ( DutCfg.AxiUserWidth ), + .AxiDebug ( 0 ), + .ApplFrac ( TAppl ), + .TestFrac ( TTest ) + ) safed_vip ( + // we use the clock generated in cheshire VIP + .clk_vip (), + .ext_clk_vip (), + // we use the reset generated in cheshire VIP + .rst_n_vip (), + .test_mode (), + .boot_mode (), + // we use the rtc generated in cheshire VIP + .rtc (), + // Not used in carfield + .axi_mst_req ( '0 ), + .axi_mst_rsp ( ), + // Virtual driver to be multiplexed and then serialized through the serial link + .axi_slv_req ( ext_to_vip_req[SafedNumAxiExtMstPorts-1:0] ), + .axi_slv_rsp ( ext_to_vip_rsp[SafedNumAxiExtMstPorts-1:0] ), + // JTAG interface + .jtag_tck ( jtag_safed_tck ), + .jtag_trst_n ( jtag_safed_trst_n ), + .jtag_tms ( jtag_safed_tms ), + .jtag_tdi ( jtag_safed_tdi ), + .jtag_tdo ( jtag_safed_tdo ), + // Exit + .exit_status ( ) + ); + + end else begin: gen_no_safed_vip + assign jtag_safed_tck = '0; + assign jtag_safed_trst_n = '0; + assign jtag_safed_tms = '0; + assign jtag_safed_tdi = '0; + end ///////////////////////// // Security island VIP // ///////////////////////// - - localparam time ClkPeriodSecdJtag = 20ns; - - // Tristate adapter - wire SPI_D0, SPI_D1, SPI_SCK, SPI_CSB; - - // I/O to INOUT behavioral conversion for security island's peripherals that require it - vip_security_island_tristate secd_vip_tristate ( - // SPI interface - .spi_secd_sd_i ( spi_secd_sd_o ), - .spi_secd_sd_o ( spi_secd_sd_i ), - .spi_secd_sd_oe_i ( spi_secd_sd_en ), - .spi_secd_csb_oe_i ( spi_secd_csb_en ), - .spi_secd_csb_i ( spi_secd_csb_o ), - .spi_secd_sck_oe_i ( spi_secd_sck_en ), - .spi_secd_sck_i ( spi_secd_sck_o ), - .SPI_D0, - .SPI_D1, - .SPI_SCK, - .SPI_CSB - ); - - // VIP - vip_security_island_soc #( - .ClkPeriodSys ( ClkPeriodSys ), - .ClkPeriodJtag ( ClkPeriodSecdJtag ), - .RstCycles ( RstCycles ), - .TAppl ( TAppl ), - .TTest ( TTest ) - ) secd_vip ( - .clk_vip ( ), - .rst_n_vip ( ), - .bootmode ( boot_mode_secd ), - // UART interface - .uart_tx ( uart_secd_tx ), - .uart_rx ( uart_secd_rx ), - // JTAG interface - .jtag_tck ( jtag_secd_tck ), - .jtag_trst_n ( jtag_secd_trst_n ), - .jtag_tms ( jtag_secd_tms ), - .jtag_tdi ( jtag_secd_tdi ), - .jtag_tdo ( jtag_secd_tdo ), - .SPI_D0, - .SPI_D1, - .SPI_SCK, - .SPI_CSB - ); + lc_ctrl_pkg::lc_tx_t secured_fetch_enable; + if (CarfieldIslandsCfg.secured.enable) begin: gen_scured_vip + localparam time ClkPeriodSecdJtag = 20ns; + + // Tristate adapter + wire SPI_D0, SPI_D1, SPI_SCK, SPI_CSB; + + assign secured_fetch_enable = i_dut.gen_secure_subsystem.i_security_island.u_RoT.u_rv_core_ibex.fetch_enable; + + // I/O to INOUT behavioral conversion for security island's peripherals that require it + vip_security_island_tristate secd_vip_tristate ( + // SPI interface + .spi_secd_sd_i ( spi_secd_sd_o ), + .spi_secd_sd_o ( spi_secd_sd_i ), + .spi_secd_sd_oe_i ( spi_secd_sd_en ), + .spi_secd_csb_oe_i ( spi_secd_csb_en ), + .spi_secd_csb_i ( spi_secd_csb_o ), + .spi_secd_sck_oe_i ( spi_secd_sck_en ), + .spi_secd_sck_i ( spi_secd_sck_o ), + .SPI_D0, + .SPI_D1, + .SPI_SCK, + .SPI_CSB + ); + + // VIP + vip_security_island_soc #( + .ClkPeriodSys ( ClkPeriodSys ), + .ClkPeriodJtag ( ClkPeriodSecdJtag ), + .RstCycles ( RstCycles ), + .TAppl ( TAppl ), + .TTest ( TTest ) + ) secd_vip ( + .clk_vip ( ), + .rst_n_vip ( ), + .bootmode ( boot_mode_secd ), + // UART interface + .uart_tx ( uart_secd_tx ), + .uart_rx ( uart_secd_rx ), + // JTAG interface + .jtag_tck ( jtag_secd_tck ), + .jtag_trst_n ( jtag_secd_trst_n ), + .jtag_tms ( jtag_secd_tms ), + .jtag_tdi ( jtag_secd_tdi ), + .jtag_tdo ( jtag_secd_tdo ), + .SPI_D0, + .SPI_D1, + .SPI_SCK, + .SPI_CSB + ); + end else begin: gen_no_scured_vip + assign secured_fetch_enable = lc_ctrl_pkg::Off; + end /////////////////// // Generic tasks // /////////////////// task passthrough_or_wait_for_secd_hw_init(); - if ((secure_boot || !i_dut.car_regs_hw2reg.security_island_isolate_status.d) && - i_dut.gen_secure_subsystem.i_security_island.u_RoT.u_rv_core_ibex.fetch_enable != lc_ctrl_pkg::On) begin + if (CarfieldIslandsCfg.secured.enable && + (secure_boot || !i_dut.car_regs_hw2reg.security_island_isolate_status.d) && + secured_fetch_enable != lc_ctrl_pkg::On) begin $display("Wait for OT to boot..."); - wait (i_dut.gen_secure_subsystem.i_security_island.u_RoT.u_rv_core_ibex.fetch_enable == lc_ctrl_pkg::On); + wait (secured_fetch_enable == lc_ctrl_pkg::On); end endtask diff --git a/target/sim/src/carfield_tb.sv b/target/sim/src/carfield_tb.sv index 3f596aa4..9d11161a 100644 --- a/target/sim/src/carfield_tb.sv +++ b/target/sim/src/carfield_tb.sv @@ -29,60 +29,9 @@ module tb_carfield_soc; bit [31:0] exit_code; bit is_dram; - // safety island - string safed_preload_elf; - logic safed_boot_mode; - bit [31:0] safed_exit_code; - bit safed_exit_status; - bit [31:0] safed_isolated; - - localparam int unsigned SafetyIslandClkEnRegAddr = 32'h20010070; - localparam int unsigned SafetyIslandIsolateRegAddr = 32'h20010040; - localparam int unsigned SafetyIslandIsolateStatusRegAddr = 32'h20010058; - - // security island - string secd_preload_elf; - string secd_flash_vmem; - logic secd_boot_mode; - // hyperbus localparam int unsigned HyperbusTburstMax = 32'h20009008; - // spatz cluster - string spatzd_preload_elf; - logic [1:0] spatzd_boot_mode; - bit [31:0] spatzd_exit_code; - doub_bt spatzd_binary_entry; - doub_bt spatzd_reg_value; - - localparam int unsigned SpatzdClkEnRegAddr = 32'h2001007c; - localparam int unsigned SpatzdIsolateRegAddr = 32'h2001004c; - localparam int unsigned SpatzdIsolateStatusRegAddr = 32'h20010064; - - // pulp cluster - // Useful register addresses - localparam int unsigned CarL2StartAddr = 32'h7800_0000; - localparam int unsigned CarDramStartAddr = 32'h8000_0000; - localparam int unsigned PulpdNumCores = 12; - localparam int unsigned PulpdBootAddrL2 = CarL2StartAddr + 32'h8080; - localparam int unsigned PulpdBootAddrDram = CarDramStartAddr + 32'h8080; - localparam int unsigned PulpdBootAddr = 32'h50200040; - localparam int unsigned PulpdRetAddr = 32'h50200100; - localparam int unsigned CarSocCtrlPulpdClkEnRegAddr = 32'h20010078; - localparam int unsigned CarSocCtrlPulpdIsolateRegAddr = 32'h20010048; - localparam int unsigned CarSocCtrlPulpdIsolateStatusRegAddr = 32'h20010060; - localparam int unsigned CarSocCtrlPulpdFetchEnAddr = 32'h200100c0; - localparam int unsigned CarSocCtrlPulpdBootEnAddr = 32'h200100dc; - localparam int unsigned CarSocCtrlPulpdBusyAddr = 32'h200100e4; - localparam int unsigned CarSocCtrlPulpdEocAddr = 32'h200100e8; - // sim variables - string pulpd_preload_elf; - logic [1:0] pulpd_boot_mode; - bit [31:0] pulpd_exit_code; - bit [31:0] pulpd_ret_val; - doub_bt pulpd_binary_entry; - doub_bt pulpd_reg_value; - // mailbox unit parameter logic [31:0] CAR_MBOX_BASE = 32'h40000000; parameter logic [31:0] CAR_NUM_MAILBOXES = 32'h25; @@ -163,9 +112,10 @@ module tb_carfield_soc; $display("[TB] INFO: Configuring Hyperbus through serial link."); fix.chs_vip.slink_write_32(HyperbusTburstMax, 32'd128); - // When Cheshire is offloading to safety island, the latter should be set in passive preloaded - // bootmode - fix.safed_vip.set_safed_boot_mode(safety_island_pkg::Preloaded); + // If the safety island is enabled, when Cheshire is offloading to it + // it should be set in passive preload bootmode + fix.boot_mode_safed = (CarfieldIslandsCfg.safed.enable) ? safety_island_pkg::Preloaded : '0; + // Preload in idle mode or wait for completion in autonomous boot if (boot_mode == 0) begin // Idle boot: preload with the specified mode @@ -220,320 +170,378 @@ module tb_carfield_soc; end // safety island standalone - initial begin - // Fetch plusargs or use safe (fail-fast) defaults - if (!$value$plusargs("SECURE_BOOT=%d", secure_boot)) secure_boot = 0; - if (!$value$plusargs("SAFED_BOOTMODE=%d", safed_boot_mode)) safed_boot_mode = 0; - if (!$value$plusargs("SAFED_BINARY=%s", safed_preload_elf)) safed_preload_elf = ""; - - // set secure boot mode - fix.set_secure_boot(secure_boot); - - // set boot mode before reset - fix.safed_vip.set_safed_boot_mode(safed_boot_mode); - - if (safed_preload_elf != "") begin - - fix.safed_vip.safed_wait_for_reset(); - - // Writing max burst length in Hyperbus configuration registers to - // prevent the Verification IPs from triggering timing checks. - $display("[TB] INFO: Configuring Hyperbus through serial link."); - fix.safed_vip.axi_write_32(HyperbusTburstMax, 32'd128); - - $display("[TB] %t - Enabling safety island clock for stand-alone tests ", $realtime); - // Clock island after PoR - fix.safed_vip.axi_write_32(SafetyIslandClkEnRegAddr, 32'h1); - $display("[TB] %t - De-isolate safety island for stand-alone tests ", $realtime); - // De-isolate island after PoR - fix.safed_vip.axi_write_32(SafetyIslandIsolateRegAddr, 32'h0); - - case (safed_boot_mode) - 0: begin - fix.safed_vip.jtag_safed_init(); - fix.safed_vip.jtag_write_test(32'h6000_1000, 32'hABBA_ABBA); - fix.safed_vip.jtag_safed_elf_run(safed_preload_elf); - fix.safed_vip.jtag_safed_wait_for_eoc(safed_exit_code, safed_exit_status); - end 1: begin - fix.safed_vip.axi_safed_elf_run(safed_preload_elf); - fix.safed_vip.axi_safed_wait_for_eoc(safed_exit_code, safed_exit_status); - end default: begin - $fatal(1, "Unsupported boot mode %d (reserved)!", safed_boot_mode); - end - endcase + if (CarfieldIslandsCfg.safed.enable) begin : gen_safed_tb + // safety island + string safed_preload_elf; + logic safed_boot_mode; + bit [31:0] safed_exit_code; + bit safed_exit_status; + bit [31:0] safed_isolated; + + localparam int unsigned SafetyIslandClkEnRegAddr = 32'h20010070; + localparam int unsigned SafetyIslandIsolateRegAddr = 32'h20010040; + localparam int unsigned SafetyIslandIsolateStatusRegAddr = 32'h20010058; + + initial begin + // Fetch plusargs or use safe (fail-fast) defaults + if (!$value$plusargs("SECURE_BOOT=%d", secure_boot)) secure_boot = 0; + if (!$value$plusargs("SAFED_BOOTMODE=%d", safed_boot_mode)) safed_boot_mode = 0; + if (!$value$plusargs("SAFED_BINARY=%s", safed_preload_elf)) safed_preload_elf = ""; + + // set secure boot mode + fix.set_secure_boot(secure_boot); + + // set boot mode before reset + fix.boot_mode_safed = safed_boot_mode; + + if (safed_preload_elf != "") begin + + fix.gen_safed_vip.safed_vip.safed_wait_for_reset(); + + // Writing max burst length in Hyperbus configuration registers to + // prevent the Verification IPs from triggering timing checks. + $display("[TB] INFO: Configuring Hyperbus through serial link."); + fix.gen_safed_vip.safed_vip.axi_write_32(HyperbusTburstMax, 32'd128); + + $display("[TB] %t - Enabling safety island clock for stand-alone tests ", $realtime); + // Clock island after PoR + fix.gen_safed_vip.safed_vip.axi_write_32(SafetyIslandClkEnRegAddr, 32'h1); + $display("[TB] %t - De-isolate safety island for stand-alone tests ", $realtime); + // De-isolate island after PoR + fix.gen_safed_vip.safed_vip.axi_write_32(SafetyIslandIsolateRegAddr, 32'h0); + + case (safed_boot_mode) + 0: begin + fix.gen_safed_vip.safed_vip.jtag_safed_init(); + fix.gen_safed_vip.safed_vip.jtag_write_test(32'h6000_1000, 32'hABBA_ABBA); + fix.gen_safed_vip.safed_vip.jtag_safed_elf_run(safed_preload_elf); + fix.gen_safed_vip.safed_vip.jtag_safed_wait_for_eoc(safed_exit_code, safed_exit_status); + end 1: begin + fix.gen_safed_vip.safed_vip.axi_safed_elf_run(safed_preload_elf); + fix.gen_safed_vip.safed_vip.axi_safed_wait_for_eoc(safed_exit_code, safed_exit_status); + end default: begin + $fatal(1, "Unsupported boot mode %d (reserved)!", safed_boot_mode); + end + endcase - $finish; + $finish; + end end end - // security island standalone - initial begin - // Fetch plusargs or use safe (fail-fast) defaults - if (!$value$plusargs("SECURE_BOOT=%d", secure_boot)) secure_boot = 0; - if (!$value$plusargs("SECD_IMAGE=%s", secd_flash_vmem)) secd_flash_vmem = ""; - if (!$value$plusargs("SECD_BINARY=%s", secd_preload_elf)) secd_preload_elf = ""; - if (!$value$plusargs("SECD_BOOTMODE=%d", secd_boot_mode)) secd_boot_mode = 0; - - // set secure boot mode - fix.set_secure_boot(secure_boot); + // security island + if (CarfieldIslandsCfg.secured.enable) begin: gen_secured_tb + string secd_preload_elf; + string secd_flash_vmem; + logic secd_boot_mode; + + // security island standalone + initial begin + // Fetch plusargs or use safe (fail-fast) defaults + if (!$value$plusargs("SECURE_BOOT=%d", secure_boot)) secure_boot = 0; + if (!$value$plusargs("SECD_IMAGE=%s", secd_flash_vmem)) secd_flash_vmem = ""; + if (!$value$plusargs("SECD_BINARY=%s", secd_preload_elf)) secd_preload_elf = ""; + if (!$value$plusargs("SECD_BOOTMODE=%d", secd_boot_mode)) secd_boot_mode = 0; + + // set secure boot mode + fix.set_secure_boot(secure_boot); + + // set bootmode + fix.gen_scured_vip.secd_vip.set_secd_boot_mode(secd_boot_mode); + + if (secd_preload_elf != "" || secd_flash_vmem != "") begin + // Wait for reset + fix.chs_vip.wait_for_reset(); + + // Writing max burst length in Hyperbus configuration registers to + // prevent the Verification IPs from triggering timing checks. + $display("[TB] INFO: Configuring Hyperbus through serial link."); + fix.chs_vip.slink_write_32(HyperbusTburstMax, 32'd128); + + case(secd_boot_mode) + 0: begin + // Wait before security island HW is initialized + repeat(10000) + @(posedge fix.clk); + fix.gen_scured_vip.secd_vip.debug_secd_module_init(); + fix.gen_scured_vip.secd_vip.load_secd_binary(secd_preload_elf); + fix.gen_scured_vip.secd_vip.jtag_secd_data_preload(); + fix.gen_scured_vip.secd_vip.jtag_secd_wakeup(32'hE0000080); + fix.gen_scured_vip.secd_vip.jtag_secd_wait_eoc(); + end 1: begin + fix.gen_scured_vip.secd_vip.spih_norflash_preload(secd_flash_vmem); + repeat(10000) + @(posedge fix.clk); + fix.gen_scured_vip.secd_vip.jtag_secd_wait_eoc(); + end default: begin + $fatal(1, "Unsupported boot mode %d (reserved)!", secd_boot_mode); + end + endcase + end + end + end - // set bootmode - fix.secd_vip.set_secd_boot_mode(secd_boot_mode); + // pulp cluster standalone + if (CarfieldIslandsCfg.pulp.enable) begin: gen_pulp_tb + // Useful register addresses + localparam int unsigned CarL2StartAddr = 32'h7800_0000; + localparam int unsigned CarDramStartAddr = 32'h8000_0000; + localparam int unsigned PulpdNumCores = 12; + localparam int unsigned PulpdBootAddrL2 = CarL2StartAddr + 32'h8080; + localparam int unsigned PulpdBootAddrDram = CarDramStartAddr + 32'h8080; + localparam int unsigned PulpdBootAddr = 32'h50200040; + localparam int unsigned PulpdRetAddr = 32'h50200100; + localparam int unsigned CarSocCtrlPulpdClkEnRegAddr = 32'h20010078; + localparam int unsigned CarSocCtrlPulpdIsolateRegAddr = 32'h20010048; + localparam int unsigned CarSocCtrlPulpdIsolateStatusRegAddr = 32'h20010060; + localparam int unsigned CarSocCtrlPulpdFetchEnAddr = 32'h200100c0; + localparam int unsigned CarSocCtrlPulpdBootEnAddr = 32'h200100dc; + localparam int unsigned CarSocCtrlPulpdBusyAddr = 32'h200100e4; + localparam int unsigned CarSocCtrlPulpdEocAddr = 32'h200100e8; + // sim variables + string pulpd_preload_elf; + logic [1:0] pulpd_boot_mode; + bit [31:0] pulpd_exit_code; + bit [31:0] pulpd_ret_val; + doub_bt pulpd_binary_entry; + doub_bt pulpd_reg_value; + + initial begin + // Fetch plusargs or use safe (fail-fast) defaults + if (!$value$plusargs("PULPD_BOOTMODE=%d", pulpd_boot_mode)) pulpd_boot_mode = 0; + if (!$value$plusargs("PULPD_BINARY=%s", pulpd_preload_elf)) pulpd_preload_elf = ""; + if (!$value$plusargs("HYP_USER_PRELOAD=%s", hyp_user_preload)) hyp_user_preload = 0; - if (secd_preload_elf != "" || secd_flash_vmem != "") begin // Wait for reset fix.chs_vip.wait_for_reset(); - // Writing max burst length in Hyperbus configuration registers to - // prevent the Verification IPs from triggering timing checks. - $display("[TB] INFO: Configuring Hyperbus through serial link."); - fix.chs_vip.slink_write_32(HyperbusTburstMax, 32'd128); + if (pulpd_preload_elf != "") begin - case(secd_boot_mode) - 0: begin - // Wait before security island HW is initialized - repeat(10000) - @(posedge fix.clk); - fix.secd_vip.debug_secd_module_init(); - fix.secd_vip.load_secd_binary(secd_preload_elf); - fix.secd_vip.jtag_secd_data_preload(); - fix.secd_vip.jtag_secd_wakeup(32'hE0000080); - fix.secd_vip.jtag_secd_wait_eoc(); - end 1: begin - fix.secd_vip.spih_norflash_preload(secd_flash_vmem); - repeat(10000) - @(posedge fix.clk); - fix.secd_vip.jtag_secd_wait_eoc(); - end default: begin - $fatal(1, "Unsupported boot mode %d (reserved)!", safed_boot_mode); - end - endcase - end - end + $display("[TB] %t - Enabling PULP cluster clock for stand-alone tests ", $realtime); + // Clock island after PoR + fix.chs_vip.slink_write_32(CarSocCtrlPulpdClkEnRegAddr, 32'h1); + $display("[TB] %t - De-isolate PULP cluster for stand-alone tests ", $realtime); + // De-isolate island after PoR + fix.chs_vip.slink_write_32(CarSocCtrlPulpdIsolateRegAddr, 32'h0); - // pulp cluster standalone - initial begin - // Fetch plusargs or use safe (fail-fast) defaults - if (!$value$plusargs("PULPD_BOOTMODE=%d", pulpd_boot_mode)) pulpd_boot_mode = 0; - if (!$value$plusargs("PULPD_BINARY=%s", pulpd_preload_elf)) pulpd_preload_elf = ""; - if (!$value$plusargs("HYP_USER_PRELOAD=%s", hyp_user_preload)) hyp_user_preload = 0; - - // Wait for reset - fix.chs_vip.wait_for_reset(); - - if (pulpd_preload_elf != "") begin - - $display("[TB] %t - Enabling PULP cluster clock for stand-alone tests ", $realtime); - // Clock island after PoR - fix.chs_vip.slink_write_32(CarSocCtrlPulpdClkEnRegAddr, 32'h1); - $display("[TB] %t - De-isolate PULP cluster for stand-alone tests ", $realtime); - // De-isolate island after PoR - fix.chs_vip.slink_write_32(CarSocCtrlPulpdIsolateRegAddr, 32'h0); - - case (pulpd_boot_mode) - 0: begin - // JTAG - $display("[JTAG PULPD] Init "); - fix.chs_vip.jtag_init(); - $display("[JTAG PULPD] Halt the core and load the binary to L2 "); - fix.chs_vip.jtag_elf_halt_load(pulpd_preload_elf, pulpd_binary_entry ); - - // boot - // Write bootaddress to each core - $display("[JTAG PULPD] Write PULP cluster boot address for each core"); - for (int c = 0; c < PulpdNumCores; c++) begin - fix.chs_vip.jtag_write_reg32(PulpdBootAddr + c*32'h4, PulpdBootAddrL2); + case (pulpd_boot_mode) + 0: begin + // JTAG + $display("[JTAG PULPD] Init "); + fix.chs_vip.jtag_init(); + $display("[JTAG PULPD] Halt the core and load the binary to L2 "); + fix.chs_vip.jtag_elf_halt_load(pulpd_preload_elf, pulpd_binary_entry ); + + // boot + // Write bootaddress to each core + $display("[JTAG PULPD] Write PULP cluster boot address for each core"); + for (int c = 0; c < PulpdNumCores; c++) begin + fix.chs_vip.jtag_write_reg32(PulpdBootAddr + c*32'h4, PulpdBootAddrL2); + end + // Write boot enable + $display("[JTAG PULPD] Write PULP cluster boot enable"); + fix.chs_vip.jtag_write_reg32(CarSocCtrlPulpdBootEnAddr, 32'h1); + // Write fetch enable + $display("[JTAG PULPD] Write PULP cluster fetch enable"); + fix.chs_vip.jtag_write_reg32(CarSocCtrlPulpdFetchEnAddr, 32'h1); + + // Poll memory address for PULP EOC + fix.chs_vip.jtag_poll_bit0(CarSocCtrlPulpdEocAddr, pulpd_exit_code, 20); + fix.slink_read_reg(PulpdRetAddr, pulpd_ret_val, 20); + if (pulpd_ret_val[30:0] != 'h0) $error("[JTAG PULP] FAILED: return code %x", pulpd_ret_val); + else $display("[JTAG PULP] SUCCESS"); end - // Write boot enable - $display("[JTAG PULPD] Write PULP cluster boot enable"); - fix.chs_vip.jtag_write_reg32(CarSocCtrlPulpdBootEnAddr, 32'h1); - // Write fetch enable - $display("[JTAG PULPD] Write PULP cluster fetch enable"); - fix.chs_vip.jtag_write_reg32(CarSocCtrlPulpdFetchEnAddr, 32'h1); - - // Poll memory address for PULP EOC - fix.chs_vip.jtag_poll_bit0(CarSocCtrlPulpdEocAddr, pulpd_exit_code, 20); - fix.slink_read_reg(PulpdRetAddr, pulpd_ret_val, 20); - if (pulpd_ret_val[30:0] != 'h0) $error("[JTAG PULP] FAILED: return code %x", pulpd_ret_val); - else $display("[JTAG PULP] SUCCESS"); - end - 1: begin - // serial link + 1: begin + // serial link - // preload - $display("[SLINK PULPD] Preload the binary to L2 "); - fix.chs_vip.slink_elf_preload(pulpd_preload_elf, pulpd_binary_entry); + // preload + $display("[SLINK PULPD] Preload the binary to L2 "); + fix.chs_vip.slink_elf_preload(pulpd_preload_elf, pulpd_binary_entry); - // boot - // Write bootaddress to each core - $display("[SLINK PULPD] Write PULP cluster boot address for each core"); - for (int c = 0; c < PulpdNumCores; c++) begin - fix.chs_vip.slink_write_32(PulpdBootAddr + c*32'h4, PulpdBootAddrL2); + // boot + // Write bootaddress to each core + $display("[SLINK PULPD] Write PULP cluster boot address for each core"); + for (int c = 0; c < PulpdNumCores; c++) begin + fix.chs_vip.slink_write_32(PulpdBootAddr + c*32'h4, PulpdBootAddrL2); + end + // Write boot enable + $display("[SLINK PULPD] Write PULP cluster boot enable"); + fix.chs_vip.slink_write_32(CarSocCtrlPulpdBootEnAddr, 32'h1); + // Write fetch enable + $display("[SLINK PULPD] Write PULP cluster fetch enable"); + fix.chs_vip.slink_write_32(CarSocCtrlPulpdFetchEnAddr, 32'h1); + + // Poll memory address for PULP EOC + fix.chs_vip.slink_poll_bit0(CarSocCtrlPulpdEocAddr, pulpd_exit_code, 20); + fix.slink_read_reg(PulpdRetAddr, pulpd_ret_val, 20); + if (pulpd_ret_val[30:0] != 'h0) $error("[SLINK PULP] FAILED: return code %x", pulpd_ret_val); + else $display("[SLINK PULP] SUCCESS"); end - // Write boot enable - $display("[SLINK PULPD] Write PULP cluster boot enable"); - fix.chs_vip.slink_write_32(CarSocCtrlPulpdBootEnAddr, 32'h1); - // Write fetch enable - $display("[SLINK PULPD] Write PULP cluster fetch enable"); - fix.chs_vip.slink_write_32(CarSocCtrlPulpdFetchEnAddr, 32'h1); - - // Poll memory address for PULP EOC - fix.chs_vip.slink_poll_bit0(CarSocCtrlPulpdEocAddr, pulpd_exit_code, 20); - fix.slink_read_reg(PulpdRetAddr, pulpd_ret_val, 20); - if (pulpd_ret_val[30:0] != 'h0) $error("[SLINK PULP] FAILED: return code %x", pulpd_ret_val); - else $display("[SLINK PULP] SUCCESS"); - end - default: begin - $fatal(1, "Unsupported boot mode %d (reserved)!", pulpd_boot_mode); - end - endcase - - $finish; - end + default: begin + $fatal(1, "Unsupported boot mode %d (reserved)!", pulpd_boot_mode); + end + endcase - // Fast preload of hyperram - if (hyp_user_preload != 0 && pulpd_preload_elf == "") begin - $warning( "[TB] - Instantly preload hyperram0 and hyperrram1 models at time 0. This preload \ - mode should be used for simulation only, because it does not check whether we can \ - preload the hyperram using physical interfaces, e.g., JTAG or SL. If there is enough \ - confidence physical interfaces are working correctly with a gate-level netlist, this \ - mode could be used to speed up the simulation, but at your own risk. You were \ - warned. \n"); - // Hyperrams models are preloaded at time 0. Preferably, this bootflow is used with cluster - // accelerators, but can be extended to other islands as well. We check the EOC with the JTAG - - $display("[TB] %t - Wait for HyperRAM", $realtime); - repeat(HyperRstCycles) - @(posedge fix.clk); - - $display("[TB] %t - Enabling PULP cluster clock for stand-alone tests ", $realtime); - // Clock island after PoR - fix.chs_vip.slink_write_32(CarSocCtrlPulpdClkEnRegAddr, 32'h1); - $display("[TB] %t - De-isolate PULP cluster for stand-alone tests ", $realtime); - // De-isolate island after PoR - fix.chs_vip.slink_write_32(CarSocCtrlPulpdIsolateRegAddr, 32'h0); - - // Write bootaddress to each core - $display("[SLINK PULPD] Write PULP cluster boot address for each core"); - for (int c = 0; c < PulpdNumCores; c++) begin - fix.chs_vip.slink_write_32(PulpdBootAddr + c*32'h4, PulpdBootAddrDram); + $finish; end - // Write boot enable - $display("[SLINK PULPD] Write PULP cluster boot enable"); - fix.chs_vip.slink_write_32(CarSocCtrlPulpdBootEnAddr, 32'h1); - // Write fetch enable - $display("[SLINK PULPD] Write PULP cluster fetch enable"); - fix.chs_vip.slink_write_32(CarSocCtrlPulpdFetchEnAddr, 32'h1); - - // Poll memory address for PULP EOC - fix.chs_vip.slink_poll_bit0(CarSocCtrlPulpdEocAddr, pulpd_exit_code, 20); - fix.slink_read_reg(PulpdRetAddr, pulpd_ret_val, 20); - if (pulpd_ret_val[30:0] != 'h0) $error("[JTAG PULP] FAILED: return code %x", pulpd_ret_val); - else $display("[SLINK PULP] SUCCESS"); - $finish; + // Fast preload of hyperram + if (hyp_user_preload != 0 && pulpd_preload_elf == "") begin + $warning( "[TB] - Instantly preload hyperram0 and hyperrram1 models at time 0. This preload \ + mode should be used for simulation only, because it does not check whether we can \ + preload the hyperram using physical interfaces, e.g., JTAG or SL. If there is enough \ + confidence physical interfaces are working correctly with a gate-level netlist, this \ + mode could be used to speed up the simulation, but at your own risk. You were \ + warned. \n"); + // Hyperrams models are preloaded at time 0. Preferably, this bootflow is used with cluster + // accelerators, but can be extended to other islands as well. We check the EOC with the JTAG + + $display("[TB] %t - Wait for HyperRAM", $realtime); + repeat(HyperRstCycles) + @(posedge fix.clk); + + $display("[TB] %t - Enabling PULP cluster clock for stand-alone tests ", $realtime); + // Clock island after PoR + fix.chs_vip.slink_write_32(CarSocCtrlPulpdClkEnRegAddr, 32'h1); + $display("[TB] %t - De-isolate PULP cluster for stand-alone tests ", $realtime); + // De-isolate island after PoR + fix.chs_vip.slink_write_32(CarSocCtrlPulpdIsolateRegAddr, 32'h0); + + // Write bootaddress to each core + $display("[SLINK PULPD] Write PULP cluster boot address for each core"); + for (int c = 0; c < PulpdNumCores; c++) begin + fix.chs_vip.slink_write_32(PulpdBootAddr + c*32'h4, PulpdBootAddrDram); + end + // Write boot enable + $display("[SLINK PULPD] Write PULP cluster boot enable"); + fix.chs_vip.slink_write_32(CarSocCtrlPulpdBootEnAddr, 32'h1); + // Write fetch enable + $display("[SLINK PULPD] Write PULP cluster fetch enable"); + fix.chs_vip.slink_write_32(CarSocCtrlPulpdFetchEnAddr, 32'h1); + + // Poll memory address for PULP EOC + fix.chs_vip.slink_poll_bit0(CarSocCtrlPulpdEocAddr, pulpd_exit_code, 20); + fix.slink_read_reg(PulpdRetAddr, pulpd_ret_val, 20); + if (pulpd_ret_val[30:0] != 'h0) $error("[JTAG PULP] FAILED: return code %x", pulpd_ret_val); + else $display("[SLINK PULP] SUCCESS"); + + $finish; + end end end // spatz cluster standalone - initial begin - // Fetch plusargs or use safe (fail-fast) defaults - if (!$value$plusargs("SECURE_BOOT=%d", secure_boot)) secure_boot = 0; - if (!$value$plusargs("SPATZD_BOOTMODE=%d", spatzd_boot_mode)) spatzd_boot_mode = 0; - if (!$value$plusargs("SPATZD_BINARY=%s", spatzd_preload_elf)) spatzd_preload_elf = ""; + if (CarfieldIslandsCfg.spatz.enable) begin: gen_spatz_tb + // spatz cluster + string spatzd_preload_elf; + logic [1:0] spatzd_boot_mode; + bit [31:0] spatzd_exit_code; + doub_bt spatzd_binary_entry; + doub_bt spatzd_reg_value; + + localparam int unsigned SpatzdClkEnRegAddr = 32'h2001007c; + localparam int unsigned SpatzdIsolateRegAddr = 32'h2001004c; + localparam int unsigned SpatzdIsolateStatusRegAddr = 32'h20010064; + + initial begin + // Fetch plusargs or use safe (fail-fast) defaults + if (!$value$plusargs("SECURE_BOOT=%d", secure_boot)) secure_boot = 0; + if (!$value$plusargs("SPATZD_BOOTMODE=%d", spatzd_boot_mode)) spatzd_boot_mode = 0; + if (!$value$plusargs("SPATZD_BINARY=%s", spatzd_preload_elf)) spatzd_preload_elf = ""; + + // set secure boot mode + fix.set_secure_boot(secure_boot); + + if (spatzd_preload_elf != "") begin + + // Wait for reset + fix.chs_vip.wait_for_reset(); + + // Writing max burst length in Hyperbus configuration registers to + // prevent the Verification IPs from triggering timing checks. + $display("[TB] INFO: Configuring Hyperbus through serial link."); + fix.chs_vip.slink_write_32(HyperbusTburstMax, 32'd128); + + $display("[TB] %t - Enabling spatz clock for stand-alone tests ", $realtime); + // Clock island after PoR + fix.chs_vip.slink_write_32(SpatzdClkEnRegAddr, 32'h1); + $display("[TB] %t - De-isolate spatz for stand-alone tests ", $realtime); + // De-isolate island after PoR + fix.chs_vip.slink_write_32(SpatzdIsolateRegAddr, 32'h0); + + case (spatzd_boot_mode) + 0: begin + // JTAG + $display("[JTAG SPATZD] Init "); + fix.chs_vip.jtag_init(); + $display("[JTAG SPATZD] Halt the core and load the binary to L2 "); + fix.chs_vip.jtag_elf_halt_load(spatzd_preload_elf, spatzd_binary_entry ); - // set secure boot mode - fix.set_secure_boot(secure_boot); + // write start address into the csr + $display("[JTAG SPATZD] write the CSR %x of spatz with the entry point %x", spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET, spatzd_binary_entry); + fix.chs_vip.jtag_write_reg(spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET, spatzd_binary_entry ); - if (spatzd_preload_elf != "") begin + // Set interrupt on mailbox mailbox id MBOX_SPATZD_CORE0_ID and MBOX_SPATZD_CORE1_ID + spatzd_reg_value = 64'h1; + $display("[JTAG SPATZD] Set mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE0_ID, CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100)); + fix.chs_vip.jtag_write_reg32(CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100) , spatzd_reg_value); - // Wait for reset - fix.chs_vip.wait_for_reset(); + $display("[JTAG SPATZD] Set mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE1_ID, CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100)); + fix.chs_vip.jtag_write_reg32(CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100) , spatzd_reg_value); - // Writing max burst length in Hyperbus configuration registers to - // prevent the Verification IPs from triggering timing checks. - $display("[TB] INFO: Configuring Hyperbus through serial link."); - fix.chs_vip.slink_write_32(HyperbusTburstMax, 32'd128); + // Enable interrupt on mailbox id MBOX_SPATZ_CORE0_ID and MBOX_SPATZ_CORE1_ID + $display("[JTAG SPATZD] Enable mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE0_ID, CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100) ,spatzd_reg_value); + fix.chs_vip.jtag_write_reg32(CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100) , spatzd_reg_value); - $display("[TB] %t - Enabling spatz clock for stand-alone tests ", $realtime); - // Clock island after PoR - fix.chs_vip.slink_write_32(SpatzdClkEnRegAddr, 32'h1); - $display("[TB] %t - De-isolate spatz for stand-alone tests ", $realtime); - // De-isolate island after PoR - fix.chs_vip.slink_write_32(SpatzdIsolateRegAddr, 32'h0); - - case (spatzd_boot_mode) - 0: begin - // JTAG - $display("[JTAG SPATZD] Init "); - fix.chs_vip.jtag_init(); - $display("[JTAG SPATZD] Halt the core and load the binary to L2 "); - fix.chs_vip.jtag_elf_halt_load(spatzd_preload_elf, spatzd_binary_entry ); - - // write start address into the csr - $display("[JTAG SPATZD] write the CSR %x of spatz with the entry point %x", spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET, spatzd_binary_entry); - fix.chs_vip.jtag_write_reg(spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET, spatzd_binary_entry ); - - // Set interrupt on mailbox mailbox id MBOX_SPATZD_CORE0_ID and MBOX_SPATZD_CORE1_ID - spatzd_reg_value = 64'h1; - $display("[JTAG SPATZD] Set mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE0_ID, CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100)); - fix.chs_vip.jtag_write_reg32(CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100) , spatzd_reg_value); - - $display("[JTAG SPATZD] Set mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE1_ID, CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100)); - fix.chs_vip.jtag_write_reg32(CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100) , spatzd_reg_value); - - // Enable interrupt on mailbox id MBOX_SPATZ_CORE0_ID and MBOX_SPATZ_CORE1_ID - $display("[JTAG SPATZD] Enable mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE0_ID, CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100) ,spatzd_reg_value); - fix.chs_vip.jtag_write_reg32(CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100) , spatzd_reg_value); - - $display("[JTAG SPATZD] Enable mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE1_ID, CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100) ,spatzd_reg_value); - fix.chs_vip.jtag_write_reg32(CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100) , spatzd_reg_value); - - // Poll memory address for Spatz EOC - fix.chs_vip.jtag_poll_bit0(spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET, spatzd_exit_code, 20); - spatzd_exit_code >>= 1; - if (spatzd_exit_code) $error("[JTAG SPATZ] FAILED: return code %0d", spatzd_exit_code); - else $display("[JTAG SPATZD] SUCCESS"); - end + $display("[JTAG SPATZD] Enable mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE1_ID, CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100) ,spatzd_reg_value); + fix.chs_vip.jtag_write_reg32(CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100) , spatzd_reg_value); - 1: begin - // SERIAL LINK - $display("[SLINK SPATZD] Preload the binary to L2 "); - fix.chs_vip.slink_elf_preload(spatzd_preload_elf, spatzd_binary_entry); + // Poll memory address for Spatz EOC + fix.chs_vip.jtag_poll_bit0(spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET, spatzd_exit_code, 20); + spatzd_exit_code >>= 1; + if (spatzd_exit_code) $error("[JTAG SPATZ] FAILED: return code %0d", spatzd_exit_code); + else $display("[JTAG SPATZD] SUCCESS"); + end - // write start address into the csr - $display("[SLINK SPATZD] Write the CSR %x of spatz with the entry point %x", spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET, spatzd_binary_entry); - fix.chs_vip.slink_write_32(spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET, spatzd_binary_entry); + 1: begin + // SERIAL LINK + $display("[SLINK SPATZD] Preload the binary to L2 "); + fix.chs_vip.slink_elf_preload(spatzd_preload_elf, spatzd_binary_entry); - // Set interrupt on mailbox ids MBOX_SPATZ_CORE0_ID and MBOX_SPATZ_CORE1_ID - spatzd_reg_value = 64'h1; - $display("[SLINK SPATZD] Set mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE0_ID, CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100)); - fix.chs_vip.slink_write_32(CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100) , spatzd_reg_value); + // write start address into the csr + $display("[SLINK SPATZD] Write the CSR %x of spatz with the entry point %x", spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET, spatzd_binary_entry); + fix.chs_vip.slink_write_32(spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET, spatzd_binary_entry); - $display("[SLINK SPATZD] Set mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE0_ID, CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100)); - fix.chs_vip.slink_write_32(CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100) , spatzd_reg_value); + // Set interrupt on mailbox ids MBOX_SPATZ_CORE0_ID and MBOX_SPATZ_CORE1_ID + spatzd_reg_value = 64'h1; + $display("[SLINK SPATZD] Set mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE0_ID, CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100)); + fix.chs_vip.slink_write_32(CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100) , spatzd_reg_value); - // Enable interrupt on mailbox ids MBOX_SPATZ_CORE0_ID and MBOX_SPATZ_CORE1_ID - $display("[SLINK SPATZD] Enable mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE0_ID, CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100) ,spatzd_reg_value); - fix.chs_vip.slink_write_32(CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100) , spatzd_reg_value); + $display("[SLINK SPATZD] Set mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE0_ID, CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100)); + fix.chs_vip.slink_write_32(CAR_MBOX_BASE + MBOX_INT_SND_SET_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100) , spatzd_reg_value); - $display("[SLINK SPATZD] Enable mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE0_ID, CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100) ,spatzd_reg_value); - fix.chs_vip.slink_write_32(CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100) , spatzd_reg_value); + // Enable interrupt on mailbox ids MBOX_SPATZ_CORE0_ID and MBOX_SPATZ_CORE1_ID + $display("[SLINK SPATZD] Enable mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE0_ID, CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100) ,spatzd_reg_value); + fix.chs_vip.slink_write_32(CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE0_ID*32'h100) , spatzd_reg_value); - // Poll memory address for Spatz EOC - fix.chs_vip.slink_poll_bit0(spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET, spatzd_exit_code, 20); - spatzd_exit_code >>= 1; - if (spatzd_exit_code) $error("[SLINK SPATZ] FAILED: return code %0d", spatzd_exit_code); - else $display("[SLINK SPATZ] SUCCESS"); - end + $display("[SLINK SPATZD] Enable mailbox interrupt ID %x at %x ",MBOX_SPATZ_CORE0_ID, CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100) ,spatzd_reg_value); + fix.chs_vip.slink_write_32(CAR_MBOX_BASE + MBOX_INT_SND_EN_OFFSET + (MBOX_SPATZ_CORE1_ID*32'h100) , spatzd_reg_value); - default: begin - $fatal(1, "Unsupported boot mode %d (reserved)!", spatzd_boot_mode); - end - endcase + // Poll memory address for Spatz EOC + fix.chs_vip.slink_poll_bit0(spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET, spatzd_exit_code, 20); + spatzd_exit_code >>= 1; + if (spatzd_exit_code) $error("[SLINK SPATZ] FAILED: return code %0d", spatzd_exit_code); + else $display("[SLINK SPATZ] SUCCESS"); + end - $finish; + default: begin + $fatal(1, "Unsupported boot mode %d (reserved)!", spatzd_boot_mode); + end + endcase + + $finish; + end end end diff --git a/target/xilinx/constraints/carfield.xdc b/target/xilinx/constraints/carfield.xdc new file mode 100644 index 00000000..6b05a217 --- /dev/null +++ b/target/xilinx/constraints/carfield.xdc @@ -0,0 +1,87 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set SOC_TCK 20 + +#################### +# Clock generators # +#################### + +# Do not optimize anything in +set_property DONT_TOUCH TRUE [get_cells gen_domain_clock_mux[*].i_clk_mux] + +# TODO Check this +set_false_path -from [get_pins gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].clock_has_been_disabled_q_reg[*]/C] -to [get_pins gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].clock_has_been_disabled_q_reg[*]/D] +set_false_path -from [get_pins gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].clock_has_been_disabled_q_reg[*]/C] -to [get_pins gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].glitch_filter_q_reg[*][*]/D] + +# Enable all clocks (clk_en register) +set_property DONT_TOUCH TRUE [get_cells i_carfield_reg_top/u_*_clk_sel] +set_property DONT_TOUCH TRUE [get_cells i_carfield_reg_top/u_*_clk_en] +set_case_analysis 1 [get_pins {i_carfield_reg_top/u_*_clk_en/q_reg[0]/Q}] + +########## +# BUFG # +########## + +# tc_clk_mux2 are used for reset signals too, this makes Vivado flag them as clock trees and wasted precious routing ressources +set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]] +set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux +set_property CLOCK_BUFFER_TYPE NONE $all_in_mux + +#################### +# Reset Generators # +#################### + +# No max delay on sw reset since clock can be gated anyways +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {ORIG_REF_NAME=="rstgen" || REF_NAME=="rstgen"}] +set_false_path -through [get_pins -of_objects [get_cells -hier i_carfield_rstgen] -filter {DIRECTION==OUT}] +set_false_path -hold -through [get_pins -filter {DIRECTION==OUT} -of_objects [get_cells -hier -filter {REF_NAME == rstgen || ORIG_REF_NAME == rstgen}]] +set_false_path -setup -hold -from [get_pins -of_objects [get_cells -hier -filter {NAME=~*i_carfield_reg_top/u_*_rst/*}] -filter {IS_CLOCK}] -to [get_clocks *domain_clk] + +# Go large on the isolation +set_max_delay -through [get_nets *isolat*] $SOC_TCK + +# Host pwr_on_reset is resynch by the domains +set_max_delay -datapath -from [get_pins i_host_rstgen/i_rstgen_bypass/synch_regs_q_reg[3]/C] -through [get_pins -of_object [get_cells -hier -filter {REF_NAME==clk_mux_glitch_free || ORIG_REF_NAME==clk_mux_glitch_free}] -filter { NAME =~*async* }] $SOC_TCK + +################# +# Carfield CDCs # +################# + +# Note : +# For the 2 phases CDC we use max_delay and hold path as we grab everything grossly +# On the AXI CDC as we precisely select the Clk-to-Q path we use a unique set_max_delay -datapath +# All the delays are assumed to be SOC_TCK (host domain) + +# Hold and max delay on 2 phases and 2 phases clearable +set_max_delay -through [get_nets -filter {NAME=~"*async*"} -of_objects [get_cells -hier -filter {REF_NAME =~ cdc_2phase_src* || ORIG_REF_NAME =~ cdc_2phase_src*}]] $SOC_TCK +set_false_path -hold -through [get_nets -filter {NAME=~"*async*"} -of_objects [get_cells -hier -filter {REF_NAME =~ cdc_2phase_src* || ORIG_REF_NAME =~ cdc_2phase_src*}]] + +# Hold and max delay on 4 phases +set_max_delay -through [get_nets -filter {NAME=~"*async*"} -of_objects [get_cells -hier -filter {REF_NAME == cdc_4phase_src || ORIG_REF_NAME == cdc_4phase_src}]] $SOC_TCK +set_false_path -hold -through [get_nets -filter {NAME=~"*async*"} -of_objects [get_cells -hier -filter {REF_NAME == cdc_4phase_src || ORIG_REF_NAME == cdc_4phase_src}]] + +# Hold and max delay on synchronizers +set all_sync_cells [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}] +set_property KEEP_HIERARCHY SOFT $all_sync_cells +set_false_path -hold -through [get_pins -of_objects $all_sync_cells -filter {REF_PIN_NAME=~serial_i}] +set_max_delay -through [get_pins -of_objects $all_sync_cells -filter {REF_PIN_NAME=~serial_i}] $SOC_TCK + +# Hold and max delay on pulp synchronizers +set all_pulp_sync_cells [get_cells -hier -filter {ORIG_REF_NAME=="pulp_sync" || REF_NAME=="pulp_sync"}] +set_property KEEP_HIERARCHY SOFT $all_pulp_sync_cells +set_false_path -hold -through [get_pins -of_objects $all_pulp_sync_cells -filter {REF_PIN_NAME=~serial_i}] +set_max_delay -through [get_pins -of_objects $all_pulp_sync_cells -filter {REF_PIN_NAME=~serial_i}] $SOC_TCK + +# Hold and max delay on OT synchronizers +set all_ot_sync_cells [get_cells -hier -filter {ORIG_REF_NAME=="prim_ot_flop_2sync" || REF_NAME=="prim_ot_flop_2sync"}] +set_property KEEP_HIERARCHY SOFT $all_ot_sync_cells +set_false_path -hold -through [get_pins -of_objects $all_ot_sync_cells -filter {REF_PIN_NAME=~d_i*}] +set_max_delay -through [get_pins -of_objects $all_ot_sync_cells -filter {REF_PIN_NAME=~d_i*}] $SOC_TCK + +set all_edge_propagator_ack [get_cells -hier -filter {ORIG_REF_NAME=="edge_propagator_ack" || REF_NAME=="edge_propagator_ack"}] +set_property KEEP_HIERARCHY SOFT $all_edge_propagator_ack +set_false_path -through [get_nets -filter {NAME=~*sync_b} -of_object [get_cells -hier -filter {ORIG_REF_NAME==pulp_sync_wedge || REF_NAME==pulp_sync_wedge}]] diff --git a/target/xilinx/constraints/carfield_islands.tcl b/target/xilinx/constraints/carfield_islands.tcl new file mode 100644 index 00000000..d83028fb --- /dev/null +++ b/target/xilinx/constraints/carfield_islands.tcl @@ -0,0 +1,108 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +#################### +# Clock generators # +#################### + +set SOC_TCK 20 + +## Generate a clock based on the default clk_sel value for a clock mux +## @param clk_sel_path path to the clk_sel register +## @param clk_sel_val default clk_sel value +proc handle_domain_clock_mux { clk_sel_path clk_sel_val clk_name } { + upvar SOC_TCK SOC_TCK + # Start from a known clk_sel register and get fanout to find the clk_mux + set domain_clk_mux [lindex [regexp -inline {[^ ]*gen_domain_clock_mux\[[0-9]*\]} [filter [all_fanout -flat [get_pins $clk_sel_path/q[*]]] -filter {NAME=~*gen_domain_clock_mux*}]] 0] + # This domain_clk_mux not be here if the island is not activated + if { $domain_clk_mux != "" } { + # Create a unique generated clock to avoid fake clock path across the mux + create_generated_clock -source [get_pins $domain_clk_mux.i_clk_mux/clks_i[$clk_sel_val]] -divide_by 1 -name $clk_name [get_pins $domain_clk_mux.i_clk_mux/clk_o] + set_case_analysis [expr $clk_sel_val >> 0 & 1] [get_pins $clk_sel_path/q[0]] + set_case_analysis [expr $clk_sel_val >> 1 & 1] [get_pins $clk_sel_path/q[1]] + # Add max_delay 0 to spot missing CDCs + set_max_delay 0 -from [get_clocks -filter "NAME != $clk_name"] -to [get_clocks $clk_name] + set_max_delay 0 -from [get_clocks $clk_name] -to [get_clocks -filter "NAME != $clk_name"] + puts "Generated domain clock $clk_name" + } +} + +handle_domain_clock_mux [get_cells -hier u_periph_clk_sel] 2 periph_domain_clk +handle_domain_clock_mux [get_cells -hier u_safety_island_clk_sel] 1 safety_domain_clk +handle_domain_clock_mux [get_cells -hier u_security_island_clk_sel] 1 security_domain_clk +handle_domain_clock_mux [get_cells -hier u_pulp_cluster_clk_sel] 1 pulp_domain_clk +handle_domain_clock_mux [get_cells -hier u_spatz_cluster_clk_sel] 1 spatz_domain_clk +handle_domain_clock_mux [get_cells -hier u_l2_clk_sel] 0 l2_domain_clk + +################# +# Carfield CDCs # +################# + +# Safety Island +################ + +proc handle_slv_cdc { slv_cdc_path } { + upvar SOC_TCK SOC_TCK + # Start from a known slv cdc_dst and get fanout to find the mst cdc_src + set mst_cdc_path [lindex [regexp -inline {.*gen_ext_slv_src_cdc\[[0-9]*\]} [lindex [filter [all_fanout -flat [get_pins $slv_cdc_path/*rptr*]] -filter {NAME =~ *gen_ext_slv_src_cdc*}] 0]] 0] + if { $mst_cdc_path != "" } { + set_max_delay -datapath \ + -from [get_pins $mst_cdc_path.i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins $slv_cdc_path/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ + "$SOC_TCK" + set_max_delay -datapath \ + -from [get_pins $slv_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins $mst_cdc_path.i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ + "$SOC_TCK" + set_max_delay -datapath \ + -from [get_pins $mst_cdc_path.i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins $slv_cdc_path/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ + "$SOC_TCK" + set_max_delay -datapath \ + -from [get_pins $slv_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins $mst_cdc_path.i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ + "$SOC_TCK" + } + +} + +handle_slv_cdc [get_cells -hier gen_periph.i_cdc_dst_peripherals] +handle_slv_cdc [get_cells -hier gen_ethernet.i_ethernet_cdc_dst] +handle_slv_cdc [get_cells -hier gen_l2.i_reconfigurable_l2]/gen_cdc_fifos[1].i_dst_cdc +handle_slv_cdc [get_cells -hier gen_safety_island.i_safety_island_wrap]/i_cdc_in +handle_slv_cdc [get_cells -hier gen_spatz_cluster.i_fp_cluster_wrapper]/i_spatz_cluster_cdc_dst +handle_slv_cdc [get_cells -hier gen_pulp_cluster.i_integer_cluster]/axi_slave_cdc_i +handle_slv_cdc [get_cells -hier gen_l2.i_reconfigurable_l2]/gen_cdc_fifos[0].i_dst_cdc + +proc handle_mst_cdc { mst_cdc_path } { + upvar SOC_TCK SOC_TCK + # Get the dst_cdc in cheshire + set slv_cdc_path [lindex [regexp -inline {.*gen_ext_mst_dst_cdc\[[0-9]*\]} [lindex [filter [all_fanout -flat [get_pins $mst_cdc_path/*wptr*]] -filter {NAME =~ *gen_ext_mst_dst_cdc*}] 0]] 0] + if { $slv_cdc_path != "" } { + # From Safety Island master + set_max_delay -datapath \ + -from [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins $slv_cdc_path.i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ + "$SOC_TCK" + set_max_delay -datapath \ + -from [get_pins $slv_cdc_path.i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ + "$SOC_TCK" + set_max_delay -datapath \ + -from [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins $slv_cdc_path.i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ + "$SOC_TCK" + set_max_delay -datapath \ + -from [get_pins $slv_cdc_path.i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ + "$SOC_TCK" + } + +} + +handle_mst_cdc [get_cells -hier gen_safety_island.i_safety_island_wrap]/i_cdc_out +handle_mst_cdc [get_cells -hier gen_spatz_cluster.i_fp_cluster_wrapper]/i_spatz_cluster_cdc_src +handle_mst_cdc [get_cells -hier gen_pulp_cluster.i_integer_cluster]/axi_master_cdc_i diff --git a/target/xilinx/flavor_bd/flavor_bd.mk b/target/xilinx/flavor_bd/flavor_bd.mk index 08a6fe82..4a21fc3b 100644 --- a/target/xilinx/flavor_bd/flavor_bd.mk +++ b/target/xilinx/flavor_bd/flavor_bd.mk @@ -34,16 +34,19 @@ xilinx_defs_bd := $(common_defs) $(xilinx_defs_common) # Add includes files for block design $(CAR_XIL_DIR)/flavor_bd/scripts/add_includes.tcl: - ${BENDER} script vivado --only-defines --only-includes $(xilinx_targs_bd) $(xilinx_defs_bd) > $@ + ${BENDER} script vivado --only-defines --only-includes $(xilinx_targs_bd) $(xilinx_defs_bd) > $@.bak # Remove ibex's vendored prim includes as they conflict with opentitan's vendored prim includes - grep -v -P "lowrisc_ip/ip/prim/rtl" $@ > $@-tmp - mv $@-tmp $@ + grep -v -P "lowrisc_ip/ip/prim/rtl" $@.bak > $@ + # Override system verilog files + $(CAR_XIL_DIR)/scripts/overrides.sh $@ + echo "" >> $@ # Build block design bitstream $(CAR_XIL_DIR)/flavor_bd/out/%.bit: $(xilinx_ips_paths_bd) $(CAR_XIL_DIR)/flavor_bd/scripts/add_includes.tcl mkdir -p $(CAR_XIL_DIR)/flavor_bd/out cd $(CAR_XIL_DIR)/flavor_bd && $(vivado_env_bd) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run.tcl find $(CAR_XIL_DIR)/flavor_bd -name "*.ltx" -o -name "*.bit" -o -name "*routed.rpt" | xargs -I {} cp {} $(CAR_XIL_DIR)/flavor_bd/out +.PRECIOUS: $(CAR_XIL_DIR)/flavor_bd/out/%.bit car-xil-clean-bd: cd $(CAR_XIL_DIR)/flavor_bd && rm -rf scripts/add_includes.tcl* *.log *.jou *.str *.mif carfield_$(XILINX_BOARD) .Xil/ diff --git a/target/xilinx/flavor_bd/scripts/run.tcl b/target/xilinx/flavor_bd/scripts/run.tcl index a410bd12..9a529a06 100644 --- a/target/xilinx/flavor_bd/scripts/run.tcl +++ b/target/xilinx/flavor_bd/scripts/run.tcl @@ -18,8 +18,9 @@ set_param general.maxThreads 8 set_property ip_repo_paths ../xilinx_ips/carfield_ip [current_project] update_ip_catalog -# Define sources +# Add params to runs import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD).xdc +import_files -fileset constrs_1 -norecurse ../constraints/carfield_islands.tcl source scripts/add_includes.tcl # Build block design @@ -46,6 +47,9 @@ generate_target all [get_files *design_1.bd] export_ip_user_files -of_objects [get_files *design_1.bd] -no_script create_ip_run [get_files *design_1.bd] +# Make sure carfield.xdc (imported from IP) executes after carfield_islands.tcl (that generates the clocks) +set_property processing_order LATE [get_files carfield.xdc] + # Start OOC synthesis of changed IPs set synth_runs [get_runs *synth*] # Exclude the whole design (synth_1) and the carfield IP (bug) @@ -122,6 +126,7 @@ if ($DEBUG) { } # Need to save save constraints before implementing the core set_property target_constrs_file [get_files $::env(XILINX_BOARD).xdc] [current_fileset -constrset] + save_constraints -force implement_debug_core write_debug_probes -force probes.ltx diff --git a/target/xilinx/flavor_vanilla/.gitignore b/target/xilinx/flavor_vanilla/.gitignore index 5efa3060..f34690f0 100644 --- a/target/xilinx/flavor_vanilla/.gitignore +++ b/target/xilinx/flavor_vanilla/.gitignore @@ -1,5 +1,9 @@ .Xil -carfield.* +carfield.cache +carfield.ip_user_files +carfield.hw +carfield.sim +carfield.srcs scripts/add_sources.tcl* scripts/add_includes.tcl out/ diff --git a/target/xilinx/flavor_vanilla/constraints/carfield.xdc b/target/xilinx/flavor_vanilla/constraints/carfield.xdc deleted file mode 100644 index e01b35e5..00000000 --- a/target/xilinx/flavor_vanilla/constraints/carfield.xdc +++ /dev/null @@ -1,456 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# Cyril Koenig - - -################### -# Global Settings # -################### - -# The output of the reset synchronizer -set SOC_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets rst_n]] - -##################### -# Timing Parameters # -##################### - -# 10 MHz (max) JTAG clock -set JTAG_TCK 100.0 - -# UART speed is at most 5 Mb/s -set UART_IO_SPEED 200.0 - -# Host on clk_50 -set SOC_TCK 20 - -########## -# Clocks # -########## - -# Rtc clock is asynchronous -create_generated_clock -source [get_pins i_xlnx_clk_wiz/inst/mmcme4_adv_inst/CLKOUT3] -divide_by 10 -name rtc_clk [get_pins rtc_clk_q_reg/Q] -set_clock_groups -asynchronous -group {rtc_clk} -set_max_delay -from [get_pin rtc_clk_q_reg/Q] $SOC_TCK - -# System Clock -# [see in board.xdc] - -# JTAG Clock -create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i] -set_input_jitter clk_jtag 1.000 -set_clock_groups -name jtag_grp -asynchronous -group {clk_jtag} - - -#################### -# Clock generators # -#################### - -# Do not optimize anything in them -set_property DONT_TOUCH TRUE [get_cells i_carfield/gen_domain_clock_mux[*].i_clk_mux] - -# TODO Check this -set_false_path -from [get_pins i_carfield/gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].clock_has_been_disabled_q_reg[*]/C] -to [get_pins i_carfield/gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].clock_has_been_disabled_q_reg[*]/D] -set_false_path -from [get_pins i_carfield/gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].clock_has_been_disabled_q_reg[*]/C] -to [get_pins i_carfield/gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].glitch_filter_q_reg[*][*]/D] - -# Periph domain -create_generated_clock -source [get_pins i_carfield/gen_domain_clock_mux[0].i_clk_mux/clks_i[2]] -divide_by 1 -name periph_domain_clk [get_pins i_carfield/gen_domain_clock_mux[0].i_clk_mux/clk_o] -set_case_analysis 0 [get_pins {i_carfield/i_carfield_reg_top/u_periph_clk_sel/q_reg[0]/Q}] -set_case_analysis 1 [get_pins {i_carfield/i_carfield_reg_top/u_periph_clk_sel/q_reg[1]/Q}] -set_case_analysis 1 [get_pins {i_carfield/i_carfield_reg_top/u_periph_clk_en/q_reg[0]/Q}] - -# Safety domain -create_generated_clock -source [get_pins i_carfield/gen_domain_clock_mux[1].i_clk_mux/clks_i[1]] -divide_by 1 -name safety_domain_clk [get_pins i_carfield/gen_domain_clock_mux[1].i_clk_mux/clk_o] -set_case_analysis 1 [get_pins {i_carfield/i_carfield_reg_top/u_safety_island_clk_sel/q_reg[0]/Q}] -set_case_analysis 0 [get_pins {i_carfield/i_carfield_reg_top/u_safety_island_clk_sel/q_reg[1]/Q}] -set_case_analysis 1 [get_pins {i_carfield/i_carfield_reg_top/u_safety_island_clk_en/q_reg[0]/Q}] - -# Security domain -create_generated_clock -source [get_pins i_carfield/gen_domain_clock_mux[2].i_clk_mux/clks_i[1]] -divide_by 1 -name security_domain_clk [get_pins i_carfield/gen_domain_clock_mux[2].i_clk_mux/clk_o] -set_case_analysis 1 [get_pins {i_carfield/i_carfield_reg_top/u_security_island_clk_sel/q_reg[0]/Q}] -set_case_analysis 0 [get_pins {i_carfield/i_carfield_reg_top/u_security_island_clk_sel/q_reg[1]/Q}] -set_case_analysis 1 [get_pins {i_carfield/i_carfield_reg_top/u_security_island_clk_en/q_reg[0]/Q}] - -# Pulp domain -create_generated_clock -source [get_pins i_carfield/gen_domain_clock_mux[3].i_clk_mux/clks_i[1]] -divide_by 1 -name pulp_domain_clk [get_pins i_carfield/gen_domain_clock_mux[3].i_clk_mux/clk_o] -set_case_analysis 1 [get_pins {i_carfield/i_carfield_reg_top/u_pulp_cluster_clk_sel/q_reg[0]/Q}] -set_case_analysis 0 [get_pins {i_carfield/i_carfield_reg_top/u_pulp_cluster_clk_sel/q_reg[1]/Q}] -set_case_analysis 1 [get_pins {i_carfield/i_carfield_reg_top/u_pulp_cluster_clk_en/q_reg[0]/Q}] - -# Spatz domain -create_generated_clock -source [get_pins i_carfield/gen_domain_clock_mux[4].i_clk_mux/clks_i[1]] -divide_by 1 -name spatz_domain_clk [get_pins i_carfield/gen_domain_clock_mux[4].i_clk_mux/clk_o] -set_case_analysis 1 [get_pins {i_carfield/i_carfield_reg_top/u_spatz_cluster_clk_sel/q_reg[0]/Q}] -set_case_analysis 0 [get_pins {i_carfield/i_carfield_reg_top/u_spatz_cluster_clk_sel/q_reg[1]/Q}] -set_case_analysis 1 [get_pins {i_carfield/i_carfield_reg_top/u_spatz_cluster_clk_en/q_reg[0]/Q}] - -# L2 Domain -create_generated_clock -source [get_pins i_carfield/gen_domain_clock_mux[5].i_clk_mux/clks_i[0]] -divide_by 1 -name l2_domain_clk [get_pins i_carfield/gen_domain_clock_mux[5].i_clk_mux/clk_o] -set_case_analysis 0 [get_pins {i_carfield/i_carfield_reg_top/u_l2_clk_sel/q_reg[0]/Q}] -set_case_analysis 0 [get_pins {i_carfield/i_carfield_reg_top/u_l2_clk_sel/q_reg[1]/Q}] -set_case_analysis 1 [get_pins {i_carfield/i_carfield_reg_top/u_l2_clk_en/q_reg[0]/Q}] - -########## -# BUFG # -########## - -# JTAG are on non clock capable GPIOs (if not using BSCANE) -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]] -set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]] - -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports cpu_reset]] -set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports cpu_reset]] - -set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]] -set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux -set_property CLOCK_BUFFER_TYPE NONE $all_in_mux - -######## -# JTAG # -######## - -set_input_delay -min -clock clk_jtag [expr 0.10 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}] -set_input_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}] - -set_output_delay -min -clock clk_jtag [expr 0.10 * $JTAG_TCK] [get_ports jtag_tdo_o] -set_output_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports jtag_tdo_o] - -set_max_delay -from [get_ports jtag_trst_ni] $JTAG_TCK -set_false_path -hold -from [get_ports jtag_trst_ni] - -######## -# UART # -######## - -set_max_delay [expr $UART_IO_SPEED * 0.35] -from [get_ports uart_rx_i] -set_false_path -hold -from [get_ports uart_rx_i] - -set_max_delay [expr $UART_IO_SPEED * 0.35] -to [get_ports uart_tx_o] -set_false_path -hold -to [get_ports uart_tx_o] - -################# -# Carfield CDCs # -################# - -# Note : -# For the 2 phases CDC we use max_delay and hold path as we grab everything grossly -# On the AXI CDC as we precisely select the Clk-to-Q path we use a unique set_max_delay -datapath -# All the delays are assumed to be SOC_TCK (host domain) - -# Hold and max delay on 2 phases and 2 phases clearable -set_max_delay -through [get_nets -filter {NAME=~"*async*"} -of_objects [get_cells -hier -filter {REF_NAME =~ cdc_2phase_src* || ORIG_REF_NAME =~ cdc_2phase_src*}]] $SOC_TCK -set_false_path -hold -through [get_nets -filter {NAME=~"*async*"} -of_objects [get_cells -hier -filter {REF_NAME =~ cdc_2phase_src* || ORIG_REF_NAME =~ cdc_2phase_src*}]] - -# Hold and max delay on 4 phases -set_max_delay -through [get_nets -filter {NAME=~"*async*"} -of_objects [get_cells -hier -filter {REF_NAME == cdc_4phase_src || ORIG_REF_NAME == cdc_4phase_src}]] $SOC_TCK -set_false_path -hold -through [get_nets -filter {NAME=~"*async*"} -of_objects [get_cells -hier -filter {REF_NAME == cdc_4phase_src || ORIG_REF_NAME == cdc_4phase_src}]] - -# Hold and max delay on synchronizers -set all_sync_cells [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}] -set_property KEEP_HIERARCHY SOFT $all_sync_cells -set_false_path -hold -through [get_pins -of_objects $all_sync_cells -filter {REF_PIN_NAME=~serial_i}] -set_max_delay -through [get_pins -of_objects $all_sync_cells -filter {REF_PIN_NAME=~serial_i}] $SOC_TCK - -# Hold and max delay on pulp synchronizers -set all_pulp_sync_cells [get_cells -hier -filter {ORIG_REF_NAME=="pulp_sync" || REF_NAME=="pulp_sync"}] -set_property KEEP_HIERARCHY SOFT $all_pulp_sync_cells -set_false_path -hold -through [get_pins -of_objects $all_pulp_sync_cells -filter {REF_PIN_NAME=~serial_i}] -set_max_delay -through [get_pins -of_objects $all_pulp_sync_cells -filter {REF_PIN_NAME=~serial_i}] $SOC_TCK - -# Hold and max delay on OT synchronizers -set all_ot_sync_cells [get_cells -hier -filter {ORIG_REF_NAME=="prim_ot_flop_2sync" || REF_NAME=="prim_ot_flop_2sync"}] -set_property KEEP_HIERARCHY SOFT $all_ot_sync_cells -set_false_path -hold -through [get_pins -of_objects $all_ot_sync_cells -filter {REF_PIN_NAME=~d_i*}] -set_max_delay -through [get_pins -of_objects $all_ot_sync_cells -filter {REF_PIN_NAME=~d_i*}] $SOC_TCK - -set all_edge_propagator_ack [get_cells -hier -filter {ORIG_REF_NAME=="edge_propagator_ack" || REF_NAME=="edge_propagator_ack"}] -set_property KEEP_HIERARCHY SOFT $all_edge_propagator_ack -set_false_path -through [get_nets -filter {NAME=~*sync_b} -of_object [get_cells -hier -filter {ORIG_REF_NAME==pulp_sync_wedge || REF_NAME==pulp_sync_wedge}]] - -# Peripherals -############## - -# i_carfield/i_cdc_dst_peripherals -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cdc_dst_peripherals/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[4].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[4].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cdc_dst_peripherals/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cdc_dst_peripherals/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[4].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[4].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cdc_dst_peripherals/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# Safety Island -################ - -# To Safety Island error slave -# i_carfield/gen_no_safety_island.i_safety_island_axi_err/i_cdc_in -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_no_safety_island.i_safety_island_axi_err/i_cdc_in/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_no_safety_island.i_safety_island_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_no_safety_island.i_safety_island_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_no_safety_island.i_safety_island_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# To Safety Island slave -# i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_in -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_in/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_in/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# From Safety Island master -# i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[0].i_cheshire_ext_mst_cdc_dst -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_out/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[0].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[0].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_out/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_out/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[0].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[0].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_out/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# Pulp Cluster -################ - -# To Pulp cluster error slave -# i_carfield/gen_no_pulp_cluster.i_pulp_cluster_axi_err/i_cdc_in -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_no_pulp_cluster.i_pulp_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_no_pulp_cluster.i_pulp_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_no_pulp_cluster.i_pulp_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_no_pulp_cluster.i_pulp_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# To Pulp cluster slave -# i_carfield/gen_pulp_cluster.i_integer_cluster/axi_slave_cdc_i -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_pulp_cluster.i_integer_cluster/axi_slave_cdc_i/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_pulp_cluster.i_integer_cluster/axi_slave_cdc_i/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_pulp_cluster.i_integer_cluster/axi_slave_cdc_i/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_pulp_cluster.i_integer_cluster/axi_slave_cdc_i/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# From Pulp cluster master -# i_carfield/i_cheshire_wrap/i_intcluster_mst_cdc -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_pulp_cluster.i_integer_cluster/axi_master_cdc_i/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/i_intcluster_mst_cdc/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/i_intcluster_mst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_pulp_cluster.i_integer_cluster/axi_master_cdc_i/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_pulp_cluster.i_integer_cluster/axi_master_cdc_i/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/i_intcluster_mst_cdc/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/i_intcluster_mst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_pulp_cluster.i_integer_cluster/axi_master_cdc_i/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# Spatz cluster -############### - -# To Spatz cluster error slave -# i_carfield/gen_no_spatz_cluster.i_spatz_cluster_axi_err/i_cdc_in -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_no_spatz_cluster.i_spatz_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_no_spatz_cluster.i_spatz_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_no_spatz_cluster.i_spatz_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_no_spatz_cluster.i_spatz_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# To Spatz cluster slave -# i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_dst -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_dst/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_dst/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# From Spatz cluster master -# i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[2].i_cheshire_ext_mst_cdc_dst -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[2].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[2].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[2].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[2].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# Reconfigurable L2 -################### - -# i_carfield/i_reconfigurable_l2/gen_cdc_fifos[0].i_dst_cdc -set_max_delay -datapath \ - -from [get_pins i_carfield/i_reconfigurable_l2/gen_cdc_fifos[0].i_dst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[0].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D -] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[0].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_reconfigurable_l2/gen_cdc_fifos[0].i_dst_cdc/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_reconfigurable_l2/gen_cdc_fifos[0].i_dst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[0].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[0].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_reconfigurable_l2/gen_cdc_fifos[0].i_dst_cdc/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc -set_max_delay -datapath \ - -from [get_pins i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc -set_max_delay -datapath \ - -from [get_pins i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -#i_hyper_cdc_dst -set_max_delay -datapath \ - -from [get_pins i_hyper_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_hyper_cdc_dst/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_hyper_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_hyper_cdc_dst/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -#################### -# Reset Generators # -#################### - -set_max_delay -from $SOC_RST_SRC $SOC_TCK -set_false_path -hold -from $SOC_RST_SRC -# No max delay on sw reset since clock can be gated anyways -set_false_path -through [get_pins -of_objects [get_cells i_carfield/i_carfield_rstgen] -filter {DIRECTION==OUT}] -set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {ORIG_REF_NAME=="rstgen" || REF_NAME=="rstgen"}] -set_false_path -hold -through [get_pins -filter {DIRECTION==OUT} -of_objects [get_cells -hier -filter {REF_NAME == rstgen || ORIG_REF_NAME == rstgen}]] diff --git a/target/xilinx/flavor_vanilla/constraints/carfield_top_xilinx.xdc b/target/xilinx/flavor_vanilla/constraints/carfield_top_xilinx.xdc new file mode 100644 index 00000000..43e50249 --- /dev/null +++ b/target/xilinx/flavor_vanilla/constraints/carfield_top_xilinx.xdc @@ -0,0 +1,99 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set SOC_TCK 20 +set JTAG_TCK 100.0 +set UART_IO_SPEED 200.0 + +################### +# Top level reset # +################### + +# The output of the top level reset synchronizer +set SOC_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets rst_n]] +set_max_delay -through $SOC_RST_SRC $SOC_TCK +set_false_path -hold -through $SOC_RST_SRC + +########## +# Clocks # +########## + +# Rtc clock is asynchronous +create_generated_clock -source [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets clk_10]] -divide_by 10 -name rtc_clk [get_pins rtc_clk_q_reg/Q] +set_clock_groups -asynchronous -group {rtc_clk} + +# System Clock +# [see in $XILINX_BOARD.xdc] + +# JTAG Clock +create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i] +set_input_jitter clk_jtag 1.000 +set_clock_groups -name jtag_grp -asynchronous -group {clk_jtag} + +########## +# BUFG # +########## + +# JTAG are on non clock capable GPIOs (if not using BSCANE) +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]] +set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports cpu_reset]] +set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports cpu_reset]] + +######## +# JTAG # +######## + +set_input_delay -min -clock clk_jtag [expr 0.10 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}] +set_input_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}] + +set_output_delay -min -clock clk_jtag [expr 0.10 * $JTAG_TCK] [get_ports jtag_tdo_o] +set_output_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports jtag_tdo_o] + +set_max_delay -from [get_ports jtag_trst_ni] $JTAG_TCK +set_false_path -hold -from [get_ports jtag_trst_ni] + +######## +# UART # +######## + +set_max_delay [expr $UART_IO_SPEED * 0.35] -from [get_ports uart_rx_i] +set_false_path -hold -from [get_ports uart_rx_i] + +set_max_delay [expr $UART_IO_SPEED * 0.35] -to [get_ports uart_tx_o] +set_false_path -hold -to [get_ports uart_tx_o] + +######## +# VIOs # +######## + +set_false_path -through [get_pins -of_object [get_cells -hier -filter {REF_NAME =~ xlnx_vio || ORIG_REF_NAME =~ xlnx_vio}] -filter {NAME =~ *probe*}] + +################# +# Carfield CDCs # +################# + +# Hyper +################### + +# i_hyper_cdc_dst +set_max_delay -datapath \ + -from [get_pins i_hyper_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ + $SOC_TCK +set_max_delay -datapath \ + -from [get_pins i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_hyper_cdc_dst/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ + $SOC_TCK +set_max_delay -datapath \ + -from [get_pins i_hyper_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ + $SOC_TCK +set_max_delay -datapath \ + -from [get_pins i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_hyper_cdc_dst/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ + $SOC_TCK diff --git a/target/xilinx/flavor_vanilla/constraints/vcu128.xdc b/target/xilinx/flavor_vanilla/constraints/vcu128.xdc index a55db78d..d810d1d6 100644 --- a/target/xilinx/flavor_vanilla/constraints/vcu128.xdc +++ b/target/xilinx/flavor_vanilla/constraints/vcu128.xdc @@ -17,8 +17,6 @@ set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] # Dram axi clock : 750ps * 4 set MIG_TCK 3 -create_generated_clock -source [get_pins i_dram_wrapper/i_dram/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0] \ - -divide_by 1 -add -master_clock mmcm_clkout0 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk] # Aynch reset in set MIG_RST_I [get_pin i_dram_wrapper/i_dram/inst/c0_ddr4_aresetn] set_false_path -hold -setup -through $MIG_RST_I diff --git a/target/xilinx/flavor_vanilla/flavor_vanilla.mk b/target/xilinx/flavor_vanilla/flavor_vanilla.mk index 37e6c80a..4302e951 100644 --- a/target/xilinx/flavor_vanilla/flavor_vanilla.mk +++ b/target/xilinx/flavor_vanilla/flavor_vanilla.mk @@ -36,20 +36,20 @@ vivado_env_vanilla := \ # Generate bender scripts (! attention ! modified on the fly) $(CAR_XIL_DIR)/flavor_vanilla/scripts/add_sources.tcl: Bender.yml - $(BENDER) script vivado $(common_targs) $(xilinx_targs_vanilla) $(common_defs) $(xilinx_defs_vanilla) > $@ - cp $@ $@.bak + $(BENDER) script vivado $(common_targs) $(xilinx_targs_vanilla) $(common_defs) $(xilinx_defs_vanilla) > $@.bak # Remove ibex's vendored prim includes as they conflict with opentitan's vendored prim includes - grep -v -P "lowrisc_ip/ip/prim/rtl" $@ > $@-tmp - mv $@-tmp $@ -# Override system verilog files + grep -v -P "lowrisc_ip/ip/prim/rtl" $@.bak > $@ + # Override system verilog files $(CAR_XIL_DIR)/scripts/overrides.sh $@ echo "" >> $@ + # Compile bitstream $(CAR_XIL_DIR)/flavor_vanilla/out/%.bit: $(xilinx_ips_paths_vanilla) $(CAR_XIL_DIR)/flavor_vanilla/scripts/add_sources.tcl @mkdir -p $(CAR_XIL_DIR)/flavor_vanilla/out cd $(CAR_XIL_DIR)/flavor_vanilla && $(vivado_env) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run.tcl find $(CAR_XIL_DIR)/flavor_vanilla -name "*.ltx" -o -name "*.bit" -o -name "*routed.rpt" | xargs -I {} cp {} $(CAR_XIL_DIR)/flavor_vanilla/out +.PRECIOUS: $(CAR_XIL_DIR)/flavor_vanilla/out/%.bit car-xil-clean-vanilla: cd $(CAR_XIL_DIR)/flavor_vanilla && rm -rf scripts/add_sources.tcl* *.log *.jou *.str *.mif carfield.* .Xil/ diff --git a/target/xilinx/flavor_vanilla/scripts/run.tcl b/target/xilinx/flavor_vanilla/scripts/run.tcl index d7b1b520..c14efe8e 100644 --- a/target/xilinx/flavor_vanilla/scripts/run.tcl +++ b/target/xilinx/flavor_vanilla/scripts/run.tcl @@ -14,9 +14,15 @@ set_param general.maxThreads 8 # Contraints files selection switch $::env(XILINX_BOARD) { - "genesys2" - "kc705" - "vc707" - "vcu128" - "zcu102" { + "vcu128" { import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD).xdc - import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_PROJECT).xdc + import_files -fileset constrs_1 -norecurse constraints/carfield_top_xilinx.xdc + # General constraints + import_files -fileset constrs_1 -norecurse ../constraints/carfield_islands.tcl + # Make sure carfield.xdc executes after carfield_islands.tcl (that generates the clocks) + import_files -fileset constrs_1 -norecurse ../constraints/carfield.xdc + set_property SCOPED_TO_REF carfield [get_files carfield.xdc] + set_property processing_order LATE [get_files carfield.xdc] } default { exit 1 @@ -46,8 +52,6 @@ if {[info exists ::env(XILINX_ELABORATION_ONLY)] && $::env(XILINX_ELABORATION_ON set_property XPM_LIBRARIES XPM_MEMORY [current_project] - synth_design -rtl -name rtl_1 -sfcu - set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] # Enable sfcu due to package conflicts set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-sfcu} -objects [get_runs synth_1] diff --git a/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv b/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv index 23ba5d3d..1d35fbd5 100644 --- a/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv +++ b/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv @@ -124,9 +124,10 @@ module carfield_top_xilinx `endif logic sys_rst; - wire clk_100, clk_50, clk_20, clk_10; + wire clk_100, clk_50, clk_20; + (* dont_touch = "yes" *) wire clk_10; wire soc_clk, host_clk, alt_clk, periph_clk; - (* dont_touch = "yes" *) wire rst_n; + (* dont_touch = "yes" *) wire rst_n; /////////////////// // GPIOs // @@ -399,32 +400,9 @@ module carfield_top_xilinx // Carfield Cfg // ////////////////// -`ifndef GEN_PULP_CLUSTER -`define GEN_PULP_CLUSTER 0 -`endif -`ifndef GEN_SAFETY_ISLAND -`define GEN_SAFETY_ISLAND 0 -`endif -`ifndef GEN_SPATZ_CLUSTER -`define GEN_SPATZ_CLUSTER 0 -`endif -`ifndef GEN_OPEN_TITAN -`define GEN_OPEN_TITAN 0 -`endif - localparam cheshire_cfg_t Cfg = carfield_pkg::CarfieldCfgDefault; `CHESHIRE_TYPEDEF_ALL(carfield_, Cfg) - localparam islands_cfg_t IslandsCfg = '{ - EnPulpCluster : `GEN_PULP_CLUSTER, - EnSafetyIsland : `GEN_SAFETY_ISLAND, - EnSpatzCluster : `GEN_SPATZ_CLUSTER, - EnOpenTitan : `GEN_OPEN_TITAN, - EnCan : 0, - EnEthernet : 0, - default : '1 - }; - /////////////////// // LLC interface // /////////////////// @@ -498,7 +476,6 @@ module carfield_top_xilinx carfield #( .Cfg (carfield_pkg::CarfieldCfgDefault), - .IslandsCfg(IslandsCfg), .reg_req_t(carfield_reg_req_t), .reg_rsp_t(carfield_reg_rsp_t), `ifdef GEN_NO_HYPERBUS diff --git a/target/xilinx/scripts/overrides.sh b/target/xilinx/scripts/overrides.sh index 570e1f7e..c1db7201 100755 --- a/target/xilinx/scripts/overrides.sh +++ b/target/xilinx/scripts/overrides.sh @@ -10,15 +10,15 @@ SCRIPT_DIR="$(dirname "$(readlink -f "$0")")" for f in `find $SCRIPT_DIR/../src/overrides -not -type d -printf "%f\n"`; do - echo "Removing $f" - grep -v -P "(? /tmp/overrides-tmp - diff /tmp/overrides-tmp $@ | grep ">\|<" - cp /tmp/overrides-tmp $1 + echo "Removing $f $1.tmp" + grep -v -P "(? $1.tmp + mv $1.tmp $1 done -for f in `find $SCRIPT_DIR/../src/overrides -not -type d -printf "%f\n"`; do - echo "Removing $f" - grep -v -P "(? /tmp/overrides-tmp - diff /tmp/overrides-tmp $@ | grep ">\|<" - cp /tmp/overrides-tmp $1 -done + +#for f in `find $SCRIPT_DIR/../src/overrides -not -type d -printf "%f\n"`; do +# echo "Removing $f $1.tmp" +# grep -v -P "(? $1.tmp +# diff $1.tmp $@ | grep ">\|<" +# mv $1.tmp $1 +#done diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk index 48db220d..14424794 100644 --- a/target/xilinx/xilinx.mk +++ b/target/xilinx/xilinx.mk @@ -35,7 +35,7 @@ VIVADO_MODE ?= batch VIVADO_FLAGS ?= -nojournal -mode $(VIVADO_MODE) xilinx_ip_dir := $(CAR_XIL_DIR)/xilinx_ips -xilinx_bit := $(CAR_XIL_DIR)/out/$(XILINX_PROJECT)_$(XILINX_FLAVOR)_$(XILINX_BOARD).bit +xilinx_bit := $(CAR_XIL_DIR)/out/$(XILINX_PROJECT)_$(XILINX_FLAVOR)_$(XILINX_BOARD)_$(CARFIELD_CONFIG).bit # # Include other makefiles flavors @@ -76,6 +76,7 @@ $(CAR_XIL_DIR)/out/%.bit: $(xilinx_bit_$(XILINX_FLAVOR)) ## @param XILINX_PROJECT The name of the Xilinx project ## @param XILINX_FLAVOR= The flavor of the implementation ## @param XILINX_BOARD The target Xilinx board +## @param CARFIELD_CONFIG The SoC configuration to be used car-xil-all: $(xilinx_bit) ## Program last bitstream for Carfield diff --git a/target/xilinx/xilinx_ips/carfield_ip/carfield_ip.mk b/target/xilinx/xilinx_ips/carfield_ip/carfield_ip.mk index c3a4e5a5..bbc8a59f 100644 --- a/target/xilinx/xilinx_ips/carfield_ip/carfield_ip.mk +++ b/target/xilinx/xilinx_ips/carfield_ip/carfield_ip.mk @@ -12,10 +12,6 @@ IP_DEP_carfield_ip := $(CAR_XIL_DIR)/xilinx_ips/carfield_ip/tcl/add_sources.tcl $(CAR_XIL_DIR)/xilinx_ips/carfield_ip/tcl/add_sources.tcl: Bender.yml # Add source files for ip $(BENDER) script vivado $(xilinx_targs) $(common_defs) $(xilinx_defs_bd) > $@ - cp $@ $@.bak + mv $@ $@.bak # Remove ibex's vendored prim includes as they conflict with opentitan's vendored prim includes - grep -v -P "lowrisc_ip/ip/prim/rtl" $@ > $@-tmp - mv $@-tmp $@ -# Override system verilog files - target/xilinx/scripts/overrides.sh $@ - echo "" >> $@ + grep -v -P "lowrisc_ip/ip/prim/rtl" $@.bak > $@ diff --git a/target/xilinx/xilinx_ips/carfield_ip/constraints/carfield_ip.xdc b/target/xilinx/xilinx_ips/carfield_ip/constraints/carfield_ip.xdc deleted file mode 100644 index 6175f6d8..00000000 --- a/target/xilinx/xilinx_ips/carfield_ip/constraints/carfield_ip.xdc +++ /dev/null @@ -1,443 +0,0 @@ - -################### -# Global Settings # -################### - -# The output of the reset synchronizer -set_false_path -from [get_ports cpu_reset*] - -##################### -# Timing Parameters # -##################### - -# Host on clk_50 -set SOC_TCK 20 - -set JTAG_TCK 100 - -########## -# Clocks # -########## - -# Rtc clock is asynchronous -create_generated_clock -source [get_ports clk_10] -divide_by 10 -name rtc_clk [get_pins i_carfield_xilinx/rtc_clk_q_reg/Q] -set_clock_groups -asynchronous -group {rtc_clk} -set_max_delay -from [get_pin i_carfield_xilinx/rtc_clk_q_reg/Q] $SOC_TCK - -# System Clock -# [see in board.xdc] - -# JTAG Clock -create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i] -set_clock_groups -name jtag_grp -asynchronous -group {clk_jtag} - -########## -# BUFG # -########## - -# JTAG are on non clock capable GPIOs (if not using BSCANE) -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]] -set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]] - -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports cpu_reset]] -set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports cpu_reset]] - -set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]] -set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux -set_property CLOCK_BUFFER_TYPE NONE $all_in_mux - -#################### -# Clock generators # -#################### - -# Do not optimize anything in them -set_property DONT_TOUCH TRUE [get_cells i_carfield_xilinx/i_carfield/gen_domain_clock_mux[*].i_clk_mux] - -# TODO Check this -set_false_path -from [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].clock_has_been_disabled_q_reg[*]/C] -to [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].clock_has_been_disabled_q_reg[*]/D] -set_false_path -from [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].clock_has_been_disabled_q_reg[*]/C] -to [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[*].i_clk_mux/gen_input_stages[*].glitch_filter_q_reg[*][*]/D] - -# Periph domain -create_generated_clock -source [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[0].i_clk_mux/clks_i[2]] -divide_by 1 -name periph_domain_clk [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[0].i_clk_mux/clk_o] -set_case_analysis 0 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_periph_clk_sel/q_reg[0]/Q}] -set_case_analysis 1 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_periph_clk_sel/q_reg[1]/Q}] -set_case_analysis 1 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_periph_clk_en/q_reg[0]/Q}] - -# Safety domain -create_generated_clock -source [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[1].i_clk_mux/clks_i[1]] -divide_by 1 -name safety_domain_clk [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[1].i_clk_mux/clk_o] -set_case_analysis 1 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_safety_island_clk_sel/q_reg[0]/Q}] -set_case_analysis 0 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_safety_island_clk_sel/q_reg[1]/Q}] -set_case_analysis 1 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_safety_island_clk_en/q_reg[0]/Q}] - -# Security domain -create_generated_clock -source [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[2].i_clk_mux/clks_i[1]] -divide_by 1 -name security_domain_clk [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[2].i_clk_mux/clk_o] -set_case_analysis 1 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_security_island_clk_sel/q_reg[0]/Q}] -set_case_analysis 0 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_security_island_clk_sel/q_reg[1]/Q}] -set_case_analysis 1 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_security_island_clk_en/q_reg[0]/Q}] - -# Pulp domain -create_generated_clock -source [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[3].i_clk_mux/clks_i[1]] -divide_by 1 -name pulp_domain_clk [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[3].i_clk_mux/clk_o] -set_case_analysis 1 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_pulp_cluster_clk_sel/q_reg[0]/Q}] -set_case_analysis 0 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_pulp_cluster_clk_sel/q_reg[1]/Q}] -set_case_analysis 1 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_pulp_cluster_clk_en/q_reg[0]/Q}] - -# Spatz domain -create_generated_clock -source [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[4].i_clk_mux/clks_i[1]] -divide_by 1 -name spatz_domain_clk [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[4].i_clk_mux/clk_o] -set_case_analysis 1 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_spatz_cluster_clk_sel/q_reg[0]/Q}] -set_case_analysis 0 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_spatz_cluster_clk_sel/q_reg[1]/Q}] -set_case_analysis 1 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_spatz_cluster_clk_en/q_reg[0]/Q}] - -# L2 Domain -create_generated_clock -source [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[5].i_clk_mux/clks_i[0]] -divide_by 1 -name l2_domain_clk [get_pins i_carfield_xilinx/i_carfield/gen_domain_clock_mux[5].i_clk_mux/clk_o] -set_case_analysis 0 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_l2_clk_sel/q_reg[0]/Q}] -set_case_analysis 0 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_l2_clk_sel/q_reg[1]/Q}] -set_case_analysis 1 [get_pins {i_carfield_xilinx/i_carfield/i_carfield_reg_top/u_l2_clk_en/q_reg[0]/Q}] - -################# -# Carfield CDCs # -################# - -# Note : -# For the 2 phases CDC we use max_delay and hold path as we grab everything grossly -# On the AXI CDC as we precisely select the Clk-to-Q path we use a unique set_max_delay -datapath -# All the delays are assumed to be SOC_TCK (host domain) - -# Hold and max delay on 2 phases and 2 phases clearable -set_max_delay -through [get_nets -filter {NAME=~"*async*"} -of_objects [get_cells -hier -filter {REF_NAME =~ cdc_2phase_src* || ORIG_REF_NAME =~ cdc_2phase_src*}]] $SOC_TCK -set_false_path -hold -through [get_nets -filter {NAME=~"*async*"} -of_objects [get_cells -hier -filter {REF_NAME =~ cdc_2phase_src* || ORIG_REF_NAME =~ cdc_2phase_src*}]] - -# Hold and max delay on 4 phases -set_max_delay -through [get_nets -filter {NAME=~"*async*"} -of_objects [get_cells -hier -filter {REF_NAME == cdc_4phase_src || ORIG_REF_NAME == cdc_4phase_src}]] $SOC_TCK -set_false_path -hold -through [get_nets -filter {NAME=~"*async*"} -of_objects [get_cells -hier -filter {REF_NAME == cdc_4phase_src || ORIG_REF_NAME == cdc_4phase_src}]] - -# Hold and max delay on synchronizers -set all_sync_cells [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}] -set_property KEEP_HIERARCHY SOFT $all_sync_cells -set_false_path -hold -through [get_pins -of_objects $all_sync_cells -filter {REF_PIN_NAME=~serial_i}] -set_max_delay -through [get_pins -of_objects $all_sync_cells -filter {REF_PIN_NAME=~serial_i}] $SOC_TCK - -# Hold and max delay on pulp synchronizers -set all_pulp_sync_cells [get_cells -hier -filter {ORIG_REF_NAME=="pulp_sync" || REF_NAME=="pulp_sync"}] -set_property KEEP_HIERARCHY SOFT $all_pulp_sync_cells -set_false_path -hold -through [get_pins -of_objects $all_pulp_sync_cells -filter {REF_PIN_NAME=~serial_i}] -set_max_delay -through [get_pins -of_objects $all_pulp_sync_cells -filter {REF_PIN_NAME=~serial_i}] $SOC_TCK - -# Hold and max delay on OT synchronizers -set all_ot_sync_cells [get_cells -hier -filter {ORIG_REF_NAME=="prim_ot_flop_2sync" || REF_NAME=="prim_ot_flop_2sync"}] -set_property KEEP_HIERARCHY SOFT $all_ot_sync_cells -set_false_path -hold -through [get_pins -of_objects $all_ot_sync_cells -filter {REF_PIN_NAME=~d_i*}] -set_max_delay -through [get_pins -of_objects $all_ot_sync_cells -filter {REF_PIN_NAME=~d_i*}] $SOC_TCK - -set all_edge_propagator_ack [get_cells -hier -filter {ORIG_REF_NAME=="edge_propagator_ack" || REF_NAME=="edge_propagator_ack"}] -set_property KEEP_HIERARCHY SOFT $all_edge_propagator_ack -set_false_path -through [get_nets -filter {NAME=~*sync_b} -of_object [get_cells -hier -filter {ORIG_REF_NAME==pulp_sync_wedge || REF_NAME==pulp_sync_wedge}]] - -# Ethernet -############## - -# i_carfield_xilinx/i_carfield/gen*_ethernet.i_ethernet_cdc_dst -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen*_ethernet.i_ethernet_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[3].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[3].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen*_ethernet.i_ethernet_cdc_dst/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen*_ethernet.i_ethernet_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[3].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[3].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen*_ethernet.i_ethernet_cdc_dst/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# Peripherals -############## - -# i_carfield_xilinx/i_carfield/i_cdc_dst_peripherals -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cdc_dst_peripherals/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[4].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[4].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cdc_dst_peripherals/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cdc_dst_peripherals/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[4].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[4].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cdc_dst_peripherals/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# Safety Island -################ - -# To Safety Island error slave -# i_carfield_xilinx/i_carfield/gen_no_safety_island.i_safety_island_axi_err/i_cdc_in -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_no_safety_island.i_safety_island_axi_err/i_cdc_in/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_no_safety_island.i_safety_island_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_no_safety_island.i_safety_island_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_no_safety_island.i_safety_island_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# To Safety Island slave -# i_carfield_xilinx/i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_in -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_in/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_in/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[2].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# From Safety Island master -# i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[0].i_cheshire_ext_mst_cdc_dst -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_out/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[0].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[0].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_out/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_out/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[0].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[0].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_safety_island.i_safety_island_wrap/i_cdc_out/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# Pulp Cluster -################ - -# To Pulp cluster error slave -# i_carfield_xilinx/i_carfield/gen_no_pulp_cluster.i_pulp_cluster_axi_err/i_cdc_in -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_no_pulp_cluster.i_pulp_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_no_pulp_cluster.i_pulp_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_no_pulp_cluster.i_pulp_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_no_pulp_cluster.i_pulp_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# To Pulp cluster slave -# i_carfield_xilinx/i_carfield/gen_pulp_cluster.i_integer_cluster/axi_slave_cdc_i -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_pulp_cluster.i_integer_cluster/axi_slave_cdc_i/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_pulp_cluster.i_integer_cluster/axi_slave_cdc_i/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_pulp_cluster.i_integer_cluster/axi_slave_cdc_i/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_pulp_cluster.i_integer_cluster/axi_slave_cdc_i/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_intcluster_slv_cdc/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# From Pulp cluster master -# i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_intcluster_mst_cdc -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_pulp_cluster.i_integer_cluster/axi_master_cdc_i/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_intcluster_mst_cdc/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_intcluster_mst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_pulp_cluster.i_integer_cluster/axi_master_cdc_i/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_pulp_cluster.i_integer_cluster/axi_master_cdc_i/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_intcluster_mst_cdc/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_intcluster_mst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_pulp_cluster.i_integer_cluster/axi_master_cdc_i/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# Spatz cluster -############### - -# To Spatz cluster error slave -# i_carfield_xilinx/i_carfield/gen_no_spatz_cluster.i_spatz_cluster_axi_err/i_cdc_in -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_no_spatz_cluster.i_spatz_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_no_spatz_cluster.i_spatz_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_no_spatz_cluster.i_spatz_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_no_spatz_cluster.i_spatz_cluster_axi_err/i_cdc_in/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# To Spatz cluster slave -# i_carfield_xilinx/i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_dst -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_dst/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_dst/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[5].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# From Spatz cluster master -# i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[2].i_cheshire_ext_mst_cdc_dst -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[2].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[2].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[2].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_mst_dst_cdc[2].i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/gen_spatz_cluster.i_fp_cluster_wrapper/i_spatz_cluster_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# Reconfigurable L2 -################### - -# i_carfield_xilinx/i_carfield/i_reconfigurable_l2/gen_cdc_fifos[0].i_dst_cdc -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_reconfigurable_l2/gen_cdc_fifos[0].i_dst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[0].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D -] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[0].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_reconfigurable_l2/gen_cdc_fifos[0].i_dst_cdc/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_reconfigurable_l2/gen_cdc_fifos[0].i_dst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[0].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[0].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_reconfigurable_l2/gen_cdc_fifos[0].i_dst_cdc/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# i_carfield_xilinx/i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -# i_carfield_xilinx/i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/gen_ext_slv_src_cdc[1].i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_reconfigurable_l2/gen_cdc_fifos[1].i_dst_cdc/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -#i_hyper_cdc_dst -set_max_delay -datapath \ - -from [get_pins i_hyper_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_hyper_cdc_dst/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_hyper_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK -set_max_delay -datapath \ - -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_hyper_cdc_dst/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ - $SOC_TCK - -#################### -# Reset Generators # -#################### - -set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {ORIG_REF_NAME=="rstgen" || REF_NAME=="rstgen"}] -# Relax constraints on synchronous for the islands (since they are clock-gated at sw-reset) -set_false_path -through [get_pins -hier -filter { NAME =~ "*_rst/q_reg[0]/Q" } ] -set_false_path -hold -through [get_cells -hier -filter {REF_NAME == rstgen || ORIG_REF_NAME == rstgen} -regexp .*gen_domain.*] -# Go large on the isolation -set_max_delay -datapath -to [get_nets i_carfield_xilinx/i_carfield/*isolat*] $SOC_TCK -set_false_path -hold -through [get_nets i_carfield_xilinx/i_carfield/*isolat*] diff --git a/target/xilinx/xilinx_ips/carfield_ip/constraints/carfield_xilinx_ip.xdc b/target/xilinx/xilinx_ips/carfield_ip/constraints/carfield_xilinx_ip.xdc new file mode 100644 index 00000000..1a23e1aa --- /dev/null +++ b/target/xilinx/xilinx_ips/carfield_ip/constraints/carfield_xilinx_ip.xdc @@ -0,0 +1,72 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set SOC_TCK 20 +set JTAG_TCK 100.0 +set UART_IO_SPEED 200.0 + +################### +# Global Settings # +################### + +# The output of the reset synchronizer +set_false_path -from [get_ports cpu_reset*] + +########## +# Clocks # +########## + +# Rtc clock is asynchronous +create_generated_clock -source [get_ports clk_10] -divide_by 10 -name rtc_clk [get_pins i_carfield_xilinx/rtc_clk_q_reg/Q] +set_clock_groups -asynchronous -group {rtc_clk} +set_max_delay -from [get_pin i_carfield_xilinx/rtc_clk_q_reg/Q] $SOC_TCK + +# System Clock +# [see in board.xdc] + +# JTAG Clock +create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i] +set_clock_groups -name jtag_grp -asynchronous -group {clk_jtag} + +########## +# BUFG # +########## + +# JTAG are on non clock capable GPIOs (if not using BSCANE) +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]] +set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports cpu_reset]] +set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports cpu_reset]] + +set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]] +set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux +set_property CLOCK_BUFFER_TYPE NONE $all_in_mux + +################# +# Carfield CDCs # +################# + +# Hyper +################ + +#i_hyper_cdc_dst +set_max_delay -datapath \ + -from [get_pins i_carfield_xilinx/i_hyper_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ + $SOC_TCK +set_max_delay -datapath \ + -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_carfield_xilinx/i_hyper_cdc_dst/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \ + $SOC_TCK +set_max_delay -datapath \ + -from [get_pins i_carfield_xilinx/i_hyper_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ + $SOC_TCK +set_max_delay -datapath \ + -from [get_pins i_carfield_xilinx/i_carfield/i_cheshire_wrap/i_cheshire_ext_llc_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_carfield_xilinx/i_hyper_cdc_dst/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \ + $SOC_TCK diff --git a/target/xilinx/xilinx_ips/carfield_ip/constraints/ooc_carfield_ip.xdc b/target/xilinx/xilinx_ips/carfield_ip/constraints/ooc_carfield_ip.xdc index 3a2446e3..c8529797 100644 --- a/target/xilinx/xilinx_ips/carfield_ip/constraints/ooc_carfield_ip.xdc +++ b/target/xilinx/xilinx_ips/carfield_ip/constraints/ooc_carfield_ip.xdc @@ -3,3 +3,9 @@ create_clock -name carfield_ooc_synth_clk_50 -period 50 [get_ports clk_50] create_clock -name carfield_ooc_synth_clk_20 -period 20 [get_ports clk_20] create_clock -name carfield_ooc_synth_clk_10 -period 10 [get_ports clk_10] set_case_analysis 0 [get_ports testmode_i] + +set_clock_groups -name async_clks -asynchronous \ +-group [get_clocks -include_generated_clocks carfield_ooc_synth_clk_100] \ +-group [get_clocks -include_generated_clocks carfield_ooc_synth_clk_50] \ +-group [get_clocks -include_generated_clocks carfield_ooc_synth_clk_20] \ +-group [get_clocks -include_generated_clocks carfield_ooc_synth_clk_10] diff --git a/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv b/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv index b6c46097..2efcb7b9 100644 --- a/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv +++ b/target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv @@ -9,19 +9,6 @@ `include "axi/typedef.svh" `include "cheshire/typedef.svh" -`ifndef GEN_PULP_CLUSTER -`define GEN_PULP_CLUSTER 0 -`endif -`ifndef GEN_SAFETY_ISLAND -`define GEN_SAFETY_ISLAND 0 -`endif -`ifndef GEN_SPATZ_CLUSTER -`define GEN_SPATZ_CLUSTER 0 -`endif -`ifndef GEN_OPEN_TITAN -`define GEN_OPEN_TITAN 0 -`endif - module carfield_xilinx import carfield_pkg::*; import cheshire_pkg::*; @@ -294,16 +281,6 @@ module carfield_xilinx localparam cheshire_cfg_t Cfg = carfield_pkg::CarfieldCfgDefault; `CHESHIRE_TYPEDEF_ALL(carfield_, Cfg) - localparam islands_cfg_t IslandsCfg = '{ - EnPulpCluster : `GEN_PULP_CLUSTER, - EnSafetyIsland : `GEN_SAFETY_ISLAND, - EnSpatzCluster : `GEN_SPATZ_CLUSTER, - EnOpenTitan : `GEN_OPEN_TITAN, - EnCan : 0, - EnEthernet : 0, - default : '1 - }; - /////////////////// // LLC interface // /////////////////// @@ -713,8 +690,7 @@ module carfield_xilinx logic jtag_host_to_safety, jtag_safety_to_ot; carfield #( - .Cfg (carfield_pkg::CarfieldCfgDefault), - .IslandsCfg(IslandsCfg), + .Cfg (carfield_pkg::CarfieldCfgDefault), .reg_req_t(carfield_reg_req_t), .reg_rsp_t(carfield_reg_rsp_t), `ifdef GEN_NO_HYPERBUS // bender-xilinx.mk diff --git a/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl b/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl index 0ca61594..70467762 100644 --- a/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl +++ b/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl @@ -18,8 +18,12 @@ source tcl/add_sources.tcl # Add constraints add_files -fileset constrs_1 constraints/ooc_carfield_ip.xdc -set_property USED_IN {synthesis out_of_context} [get_files constraints/ooc_carfield_ip.xdc] -add_files -fileset constrs_1 constraints/carfield_ip.xdc +set_property USED_IN {synthesis out_of_context} [get_files ooc_carfield_ip.xdc] +import_files -fileset constrs_1 -norecurse constraints/carfield_xilinx_ip.xdc +# General constraints +import_files -fileset constrs_1 -norecurse ../../constraints/carfield.xdc +set_property SCOPED_TO_REF carfield [get_files carfield.xdc] +set_property processing_order LATE [get_files carfield.xdc] # Package IP set_property top carfield_xilinx_ip [current_fileset] diff --git a/target/xilinx/xilinx_ips/xilinx_ips.mk b/target/xilinx/xilinx_ips/xilinx_ips.mk index 750fddb2..8b45c0ed 100644 --- a/target/xilinx/xilinx_ips/xilinx_ips.mk +++ b/target/xilinx/xilinx_ips/xilinx_ips.mk @@ -22,6 +22,8 @@ endif $(CAR_XIL_DIR)/xilinx_ips/$(1)/$(1).xpr: cd $$(ROOT_$(1)) && $(vivado_env) $(VIVADO) -mode batch -source tcl/run.tcl + +.PRECIOUS: $(CAR_XIL_DIR)/xilinx_ips/$(1)/$(1).xpr $(CAR_XIL_DIR)/xilinx_ips/$(1)/%.xci endef # Call xlnx_ips_vars_and_deps