diff --git a/Bender.lock b/Bender.lock index 412ac605..d46fe8e3 100644 --- a/Bender.lock +++ b/Bender.lock @@ -46,7 +46,7 @@ packages: dependencies: - axi_slice axi_llc: - revision: 7d7fc1349d4915a657de535a491bc26fbf0d2cfa + revision: 7c681312ae1eb912052de98ddaf5d19e1c2b76ff version: null source: Git: https://github.com/pulp-platform/axi_llc @@ -114,7 +114,7 @@ packages: Git: git@github.com:AlSaqr-platform/can_bus.git dependencies: [] cheshire: - revision: 0c95210cf242c384fafe3019e84b8974c3ff1e92 + revision: 0071e68fdca331a81e9467ea11be222fefeae4cc version: null source: Git: https://github.com/pulp-platform/cheshire.git diff --git a/Bender.yml b/Bender.yml index 60ab212e..2799319e 100644 --- a/Bender.yml +++ b/Bender.yml @@ -9,11 +9,12 @@ package: - "Alessandro Ottaviano " - "Robert Balas " - "Yvan Tortorella " + - "Cyril Koenig " dependencies: register_interface: { git: https://github.com/pulp-platform/register_interface.git, version: 0.4.2 } axi: { git: https://github.com/pulp-platform/axi.git, version: 0.39.1 } - cheshire: { git: https://github.com/pulp-platform/cheshire.git, rev: 0c95210cf242c384fafe3019e84b8974c3ff1e92 } # branch: aottaviano/carfield + cheshire: { git: https://github.com/pulp-platform/cheshire.git, rev: 0071e68fdca331a81e9467ea11be222fefeae4cc } # branch: aottaviano/carfield hyperbus: { git: https://github.com/pulp-platform/hyperbus.git, rev: f039e601c8b6590181734e6d26ff8b77aa380412 } # branch: chi/add_fsm_with_Tcsh dyn_mem: { git: https://github.com/pulp-platform/dyn_spm.git, rev: 480590062742230dc9bd4050358a15b4747bdf34 } # branch: main safety_island: { git: https://github.com/pulp-platform/safety_island.git, rev: aaef55c798ab53560faaf451a86668fa1e6d0f3b } # branch: carfield diff --git a/hw/carfield_pkg.sv b/hw/carfield_pkg.sv index e63971be..7a775854 100644 --- a/hw/carfield_pkg.sv +++ b/hw/carfield_pkg.sv @@ -624,8 +624,8 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{ LlcOutConnect : 1, LlcOutRegionStart : 'h8000_0000, LlcOutRegionEnd : 'h1_0000_0000, - LlcBypassRegionStart : 'h8_0000_0000, - LlcBypassRegionEnd : 'h8_8000_0000, + LlcBypassRegionStart : 'h2_8000_0000, + LlcBypassRegionEnd : 'h3_0000_0000, LlcUserMsb : 9, LlcUserLsb : 5, LlcCachePartition : 1, diff --git a/sw/include/car_memory_map.h b/sw/include/car_memory_map.h index fb9888a5..c6b12bc9 100644 --- a/sw/include/car_memory_map.h +++ b/sw/include/car_memory_map.h @@ -76,6 +76,9 @@ extern void *__base_l2; #define CAR_HYPERRAM_BASE_ADDR 0x80400000 #define CAR_HYPERRAM_END_ADDR 0x80800000 +// Bypass LLC +#define CAR_LLC_BYPASS_OFFSET 0x200000000 + // Peripheral devices // from cheshire #define CAR_BOOTROM_BASE_ADDR 0x000002000000 diff --git a/sw/sw.mk b/sw/sw.mk index 52f243c5..a278def9 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -66,12 +66,16 @@ CAR_ELFLOAD_PULPD_INTF_PATH := $(basename $(CAR_ELFLOAD_PULPD_INTF_SRC_C)) CAR_SW_TEST_SRCS_S = $(wildcard $(CAR_SW_DIR)/tests/bare-metal/hostd/*.S) CAR_SW_TEST_SRCS_C = $(filter-out $(CAR_ELFLOAD_BLOCKING_SAFED_SRC_C) $(CAR_ELFLOAD_BLOCKING_PULPD_SRC_C) $(CAR_ELFLOAD_PULPD_INTF_SRC_C), $(wildcard $(CAR_SW_DIR)/tests/bare-metal/hostd/*.c)) -CAR_SW_TEST_DRAM_DUMP = $(CAR_SW_TEST_SRCS_S:.S=.car.dram.dump) $(CAR_SW_TEST_SRCS_C:.c=.car.dram.dump) -CAR_SW_TEST_DRAM_SLM = $(CAR_SW_TEST_SRCS_S:.S=.car.dram.slm) $(CAR_SW_TEST_SRCS_C:.c=.car.dram.slm) -CAR_SW_TEST_SPM_DUMP = $(CAR_SW_TEST_SRCS_S:.S=.car.spm.dump) $(CAR_SW_TEST_SRCS_C:.c=.car.spm.dump) -CAR_SW_TEST_L2_DUMP = $(CAR_SW_TEST_SRCS_S:.S=.car.l2.dump) $(CAR_SW_TEST_SRCS_C:.c=.car.l2.dump) -CAR_SW_TEST_SPM_ROMH = $(CAR_SW_TEST_SRCS_S:.S=.car.rom.memh) $(CAR_SW_TEST_SRCS_C:.c=.car.rom.memh) -CAR_SW_TEST_SPM_GPTH = $(CAR_SW_TEST_SRCS_S:.S=.car.gpt.memh) $(CAR_SW_TEST_SRCS_C:.c=.car.gpt.memh) +CAR_SW_TEST_SRC_EXCLUDE_DRAM = +CAR_SW_TEST_SRC_EXCLUDE_SPM = llc_test.c +CAR_SW_TEST_SRC_EXCLUDE_L2 = llc_test.c + +CAR_SW_TEST_DRAM_DUMP = $(CAR_SW_TEST_SRCS_S:.S=.car.dram.dump) $(filter-out $(CAR_SW_TEST_SRC_EXCLUDE_DRAM),$(CAR_SW_TEST_SRCS_C:.c=.car.dram.dump)) +CAR_SW_TEST_DRAM_SLM = $(CAR_SW_TEST_SRCS_S:.S=.car.dram.slm) $(filter-out $(CAR_SW_TEST_SRC_EXCLUDE_DRAM),$(CAR_SW_TEST_SRCS_C:.c=.car.dram.slm)) +CAR_SW_TEST_SPM_DUMP = $(CAR_SW_TEST_SRCS_S:.S=.car.spm.dump) $(filter-out $(CAR_SW_TEST_SRC_EXCLUDE_SPM),$(CAR_SW_TEST_SRCS_C:.c=.car.spm.dump)) +CAR_SW_TEST_L2_DUMP = $(CAR_SW_TEST_SRCS_S:.S=.car.l2.dump) $(filter-out $(CAR_SW_TEST_SRC_EXCLUDE_L2),$(CAR_SW_TEST_SRCS_C:.c=.car.l2.dump)) +CAR_SW_TEST_SPM_ROMH = $(CAR_SW_TEST_SRCS_S:.S=.car.rom.memh) $(filter-out $(CAR_SW_TEST_SRC_EXCLUDE_SPM),$(CAR_SW_TEST_SRCS_C:.c=.car.rom.memh)) +CAR_SW_TEST_SPM_GPTH = $(CAR_SW_TEST_SRCS_S:.S=.car.gpt.memh) $(filter-out $(CAR_SW_TEST_SRC_EXCLUDE_SPM),$(CAR_SW_TEST_SRCS_C:.c=.car.gpt.memh)) car-sw-tests: $(CAR_SW_TEST_DRAM_DUMP) $(CAR_SW_TEST_SPM_DUMP) $(CAR_SW_TEST_L2_DUMP) $(CAR_SW_TEST_DRAM_SLM) $(CAR_SW_TEST_SPM_ROMH) $(CAR_SW_TEST_SPM_GPTH) car-pulpd-sw-offload-tests car-safed-sw-offload-tests mibench-automotive diff --git a/sw/tests/bare-metal/hostd/llc_test.c b/sw/tests/bare-metal/hostd/llc_test.c new file mode 100644 index 00000000..e8535c37 --- /dev/null +++ b/sw/tests/bare-metal/hostd/llc_test.c @@ -0,0 +1,99 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Cyril Koenig +// +// Simple program to test LLC enable, disable, flush and bypass + +#include "regs/cheshire.h" +#include "dif/clint.h" +#include "params.h" +#include "util.h" +#include "car_memory_map.h" +#include "car_util.h" + +volatile uint32_t dram_data_cached[64]; +volatile uint32_t *dram_data_uncached; + +int main(void) { + + // Init the HW + car_init_start(); + + // Disable CVA6 cache + fence(); + asm volatile ("csrwi 0x701, 0" :: ); + + dram_data_uncached = (uint32_t *)((void *)dram_data_cached + CAR_LLC_BYPASS_OFFSET); + + for ( int i = 0; i < 64 ; i++ ) { + dram_data_uncached[i] = dram_data_uncached[i] + 1; + if(dram_data_uncached[i] != 1) goto fail; + } + fence(); + + llc_enable(); + + for ( int i = 0; i < 64 ; i++ ) { + dram_data_cached[i] = dram_data_cached[i] + 10; + if(dram_data_cached[i] != 11) goto fail; + } + fence(); + + for ( int i = 0; i < 64 ; i++ ) { + dram_data_uncached[i] = dram_data_uncached[i] + 1; + if(dram_data_uncached[i] != 2) goto fail; + } + fence(); + + for ( int i = 0; i < 64 ; i++ ) { + dram_data_cached[i] = dram_data_cached[i] + 10; + if(dram_data_cached[i] != 21) goto fail; + } + fence(); + + fence(); + llc_flush(); + + for ( int i = 0; i < 64 ; i++ ) { + dram_data_uncached[i] = dram_data_uncached[i] + 1; + if(dram_data_uncached[i] != 22) goto fail; + } + fence(); + + // The LLC has been flushed, thus will have the latest value (22) + for ( int i = 0; i < 64 ; i++ ) { + dram_data_cached[i] = dram_data_cached[i] + 10; + if(dram_data_cached[i] != 32) goto fail; + } + fence(); + + for ( int i = 0; i < 64 ; i++ ) { + dram_data_uncached[i] = dram_data_uncached[i] + 1; + if(dram_data_uncached[i] != 23) goto fail; + } + fence(); + + // From now on, we are not anymore synched with the DRAM content + for ( int i = 0; i < 64 ; i++ ) { + dram_data_cached[i] = dram_data_cached[i] + 10; + if(dram_data_cached[i] != 42) goto fail; + } + fence(); + + llc_disable(); + + for ( int i = 0; i < 64 ; i++ ) { + if(dram_data_cached[i] != dram_data_uncached[i]) goto fail; + } + + // Stress a bit more the LLC with the icache + llc_enable(); + fencei(); + llc_disable(); + + return 0; + fail: + return 1; +}