diff --git a/Bender.yml b/Bender.yml index 4788e056c..839bf8891 100644 --- a/Bender.yml +++ b/Bender.yml @@ -42,6 +42,7 @@ sources: # package. Files in level 1 only depend on files in level 0, files in level 2 on files in # levels 1 and 0, etc. Files within a level are ordered alphabetically. # Level 0 + - hw/carfield_cfg_pkg.sv - hw/carfield_pkg.sv - hw/regs/carfield_reg_pkg.sv - hw/regs/carfield_reg_top.sv diff --git a/hw/carfield.sv b/hw/carfield.sv index 52bdf6dab..98a54de03 100644 --- a/hw/carfield.sv +++ b/hw/carfield.sv @@ -14,6 +14,7 @@ /// Top-level implementation of Carfield module carfield + import carfield_cfg_pkg::*; import carfield_pkg::*; import carfield_reg_pkg::*; import cheshire_pkg::*; @@ -1318,7 +1319,7 @@ assign safed_intrs = { }; // verilog_lint: waive-stop line-length -if (IslandsCfg.EnSafetyIsland) begin : gen_safety_island +if (CarfieldEnIslands.safed) begin : gen_safety_island `ifndef SAFED_NETLIST safety_island_synth_wrapper #( .SafetyIslandCfg ( SafetyIslandCfg ), @@ -1430,54 +1431,53 @@ if (IslandsCfg.EnSafetyIsland) begin : gen_safety_island .async_axi_out_r_rptr_o ( axi_mst_ext_r_rptr [SafetyIslandMstIdx] ) ); end -else begin : gen_no_safety_island - assign jtag_safety_island_tdo_o = jtag_safety_island_tdi_i; - cdc_dst_axi_err #( - .AxiInIdWidth ( AxiSlvIdWidth ), - .LogDepth ( LogDepth ), - .CdcSyncStages ( SyncStages ), - .axi_in_aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .axi_in_w_chan_t ( carfield_axi_slv_w_chan_t ), - .axi_in_b_chan_t ( carfield_axi_slv_b_chan_t ), - .axi_in_ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .axi_in_r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_in_resp_t ( carfield_axi_slv_rsp_t ), - .axi_in_req_t ( carfield_axi_slv_req_t ), - .AsyncAxiInAwWidth ( CarfieldAxiSlvAwWidth ), - .AsyncAxiInWWidth ( CarfieldAxiSlvWWidth ), - .AsyncAxiInBWidth ( CarfieldAxiSlvBWidth ), - .AsyncAxiInArWidth ( CarfieldAxiSlvArWidth ), - .AsyncAxiInRWidth ( CarfieldAxiSlvRWidth ) - ) i_safety_island_axi_err ( - .clk_i ( safety_clk ), - .rst_ni ( safety_rst_n ), - .pwr_on_rst_ni ( safety_pwr_on_rst_n ), - .async_axi_in_aw_data_i ( axi_slv_ext_aw_data [SafetyIslandSlvIdx] ), - .async_axi_in_aw_wptr_i ( axi_slv_ext_aw_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_aw_rptr_o ( axi_slv_ext_aw_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_ar_data_i ( axi_slv_ext_ar_data [SafetyIslandSlvIdx] ), - .async_axi_in_ar_wptr_i ( axi_slv_ext_ar_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_ar_rptr_o ( axi_slv_ext_ar_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_w_data_i ( axi_slv_ext_w_data [SafetyIslandSlvIdx] ), - .async_axi_in_w_wptr_i ( axi_slv_ext_w_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_w_rptr_o ( axi_slv_ext_w_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_r_data_o ( axi_slv_ext_r_data [SafetyIslandSlvIdx] ), - .async_axi_in_r_wptr_o ( axi_slv_ext_r_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_r_rptr_i ( axi_slv_ext_r_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_b_data_o ( axi_slv_ext_b_data [SafetyIslandSlvIdx] ), - .async_axi_in_b_wptr_o ( axi_slv_ext_b_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_b_rptr_i ( axi_slv_ext_b_rptr [SafetyIslandSlvIdx] ) - ); -end +// else begin : gen_no_safety_island +// assign jtag_safety_island_tdo_o = jtag_safety_island_tdi_i; +// cdc_dst_axi_err #( +// .AxiInIdWidth ( AxiSlvIdWidth ), +// .LogDepth ( LogDepth ), +// .CdcSyncStages ( SyncStages ), +// .axi_in_aw_chan_t ( carfield_axi_slv_aw_chan_t ), +// .axi_in_w_chan_t ( carfield_axi_slv_w_chan_t ), +// .axi_in_b_chan_t ( carfield_axi_slv_b_chan_t ), +// .axi_in_ar_chan_t ( carfield_axi_slv_ar_chan_t ), +// .axi_in_r_chan_t ( carfield_axi_slv_r_chan_t ), +// .axi_in_resp_t ( carfield_axi_slv_rsp_t ), +// .axi_in_req_t ( carfield_axi_slv_req_t ), +// .AsyncAxiInAwWidth ( CarfieldAxiSlvAwWidth ), +// .AsyncAxiInWWidth ( CarfieldAxiSlvWWidth ), +// .AsyncAxiInBWidth ( CarfieldAxiSlvBWidth ), +// .AsyncAxiInArWidth ( CarfieldAxiSlvArWidth ), +// .AsyncAxiInRWidth ( CarfieldAxiSlvRWidth ) +// ) i_safety_island_axi_err ( +// .clk_i ( safety_clk ), +// .rst_ni ( safety_rst_n ), +// .pwr_on_rst_ni ( safety_pwr_on_rst_n ), +// .async_axi_in_aw_data_i ( axi_slv_ext_aw_data [SafetyIslandSlvIdx] ), +// .async_axi_in_aw_wptr_i ( axi_slv_ext_aw_wptr [SafetyIslandSlvIdx] ), +// .async_axi_in_aw_rptr_o ( axi_slv_ext_aw_rptr [SafetyIslandSlvIdx] ), +// .async_axi_in_ar_data_i ( axi_slv_ext_ar_data [SafetyIslandSlvIdx] ), +// .async_axi_in_ar_wptr_i ( axi_slv_ext_ar_wptr [SafetyIslandSlvIdx] ), +// .async_axi_in_ar_rptr_o ( axi_slv_ext_ar_rptr [SafetyIslandSlvIdx] ), +// .async_axi_in_w_data_i ( axi_slv_ext_w_data [SafetyIslandSlvIdx] ), +// .async_axi_in_w_wptr_i ( axi_slv_ext_w_wptr [SafetyIslandSlvIdx] ), +// .async_axi_in_w_rptr_o ( axi_slv_ext_w_rptr [SafetyIslandSlvIdx] ), +// .async_axi_in_r_data_o ( axi_slv_ext_r_data [SafetyIslandSlvIdx] ), +// .async_axi_in_r_wptr_o ( axi_slv_ext_r_wptr [SafetyIslandSlvIdx] ), +// .async_axi_in_r_rptr_i ( axi_slv_ext_r_rptr [SafetyIslandSlvIdx] ), +// .async_axi_in_b_data_o ( axi_slv_ext_b_data [SafetyIslandSlvIdx] ), +// .async_axi_in_b_wptr_o ( axi_slv_ext_b_wptr [SafetyIslandSlvIdx] ), +// .async_axi_in_b_rptr_i ( axi_slv_ext_b_rptr [SafetyIslandSlvIdx] ) +// ); +// end // PULP integer cluster +if (CarfieldEnIslands.pulp) begin : gen_pulp_cluster logic pulpcl_mbox_intr; assign car_regs_hw2reg.pulp_cluster_eoc.de = 1'b1; assign car_regs_hw2reg.pulp_cluster_busy.de = 1'b1; assign car_regs_hw2reg.pulp_cluster_eoc.d = pulpcl_eoc; - -if (IslandsCfg.EnPulpCluster) begin : gen_pulp_cluster `ifndef INT_CLUSTER_NETLIST pulp_cluster #( .NB_CORES ( IntClusterNumCores ), @@ -1582,50 +1582,50 @@ int_cluster i_integer_cluster ( .async_data_master_b_rptr_o ( axi_mst_intcluster_b_rptr ) ); end -else begin : gen_no_pulp_cluster - cdc_dst_axi_err #( - .AxiInIdWidth ( IntClusterAxiIdInWidth ), - .LogDepth ( LogDepth ), - .CdcSyncStages ( SyncStages ), - .axi_in_aw_chan_t ( axi_intcluster_slv_aw_chan_t ), - .axi_in_w_chan_t ( axi_intcluster_slv_w_chan_t ), - .axi_in_b_chan_t ( axi_intcluster_slv_b_chan_t ), - .axi_in_ar_chan_t ( axi_intcluster_slv_ar_chan_t ), - .axi_in_r_chan_t ( axi_intcluster_slv_r_chan_t ), - .axi_in_resp_t ( axi_intcluster_slv_rsp_t ), - .axi_in_req_t ( axi_intcluster_slv_req_t ), - .AsyncAxiInAwWidth ( (2**LogDepth)*axi_pkg::aw_width(Cfg.AddrWidth,IntClusterAxiIdInWidth, - Cfg.AxiUserWidth)), - .AsyncAxiInWWidth ( (2**LogDepth)*axi_pkg::w_width(Cfg.AxiDataWidth,Cfg.AxiUserWidth) ), - .AsyncAxiInBWidth ( (2**LogDepth)*axi_pkg::b_width(IntClusterAxiIdInWidth,Cfg.AxiUserWidth) ), - .AsyncAxiInArWidth ( (2**LogDepth)*axi_pkg::ar_width(Cfg.AddrWidth,IntClusterAxiIdInWidth, - Cfg.AxiUserWidth)), - .AsyncAxiInRWidth ( (2**LogDepth)*axi_pkg::r_width(Cfg.AxiDataWidth,IntClusterAxiIdInWidth, - Cfg.AxiUserWidth)) - ) i_pulp_cluster_axi_err ( - .clk_i ( pulp_clk ), - .rst_ni ( pulp_rst_n ), - .pwr_on_rst_ni ( pulp_pwr_on_rst_n ), - .async_axi_in_aw_data_i ( axi_slv_intcluster_aw_data ), - .async_axi_in_aw_wptr_i ( axi_slv_intcluster_aw_wptr ), - .async_axi_in_aw_rptr_o ( axi_slv_intcluster_aw_rptr ), - .async_axi_in_ar_data_i ( axi_slv_intcluster_ar_data ), - .async_axi_in_ar_wptr_i ( axi_slv_intcluster_ar_wptr ), - .async_axi_in_ar_rptr_o ( axi_slv_intcluster_ar_rptr ), - .async_axi_in_w_data_i ( axi_slv_intcluster_w_data ), - .async_axi_in_w_wptr_i ( axi_slv_intcluster_w_wptr ), - .async_axi_in_w_rptr_o ( axi_slv_intcluster_w_rptr ), - .async_axi_in_r_data_o ( axi_slv_intcluster_r_data ), - .async_axi_in_r_wptr_o ( axi_slv_intcluster_r_wptr ), - .async_axi_in_r_rptr_i ( axi_slv_intcluster_r_rptr ), - .async_axi_in_b_data_o ( axi_slv_intcluster_b_data ), - .async_axi_in_b_wptr_o ( axi_slv_intcluster_b_wptr ), - .async_axi_in_b_rptr_i ( axi_slv_intcluster_b_rptr ) - ); -end +// else begin : gen_no_pulp_cluster +// cdc_dst_axi_err #( +// .AxiInIdWidth ( IntClusterAxiIdInWidth ), +// .LogDepth ( LogDepth ), +// .CdcSyncStages ( SyncStages ), +// .axi_in_aw_chan_t ( axi_intcluster_slv_aw_chan_t ), +// .axi_in_w_chan_t ( axi_intcluster_slv_w_chan_t ), +// .axi_in_b_chan_t ( axi_intcluster_slv_b_chan_t ), +// .axi_in_ar_chan_t ( axi_intcluster_slv_ar_chan_t ), +// .axi_in_r_chan_t ( axi_intcluster_slv_r_chan_t ), +// .axi_in_resp_t ( axi_intcluster_slv_rsp_t ), +// .axi_in_req_t ( axi_intcluster_slv_req_t ), +// .AsyncAxiInAwWidth ( (2**LogDepth)*axi_pkg::aw_width(Cfg.AddrWidth,IntClusterAxiIdInWidth, +// Cfg.AxiUserWidth)), +// .AsyncAxiInWWidth ( (2**LogDepth)*axi_pkg::w_width(Cfg.AxiDataWidth,Cfg.AxiUserWidth) ), +// .AsyncAxiInBWidth ( (2**LogDepth)*axi_pkg::b_width(IntClusterAxiIdInWidth,Cfg.AxiUserWidth) ), +// .AsyncAxiInArWidth ( (2**LogDepth)*axi_pkg::ar_width(Cfg.AddrWidth,IntClusterAxiIdInWidth, +// Cfg.AxiUserWidth)), +// .AsyncAxiInRWidth ( (2**LogDepth)*axi_pkg::r_width(Cfg.AxiDataWidth,IntClusterAxiIdInWidth, +// Cfg.AxiUserWidth)) +// ) i_pulp_cluster_axi_err ( +// .clk_i ( pulp_clk ), +// .rst_ni ( pulp_rst_n ), +// .pwr_on_rst_ni ( pulp_pwr_on_rst_n ), +// .async_axi_in_aw_data_i ( axi_slv_intcluster_aw_data ), +// .async_axi_in_aw_wptr_i ( axi_slv_intcluster_aw_wptr ), +// .async_axi_in_aw_rptr_o ( axi_slv_intcluster_aw_rptr ), +// .async_axi_in_ar_data_i ( axi_slv_intcluster_ar_data ), +// .async_axi_in_ar_wptr_i ( axi_slv_intcluster_ar_wptr ), +// .async_axi_in_ar_rptr_o ( axi_slv_intcluster_ar_rptr ), +// .async_axi_in_w_data_i ( axi_slv_intcluster_w_data ), +// .async_axi_in_w_wptr_i ( axi_slv_intcluster_w_wptr ), +// .async_axi_in_w_rptr_o ( axi_slv_intcluster_w_rptr ), +// .async_axi_in_r_data_o ( axi_slv_intcluster_r_data ), +// .async_axi_in_r_wptr_o ( axi_slv_intcluster_r_wptr ), +// .async_axi_in_r_rptr_i ( axi_slv_intcluster_r_rptr ), +// .async_axi_in_b_data_o ( axi_slv_intcluster_b_data ), +// .async_axi_in_b_wptr_o ( axi_slv_intcluster_b_wptr ), +// .async_axi_in_b_rptr_i ( axi_slv_intcluster_b_rptr ) +// ); +// end // Floating Point Spatz Cluster - +if (CarfieldEnIslands.spatz) begin : gen_spatz_cluster // Spatz cluster interrupts // msi (machine software interrupt): hostd, safed logic [spatz_cluster_pkg::NumCores-1:0] spatzcl_mbox_intr; @@ -1636,7 +1636,6 @@ logic [spatz_cluster_pkg::NumCores-1:0] spatzcl_timer_intr; assign spatzcl_timer_intr = { chs_mti[FPClusterIntrHart1Idx], chs_mti[FPClusterIntrHart0Idx] }; -if (IslandsCfg.EnSpatzCluster) begin : gen_spatz_cluster `ifndef FP_CLUSTER_NETLIST spatz_cluster_wrapper #( .AxiAddrWidth ( Cfg.AddrWidth ), @@ -1729,48 +1728,48 @@ if (IslandsCfg.EnSpatzCluster) begin : gen_spatz_cluster .cluster_probe_o ( car_regs_hw2reg.spatz_cluster_busy.d ) ); end -else begin : gen_no_spatz_cluster - cdc_dst_axi_err #( - .AxiInIdWidth ( AxiSlvIdWidth ), - .LogDepth ( LogDepth ), - .CdcSyncStages ( SyncStages ), - .axi_in_aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .axi_in_w_chan_t ( carfield_axi_slv_w_chan_t ), - .axi_in_b_chan_t ( carfield_axi_slv_b_chan_t ), - .axi_in_ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .axi_in_r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_in_resp_t ( carfield_axi_slv_rsp_t ), - .axi_in_req_t ( carfield_axi_slv_req_t ), - .AsyncAxiInAwWidth ( CarfieldAxiSlvAwWidth ), - .AsyncAxiInWWidth ( CarfieldAxiSlvWWidth ), - .AsyncAxiInBWidth ( CarfieldAxiSlvBWidth ), - .AsyncAxiInArWidth ( CarfieldAxiSlvArWidth ), - .AsyncAxiInRWidth ( CarfieldAxiSlvRWidth ) - ) i_spatz_cluster_axi_err ( - .clk_i ( spatz_clk ), - .rst_ni ( spatz_rst_n ), - .pwr_on_rst_ni ( spatz_pwr_on_rst_n ), - .async_axi_in_aw_data_i ( axi_slv_ext_aw_data [FPClusterSlvIdx] ), - .async_axi_in_aw_wptr_i ( axi_slv_ext_aw_wptr [FPClusterSlvIdx] ), - .async_axi_in_aw_rptr_o ( axi_slv_ext_aw_rptr [FPClusterSlvIdx] ), - .async_axi_in_ar_data_i ( axi_slv_ext_ar_data [FPClusterSlvIdx] ), - .async_axi_in_ar_wptr_i ( axi_slv_ext_ar_wptr [FPClusterSlvIdx] ), - .async_axi_in_ar_rptr_o ( axi_slv_ext_ar_rptr [FPClusterSlvIdx] ), - .async_axi_in_w_data_i ( axi_slv_ext_w_data [FPClusterSlvIdx] ), - .async_axi_in_w_wptr_i ( axi_slv_ext_w_wptr [FPClusterSlvIdx] ), - .async_axi_in_w_rptr_o ( axi_slv_ext_w_rptr [FPClusterSlvIdx] ), - .async_axi_in_r_data_o ( axi_slv_ext_r_data [FPClusterSlvIdx] ), - .async_axi_in_r_wptr_o ( axi_slv_ext_r_wptr [FPClusterSlvIdx] ), - .async_axi_in_r_rptr_i ( axi_slv_ext_r_rptr [FPClusterSlvIdx] ), - .async_axi_in_b_data_o ( axi_slv_ext_b_data [FPClusterSlvIdx] ), - .async_axi_in_b_wptr_o ( axi_slv_ext_b_wptr [FPClusterSlvIdx] ), - .async_axi_in_b_rptr_i ( axi_slv_ext_b_rptr [FPClusterSlvIdx] ) - ); -end +// else begin : gen_no_spatz_cluster +// cdc_dst_axi_err #( +// .AxiInIdWidth ( AxiSlvIdWidth ), +// .LogDepth ( LogDepth ), +// .CdcSyncStages ( SyncStages ), +// .axi_in_aw_chan_t ( carfield_axi_slv_aw_chan_t ), +// .axi_in_w_chan_t ( carfield_axi_slv_w_chan_t ), +// .axi_in_b_chan_t ( carfield_axi_slv_b_chan_t ), +// .axi_in_ar_chan_t ( carfield_axi_slv_ar_chan_t ), +// .axi_in_r_chan_t ( carfield_axi_slv_r_chan_t ), +// .axi_in_resp_t ( carfield_axi_slv_rsp_t ), +// .axi_in_req_t ( carfield_axi_slv_req_t ), +// .AsyncAxiInAwWidth ( CarfieldAxiSlvAwWidth ), +// .AsyncAxiInWWidth ( CarfieldAxiSlvWWidth ), +// .AsyncAxiInBWidth ( CarfieldAxiSlvBWidth ), +// .AsyncAxiInArWidth ( CarfieldAxiSlvArWidth ), +// .AsyncAxiInRWidth ( CarfieldAxiSlvRWidth ) +// ) i_spatz_cluster_axi_err ( +// .clk_i ( spatz_clk ), +// .rst_ni ( spatz_rst_n ), +// .pwr_on_rst_ni ( spatz_pwr_on_rst_n ), +// .async_axi_in_aw_data_i ( axi_slv_ext_aw_data [FPClusterSlvIdx] ), +// .async_axi_in_aw_wptr_i ( axi_slv_ext_aw_wptr [FPClusterSlvIdx] ), +// .async_axi_in_aw_rptr_o ( axi_slv_ext_aw_rptr [FPClusterSlvIdx] ), +// .async_axi_in_ar_data_i ( axi_slv_ext_ar_data [FPClusterSlvIdx] ), +// .async_axi_in_ar_wptr_i ( axi_slv_ext_ar_wptr [FPClusterSlvIdx] ), +// .async_axi_in_ar_rptr_o ( axi_slv_ext_ar_rptr [FPClusterSlvIdx] ), +// .async_axi_in_w_data_i ( axi_slv_ext_w_data [FPClusterSlvIdx] ), +// .async_axi_in_w_wptr_i ( axi_slv_ext_w_wptr [FPClusterSlvIdx] ), +// .async_axi_in_w_rptr_o ( axi_slv_ext_w_rptr [FPClusterSlvIdx] ), +// .async_axi_in_r_data_o ( axi_slv_ext_r_data [FPClusterSlvIdx] ), +// .async_axi_in_r_wptr_o ( axi_slv_ext_r_wptr [FPClusterSlvIdx] ), +// .async_axi_in_r_rptr_i ( axi_slv_ext_r_rptr [FPClusterSlvIdx] ), +// .async_axi_in_b_data_o ( axi_slv_ext_b_data [FPClusterSlvIdx] ), +// .async_axi_in_b_wptr_o ( axi_slv_ext_b_wptr [FPClusterSlvIdx] ), +// .async_axi_in_b_rptr_i ( axi_slv_ext_b_rptr [FPClusterSlvIdx] ) +// ); +// end // Security Island +if (CarfieldEnIslands.secured) begin : gen_secure_subsystem logic secd_mbox_intr; -if (IslandsCfg.EnOpenTitan) begin : gen_secure_subsystem `ifndef SECD_NETLIST secure_subsystem_synth_wrap #( .HartIdOffs ( OpnTitHartIdOffs ), @@ -2046,10 +2045,9 @@ mailbox_unit #( // Carfield peripherals // Ethernet // Peripheral Clock Domain +if (CarfieldEnIslands.ethernet) begin : gen_ethernet carfield_axi_slv_req_t axi_ethernet_req; carfield_axi_slv_rsp_t axi_ethernet_rsp; - -if (IslandsCfg.EnEthernet) begin : gen_ethernet axi_cdc_dst #( .LogDepth ( LogDepth ), .SyncStages ( SyncStages ), @@ -2223,63 +2221,62 @@ eth_rgmii #( ); end else begin : gen_no_ethernet - -axi_cdc_dst #( - .LogDepth ( LogDepth ), - .SyncStages ( SyncStages ), - .aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .w_chan_t ( carfield_axi_slv_w_chan_t ), - .b_chan_t ( carfield_axi_slv_b_chan_t ), - .ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_resp_t ( carfield_axi_slv_rsp_t ) -) i_ethernet_cdc_dst ( - .async_data_slave_aw_data_i ( axi_slv_ext_aw_data [EthernetSlvIdx] ), - .async_data_slave_aw_wptr_i ( axi_slv_ext_aw_wptr [EthernetSlvIdx] ), - .async_data_slave_aw_rptr_o ( axi_slv_ext_aw_rptr [EthernetSlvIdx] ), - .async_data_slave_w_data_i ( axi_slv_ext_w_data [EthernetSlvIdx] ), - .async_data_slave_w_wptr_i ( axi_slv_ext_w_wptr [EthernetSlvIdx] ), - .async_data_slave_w_rptr_o ( axi_slv_ext_w_rptr [EthernetSlvIdx] ), - .async_data_slave_b_data_o ( axi_slv_ext_b_data [EthernetSlvIdx] ), - .async_data_slave_b_wptr_o ( axi_slv_ext_b_wptr [EthernetSlvIdx] ), - .async_data_slave_b_rptr_i ( axi_slv_ext_b_rptr [EthernetSlvIdx] ), - .async_data_slave_ar_data_i ( axi_slv_ext_ar_data [EthernetSlvIdx] ), - .async_data_slave_ar_wptr_i ( axi_slv_ext_ar_wptr [EthernetSlvIdx] ), - .async_data_slave_ar_rptr_o ( axi_slv_ext_ar_rptr [EthernetSlvIdx] ), - .async_data_slave_r_data_o ( axi_slv_ext_r_data [EthernetSlvIdx] ), - .async_data_slave_r_wptr_o ( axi_slv_ext_r_wptr [EthernetSlvIdx] ), - .async_data_slave_r_rptr_i ( axi_slv_ext_r_rptr [EthernetSlvIdx] ), - .dst_clk_i ( periph_clk ), - .dst_rst_ni ( periph_rst_n ), - .dst_req_o ( axi_ethernet_req ), - .dst_resp_i ( axi_ethernet_rsp ) -); - -axi_err_slv #( - .AxiIdWidth ( AxiSlvIdWidth ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_resp_t ( carfield_axi_slv_rsp_t ), - .Resp ( axi_pkg::RESP_DECERR ), - .ATOPs ( 1'b0 ), - .MaxTrans ( 4 ) -) i_axi_err_slv_ethernet ( - .clk_i ( periph_clk ), - .rst_ni ( periph_pwr_on_rst_n ), - .test_i ( test_mode_i ), - // slave port - .slv_req_i ( axi_ethernet_req ), - .slv_resp_o ( axi_ethernet_rsp ) -); - -assign car_eth_intr = '0; -assign eth_md_o = '0; -assign eth_md_oe = '0; -assign eth_mdc_o = '0; -assign eth_rst_n_o = '0; -assign eth_txck_o = '0; -assign eth_txctl_o = '0; -assign eth_txd_o = '0; + + assign car_eth_intr = '0; + assign eth_md_o = '0; + assign eth_md_oe = '0; + assign eth_mdc_o = '0; + assign eth_rst_n_o = '0; + assign eth_txck_o = '0; + assign eth_txctl_o = '0; + assign eth_txd_o = '0; +// axi_cdc_dst #( +// .LogDepth ( LogDepth ), +// .SyncStages ( SyncStages ), +// .aw_chan_t ( carfield_axi_slv_aw_chan_t ), +// .w_chan_t ( carfield_axi_slv_w_chan_t ), +// .b_chan_t ( carfield_axi_slv_b_chan_t ), +// .ar_chan_t ( carfield_axi_slv_ar_chan_t ), +// .r_chan_t ( carfield_axi_slv_r_chan_t ), +// .axi_req_t ( carfield_axi_slv_req_t ), +// .axi_resp_t ( carfield_axi_slv_rsp_t ) +// ) i_ethernet_cdc_dst ( +// .async_data_slave_aw_data_i ( axi_slv_ext_aw_data [EthernetSlvIdx] ), +// .async_data_slave_aw_wptr_i ( axi_slv_ext_aw_wptr [EthernetSlvIdx] ), +// .async_data_slave_aw_rptr_o ( axi_slv_ext_aw_rptr [EthernetSlvIdx] ), +// .async_data_slave_w_data_i ( axi_slv_ext_w_data [EthernetSlvIdx] ), +// .async_data_slave_w_wptr_i ( axi_slv_ext_w_wptr [EthernetSlvIdx] ), +// .async_data_slave_w_rptr_o ( axi_slv_ext_w_rptr [EthernetSlvIdx] ), +// .async_data_slave_b_data_o ( axi_slv_ext_b_data [EthernetSlvIdx] ), +// .async_data_slave_b_wptr_o ( axi_slv_ext_b_wptr [EthernetSlvIdx] ), +// .async_data_slave_b_rptr_i ( axi_slv_ext_b_rptr [EthernetSlvIdx] ), +// .async_data_slave_ar_data_i ( axi_slv_ext_ar_data [EthernetSlvIdx] ), +// .async_data_slave_ar_wptr_i ( axi_slv_ext_ar_wptr [EthernetSlvIdx] ), +// .async_data_slave_ar_rptr_o ( axi_slv_ext_ar_rptr [EthernetSlvIdx] ), +// .async_data_slave_r_data_o ( axi_slv_ext_r_data [EthernetSlvIdx] ), +// .async_data_slave_r_wptr_o ( axi_slv_ext_r_wptr [EthernetSlvIdx] ), +// .async_data_slave_r_rptr_i ( axi_slv_ext_r_rptr [EthernetSlvIdx] ), +// .dst_clk_i ( periph_clk ), +// .dst_rst_ni ( periph_rst_n ), +// .dst_req_o ( axi_ethernet_req ), +// .dst_resp_i ( axi_ethernet_rsp ) +// ); +// +// axi_err_slv #( +// .AxiIdWidth ( AxiSlvIdWidth ), +// .axi_req_t ( carfield_axi_slv_req_t ), +// .axi_resp_t ( carfield_axi_slv_rsp_t ), +// .Resp ( axi_pkg::RESP_DECERR ), +// .ATOPs ( 1'b0 ), +// .MaxTrans ( 4 ) +// ) i_axi_err_slv_ethernet ( +// .clk_i ( periph_clk ), +// .rst_ni ( periph_pwr_on_rst_n ), +// .test_i ( test_mode_i ), +// // slave port +// .slv_req_i ( axi_ethernet_req ), +// .slv_resp_o ( axi_ethernet_rsp ) +// ); end diff --git a/hw/carfield_cfg_pkg.sv b/hw/carfield_cfg_pkg.sv new file mode 100644 index 000000000..1a8a302cb --- /dev/null +++ b/hw/carfield_cfg_pkg.sv @@ -0,0 +1,229 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +/// Configuration package +package carfield_cfg_pkg; + +import cheshire_pkg::*; + +// Structure where each field defines if an island +// is present or not. 1: present; 0: not present. +typedef struct packed { + bit l2; + bit l2_dualport; + bit safed; + bit ethernet; + bit periph; + bit spatz; + bit pulp; + bit secured; +} enable_islands_t; + +// Structure used to define the address range of each island. +// N.B. island_cfg_t and enable_islands_t structures could be +// packed into a single one. +typedef struct packed { + doub_bt l2_port0_base; + doub_bt l2_port1_base; + doub_bt l2_size; + doub_bt safed_base; + doub_bt safed_size; + doub_bt ethernet_base; + doub_bt ethernet_size; + doub_bt periph_base; + doub_bt periph_size; + doub_bt spatz_base; + doub_bt spatz_size; + doub_bt pulp_base; + doub_bt pulp_size; + doub_bt otmbox_base; + doub_bt otmbox_size; +} island_cfg_t; + +// Types are obtained from Cheshire package +// Parameter MaxExtAxiSlvWidth is obtained from Cheshire +// Structure used to create the AXI map to be passed to +// the Cheshire configuration parameter to create the +// AXI crossbar. +typedef struct packed { + byte_bt [2**MaxExtAxiSlvWidth-1:0] AxiIdx; + doub_bt [2**MaxExtAxiSlvWidth-1:0] AxiStart; + doub_bt [2**MaxExtAxiSlvWidth-1:0] AxiEnd; +} axi_struct_t; + +typedef struct packed { + byte_bt l2_port0; + byte_bt l2_port1; + byte_bt safed; + byte_bt ethernet; + byte_bt periph; + byte_bt spatz; + byte_bt pulp; + byte_bt mbox; +} carfield_slave_idx_t; + +typedef struct packed { + byte_bt safed; + byte_bt spatz; + byte_bt pulp; + byte_bt secured; +} carfield_master_idx_t; + +// TODO: specify this is for AXI +// Generate the number of AXI slave devices to be connected to the +// crossbar starting from the islands enable structure. +function automatic int unsigned gen_num_slave(enable_islands_t en); + int unsigned ret = 0; // Number of slaves starts from 0 + if (en.l2) begin + ret++; // If we enable L2, we increase by 1 + if (en.l2_dualport) + ret++; // If the L2 is dualport, increase again + end + if (en.safed ) begin ret++; end + if (en.periph ) begin ret++; end + if (en.ethernet) begin ret++; end + if (en.spatz ) begin ret++; end + if (en.pulp ) begin ret++; end + if (en.secured ) begin ret++; end + return ret; +endfunction + +// TODO: specify this is for AXI +// Generate the IDs for each AXI slave device +function automatic carfield_slave_idx_t carfield_gen_slave_idx(enable_islands_t en); + carfield_slave_idx_t ret = 0; // Initialize struct first + unsigned int i = 0; + if (en.l2) begin ret.l2_port0 = i; i++; + if (en.l2_dualport) begin ret.l2_port1 = i; i++; end + end + if (en.safed ) begin ret.safed = i; i++; end + if (en.ethernet) begin ret.ethernet = i; i++; end + if (en.periph ) begin ret.periph = i; i++; end + if (en.spatz ) begin ret.spatz = i; i++; end + if (en.pulp ) begin ret.pulp = i; i++; end + if (en.secured ) begin ret.mbox = i; i++; end + return ret; +endfunction + +// TODO: specify this is for AXI +// Generate the number of AXI master devices that connect to the +// crossbar starting from the islands enable structure. +function automatic int unsigned gen_num_master(enable_islands_t en); + int unsigned ret = 0; // Number of masters starts from 0 + if (en.safed ) begin ret++; end + if (en.spatz ) begin ret++; end + if (en.pulp ) begin ret++; end + if (en.secured) begin ret++; end + return ret; +endfunction + +// TODO: specify this is for AXI +// Generate the IDs for each AXI master device +function automatic carfield_master_idx_t carfield_gen_master_idx(enable_islands_t en); + carfield_master_idx_t ret = 0; // Initialize struct first + unsigned int i = 0; + if (en.safed ) begin ret.safed = i; i++; end + if (en.spatz ) begin ret.spatz = i; i++; end + if (en.pulp ) begin ret.pulp = i; i++; end + if (en.secured ) begin ret.secured = i; i++; end + return ret; +endfunction + +// Starting from the islands map and the islands enable structures, +// this function will generate structure to be passed for the +// generation or not of AXI crossbar ports for each slave. +function automatic axi_struct_t carfield_gen_axi_map(int unsigned NumSlave, enable_islands_t en_islands, island_cfg_t island_cfg); + axi_struct_t ret = '0; // Initialize the map first + int unsigned i = 0; + if (en_islands.l2) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.l2_port0_base; + ret.AxiEnd[i] = island_cfg.l2_port0_base + island_cfg.l2_size; + if (i < NumSlave - 1) i++; + if (en_islands.l2_dualport) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.l2_port1_base; + ret.AxiEnd[i] = island_cfg.l2_port1_base + island_cfg.l2_size; + if (i < NumSlave - 1) i++; + end + end + if (en_islands.safed) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.safed_base; + ret.AxiEnd[i] = island_cfg.safed_base + island_cfg.safed_size; + if (i < NumSlave - 1) i++; + end + if (en_islands.ethernet) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.ethernet_base; + ret.AxiEnd[i] = island_cfg.ethernet_base + island_cfg.ethernet_size; + if (i < NumSlave - 1) i++; + end + if (en_islands.periph) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.periph_base; + ret.AxiEnd[i] = island_cfg.periph_base + island_cfg.periph_size; + if (i < NumSlave - 1) i++; + end + if (en_islands.spatz) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.spatz_base; + ret.AxiEnd[i] = island_cfg.spatz_base + island_cfg.spatz_size; + if (i < NumSlave - 1) i++; + end + if (en_islands.pulp) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.pulp_base; + ret.AxiEnd[i] = island_cfg.pulp_base + island_cfg.pulp_size; + if (i < NumSlave - 1) i++; + end + if (en_islands.secured) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.otmbox_base; + ret.AxiEnd[i] = island_cfg.otmbox_base + island_cfg.otmbox_size; + if (i < NumSlave - 1) i++; + end + return ret; +endfunction + +localparam enable_islands_t CarfieldEnIslands = '{ + l2: 1, + l2_dualport: 1, + safed: 1, + ethernet: 0, + periph: 1, + spatz: 1, + pulp: 1, + secured: 1 +}; + +localparam island_cfg_t CarfieldIslandCfg = '{ + l2_port0_base: 'h78000000, + l2_port1_base: 'h78200000, + l2_size: 'h00200000, + safed_base: 'h60000000, + safed_size: 'h00800000, + ethernet_base: 'h20000000, + ethernet_size: 'h00001000, + periph_base: 'h20001000, + periph_size: 'h00009000, + spatz_base: 'h51000000, + spatz_size: 'h00800000, + pulp_base: 'h50000000, + pulp_size: 'h00800000, + otmbox_base: 'h40000000, + otmbox_size: 'h00001000 +}; + +// TODO: specify this is for AXI +localparam int unsigned CarfieldNumSlaves = gen_num_slave(CarfieldEnIslands); +localparam carfield_slave_idx_t CarfieldSlvIdx = carfield_gen_slave_idx(CarfieldEnIslands); +localparam int unsigned CarfieldNumMasters = gen_num_master(CarfieldEnIslands); +localparam carfield_master_idx_t CarfieldMstIdx = carfield_gen_master_idx(CarfieldEnIslands); + +localparam axi_struct_t CarfieldAxiMap = carfield_gen_axi_map(CarfieldNumSlaves, CarfieldEnIslands, CarfieldIslandCfg); + +endpackage diff --git a/hw/carfield_cfg_pkg_new.sv b/hw/carfield_cfg_pkg_new.sv new file mode 100644 index 000000000..0ff25add0 --- /dev/null +++ b/hw/carfield_cfg_pkg_new.sv @@ -0,0 +1,221 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +/// Configuration package +package carfield_cfg_pkg; + +import cheshire_pkg::*; + +typedef struct packed { + bit enable; + doub_bt addr_base; + doub_bt addr_size; +} islands_properties_t; + +typedef struct packed { + islands_properties_t l2_port0; + islands_properties_t l2_port1; + islands_properties_t safed; + islands_properties_t ethernet; + islands_properties_t periph; + islands_properties_t spatz; + islands_properties_t pulp; + islands_properties_t secured; +} islands_cfg_t; + +// Structure where each field defines if an island +// is present or not. 1: present; 0: not present. +typedef struct packed { + bit l2; + bit l2_dualport; + bit safed; + bit ethernet; + bit periph; + bit spatz; + bit pulp; + bit secured; +} enable_islands_t; + +// Structure used to define the address range of each island. +// N.B. island_cfg_t and enable_islands_t structures could be +// packed into a single one. +typedef struct packed { + doub_bt l2_port0_base; + doub_bt l2_port1_base; + doub_bt l2_size; + doub_bt safed_base; + doub_bt safed_size; + doub_bt ethernet_base; + doub_bt ethernet_size; + doub_bt periph_base; + doub_bt periph_size; + doub_bt spatz_base; + doub_bt spatz_size; + doub_bt pulp_base; + doub_bt pulp_size; + doub_bt otmbox_base; + doub_bt otmbox_size; +} island_cfg_t; + +// Types are obtained from Cheshire package +// Parameter MaxExtAxiSlvWidth is obtained from Cheshire +// Structure used to create the AXI map to be passed to +// the Cheshire configuration parameter to create the +// AXI crossbar. +typedef struct packed { + byte_bt [2**MaxExtAxiSlvWidth-1:0] AxiIdx; + doub_bt [2**MaxExtAxiSlvWidth-1:0] AxiStart; + doub_bt [2**MaxExtAxiSlvWidth-1:0] AxiEnd; +} axi_struct_t; + +// Generate the number of AXI slave devices to be connected to the +// crossbar starting from the islands enable structure. +function automatic int unsigned gen_num_slave(enable_islands_t en); + int unsigned ret = 0; // Number of slaves starts from 0 + if (en.l2) begin + ret++; // If we enable L2, we increase by 1 + if (en.l2_dualport) + ret++; // If the L2 is dualport, increase again + end + if (en.safed ) begin ret++; end + if (en.periph ) begin ret++; end + if (en.ethernet) begin ret++; end + if (en.spatz ) begin ret++; end + if (en.pulp ) begin ret++; end + if (en.secured ) begin ret++; end + return ret; +endfunction + +// Generate the number of AXI master devices that connect to the +// crossbar starting from the islands enable structure. +function automatic int unsigned gen_num_master(enable_islands_t en); + int unsigned ret = 0; // Number of masters starts from 0 + if (en.safed ) begin ret++; end + if (en.spatz ) begin ret++; end + if (en.pulp ) begin ret++; end + if (en.secured) begin ret++; end + return ret; +endfunction + +// Starting from the islands map and the islands enable structures, +// this function will generate structure to be passed for the +// generation or not of AXI crossbar ports for each slave. +function automatic axi_struct_t carfield_gen_axi_map(int unsigned NumSlave, enable_islands_t en_islands, island_cfg_t island_cfg); + axi_struct_t ret = '0; // Initialize the map first + int unsigned i = 0; + if (en_islands.l2) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.l2_port0_base; + ret.AxiEnd[i] = island_cfg.l2_port0_base + island_cfg.l2_size; + if (i < NumSlave - 1) i++; + if (en_islands.l2_dualport) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.l2_port1_base; + ret.AxiEnd[i] = island_cfg.l2_port1_base + island_cfg.l2_size; + if (i < NumSlave - 1) i++; + end + end + if (en_islands.safed) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.safed_base; + ret.AxiEnd[i] = island_cfg.safed_base + island_cfg.safed_size; + if (i < NumSlave - 1) i++; + end + if (en_islands.ethernet) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.ethernet_base; + ret.AxiEnd[i] = island_cfg.ethernet_base + island_cfg.ethernet_size; + if (i < NumSlave - 1) i++; + end + if (en_islands.periph) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.periph_base; + ret.AxiEnd[i] = island_cfg.periph_base + island_cfg.periph_size; + if (i < NumSlave - 1) i++; + end + if (en_islands.spatz) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.spatz_base; + ret.AxiEnd[i] = island_cfg.spatz_base + island_cfg.spatz_size; + if (i < NumSlave - 1) i++; + end + if (en_islands.pulp) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.pulp_base; + ret.AxiEnd[i] = island_cfg.pulp_base + island_cfg.pulp_size; + if (i < NumSlave - 1) i++; + end + if (en_islands.secured) begin + ret.AxiIdx[i] = i; + ret.AxiStart[i] = island_cfg.otmbox_base; + ret.AxiEnd[i] = island_cfg.otmbox_base + island_cfg.otmbox_size; + if (i < NumSlave - 1) i++; + end + return ret; +endfunction + +localparam enable_islands_t CarfieldEnIslands = '{ + l2: 1, + l2_dualport: 1, + safed: 1, + ethernet: 0, + periph: 1, + spatz: 1, + pulp: 1, + secured: 1 +}; + +localparam island_cfg_t CarfieldIslandCfg = '{ + l2_port0_base: 'h78000000, + l2_port1_base: 'h78200000, + l2_size: 'h00200000, + safed_base: 'h60000000, + safed_size: 'h00800000, + ethernet_base: 'h20000000, + ethernet_size: 'h00001000, + periph_base: 'h20001000, + periph_size: 'h00009000, + spatz_base: 'h51000000, + spatz_size: 'h00800000, + pulp_base: 'h50000000, + pulp_size: 'h00800000, + otmbox_base: 'h40000000, + otmbox_size: 'h00001000 +}; + +localparam islands_cfg_t CarfieldIslandsCfg = '{ + l2_port0.enable : 1, + l2_port0.addr_base: 'h78000000, + l2_port0.addr_size: 'h00200000, + l2_port1.enable : 1, + l2_port1.addr_base: 'h78200000, + l2_port1.addr_size: 'h00200000, + safed.enable : 1, + safed.addr_base: 'h60000000, + safed.addr_size: 'h00800000, + ethernet.enable : 1, + ethernet.addr_base: 'h20000000, + ethernet.addr_size: 'h00001000, + periph.enable : 1, + periph.addr_base: 'h20010000, + periph.addr_size: 'h00009000, + spatz.enable : 1, + spatz.addr_base: 'h51000000, + spatz.addr_size: 'h00800000, + pulp.enable : 1, + pulp.addr_base: 'h50000000, + pulp.addr_size: 'h00800000, + secured.enable : 1, + secured.addr_base: 'h40000000, + secured.addr_size: 'h00001000 +}; + +localparam int unsigned CarfieldNumSlaves = gen_num_slave(CarfieldEnIslands); +localparam int unsigned CarfieldNumMasters = gen_num_master(CarfieldEnIslands); + +localparam axi_struct_t CarfieldAxiMap = carfield_gen_axi_map(CarfieldNumSlaves, CarfieldEnIslands, CarfieldIslandCfg); + +endpackage diff --git a/hw/carfield_pkg.sv b/hw/carfield_pkg.sv index 4c3d64790..206e1a377 100644 --- a/hw/carfield_pkg.sv +++ b/hw/carfield_pkg.sv @@ -12,6 +12,7 @@ package carfield_pkg; import cheshire_pkg::*; +import carfield_cfg_pkg::*; localparam int unsigned CarfieldNumExtIntrs = 32; // Number of external interrupts localparam int unsigned CarfieldNumInterruptibleHarts = 2; // Spatz (2 Snitch cores) @@ -294,34 +295,13 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{ RegAmoNumCuts : 1, RegAmoPostCut : 1, // External AXI ports (at most 8 ports and rules) - AxiExtNumMst : AxiNumExtMst, - AxiExtNumSlv : AxiNumExtSlv, - AxiExtNumRules : AxiNumExtSlv, + AxiExtNumMst : CarfieldNumMasters, + AxiExtNumSlv : CarfieldNumSlaves, + AxiExtNumRules : CarfieldNumSlaves, // External AXI region map - AxiExtRegionIdx : '{0, 0, 0, 0, 0, 0, 0, 0, MailboxSlvIdx , - IntClusterSlvIdx , - FPClusterSlvIdx , - PeriphsSlvIdx , - EthernetSlvIdx , - SafetyIslandSlvIdx, - L2Port1SlvIdx , - L2Port0SlvIdx }, - AxiExtRegionStart : '{0, 0, 0, 0, 0, 0, 0, 0, MailboxBase , - IntClusterBase , - FPClusterBase , - PeriphsBase , - EthernetBase , - SafetyIslandBase, - L2Port1Base , - L2Port0Base }, - AxiExtRegionEnd : '{0, 0, 0, 0, 0, 0, 0, 0, MailboxEnd , - IntClusterEnd , - FPClusterEnd , - PeriphsEnd , - EthernetEnd , - SafetyIslandEnd, - L2Port1End , - L2Port0End }, + AxiExtRegionIdx: CarfieldAxiMap.AxiIdx, + AxiExtRegionStart: CarfieldAxiMap.AxiStart, + AxiExtRegionEnd: CarfieldAxiMap.AxiEnd, // External reg slaves (at most 8 ports and rules) RegExtNumSlv : NumTotalRegSlv, RegExtNumRules : NumTotalRegRules, @@ -412,22 +392,12 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{ // Control which island to add typedef struct packed { - bit EnPulpCluster; - bit EnSafetyIsland; - bit EnSpatzCluster; - bit EnOpenTitan; bit EnCan; - bit EnEthernet; } islands_cfg_t; // Enable all islands by default localparam islands_cfg_t IslandsCfgDefault = '{ - EnPulpCluster : 1, - EnSafetyIsland : 1, - EnSpatzCluster : 1, - EnOpenTitan : 1, EnCan : 1, - EnEthernet : 0, default : '1 }; diff --git a/hw/cheshire_wrap.sv b/hw/cheshire_wrap.sv index 9b3e7c445..bac2d15c4 100644 --- a/hw/cheshire_wrap.sv +++ b/hw/cheshire_wrap.sv @@ -7,11 +7,12 @@ // Alessandro Ottaviano `include "cheshire/typedef.svh" - `include "axi/typedef.svh" - `include "axi/assign.svh" +`include "axi/typedef.svh" +`include "axi/assign.svh" module cheshire_wrap import axi_pkg::*; + import carfield_cfg_pkg::*; import carfield_pkg::*; import cheshire_pkg::*; #( @@ -340,8 +341,8 @@ cheshire_axi_ext_llc_req_t axi_llc_mst_req, axi_llc_mst_isolated_req; cheshire_axi_ext_llc_rsp_t axi_llc_mst_rsp, axi_llc_mst_isolated_rsp; // Feedthrough mailbox req/rsp: same clock domain of cheshire (no CDCs) -`AXI_ASSIGN_REQ_STRUCT(axi_mbox_slv_req_o, axi_ext_slv_req[MailboxSlvIdx]) -`AXI_ASSIGN_RESP_STRUCT(axi_ext_slv_rsp[MailboxSlvIdx], axi_mbox_slv_rsp_i) +`AXI_ASSIGN_REQ_STRUCT(axi_mbox_slv_req_o, axi_ext_slv_req[CarfieldSlvIdx.mbox]) +`AXI_ASSIGN_RESP_STRUCT(axi_ext_slv_rsp[CarfieldSlvIdx.mbox], axi_mbox_slv_rsp_i) cheshire_reg_ext_req_t [iomsb(Cfg.RegExtNumSlv):0] ext_reg_req; cheshire_reg_ext_rsp_t [iomsb(Cfg.RegExtNumSlv):0] ext_reg_rsp; @@ -500,7 +501,7 @@ for (genvar i = 0; i < Cfg.AxiExtNumSlv - 2; i++) begin: gen_ext_slv_src_cdc end -// Cheshire's AXI slave cdc and isolate generation, except for the Integer Cluster (slave 7) +// Cheshire's AXI slave cdc and isolate generation, except for the Integer Cluster (master 3) for (genvar i = 0; i < Cfg.AxiExtNumMst - 1; i++) begin: gen_ext_mst_dst_cdc axi_cdc_dst #( .LogDepth ( LogDepth ), @@ -594,137 +595,158 @@ axi_cdc_src #( ); // Integer Cluster slave bus -axi_intcluster_slv_req_t axi_intcluster_ser_slv_req, axi_intcluster_ser_isolated_slv_req; -axi_intcluster_slv_rsp_t axi_intcluster_ser_slv_rsp, axi_intcluster_ser_isolated_slv_rsp; +if (CarfieldEnIslands.pulp) begin: gen_pulp_connection + axi_intcluster_slv_req_t axi_intcluster_ser_slv_req, axi_intcluster_ser_isolated_slv_req; + axi_intcluster_slv_rsp_t axi_intcluster_ser_slv_rsp, axi_intcluster_ser_isolated_slv_rsp; -axi_id_remap #( - .AxiSlvPortIdWidth ( ExtSlvIdWidth ), - .AxiSlvPortMaxUniqIds ( IntClusterMaxUniqId ), - .AxiMaxTxnsPerId ( Cfg.AxiMaxSlvTrans ), - .AxiMstPortIdWidth ( IntClusterAxiIdInWidth ), - .slv_req_t ( cheshire_axi_ext_slv_req_t ), - .slv_resp_t ( cheshire_axi_ext_slv_rsp_t ), - .mst_req_t ( axi_intcluster_slv_req_t ), - .mst_resp_t ( axi_intcluster_slv_rsp_t ) -) i_integer_cluster_axi_slv_id_remap ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( axi_ext_slv_req[IntClusterSlvIdx] ), - .slv_resp_o ( axi_ext_slv_rsp[IntClusterSlvIdx] ), - .mst_req_o ( axi_intcluster_ser_slv_req ), - .mst_resp_i ( axi_intcluster_ser_slv_rsp ) -); + axi_id_remap #( + .AxiSlvPortIdWidth ( ExtSlvIdWidth ), + .AxiSlvPortMaxUniqIds ( IntClusterMaxUniqId ), + .AxiMaxTxnsPerId ( Cfg.AxiMaxSlvTrans ), + .AxiMstPortIdWidth ( IntClusterAxiIdInWidth ), + .slv_req_t ( cheshire_axi_ext_slv_req_t ), + .slv_resp_t ( cheshire_axi_ext_slv_rsp_t ), + .mst_req_t ( axi_intcluster_slv_req_t ), + .mst_resp_t ( axi_intcluster_slv_rsp_t ) + ) i_integer_cluster_axi_slv_id_remap ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( axi_ext_slv_req[CarfieldSlvIdx.pulp] ), + .slv_resp_o ( axi_ext_slv_rsp[CarfieldSlvIdx.pulp] ), + .mst_req_o ( axi_intcluster_ser_slv_req ), + .mst_resp_i ( axi_intcluster_ser_slv_rsp ) + ); -axi_isolate #( - .NumPending ( Cfg.AxiMaxSlvTrans ), - .TerminateTransaction ( 1 ), - .AtopSupport ( 1 ), - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiIdWidth ( IntClusterAxiIdInWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .axi_req_t ( axi_intcluster_slv_req_t ), - .axi_resp_t ( axi_intcluster_slv_rsp_t ) -) i_axi_intcluster_isolate ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( axi_intcluster_ser_slv_req ), - .slv_resp_o ( axi_intcluster_ser_slv_rsp ), - .mst_req_o ( axi_intcluster_ser_isolated_slv_req ), - .mst_resp_i ( axi_intcluster_ser_isolated_slv_rsp ), - .isolate_i ( axi_ext_slv_isolate_i [IntClusterSlvIdx] ), - .isolated_o ( axi_ext_slv_isolated_o[IntClusterSlvIdx] ) -); + axi_isolate #( + .NumPending ( Cfg.AxiMaxSlvTrans ), + .TerminateTransaction ( 1 ), + .AtopSupport ( 1 ), + .AxiAddrWidth ( Cfg.AddrWidth ), + .AxiDataWidth ( Cfg.AxiDataWidth ), + .AxiIdWidth ( IntClusterAxiIdInWidth ), + .AxiUserWidth ( Cfg.AxiUserWidth ), + .axi_req_t ( axi_intcluster_slv_req_t ), + .axi_resp_t ( axi_intcluster_slv_rsp_t ) + ) i_axi_intcluster_isolate ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( axi_intcluster_ser_slv_req ), + .slv_resp_o ( axi_intcluster_ser_slv_rsp ), + .mst_req_o ( axi_intcluster_ser_isolated_slv_req ), + .mst_resp_i ( axi_intcluster_ser_isolated_slv_rsp ), + .isolate_i ( axi_ext_slv_isolate_i [CarfieldSlvIdx.pulp] ), + .isolated_o ( axi_ext_slv_isolated_o[CarfieldSlvIdx.pulp] ) + ); -axi_cdc_src #( - .LogDepth ( LogDepth ), - .SyncStages ( CdcSyncStages ), - .aw_chan_t ( axi_intcluster_slv_aw_chan_t ), - .w_chan_t ( axi_intcluster_slv_w_chan_t ), - .b_chan_t ( axi_intcluster_slv_b_chan_t ), - .ar_chan_t ( axi_intcluster_slv_ar_chan_t ), - .r_chan_t ( axi_intcluster_slv_r_chan_t ), - .axi_req_t ( axi_intcluster_slv_req_t ), - .axi_resp_t ( axi_intcluster_slv_rsp_t ) -) i_intcluster_slv_cdc ( - // synchronous slave port - .src_clk_i ( clk_i ), - .src_rst_ni ( rst_ni ), - .src_req_i ( axi_intcluster_ser_isolated_slv_req ), - .src_resp_o ( axi_intcluster_ser_isolated_slv_rsp ), - // asynchronous master port - .async_data_master_aw_data_o ( axi_slv_intcluster_aw_data_o ), - .async_data_master_aw_wptr_o ( axi_slv_intcluster_aw_wptr_o ), - .async_data_master_aw_rptr_i ( axi_slv_intcluster_aw_rptr_i ), - .async_data_master_w_data_o ( axi_slv_intcluster_w_data_o ), - .async_data_master_w_wptr_o ( axi_slv_intcluster_w_wptr_o ), - .async_data_master_w_rptr_i ( axi_slv_intcluster_w_rptr_i ), - .async_data_master_b_data_i ( axi_slv_intcluster_b_data_i ), - .async_data_master_b_wptr_i ( axi_slv_intcluster_b_wptr_i ), - .async_data_master_b_rptr_o ( axi_slv_intcluster_b_rptr_o ), - .async_data_master_ar_data_o ( axi_slv_intcluster_ar_data_o ), - .async_data_master_ar_wptr_o ( axi_slv_intcluster_ar_wptr_o ), - .async_data_master_ar_rptr_i ( axi_slv_intcluster_ar_rptr_i ), - .async_data_master_r_data_i ( axi_slv_intcluster_r_data_i ), - .async_data_master_r_wptr_i ( axi_slv_intcluster_r_wptr_i ), - .async_data_master_r_rptr_o ( axi_slv_intcluster_r_rptr_o ) -); + axi_cdc_src #( + .LogDepth ( LogDepth ), + .SyncStages ( CdcSyncStages ), + .aw_chan_t ( axi_intcluster_slv_aw_chan_t ), + .w_chan_t ( axi_intcluster_slv_w_chan_t ), + .b_chan_t ( axi_intcluster_slv_b_chan_t ), + .ar_chan_t ( axi_intcluster_slv_ar_chan_t ), + .r_chan_t ( axi_intcluster_slv_r_chan_t ), + .axi_req_t ( axi_intcluster_slv_req_t ), + .axi_resp_t ( axi_intcluster_slv_rsp_t ) + ) i_intcluster_slv_cdc ( + // synchronous slave port + .src_clk_i ( clk_i ), + .src_rst_ni ( rst_ni ), + .src_req_i ( axi_intcluster_ser_isolated_slv_req ), + .src_resp_o ( axi_intcluster_ser_isolated_slv_rsp ), + // asynchronous master port + .async_data_master_aw_data_o ( axi_slv_intcluster_aw_data_o ), + .async_data_master_aw_wptr_o ( axi_slv_intcluster_aw_wptr_o ), + .async_data_master_aw_rptr_i ( axi_slv_intcluster_aw_rptr_i ), + .async_data_master_w_data_o ( axi_slv_intcluster_w_data_o ), + .async_data_master_w_wptr_o ( axi_slv_intcluster_w_wptr_o ), + .async_data_master_w_rptr_i ( axi_slv_intcluster_w_rptr_i ), + .async_data_master_b_data_i ( axi_slv_intcluster_b_data_i ), + .async_data_master_b_wptr_i ( axi_slv_intcluster_b_wptr_i ), + .async_data_master_b_rptr_o ( axi_slv_intcluster_b_rptr_o ), + .async_data_master_ar_data_o ( axi_slv_intcluster_ar_data_o ), + .async_data_master_ar_wptr_o ( axi_slv_intcluster_ar_wptr_o ), + .async_data_master_ar_rptr_i ( axi_slv_intcluster_ar_rptr_i ), + .async_data_master_r_data_i ( axi_slv_intcluster_r_data_i ), + .async_data_master_r_wptr_i ( axi_slv_intcluster_r_wptr_i ), + .async_data_master_r_rptr_o ( axi_slv_intcluster_r_rptr_o ) + ); -// Integer Cluster master bus -axi_intcluster_mst_req_t axi_intcluster_ser_mst_req; -axi_intcluster_mst_rsp_t axi_intcluster_ser_mst_rsp; + // Integer Cluster master bus + axi_intcluster_mst_req_t axi_intcluster_ser_mst_req; + axi_intcluster_mst_rsp_t axi_intcluster_ser_mst_rsp; -axi_cdc_dst #( - .LogDepth ( LogDepth ), - .SyncStages ( CdcSyncStages ), - .aw_chan_t ( axi_intcluster_mst_aw_chan_t ), - .w_chan_t ( axi_intcluster_mst_w_chan_t ), - .b_chan_t ( axi_intcluster_mst_b_chan_t ), - .ar_chan_t ( axi_intcluster_mst_ar_chan_t ), - .r_chan_t ( axi_intcluster_mst_r_chan_t ), - .axi_req_t ( axi_intcluster_mst_req_t ), - .axi_resp_t ( axi_intcluster_mst_rsp_t ) -) i_intcluster_mst_cdc ( - // asynchronous slave port - .async_data_slave_aw_data_i ( axi_mst_intcluster_aw_data_i ), - .async_data_slave_aw_wptr_i ( axi_mst_intcluster_aw_wptr_i ), - .async_data_slave_aw_rptr_o ( axi_mst_intcluster_aw_rptr_o ), - .async_data_slave_w_data_i ( axi_mst_intcluster_w_data_i ), - .async_data_slave_w_wptr_i ( axi_mst_intcluster_w_wptr_i ), - .async_data_slave_w_rptr_o ( axi_mst_intcluster_w_rptr_o ), - .async_data_slave_b_data_o ( axi_mst_intcluster_b_data_o ), - .async_data_slave_b_wptr_o ( axi_mst_intcluster_b_wptr_o ), - .async_data_slave_b_rptr_i ( axi_mst_intcluster_b_rptr_i ), - .async_data_slave_ar_data_i ( axi_mst_intcluster_ar_data_i ), - .async_data_slave_ar_wptr_i ( axi_mst_intcluster_ar_wptr_i ), - .async_data_slave_ar_rptr_o ( axi_mst_intcluster_ar_rptr_o ), - .async_data_slave_r_data_o ( axi_mst_intcluster_r_data_o ), - .async_data_slave_r_wptr_o ( axi_mst_intcluster_r_wptr_o ), - .async_data_slave_r_rptr_i ( axi_mst_intcluster_r_rptr_i ), - // synchronous master port - .dst_clk_i ( clk_i ), - .dst_rst_ni ( rst_ni ), - .dst_req_o ( axi_intcluster_ser_mst_req ), - .dst_resp_i ( axi_intcluster_ser_mst_rsp ) -); + axi_cdc_dst #( + .LogDepth ( LogDepth ), + .SyncStages ( CdcSyncStages ), + .aw_chan_t ( axi_intcluster_mst_aw_chan_t ), + .w_chan_t ( axi_intcluster_mst_w_chan_t ), + .b_chan_t ( axi_intcluster_mst_b_chan_t ), + .ar_chan_t ( axi_intcluster_mst_ar_chan_t ), + .r_chan_t ( axi_intcluster_mst_r_chan_t ), + .axi_req_t ( axi_intcluster_mst_req_t ), + .axi_resp_t ( axi_intcluster_mst_rsp_t ) + ) i_intcluster_mst_cdc ( + // asynchronous slave port + .async_data_slave_aw_data_i ( axi_mst_intcluster_aw_data_i ), + .async_data_slave_aw_wptr_i ( axi_mst_intcluster_aw_wptr_i ), + .async_data_slave_aw_rptr_o ( axi_mst_intcluster_aw_rptr_o ), + .async_data_slave_w_data_i ( axi_mst_intcluster_w_data_i ), + .async_data_slave_w_wptr_i ( axi_mst_intcluster_w_wptr_i ), + .async_data_slave_w_rptr_o ( axi_mst_intcluster_w_rptr_o ), + .async_data_slave_b_data_o ( axi_mst_intcluster_b_data_o ), + .async_data_slave_b_wptr_o ( axi_mst_intcluster_b_wptr_o ), + .async_data_slave_b_rptr_i ( axi_mst_intcluster_b_rptr_i ), + .async_data_slave_ar_data_i ( axi_mst_intcluster_ar_data_i ), + .async_data_slave_ar_wptr_i ( axi_mst_intcluster_ar_wptr_i ), + .async_data_slave_ar_rptr_o ( axi_mst_intcluster_ar_rptr_o ), + .async_data_slave_r_data_o ( axi_mst_intcluster_r_data_o ), + .async_data_slave_r_wptr_o ( axi_mst_intcluster_r_wptr_o ), + .async_data_slave_r_rptr_i ( axi_mst_intcluster_r_rptr_i ), + // synchronous master port + .dst_clk_i ( clk_i ), + .dst_rst_ni ( rst_ni ), + .dst_req_o ( axi_intcluster_ser_mst_req ), + .dst_resp_i ( axi_intcluster_ser_mst_rsp ) + ); -axi_id_remap #( - .AxiSlvPortIdWidth ( IntClusterAxiIdOutWidth ), - .AxiSlvPortMaxUniqIds ( IntClusterMaxUniqId ), - .AxiMaxTxnsPerId ( Cfg.AxiMaxMstTrans ), - .AxiMstPortIdWidth ( Cfg.AxiMstIdWidth ), - .slv_req_t ( axi_intcluster_mst_req_t ), - .slv_resp_t ( axi_intcluster_mst_rsp_t ), - .mst_req_t ( cheshire_axi_ext_mst_req_t ), - .mst_resp_t ( cheshire_axi_ext_mst_rsp_t ) -) i_integer_cluster_axi_mst_id_remap ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( axi_intcluster_ser_mst_req ), - .slv_resp_o ( axi_intcluster_ser_mst_rsp ), - .mst_req_o ( axi_ext_mst_req[IntClusterMstIdx] ), - .mst_resp_i ( axi_ext_mst_rsp[IntClusterMstIdx] ) -); + axi_id_remap #( + .AxiSlvPortIdWidth ( IntClusterAxiIdOutWidth ), + .AxiSlvPortMaxUniqIds ( IntClusterMaxUniqId ), + .AxiMaxTxnsPerId ( Cfg.AxiMaxMstTrans ), + .AxiMstPortIdWidth ( Cfg.AxiMstIdWidth ), + .slv_req_t ( axi_intcluster_mst_req_t ), + .slv_resp_t ( axi_intcluster_mst_rsp_t ), + .mst_req_t ( cheshire_axi_ext_mst_req_t ), + .mst_resp_t ( cheshire_axi_ext_mst_rsp_t ) + ) i_integer_cluster_axi_mst_id_remap ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( axi_intcluster_ser_mst_req ), + .slv_resp_o ( axi_intcluster_ser_mst_rsp ), + .mst_req_o ( axi_ext_mst_req[CarfieldMstIdx.pulp] ), + .mst_resp_i ( axi_ext_mst_rsp[CarfieldMstIdx.pulp] ) + ); +end else begin: gen_no_pulp_connections + // Tie to 0 all PULP cluster output ports. + // Slave + assign axi_slv_intcluster_aw_data_o = '0; + assign axi_slv_intcluster_aw_wptr_o = '0; + assign axi_slv_intcluster_w_data_o = '0; + assign axi_slv_intcluster_w_wptr_o = '0; + assign axi_slv_intcluster_b_rptr_o = '0; + assign axi_slv_intcluster_ar_data_o = '0; + assign axi_slv_intcluster_ar_wptr_o = '0; + assign axi_slv_intcluster_r_rptr_o = '0; + // Master + assign axi_mst_intcluster_aw_rptr_o = '0; + assign axi_mst_intcluster_w_rptr_o = '0; + assign axi_mst_intcluster_b_data_o = '0; + assign axi_mst_intcluster_b_wptr_o = '0; + assign axi_mst_intcluster_ar_rptr_o = '0; + assign axi_mst_intcluster_r_data_o = '0; + assign axi_mst_intcluster_r_wptr_o = '0; +end // Async reg interface: // See carfield_pkg.sv for indices referring to sync and async reg interfaces.