SC succeeds after previously failed SC

[maxbjurling]

The RISC-V spec states:

An SC may succeed only if no store from another hart to the reservation set can be observed to have occurred between the LR and the SC, and if there is no other SC between the LR and itself in program order.

However, with the following sequence applied (from a single hart):

AMO.LR  AddrA
AMO.SC  AddrB  // fails -> OK
AMO.SC  AddrA  // succeeds -> NOT OK

, the last SC operation succeeds, even though there is another SC operation before it.

[maxbjurling]

This bug is triggered in a dcache unit test in the cva6 repository. To reproduce, check out this branch of cva6 and do:

$ cd corev_apu/tb/tb_wb_dcache
$ make simc # or 'make sim' for GUI

simulation output:

...
# AMO0> vector:  0 -   7426 -- paddr:   0000000000000028 -- AMO: 0x02 -- size: 00000004  -- op_a: 0000000000000028 -- op_b: ad747a8d68ccca9c
# AMO0> vector:  0 -   7426 -- exp_res: 0000000000000001 -- exp_mem: 2ac1cd55aac446d4
# AMO0> vector:  0 -   7426 -- result:  0000000000000000 -- memory: 2ac1cd5568ccca9c
# ** Error: AMO0> simulation stopped (ERROR_CNT_STOP_LEVEL =           1 reached).

[SamuelRiedel]

Thanks a lot for discovering this @maxbjurling. We will look into fixing this.