diff --git a/hardware/include/ara_pkg.sv b/hardware/include/ara_pkg.sv index a98c31822..d50e6b9e6 100644 --- a/hardware/include/ara_pkg.sv +++ b/hardware/include/ara_pkg.sv @@ -289,19 +289,6 @@ package ara_pkg; fp64_from_fp32 = fp64; endfunction - //////////////////// - // CVA6 commons // - //////////////////// - - // Definitions common to CVA6 - typedef cva6_config_pkg::exception_t exception_t; - typedef cva6_config_pkg::accelerator_req_t accelerator_req_t; - typedef cva6_config_pkg::accelerator_resp_t accelerator_resp_t; - typedef cva6_config_pkg::acc_mmu_req_t acc_mmu_req_t; - typedef cva6_config_pkg::acc_mmu_resp_t acc_mmu_resp_t; - typedef cva6_config_pkg::cva6_to_acc_t cva6_to_acc_t; - typedef cva6_config_pkg::acc_to_cva6_t acc_to_cva6_t; - //////////////////// // PE interface // //////////////////// diff --git a/hardware/src/ara.sv b/hardware/src/ara.sv index 6fbd1a530..ecfaba69c 100644 --- a/hardware/src/ara.sv +++ b/hardware/src/ara.sv @@ -19,6 +19,14 @@ module ara import ara_pkg::*; #( parameter fixpt_support_e FixPtSupport = FixedPointEnable, // CVA6 configuration parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg, + // CVA6-related parameters + parameter type exception_t = logic, + parameter type accelerator_req_t = logic, + parameter type accelerator_resp_t = logic, + parameter type acc_mmu_req_t = logic, + parameter type acc_mmu_resp_t = logic, + parameter type cva6_to_acc_t = logic, + parameter type acc_to_cva6_t = logic, // AXI Interface parameter int unsigned AxiDataWidth = 0, parameter int unsigned AxiAddrWidth = 0, diff --git a/hardware/src/ara_soc.sv b/hardware/src/ara_soc.sv index 70512a444..c780e5c95 100644 --- a/hardware/src/ara_soc.sv +++ b/hardware/src/ara_soc.sv @@ -56,6 +56,7 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( `include "axi/typedef.svh" `include "common_cells/registers.svh" `include "apb/typedef.svh" + `include "ara/intf_typedef.svh" ////////////////////// // Memory Regions // @@ -454,7 +455,6 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( cfg.RVF = FPUSupport[1]; cfg.RVD = FPUSupport[2]; cfg.NrPMPEntries = 0; - cfg.CLICNumInterruptSrc = 0; // idempotent region cfg.NrNonIdempotentRules = 2; cfg.NonIdempotentAddrBase = {UARTBase, CTRLBase}; @@ -476,6 +476,19 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( // Build the package localparam config_pkg::cva6_cfg_t CVA6AraConfig = build_config_pkg::build_config(CVA6AraConfig_user); + // Define the exception type + `CVA6_TYPEDEF_EXCEPTION(exception_t, CVA6AraConfig); + + // Standard interface + `CVA6_INTF_TYPEDEF_ACC_REQ(accelerator_req_t, CVA6AraConfig, fpnew_pkg::roundmode_e); + `CVA6_INTF_TYPEDEF_ACC_RESP(accelerator_resp_t, CVA6AraConfig, exception_t); + // MMU interface + `CVA6_INTF_TYPEDEF_MMU_REQ(acc_mmu_req_t, CVA6AraConfig); + `CVA6_INTF_TYPEDEF_MMU_RESP(acc_mmu_resp_t, CVA6AraConfig, exception_t); + // Accelerator - CVA6's top-level interface + `CVA6_INTF_TYPEDEF_CVA6_TO_ACC(cva6_to_acc_t, accelerator_req_t, acc_mmu_resp_t); + `CVA6_INTF_TYPEDEF_ACC_TO_CVA6(acc_to_cva6_t, accelerator_resp_t, acc_mmu_req_t); + `ifndef TARGET_GATESIM ara_system #( .NrLanes (NrLanes ), @@ -485,6 +498,13 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( .FPExtSupport (FPExtSupport ), .FixPtSupport (FixPtSupport ), .CVA6Cfg (CVA6AraConfig ), + .exception_t (exception_t ), + .accelerator_req_t (accelerator_req_t ), + .accelerator_resp_t(accelerator_resp_t ), + .acc_mmu_req_t (acc_mmu_req_t ), + .acc_mmu_resp_t (acc_mmu_resp_t ), + .cva6_to_acc_t (cva6_to_acc_t ), + .acc_to_cva6_t (acc_to_cva6_t ), .AxiAddrWidth (AxiAddrWidth ), .AxiIdWidth (AxiCoreIdWidth ), .AxiNarrowDataWidth(AxiNarrowDataWidth ), diff --git a/hardware/src/ara_system.sv b/hardware/src/ara_system.sv index 574e70674..5cc37970a 100644 --- a/hardware/src/ara_system.sv +++ b/hardware/src/ara_system.sv @@ -18,6 +18,14 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #( parameter fixpt_support_e FixPtSupport = FixedPointEnable, // Ariane configuration parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg, + // CVA6-related parameters + parameter type exception_t = logic, + parameter type accelerator_req_t = logic, + parameter type accelerator_resp_t = logic, + parameter type acc_mmu_req_t = logic, + parameter type acc_mmu_resp_t = logic, + parameter type cva6_to_acc_t = logic, + parameter type acc_to_cva6_t = logic, // AXI Interface parameter int unsigned AxiAddrWidth = 64, parameter int unsigned AxiIdWidth = 6, @@ -137,14 +145,14 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #( .ipi_i ('0 ), .time_irq_i ('0 ), .debug_req_i ('0 ), - .clic_irq_valid_i ('0 ), - .clic_irq_id_i ('0 ), - .clic_irq_level_i ('0 ), - .clic_irq_priv_i (riscv::priv_lvl_t'(2'b0)), - .clic_irq_shv_i ('0 ), - .clic_irq_ready_o (/* empty */ ), - .clic_kill_req_i ('0 ), - .clic_kill_ack_o (/* empty */ ), +// .clic_irq_valid_i ('0 ), +// .clic_irq_id_i ('0 ), +// .clic_irq_level_i ('0 ), +// .clic_irq_priv_i (riscv::priv_lvl_t'(2'b0)), +// .clic_irq_shv_i ('0 ), +// .clic_irq_ready_o (/* empty */ ), +// .clic_kill_req_i ('0 ), +// .clic_kill_ack_o (/* empty */ ), .rvfi_probes_o (/* empty */ ), // Accelerator ports .cvxif_req_o (acc_req ), @@ -213,22 +221,29 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #( ); ara #( - .NrLanes (NrLanes ), - .VLEN (VLEN ), - .OSSupport (OSSupport ), - .FPUSupport (FPUSupport ), - .FPExtSupport(FPExtSupport ), - .FixPtSupport(FixPtSupport ), - .CVA6Cfg (CVA6Cfg ), - .AxiDataWidth(AxiWideDataWidth), - .AxiAddrWidth(AxiAddrWidth ), - .axi_ar_t (ara_axi_ar_t ), - .axi_r_t (ara_axi_r_t ), - .axi_aw_t (ara_axi_aw_t ), - .axi_w_t (ara_axi_w_t ), - .axi_b_t (ara_axi_b_t ), - .axi_req_t (ara_axi_req_t ), - .axi_resp_t (ara_axi_resp_t ) + .NrLanes (NrLanes ), + .VLEN (VLEN ), + .OSSupport (OSSupport ), + .FPUSupport (FPUSupport ), + .FPExtSupport (FPExtSupport ), + .FixPtSupport (FixPtSupport ), + .CVA6Cfg (CVA6Cfg ), + .exception_t (exception_t ), + .accelerator_req_t (accelerator_req_t ), + .accelerator_resp_t(accelerator_resp_t), + .acc_mmu_req_t (acc_mmu_req_t ), + .acc_mmu_resp_t (acc_mmu_resp_t ), + .cva6_to_acc_t (cva6_to_acc_t ), + .acc_to_cva6_t (acc_to_cva6_t ), + .AxiDataWidth (AxiWideDataWidth ), + .AxiAddrWidth (AxiAddrWidth ), + .axi_ar_t (ara_axi_ar_t ), + .axi_r_t (ara_axi_r_t ), + .axi_aw_t (ara_axi_aw_t ), + .axi_w_t (ara_axi_w_t ), + .axi_b_t (ara_axi_b_t ), + .axi_req_t (ara_axi_req_t ), + .axi_resp_t (ara_axi_resp_t ) ) i_ara ( .clk_i (clk_i ), .rst_ni (rst_ni ),