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There is a deadlock potential if the downstream AXI network tries to sync the AW and W channel. This is sometimes necessary and also allowed by the AXI specifications (e.g. the
axi_to_mem
module needs address and data at the same time to generate a memory request). The problem with FlooNoC is that AW and W are sent over the same channels, which can causes a deadlock if the downstream AXI network waits for the W to be valid, which waits for the AW to be consumed.This PR fixes this by buffering the AWs. Since corresponding AWs and W are guaranteed to be consecutive (due to ordering issues), a buffer of size 1 is already enough to solve this deadlock situation.