From aa87bc3a8ec039f52f31e8d663a06ace00791001 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Tue, 10 Dec 2024 18:14:38 +0100 Subject: [PATCH] docs: Update CHANGELOG --- CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index d950cae2..fca94d98 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -36,6 +36,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) - The `ReorderBufferSize` parameters was shortened to `RoBSize`. - All testbenches were adapted to all changes. - All verification IPs were adapted to the new configuration structs. +- Added spill registers for outgoing AW requests in the chimneys. This is necessary since AXI allows to wait for AW *and* W to be valid before asserting the ready. Since, the AW and W beats are sent over the same channel, this might cause a deadlock if there there are no buffers downstream. #### FlooGen - The link typedefs are now renderd with the macros in `typedef.svh` instead of rendering them in pure SystemVerilog.