From 667c8f621c1459b0f53e0628d7cdff7ba5fb0e7f Mon Sep 17 00:00:00 2001 From: ZhuChenyanX Date: Thu, 19 Dec 2024 08:47:28 +0000 Subject: [PATCH] Use dgpu for codec when dual gpu case Also, remove TILING_Y/TILING_4 support for render formats in hybrid gpu mode. iGPU doesn't support TILING_4, dGPU doesn't support TILING_Y. When TILING_Y memory alloc by iGPU, but composite or display by dGPU, there will be blur screen issue. Tracked-On: OAM-128384 Signed-off-by: ZhuChenyanX --- .gitignore | 3 ++ cros_gralloc/cros_gralloc_driver.cc | 6 ++-- i915.c | 47 ++++++++++++++--------------- 3 files changed, 28 insertions(+), 28 deletions(-) create mode 100644 .gitignore diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..09d861c --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ +*.o +*.d +*.depends diff --git a/cros_gralloc/cros_gralloc_driver.cc b/cros_gralloc/cros_gralloc_driver.cc index 39784c4..ce38377 100644 --- a/cros_gralloc/cros_gralloc_driver.cc +++ b/cros_gralloc/cros_gralloc_driver.cc @@ -989,12 +989,12 @@ int cros_gralloc_driver::select_kms_driver(uint64_t gpu_grp_type) int cros_gralloc_driver::select_video_driver(uint64_t gpu_grp_type) { - if (gpu_grp_type & GPU_GRP_TYPE_HAS_INTEL_IGPU_BIT) { - return GPU_GRP_TYPE_INTEL_IGPU_IDX; - } if (gpu_grp_type & GPU_GRP_TYPE_HAS_INTEL_DGPU_BIT) { return GPU_GRP_TYPE_INTEL_DGPU_IDX; } + if (gpu_grp_type & GPU_GRP_TYPE_HAS_INTEL_IGPU_BIT) { + return GPU_GRP_TYPE_INTEL_IGPU_IDX; + } if (gpu_grp_type & GPU_GRP_TYPE_HAS_VIRTIO_GPU_BLOB_BIT) { return GPU_GRP_TYPE_VIRTIO_GPU_BLOB_IDX; } diff --git a/i915.c b/i915.c index a07a7b5..508e138 100644 --- a/i915.c +++ b/i915.c @@ -303,12 +303,6 @@ static int i915_add_combinations(struct driver *drv) &metadata_x_tiled, texture_flags_video | BO_USE_CAMERA_MASK); if (i915_has_tile4(i915)) { - // in dual gpu case, only alloc x-tiling for dgpu for render - if ((drv->gpu_grp_type & GPU_GRP_TYPE_HAS_INTEL_IGPU_BIT) || - (drv->gpu_grp_type & GPU_GRP_TYPE_HAS_VIRTIO_GPU_BLOB_BIT)) { - return 0; - } - struct format_metadata metadata_4_tiled = { .tiling = I915_TILING_4, .priority = 3, .modifier = I915_FORMAT_MOD_4_TILED }; @@ -325,22 +319,22 @@ static int i915_add_combinations(struct driver *drv) drv_add_combination(drv, DRM_FORMAT_NV12, &metadata_4_tiled, nv12_usage); drv_add_combination(drv, DRM_FORMAT_P010, &metadata_4_tiled, p010_usage); drv_add_combination(drv, DRM_FORMAT_P010_INTEL, &metadata_4_tiled, p010_usage); - drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), - &metadata_4_tiled, render_not_linear); - drv_add_combinations(drv, scanout_render_formats, - ARRAY_SIZE(scanout_render_formats), &metadata_4_tiled, - render_not_linear); - drv_add_combinations(drv, source_formats, ARRAY_SIZE(source_formats), &metadata_4_tiled, - texture_flags | BO_USE_NON_GPU_HW); + drv_add_combinations(drv, source_formats, ARRAY_SIZE(source_formats), &metadata_4_tiled, + texture_flags | BO_USE_NON_GPU_HW); + // in dual gpu case, only alloc x-tiling for dgpu for render + if (!(drv->gpu_grp_type & GPU_GRP_TYPE_HAS_INTEL_IGPU_BIT) && + !(drv->gpu_grp_type & GPU_GRP_TYPE_HAS_VIRTIO_GPU_BLOB_BIT)) { + drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), + &metadata_4_tiled, render_not_linear); + drv_add_combinations(drv, scanout_render_formats, + ARRAY_SIZE(scanout_render_formats), &metadata_4_tiled, + render_not_linear); + } } else { struct format_metadata metadata_y_tiled = { .tiling = I915_TILING_Y, .priority = 3, .modifier = I915_FORMAT_MOD_Y_TILED }; - if ((drv->gpu_grp_type & GPU_GRP_TYPE_HAS_INTEL_DGPU_BIT) || - (drv->gpu_grp_type & GPU_GRP_TYPE_HAS_VIRTIO_GPU_BLOB_P2P_BIT)) { - return 0; - } /* Support y-tiled NV12 and P010 for libva */ #ifdef I915_SCANOUT_Y_TILED const uint64_t nv12_usage = @@ -355,17 +349,20 @@ static int i915_add_combinations(struct driver *drv) drv_add_combination(drv, DRM_FORMAT_NV12, &metadata_y_tiled, nv12_usage); drv_add_combination(drv, DRM_FORMAT_P010, &metadata_y_tiled, p010_usage); drv_add_combination(drv, DRM_FORMAT_P010_INTEL, &metadata_y_tiled, p010_usage); - drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), - &metadata_y_tiled, render_not_linear); - /* Y-tiled scanout isn't available on old platforms so we add - * |scanout_render_formats| without that USE flag. - */ - drv_add_combinations(drv, scanout_render_formats, - ARRAY_SIZE(scanout_render_formats), &metadata_y_tiled, - scanout_and_render_not_linear); drv_add_combinations(drv, source_formats, ARRAY_SIZE(source_formats), &metadata_y_tiled, texture_flags | BO_USE_NON_GPU_HW); + if (!(drv->gpu_grp_type & GPU_GRP_TYPE_HAS_INTEL_DGPU_BIT) && + !(drv->gpu_grp_type & GPU_GRP_TYPE_HAS_VIRTIO_GPU_BLOB_P2P_BIT)) { + drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), + &metadata_y_tiled, render_not_linear); + /* Y-tiled scanout isn't available on old platforms so we add + * |scanout_render_formats| without that USE flag. + */ + drv_add_combinations(drv, scanout_render_formats, + ARRAY_SIZE(scanout_render_formats), &metadata_y_tiled, + scanout_and_render_not_linear); + } } return 0; }