fpga-ci.yml

name: FPGA Tests

on:
  push:
    branches: [ main, ci-fix ]
  pull_request:
    branches: [ main, ci-fix ]
  merge_group:
    branches: [ main, ci-fix ]

env:
  CODECOV_TOKEN: ${{ secrets.CODECOV_TOKEN }}

jobs:
  test-fpga:
    if: ${{ !contains(github.event.pull_request.labels.*.name, 'no-ci') }}
    runs-on: [self-hosted, linux, intel-fpga, xilinx-fpga]
    steps:
    - uses: actions/checkout@v2
      with:
        submodules: 'recursive'
    - name: Install dependencies
      run: |
        rm -f ~/.dace.conf
        rm -rf .dacecache tests/.dacecache
        python -m venv ~/.venv      # create venv so we can use pip
        source ~/.venv/bin/activate # activate venv
        python -m pip install --upgrade pip
        pip install pytest-xdist flake8 coverage click
        pip uninstall -y dace
        pip install -e ".[testing]"
        curl -Os https://uploader.codecov.io/latest/linux/codecov
        chmod +x codecov

    - name: Run FPGA Tests
      run: |
        source ~/.venv/bin/activate # activate venv
        export COVERAGE_RCFILE=`pwd`/.coveragerc

        # Xilinx setup
        export PATH=/opt/Xilinx/Vitis/2022.1/bin:/opt/Xilinx/Vitis_HLS/2022.1/bin:/opt/Xilinx/Vivado/2022.1/bin:$PATH
        export XILINX_XRT=/opt/xilinx/xrt
        export LD_LIBRARY_PATH=$XILINX_XRT/lib:$LD_LIBRARY_PATH
        export XILINX_VITIS=/opt/Xilinx/Vitis/2022.1
        export DACE_compiler_xilinx_platform=xilinx_u250_gen3x16_xdma_4_1_202210_1

        # Intel FPGA setup
        export INTELFPGAOCLSDKROOT=/opt/intelFPGA_pro/19.1/hld
        export ALTERAOCLSDKROOT=$INTELFPGAOCLSDKROOT
        export AOCL_BOARD_PACKAGE_ROOT=/opt/intelFPGA_pro/19.1/hld/board/a10_ref
        export PATH=$INTELFPGAOCLSDKROOT/bin:$PATH
        export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$AOCL_BOARD_PACKAGE_ROOT/linux64/lib
        export QUARTUS_ROOTDIR_OVERRIDE=/opt/intelFPGA_pro/19.1/quartus
        export LD_PRELOAD=/lib/x86_64-linux-gnu/libstdc++.so.6   # Work around dependency issues

        # Due to an internal bug in the Xilinx tools, where the current datetime is passed as an integer
        # and overflowed in the year 2022, run the FPGA tests pretending like it's January 1st 2021.
        # faketime -f "@2021-01-01 00:00:00" pytest -n auto --cov-report=xml --cov=dace --tb=short -m "fpga"
        # Try running without faketime
        pytest -n auto --cov-report=xml --cov=dace --tb=short -m "fpga"

        coverage report
        coverage xml
        reachable=0
        ping -W 2 -c 1 codecov.io || reachable=$?
        if [ $reachable -eq 0 ]; then
          ./codecov
        else
          echo "Codecov.io is unreachable"
        fi
        killall -9 xsim xsimk || true