Source/Sink for ADC/DAC interface

[ujinijoshi]

Hi,
We have a small data rate ADC and DACs upto 4MSPS which are interfaced with ZYNQ using LVDS channels.
We created the IP which produces ADC Samples over axi-stream interface. Can we use this frame work for data copy from PS to PL and PL to PS? Or its only designed for some computation acceleration blocks to pass data from Pothos framework running in ZYNQ PS.

[guruofquality]

This file is just a generic wrapper for the axi dma in userspace. I use it all of the time in one form or another to get data in and out of the PL: https://github.com/pothosware/PothosZynq/blob/master/driver/pothos_zynq_dma_driver.h