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vgaram.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
# Date created = 11:50:35 December 23, 2015
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# vgaram_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA4U23C6
set_global_assignment -name TOP_LEVEL_ENTITY vgaram
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:50:35 DECEMBER 23, 2015"
set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name VERILOG_FILE vgaram.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to blue_out[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to blue_out[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to blue_out[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to green_out[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hs_out
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vs_out
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to red_out[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to red_out[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to red_out[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to green_out[1]
set_location_assignment PIN_AH19 -to red_out[2]
set_location_assignment PIN_AH21 -to red_out[1]
set_location_assignment PIN_AG21 -to red_out[0]
set_location_assignment PIN_AF22 -to hs_out
set_location_assignment PIN_AH22 -to vs_out
set_location_assignment PIN_AH18 -to green_out[1]
set_location_assignment PIN_AD23 -to green_out[0]
set_location_assignment PIN_V11 -to clk50_in
set_location_assignment PIN_AE23 -to blue_out[2]
set_location_assignment PIN_AA18 -to blue_out[1]
set_location_assignment PIN_AC22 -to blue_out[0]
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top