From e925abdf554945d1573879f3dcccf01ce9cf2d7a Mon Sep 17 00:00:00 2001
From: Phil Howard <phil@pimoroni.com>
Date: Tue, 21 Mar 2023 11:44:46 +0000
Subject: [PATCH] Experimental: Overclock patch.

---
 .github/workflows/micropython.yml |  8 ++++++++
 firmware/startup_overclock.patch  | 26 ++++++++++++++++++++++++++
 2 files changed, 34 insertions(+)
 create mode 100644 firmware/startup_overclock.patch

diff --git a/.github/workflows/micropython.yml b/.github/workflows/micropython.yml
index c2c5265..3607ba6 100644
--- a/.github/workflows/micropython.yml
+++ b/.github/workflows/micropython.yml
@@ -75,6 +75,7 @@ jobs:
     env:
       RELEASE_FILE: pimoroni-${{matrix.shortname}}-${{github.event.release.tag_name || github.sha}}-micropython.uf2
       RELEASE_FILE_WITH_OS: pimoroni-${{matrix.shortname}}-${{github.event.release.tag_name || github.sha}}-micropython-with-badger-os.uf2
+      FIRMWARE_DIR: "$GITHUB_WORKSPACE/badger2040/firmware"
       BOARD_DIR: "$GITHUB_WORKSPACE/badger2040/firmware/${{matrix.board}}"
       BADGER_OS_DIR: "$GITHUB_WORKSPACE/badger2040/badger_os"
 
@@ -116,6 +117,13 @@ jobs:
         ref: v0.0.1
         path: dir2uf2
 
+     # HACK: Patch startup overclock into Pico SDK
+    - name: "HACK: Startup Overclock Patch"
+      shell: bash
+      working-directory: micropython/lib/pico-sdk
+      run: |
+        git apply "${{env.FIRMWARE_DIR}}/startup_overclock.patch"
+
     # Install apt packages
     - name: Install CCache & Compiler
       shell: bash
diff --git a/firmware/startup_overclock.patch b/firmware/startup_overclock.patch
new file mode 100644
index 0000000..0d88477
--- /dev/null
+++ b/firmware/startup_overclock.patch
@@ -0,0 +1,26 @@
+diff --git a/src/rp2_common/pico_standard_link/crt0.S b/src/rp2_common/pico_standard_link/crt0.S
+index d061108..864d31f 100644
+--- a/src/rp2_common/pico_standard_link/crt0.S
++++ b/src/rp2_common/pico_standard_link/crt0.S
+@@ -10,6 +10,8 @@
+ #include "hardware/regs/sio.h"
+ #include "pico/asm_helper.S"
+ #include "pico/binary_info/defs.h"
++#include "hardware/regs/resets.h"
++#include "hardware/regs/rosc.h"
+ 
+ #ifdef NDEBUG
+ #ifndef COLLAPSE_IRQS
+@@ -226,6 +228,12 @@ _reset_handler:
+     cmp r0, #0
+     bne hold_non_core0_in_bootrom
+ 
++    // Increase ROSC frequency to ~48MHz (range 14.4 - 96)
++    // Speeds up memory zero init and preinit phases.
++    ldr r0, =(ROSC_BASE + ROSC_DIV_OFFSET)
++    ldr r1, =0xaa2
++    str r1, [r0]
++
+     // In a NO_FLASH binary, don't perform .data copy, since it's loaded
+     // in-place by the SRAM load. Still need to clear .bss
+ #if !PICO_NO_FLASH