diff --git a/sim/pipeline-riscv.c b/sim/pipeline-riscv.c
index a4a221d1..fdeafd6b 100644
--- a/sim/pipeline-riscv.c
+++ b/sim/pipeline-riscv.c
@@ -537,16 +537,6 @@ riscvstep(Engine *E, State *S, int drain_pipeline)
 
 			switch (S->riscv->P.EX.format)
 			{
-				case INSTR_N:
-				{
-					(*(S->riscv->P.EX.fptr))(E, S);	/*	riscv_nop??	*/
-					S->dyncnt++;
-
-					S->riscv->instruction_distribution[S->riscv->P.EX.op]++;
-
-					break;
-				}
-
 				case INSTR_R:
 				{
 					uint32_t tmp = (uint32_t) S->riscv->P.EX.instr;
@@ -649,6 +639,25 @@ riscvstep(Engine *E, State *S, int drain_pipeline)
 					break;
 				}
 
+				case INSTR_R4:
+				{
+					instr_r4 *tmp;
+
+					tmp = (instr_r4 *)&S->riscv->P.EX.instr;
+					(*(S->riscv->P.EX.fptr))(E, S, tmp->rs1, tmp->rs2, tmp->rs3, tmp->rm, tmp->rd);
+					break;
+				}
+
+				case INSTR_N:
+				{
+					(*(S->riscv->P.EX.fptr))(E, S);	/*	riscv_nop??	*/
+					S->dyncnt++;
+
+					S->riscv->instruction_distribution[S->riscv->P.EX.op]++;
+
+					break;
+				}
+
 				default:
 				{
 					sfatal(E, S, "Unknown Instruction Type !!");